[linux.git] / drivers / rtc / rtc-pxa.c

/*
 * Real Time Clock interface for XScale PXA27x and PXA3xx
 *
 * Copyright (C) 2008 Robert Jarzmik
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>

#include <mach/hardware.h>

#define TIMER_FREQ		CLOCK_TICK_RATE
#define RTC_DEF_DIVIDER		(32768 - 1)
#define RTC_DEF_TRIM		0
#define MAXFREQ_PERIODIC	1000

/*
 * PXA Registers and bits definitions
 */
#define RTSR_PICE	(1 << 15)	/* Periodic interrupt count enable */
#define RTSR_PIALE	(1 << 14)	/* Periodic interrupt Alarm enable */
#define RTSR_PIAL	(1 << 13)	/* Periodic interrupt detected */
#define RTSR_SWALE2	(1 << 11)	/* RTC stopwatch alarm2 enable */
#define RTSR_SWAL2	(1 << 10)	/* RTC stopwatch alarm2 detected */
#define RTSR_SWALE1	(1 << 9)	/* RTC stopwatch alarm1 enable */
#define RTSR_SWAL1	(1 << 8)	/* RTC stopwatch alarm1 detected */
#define RTSR_RDALE2	(1 << 7)	/* RTC alarm2 enable */
#define RTSR_RDAL2	(1 << 6)	/* RTC alarm2 detected */
#define RTSR_RDALE1	(1 << 5)	/* RTC alarm1 enable */
#define RTSR_RDAL1	(1 << 4)	/* RTC alarm1 detected */
#define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */
#define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */
#define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
#define RTSR_AL		(1 << 0)	/* RTC alarm detected */
#define RTSR_TRIG_MASK	(RTSR_AL | RTSR_HZ | RTSR_RDAL1 | RTSR_RDAL2\
			 | RTSR_SWAL1 | RTSR_SWAL2)
#define RYxR_YEAR_S	9
#define RYxR_YEAR_MASK	(0xfff << RYxR_YEAR_S)
#define RYxR_MONTH_S	5
#define RYxR_MONTH_MASK	(0xf << RYxR_MONTH_S)
#define RYxR_DAY_MASK	0x1f
#define RDxR_WOM_S     20
#define RDxR_WOM_MASK  (0x7 << RDxR_WOM_S)
#define RDxR_DOW_S     17
#define RDxR_DOW_MASK  (0x7 << RDxR_DOW_S)
#define RDxR_HOUR_S	12
#define RDxR_HOUR_MASK	(0x1f << RDxR_HOUR_S)
#define RDxR_MIN_S	6
#define RDxR_MIN_MASK	(0x3f << RDxR_MIN_S)
#define RDxR_SEC_MASK	0x3f

#define RTSR		0x08
#define RTTR		0x0c
#define RDCR		0x10
#define RYCR		0x14
#define RDAR1		0x18
#define RYAR1		0x1c
#define RTCPICR		0x34
#define PIAR		0x38

#define rtc_readl(pxa_rtc, reg)	\
	__raw_readl((pxa_rtc)->base + (reg))
#define rtc_writel(pxa_rtc, reg, value)	\
	__raw_writel((value), (pxa_rtc)->base + (reg))

struct pxa_rtc {
	struct resource	*ress;
	void __iomem		*base;
	int			irq_1Hz;
	int			irq_Alrm;
	struct rtc_device	*rtc;
	spinlock_t		lock;		/* Protects this structure */
};


static u32 ryxr_calc(struct rtc_time *tm)
{
	return ((tm->tm_year + 1900) << RYxR_YEAR_S)
		| ((tm->tm_mon + 1) << RYxR_MONTH_S)
		| tm->tm_mday;
}

static u32 rdxr_calc(struct rtc_time *tm)
{
	return ((((tm->tm_mday + 6) / 7) << RDxR_WOM_S) & RDxR_WOM_MASK)
		| (((tm->tm_wday + 1) << RDxR_DOW_S) & RDxR_DOW_MASK)
		| (tm->tm_hour << RDxR_HOUR_S)
		| (tm->tm_min << RDxR_MIN_S)
		| tm->tm_sec;
}

static void tm_calc(u32 rycr, u32 rdcr, struct rtc_time *tm)
{
	tm->tm_year = ((rycr & RYxR_YEAR_MASK) >> RYxR_YEAR_S) - 1900;
	tm->tm_mon = (((rycr & RYxR_MONTH_MASK) >> RYxR_MONTH_S)) - 1;
	tm->tm_mday = (rycr & RYxR_DAY_MASK);
	tm->tm_wday = ((rycr & RDxR_DOW_MASK) >> RDxR_DOW_S) - 1;
	tm->tm_hour = (rdcr & RDxR_HOUR_MASK) >> RDxR_HOUR_S;
	tm->tm_min = (rdcr & RDxR_MIN_MASK) >> RDxR_MIN_S;
	tm->tm_sec = rdcr & RDxR_SEC_MASK;
}

static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask)
{
	u32 rtsr;

	rtsr = rtc_readl(pxa_rtc, RTSR);
	rtsr &= ~RTSR_TRIG_MASK;
	rtsr &= ~mask;
	rtc_writel(pxa_rtc, RTSR, rtsr);
}

static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask)
{
	u32 rtsr;

	rtsr = rtc_readl(pxa_rtc, RTSR);
	rtsr &= ~RTSR_TRIG_MASK;
	rtsr |= mask;
	rtc_writel(pxa_rtc, RTSR, rtsr);
}

static irqreturn_t pxa_rtc_irq(int irq, void *dev_id)
{
	struct platform_device *pdev = to_platform_device(dev_id);
	struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev);
	u32 rtsr;
	unsigned long events = 0;

	spin_lock(&pxa_rtc->lock);

	/* clear interrupt sources */
	rtsr = rtc_readl(pxa_rtc, RTSR);
	rtc_writel(pxa_rtc, RTSR, rtsr);

	/* temporary disable rtc interrupts */
	rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 | RTSR_PIALE | RTSR_HZE);

	/* clear alarm interrupt if it has occurred */
	if (rtsr & RTSR_RDAL1)
		rtsr &= ~RTSR_RDALE1;

	/* update irq data & counter */
	if (rtsr & RTSR_RDAL1)
		events |= RTC_AF | RTC_IRQF;
	if (rtsr & RTSR_HZ)
		events |= RTC_UF | RTC_IRQF;
	if (rtsr & RTSR_PIAL)
		events |= RTC_PF | RTC_IRQF;

	rtc_update_irq(pxa_rtc->rtc, 1, events);

	/* enable back rtc interrupts */
	rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK);

	spin_unlock(&pxa_rtc->lock);
	return IRQ_HANDLED;
}

static int pxa_rtc_open(struct device *dev)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	int ret;

	ret = request_irq(pxa_rtc->irq_1Hz, pxa_rtc_irq, 0,
			  "rtc 1Hz", dev);
	if (ret < 0) {
		dev_err(dev, "can't get irq %i, err %d\n", pxa_rtc->irq_1Hz,
			ret);
		goto err_irq_1Hz;
	}
	ret = request_irq(pxa_rtc->irq_Alrm, pxa_rtc_irq, 0,
			  "rtc Alrm", dev);
	if (ret < 0) {
		dev_err(dev, "can't get irq %i, err %d\n", pxa_rtc->irq_Alrm,
			ret);
		goto err_irq_Alrm;
	}

	return 0;

err_irq_Alrm:
	free_irq(pxa_rtc->irq_1Hz, dev);
err_irq_1Hz:
	return ret;
}

static void pxa_rtc_release(struct device *dev)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);

	spin_lock_irq(&pxa_rtc->lock);
	rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
	spin_unlock_irq(&pxa_rtc->lock);

	free_irq(pxa_rtc->irq_Alrm, dev);
	free_irq(pxa_rtc->irq_1Hz, dev);
}

static int pxa_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);

	spin_lock_irq(&pxa_rtc->lock);

	if (enabled)
		rtsr_set_bits(pxa_rtc, RTSR_RDALE1);
	else
		rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);

	spin_unlock_irq(&pxa_rtc->lock);
	return 0;
}

static int pxa_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	u32 rycr, rdcr;

	rycr = rtc_readl(pxa_rtc, RYCR);
	rdcr = rtc_readl(pxa_rtc, RDCR);

	tm_calc(rycr, rdcr, tm);
	return 0;
}

static int pxa_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);

	rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm));
	rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm));

	return 0;
}

static int pxa_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	u32 rtsr, ryar, rdar;

	ryar = rtc_readl(pxa_rtc, RYAR1);
	rdar = rtc_readl(pxa_rtc, RDAR1);
	tm_calc(ryar, rdar, &alrm->time);

	rtsr = rtc_readl(pxa_rtc, RTSR);
	alrm->enabled = (rtsr & RTSR_RDALE1) ? 1 : 0;
	alrm->pending = (rtsr & RTSR_RDAL1) ? 1 : 0;
	return 0;
}

static int pxa_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	u32 rtsr;

	spin_lock_irq(&pxa_rtc->lock);

	rtc_writel(pxa_rtc, RYAR1, ryxr_calc(&alrm->time));
	rtc_writel(pxa_rtc, RDAR1, rdxr_calc(&alrm->time));

	rtsr = rtc_readl(pxa_rtc, RTSR);
	if (alrm->enabled)
		rtsr |= RTSR_RDALE1;
	else
		rtsr &= ~RTSR_RDALE1;
	rtc_writel(pxa_rtc, RTSR, rtsr);

	spin_unlock_irq(&pxa_rtc->lock);

	return 0;
}

static int pxa_rtc_proc(struct device *dev, struct seq_file *seq)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);

	seq_printf(seq, "trim/divider\t: 0x%08x\n", rtc_readl(pxa_rtc, RTTR));
	seq_printf(seq, "update_IRQ\t: %s\n",
		   (rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no");
	seq_printf(seq, "periodic_IRQ\t: %s\n",
		   (rtc_readl(pxa_rtc, RTSR) & RTSR_PIALE) ? "yes" : "no");
	seq_printf(seq, "periodic_freq\t: %u\n", rtc_readl(pxa_rtc, PIAR));

	return 0;
}

static const struct rtc_class_ops pxa_rtc_ops = {
	.read_time = pxa_rtc_read_time,
	.set_time = pxa_rtc_set_time,
	.read_alarm = pxa_rtc_read_alarm,
	.set_alarm = pxa_rtc_set_alarm,
	.alarm_irq_enable = pxa_alarm_irq_enable,
	.proc = pxa_rtc_proc,
};

static int __init pxa_rtc_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct pxa_rtc *pxa_rtc;
	int ret;
	u32 rttr;

	pxa_rtc = kzalloc(sizeof(struct pxa_rtc), GFP_KERNEL);
	if (!pxa_rtc)
		return -ENOMEM;

	spin_lock_init(&pxa_rtc->lock);
	platform_set_drvdata(pdev, pxa_rtc);

	ret = -ENXIO;
	pxa_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!pxa_rtc->ress) {
		dev_err(dev, "No I/O memory resource defined\n");
		goto err_ress;
	}

	pxa_rtc->irq_1Hz = platform_get_irq(pdev, 0);
	if (pxa_rtc->irq_1Hz < 0) {
		dev_err(dev, "No 1Hz IRQ resource defined\n");
		goto err_ress;
	}
	pxa_rtc->irq_Alrm = platform_get_irq(pdev, 1);
	if (pxa_rtc->irq_Alrm < 0) {
		dev_err(dev, "No alarm IRQ resource defined\n");
		goto err_ress;
	}
	pxa_rtc_open(dev);
	ret = -ENOMEM;
	pxa_rtc->base = ioremap(pxa_rtc->ress->start,
				resource_size(pxa_rtc->ress));
	if (!pxa_rtc->base) {
		dev_err(&pdev->dev, "Unable to map pxa RTC I/O memory\n");
		goto err_map;
	}

	/*
	 * If the clock divider is uninitialized then reset it to the
	 * default value to get the 1Hz clock.
	 */
	if (rtc_readl(pxa_rtc, RTTR) == 0) {
		rttr = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16);
		rtc_writel(pxa_rtc, RTTR, rttr);
		dev_warn(dev, "warning: initializing default clock"
			 " divider/trim value\n");
	}

	rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);

	pxa_rtc->rtc = rtc_device_register("pxa-rtc", &pdev->dev, &pxa_rtc_ops,
					   THIS_MODULE);
	ret = PTR_ERR(pxa_rtc->rtc);
	if (IS_ERR(pxa_rtc->rtc)) {
		dev_err(dev, "Failed to register RTC device -> %d\n", ret);
		goto err_rtc_reg;
	}

	device_init_wakeup(dev, 1);

	return 0;

err_rtc_reg:
	 iounmap(pxa_rtc->base);
err_ress:
err_map:
	kfree(pxa_rtc);
	return ret;
}

static int __exit pxa_rtc_remove(struct platform_device *pdev)
{
	struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev);

	struct device *dev = &pdev->dev;
	pxa_rtc_release(dev);

	rtc_device_unregister(pxa_rtc->rtc);

	spin_lock_irq(&pxa_rtc->lock);
	iounmap(pxa_rtc->base);
	spin_unlock_irq(&pxa_rtc->lock);

	kfree(pxa_rtc);

	return 0;
}

#ifdef CONFIG_OF
static struct of_device_id pxa_rtc_dt_ids[] = {
	{ .compatible = "marvell,pxa-rtc" },
	{}
};
MODULE_DEVICE_TABLE(of, pxa_rtc_dt_ids);
#endif

#ifdef CONFIG_PM_SLEEP
static int pxa_rtc_suspend(struct device *dev)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		enable_irq_wake(pxa_rtc->irq_Alrm);
	return 0;
}

static int pxa_rtc_resume(struct device *dev)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		disable_irq_wake(pxa_rtc->irq_Alrm);
	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(pxa_rtc_pm_ops, pxa_rtc_suspend, pxa_rtc_resume);

static struct platform_driver pxa_rtc_driver = {
	.remove		= __exit_p(pxa_rtc_remove),
	.driver		= {
		.name	= "pxa-rtc",
		.of_match_table = of_match_ptr(pxa_rtc_dt_ids),
		.pm	= &pxa_rtc_pm_ops,
	},
};

module_platform_driver_probe(pxa_rtc_driver, pxa_rtc_probe);

MODULE_AUTHOR("Robert Jarzmik <[email protected]>");
MODULE_DESCRIPTION("PXA27x/PXA3xx Realtime Clock Driver (RTC)");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pxa-rtc");
Commit	Line	Data
dc944368 RJ	1	/*
	2	* Real Time Clock interface for XScale PXA27x and PXA3xx
	3	*
	4	* Copyright (C) 2008 Robert Jarzmik
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*
	20	*/
	21
0417ce2a	22	#include <linux/init.h>
dc944368 RJ	23	#include <linux/platform_device.h>
	24	#include <linux/module.h>
	25	#include <linux/rtc.h>
	26	#include <linux/seq_file.h>
	27	#include <linux/interrupt.h>
0417ce2a	28	#include <linux/io.h>
5a0e3ad6	29	#include <linux/slab.h>
9020b7cc DM	30	#include <linux/of.h>
9020b7cc DM	31	#include <linux/of_device.h>
dc944368	32
4216d0bd AO	33	#include <mach/hardware.h>
4216d0bd AO	34
dc944368 RJ	35	#define TIMER_FREQ CLOCK_TICK_RATE
	36	#define RTC_DEF_DIVIDER (32768 - 1)
	37	#define RTC_DEF_TRIM 0
	38	#define MAXFREQ_PERIODIC 1000
	39
	40	/*
	41	* PXA Registers and bits definitions
	42	*/
	43	#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
	44	#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
	45	#define RTSR_PIAL (1 << 13) /* Periodic interrupt detected */
	46	#define RTSR_SWALE2 (1 << 11) /* RTC stopwatch alarm2 enable */
	47	#define RTSR_SWAL2 (1 << 10) /* RTC stopwatch alarm2 detected */
	48	#define RTSR_SWALE1 (1 << 9) /* RTC stopwatch alarm1 enable */
	49	#define RTSR_SWAL1 (1 << 8) /* RTC stopwatch alarm1 detected */
	50	#define RTSR_RDALE2 (1 << 7) /* RTC alarm2 enable */
	51	#define RTSR_RDAL2 (1 << 6) /* RTC alarm2 detected */
	52	#define RTSR_RDALE1 (1 << 5) /* RTC alarm1 enable */
	53	#define RTSR_RDAL1 (1 << 4) /* RTC alarm1 detected */
	54	#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
	55	#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
	56	#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
	57	#define RTSR_AL (1 << 0) /* RTC alarm detected */
	58	#define RTSR_TRIG_MASK (RTSR_AL \| RTSR_HZ \| RTSR_RDAL1 \| RTSR_RDAL2\
	59	\| RTSR_SWAL1 \| RTSR_SWAL2)
	60	#define RYxR_YEAR_S 9
	61	#define RYxR_YEAR_MASK (0xfff << RYxR_YEAR_S)
	62	#define RYxR_MONTH_S 5
	63	#define RYxR_MONTH_MASK (0xf << RYxR_MONTH_S)
	64	#define RYxR_DAY_MASK 0x1f
c4243de7 LS	65	#define RDxR_WOM_S 20
	66	#define RDxR_WOM_MASK (0x7 << RDxR_WOM_S)
	67	#define RDxR_DOW_S 17
	68	#define RDxR_DOW_MASK (0x7 << RDxR_DOW_S)
dc944368 RJ	69	#define RDxR_HOUR_S 12
	70	#define RDxR_HOUR_MASK (0x1f << RDxR_HOUR_S)
	71	#define RDxR_MIN_S 6
	72	#define RDxR_MIN_MASK (0x3f << RDxR_MIN_S)
	73	#define RDxR_SEC_MASK 0x3f
	74
	75	#define RTSR 0x08
	76	#define RTTR 0x0c
	77	#define RDCR 0x10
	78	#define RYCR 0x14
	79	#define RDAR1 0x18
	80	#define RYAR1 0x1c
	81	#define RTCPICR 0x34
	82	#define PIAR 0x38
	83
	84	#define rtc_readl(pxa_rtc, reg) \
	85	__raw_readl((pxa_rtc)->base + (reg))
	86	#define rtc_writel(pxa_rtc, reg, value) \
	87	__raw_writel((value), (pxa_rtc)->base + (reg))
	88
	89	struct pxa_rtc {
	90	struct resource *ress;
	91	void __iomem *base;
	92	int irq_1Hz;
	93	int irq_Alrm;
	94	struct rtc_device *rtc;
	95	spinlock_t lock; /* Protects this structure */
dc944368 RJ	96	};
dc944368 RJ	97
c4243de7	98
dc944368 RJ	99	static u32 ryxr_calc(struct rtc_time *tm)
	100	{
	101	return ((tm->tm_year + 1900) << RYxR_YEAR_S)
	102	\| ((tm->tm_mon + 1) << RYxR_MONTH_S)
	103	\| tm->tm_mday;
	104	}
	105
	106	static u32 rdxr_calc(struct rtc_time *tm)
	107	{
c4243de7 LS	108	return ((((tm->tm_mday + 6) / 7) << RDxR_WOM_S) & RDxR_WOM_MASK)
	109	\| (((tm->tm_wday + 1) << RDxR_DOW_S) & RDxR_DOW_MASK)
	110	\| (tm->tm_hour << RDxR_HOUR_S)
	111	\| (tm->tm_min << RDxR_MIN_S)
dc944368 RJ	112	\| tm->tm_sec;
	113	}
	114
	115	static void tm_calc(u32 rycr, u32 rdcr, struct rtc_time *tm)
	116	{
	117	tm->tm_year = ((rycr & RYxR_YEAR_MASK) >> RYxR_YEAR_S) - 1900;
	118	tm->tm_mon = (((rycr & RYxR_MONTH_MASK) >> RYxR_MONTH_S)) - 1;
	119	tm->tm_mday = (rycr & RYxR_DAY_MASK);
c4243de7	120	tm->tm_wday = ((rycr & RDxR_DOW_MASK) >> RDxR_DOW_S) - 1;
dc944368 RJ	121	tm->tm_hour = (rdcr & RDxR_HOUR_MASK) >> RDxR_HOUR_S;
	122	tm->tm_min = (rdcr & RDxR_MIN_MASK) >> RDxR_MIN_S;
	123	tm->tm_sec = rdcr & RDxR_SEC_MASK;
	124	}
	125
	126	static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask)
	127	{
	128	u32 rtsr;
	129
	130	rtsr = rtc_readl(pxa_rtc, RTSR);
	131	rtsr &= ~RTSR_TRIG_MASK;
	132	rtsr &= ~mask;
	133	rtc_writel(pxa_rtc, RTSR, rtsr);
	134	}
	135
	136	static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask)
	137	{
	138	u32 rtsr;
	139
	140	rtsr = rtc_readl(pxa_rtc, RTSR);
	141	rtsr &= ~RTSR_TRIG_MASK;
	142	rtsr \|= mask;
	143	rtc_writel(pxa_rtc, RTSR, rtsr);
	144	}
	145
	146	static irqreturn_t pxa_rtc_irq(int irq, void *dev_id)
	147	{
	148	struct platform_device *pdev = to_platform_device(dev_id);
	149	struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev);
	150	u32 rtsr;
	151	unsigned long events = 0;
	152
	153	spin_lock(&pxa_rtc->lock);
	154
	155	/* clear interrupt sources */
	156	rtsr = rtc_readl(pxa_rtc, RTSR);
	157	rtc_writel(pxa_rtc, RTSR, rtsr);
	158
	159	/* temporary disable rtc interrupts */
	160	rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 \| RTSR_PIALE \| RTSR_HZE);
	161
	162	/* clear alarm interrupt if it has occurred */
	163	if (rtsr & RTSR_RDAL1)
	164	rtsr &= ~RTSR_RDALE1;
	165
	166	/* update irq data & counter */
	167	if (rtsr & RTSR_RDAL1)
	168	events \|= RTC_AF \| RTC_IRQF;
	169	if (rtsr & RTSR_HZ)
	170	events \|= RTC_UF \| RTC_IRQF;
	171	if (rtsr & RTSR_PIAL)
	172	events \|= RTC_PF \| RTC_IRQF;
	173
	174	rtc_update_irq(pxa_rtc->rtc, 1, events);
	175
	176	/* enable back rtc interrupts */
	177	rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK);
	178
	179	spin_unlock(&pxa_rtc->lock);
	180	return IRQ_HANDLED;
	181	}
	182
	183	static int pxa_rtc_open(struct device *dev)
	184	{
185	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
186	int ret;
187
2f6e5f94	188	ret = request_irq(pxa_rtc->irq_1Hz, pxa_rtc_irq, 0,
dc944368 RJ	189	"rtc 1Hz", dev);
	190	if (ret < 0) {
	191	dev_err(dev, "can't get irq %i, err %d\n", pxa_rtc->irq_1Hz,
	192	ret);
	193	goto err_irq_1Hz;
	194	}
2f6e5f94	195	ret = request_irq(pxa_rtc->irq_Alrm, pxa_rtc_irq, 0,
dc944368 RJ	196	"rtc Alrm", dev);
	197	if (ret < 0) {
	198	dev_err(dev, "can't get irq %i, err %d\n", pxa_rtc->irq_Alrm,
	199	ret);
	200	goto err_irq_Alrm;
	201	}
	202
	203	return 0;
	204
	205	err_irq_Alrm:
	206	free_irq(pxa_rtc->irq_1Hz, dev);
	207	err_irq_1Hz:
	208	return ret;
	209	}
	210
	211	static void pxa_rtc_release(struct device *dev)
	212	{
	213	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	214
	215	spin_lock_irq(&pxa_rtc->lock);
	216	rtsr_clear_bits(pxa_rtc, RTSR_PIALE \| RTSR_RDALE1 \| RTSR_HZE);
	217	spin_unlock_irq(&pxa_rtc->lock);
	218
	219	free_irq(pxa_rtc->irq_Alrm, dev);
	220	free_irq(pxa_rtc->irq_1Hz, dev);
	221	}
	222
93b1384f	223	static int pxa_alarm_irq_enable(struct device *dev, unsigned int enabled)
dc944368 RJ	224	{
dc944368 RJ	225	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
dc944368 RJ	226
dc944368 RJ	227	spin_lock_irq(&pxa_rtc->lock);
93b1384f WZ	228
93b1384f WZ	229	if (enabled)
dc944368	230	rtsr_set_bits(pxa_rtc, RTSR_RDALE1);
93b1384f WZ	231	else
	232	rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);
	233
	234	spin_unlock_irq(&pxa_rtc->lock);
	235	return 0;
	236	}
	237
dc944368 RJ	238	static int pxa_rtc_read_time(struct device dev, struct rtc_time tm)
	239	{
	240	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	241	u32 rycr, rdcr;
	242
	243	rycr = rtc_readl(pxa_rtc, RYCR);
	244	rdcr = rtc_readl(pxa_rtc, RDCR);
	245
	246	tm_calc(rycr, rdcr, tm);
	247	return 0;
	248	}
	249
	250	static int pxa_rtc_set_time(struct device dev, struct rtc_time tm)
	251	{
	252	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	253
	254	rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm));
	255	rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm));
	256
	257	return 0;
	258	}
	259
	260	static int pxa_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	261	{
	262	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	263	u32 rtsr, ryar, rdar;
	264
	265	ryar = rtc_readl(pxa_rtc, RYAR1);
	266	rdar = rtc_readl(pxa_rtc, RDAR1);
	267	tm_calc(ryar, rdar, &alrm->time);
	268
	269	rtsr = rtc_readl(pxa_rtc, RTSR);
	270	alrm->enabled = (rtsr & RTSR_RDALE1) ? 1 : 0;
	271	alrm->pending = (rtsr & RTSR_RDAL1) ? 1 : 0;
	272	return 0;
	273	}
	274
	275	static int pxa_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	276	{
	277	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	278	u32 rtsr;
	279
	280	spin_lock_irq(&pxa_rtc->lock);
	281
	282	rtc_writel(pxa_rtc, RYAR1, ryxr_calc(&alrm->time));
	283	rtc_writel(pxa_rtc, RDAR1, rdxr_calc(&alrm->time));
	284
	285	rtsr = rtc_readl(pxa_rtc, RTSR);
	286	if (alrm->enabled)
	287	rtsr \|= RTSR_RDALE1;
	288	else
	289	rtsr &= ~RTSR_RDALE1;
	290	rtc_writel(pxa_rtc, RTSR, rtsr);
	291
	292	spin_unlock_irq(&pxa_rtc->lock);
	293
	294	return 0;
	295	}
	296
	297	static int pxa_rtc_proc(struct device dev, struct seq_file seq)
	298	{
	299	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	300
	301	seq_printf(seq, "trim/divider\t: 0x%08x\n", rtc_readl(pxa_rtc, RTTR));
302	seq_printf(seq, "update_IRQ\t: %s\n",
303	(rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no");
304	seq_printf(seq, "periodic_IRQ\t: %s\n",
305	(rtc_readl(pxa_rtc, RTSR) & RTSR_PIALE) ? "yes" : "no");
306	seq_printf(seq, "periodic_freq\t: %u\n", rtc_readl(pxa_rtc, PIAR));
307
308	return 0;
309	}
310
311	static const struct rtc_class_ops pxa_rtc_ops = {
dc944368 RJ	312	.read_time = pxa_rtc_read_time,
	313	.set_time = pxa_rtc_set_time,
	314	.read_alarm = pxa_rtc_read_alarm,
	315	.set_alarm = pxa_rtc_set_alarm,
93b1384f	316	.alarm_irq_enable = pxa_alarm_irq_enable,
dc944368	317	.proc = pxa_rtc_proc,
dc944368 RJ	318	};
dc944368 RJ	319
0417ce2a	320	static int __init pxa_rtc_probe(struct platform_device *pdev)
dc944368 RJ	321	{
	322	struct device *dev = &pdev->dev;
	323	struct pxa_rtc *pxa_rtc;
	324	int ret;
	325	u32 rttr;
	326
dc944368 RJ	327	pxa_rtc = kzalloc(sizeof(struct pxa_rtc), GFP_KERNEL);
dc944368 RJ	328	if (!pxa_rtc)
0417ce2a AZ	329	return -ENOMEM;
	330
	331	spin_lock_init(&pxa_rtc->lock);
	332	platform_set_drvdata(pdev, pxa_rtc);
dc944368 RJ	333
	334	ret = -ENXIO;
	335	pxa_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	336	if (!pxa_rtc->ress) {
	337	dev_err(dev, "No I/O memory resource defined\n");
	338	goto err_ress;
	339	}
	340
	341	pxa_rtc->irq_1Hz = platform_get_irq(pdev, 0);
	342	if (pxa_rtc->irq_1Hz < 0) {
	343	dev_err(dev, "No 1Hz IRQ resource defined\n");
	344	goto err_ress;
	345	}
	346	pxa_rtc->irq_Alrm = platform_get_irq(pdev, 1);
	347	if (pxa_rtc->irq_Alrm < 0) {
	348	dev_err(dev, "No alarm IRQ resource defined\n");
	349	goto err_ress;
	350	}
a44802f8	351	pxa_rtc_open(dev);
dc944368 RJ	352	ret = -ENOMEM;
dc944368 RJ	353	pxa_rtc->base = ioremap(pxa_rtc->ress->start,
0417ce2a	354	resource_size(pxa_rtc->ress));
dc944368 RJ	355	if (!pxa_rtc->base) {
	356	dev_err(&pdev->dev, "Unable to map pxa RTC I/O memory\n");
	357	goto err_map;
	358	}
	359
	360	/*
	361	* If the clock divider is uninitialized then reset it to the
	362	* default value to get the 1Hz clock.
	363	*/
	364	if (rtc_readl(pxa_rtc, RTTR) == 0) {
	365	rttr = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16);
	366	rtc_writel(pxa_rtc, RTTR, rttr);
	367	dev_warn(dev, "warning: initializing default clock"
	368	" divider/trim value\n");
	369	}
	370
	371	rtsr_clear_bits(pxa_rtc, RTSR_PIALE \| RTSR_RDALE1 \| RTSR_HZE);
0417ce2a AZ	372
	373	pxa_rtc->rtc = rtc_device_register("pxa-rtc", &pdev->dev, &pxa_rtc_ops,
	374	THIS_MODULE);
	375	ret = PTR_ERR(pxa_rtc->rtc);
	376	if (IS_ERR(pxa_rtc->rtc)) {
	377	dev_err(dev, "Failed to register RTC device -> %d\n", ret);
	378	goto err_rtc_reg;
	379	}
	380
dc944368 RJ	381	device_init_wakeup(dev, 1);
	382
	383	return 0;
	384
dc944368	385	err_rtc_reg:
0417ce2a	386	iounmap(pxa_rtc->base);
dc944368	387	err_ress:
0417ce2a	388	err_map:
dc944368	389	kfree(pxa_rtc);
dc944368 RJ	390	return ret;
	391	}
	392
0417ce2a	393	static int __exit pxa_rtc_remove(struct platform_device *pdev)
dc944368 RJ	394	{
	395	struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev);
	396
a44802f8 LS	397	struct device *dev = &pdev->dev;
	398	pxa_rtc_release(dev);
	399
0417ce2a AZ	400	rtc_device_unregister(pxa_rtc->rtc);
0417ce2a AZ	401
dc944368 RJ	402	spin_lock_irq(&pxa_rtc->lock);
dc944368 RJ	403	iounmap(pxa_rtc->base);
dc944368 RJ	404	spin_unlock_irq(&pxa_rtc->lock);
dc944368 RJ	405
dc944368 RJ	406	kfree(pxa_rtc);
	407
	408	return 0;
	409	}
	410
9020b7cc DM	411	#ifdef CONFIG_OF
	412	static struct of_device_id pxa_rtc_dt_ids[] = {
	413	{ .compatible = "marvell,pxa-rtc" },
	414	{}
	415	};
	416	MODULE_DEVICE_TABLE(of, pxa_rtc_dt_ids);
	417	#endif
	418
c5a40618	419	#ifdef CONFIG_PM_SLEEP
e6e698a4	420	static int pxa_rtc_suspend(struct device *dev)
dc944368	421	{
e6e698a4	422	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
dc944368	423
e6e698a4	424	if (device_may_wakeup(dev))
dc944368 RJ	425	enable_irq_wake(pxa_rtc->irq_Alrm);
	426	return 0;
	427	}
	428
e6e698a4	429	static int pxa_rtc_resume(struct device *dev)
dc944368	430	{
e6e698a4	431	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
dc944368	432
e6e698a4	433	if (device_may_wakeup(dev))
dc944368 RJ	434	disable_irq_wake(pxa_rtc->irq_Alrm);
	435	return 0;
	436	}
dc944368 RJ	437	#endif
dc944368 RJ	438
c5a40618 JH	439	static SIMPLE_DEV_PM_OPS(pxa_rtc_pm_ops, pxa_rtc_suspend, pxa_rtc_resume);
c5a40618 JH	440
dc944368	441	static struct platform_driver pxa_rtc_driver = {
dc944368	442	.remove = __exit_p(pxa_rtc_remove),
dc944368	443	.driver = {
e6e698a4	444	.name = "pxa-rtc",
9020b7cc	445	.of_match_table = of_match_ptr(pxa_rtc_dt_ids),
e6e698a4	446	.pm = &pxa_rtc_pm_ops,
dc944368 RJ	447	},
	448	};
	449
7daba88e	450	module_platform_driver_probe(pxa_rtc_driver, pxa_rtc_probe);
dc944368	451
57f63bc8	452	MODULE_AUTHOR("Robert Jarzmik <[email protected]>");
dc944368 RJ	453	MODULE_DESCRIPTION("PXA27x/PXA3xx Realtime Clock Driver (RTC)");
	454	MODULE_LICENSE("GPL");
	455	MODULE_ALIAS("platform:pxa-rtc");