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1da177e4 LT |
1 | #ifndef _ALPHA_HARDIRQ_H |
2 | #define _ALPHA_HARDIRQ_H | |
3 | ||
1da177e4 LT |
4 | #include <linux/threads.h> |
5 | #include <linux/cache.h> | |
6 | ||
7 | ||
8 | /* entry.S is sensitive to the offsets of these fields */ | |
9 | typedef struct { | |
10 | unsigned long __softirq_pending; | |
11 | } ____cacheline_aligned irq_cpustat_t; | |
12 | ||
13 | #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ | |
14 | ||
0595bf3b IK |
15 | void ack_bad_irq(unsigned int irq); |
16 | ||
1da177e4 LT |
17 | #define HARDIRQ_BITS 12 |
18 | ||
19 | /* | |
20 | * The hardirq mask has to be large enough to have | |
21 | * space for potentially nestable IRQ sources in the system | |
22 | * to nest on a single CPU. On Alpha, interrupts are masked at the CPU | |
23 | * by IPL as well as at the system level. We only have 8 IPLs (UNIX PALcode) | |
24 | * so we really only have 8 nestable IRQs, but allow some overhead | |
25 | */ | |
26 | #if (1 << HARDIRQ_BITS) < 16 | |
27 | #error HARDIRQ_BITS is too low! | |
28 | #endif | |
29 | ||
30 | #endif /* _ALPHA_HARDIRQ_H */ |