[linux.git] / drivers / watchdog / imx2_wdt.c

/*
 * Watchdog driver for IMX2 and later processors
 *
 *  Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <[email protected]>
 *  Copyright (C) 2014 Freescale Semiconductor, Inc.
 *
 * some parts adapted by similar drivers from Darius Augulis and Vladimir
 * Zapolskiy, additional improvements by Wim Van Sebroeck.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
 *
 *			MX1:		MX2+:
 *			----		-----
 * Registers:		32-bit		16-bit
 * Stopable timer:	Yes		No
 * Need to enable clk:	No		Yes
 * Halt on suspend:	Manual		Can be automatic
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/timer.h>
#include <linux/watchdog.h>

#define DRIVER_NAME "imx2-wdt"

#define IMX2_WDT_WCR		0x00		/* Control Register */
#define IMX2_WDT_WCR_WT		(0xFF << 8)	/* -> Watchdog Timeout Field */
#define IMX2_WDT_WCR_WRE	(1 << 3)	/* -> WDOG Reset Enable */
#define IMX2_WDT_WCR_WDE	(1 << 2)	/* -> Watchdog Enable */
#define IMX2_WDT_WCR_WDZST	(1 << 0)	/* -> Watchdog timer Suspend */

#define IMX2_WDT_WSR		0x02		/* Service Register */
#define IMX2_WDT_SEQ1		0x5555		/* -> service sequence 1 */
#define IMX2_WDT_SEQ2		0xAAAA		/* -> service sequence 2 */

#define IMX2_WDT_WRSR		0x04		/* Reset Status Register */
#define IMX2_WDT_WRSR_TOUT	(1 << 1)	/* -> Reset due to Timeout */

#define IMX2_WDT_WMCR		0x08		/* Misc Register */

#define IMX2_WDT_MAX_TIME	128
#define IMX2_WDT_DEFAULT_TIME	60		/* in seconds */

#define WDOG_SEC_TO_COUNT(s)	((s * 2 - 1) << 8)

struct imx2_wdt_device {
	struct clk *clk;
	struct regmap *regmap;
	struct timer_list timer;	/* Pings the watchdog when closed */
	struct watchdog_device wdog;
};

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");


static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
				__MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");

static const struct watchdog_info imx2_wdt_info = {
	.identity = "imx2+ watchdog",
	.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
};

static int imx2_wdt_restart(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	unsigned int wcr_enable = IMX2_WDT_WCR_WDE;

	/* Assert SRS signal */
	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
	/*
	 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
	 * written twice), we add another two writes to ensure there must be at
	 * least two writes happen in the same one 32kHz clock period.  We save
	 * the target check here, since the writes shouldn't be a huge burden
	 * for other platforms.
	 */
	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);

	/* wait for reset to assert... */
	mdelay(500);

	return 0;
}

static inline void imx2_wdt_setup(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	u32 val;

	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);

	/* Suspend timer in low power mode, write once-only */
	val |= IMX2_WDT_WCR_WDZST;
	/* Strip the old watchdog Time-Out value */
	val &= ~IMX2_WDT_WCR_WT;
	/* Generate reset if WDOG times out */
	val &= ~IMX2_WDT_WCR_WRE;
	/* Keep Watchdog Disabled */
	val &= ~IMX2_WDT_WCR_WDE;
	/* Set the watchdog's Time-Out value */
	val |= WDOG_SEC_TO_COUNT(wdog->timeout);

	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);

	/* enable the watchdog */
	val |= IMX2_WDT_WCR_WDE;
	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
}

static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
{
	u32 val;

	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);

	return val & IMX2_WDT_WCR_WDE;
}

static int imx2_wdt_ping(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
	return 0;
}

static void imx2_wdt_timer_ping(unsigned long arg)
{
	struct watchdog_device *wdog = (struct watchdog_device *)arg;
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	/* ping it every wdog->timeout / 2 seconds to prevent reboot */
	imx2_wdt_ping(wdog);
	mod_timer(&wdev->timer, jiffies + wdog->timeout * HZ / 2);
}

static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
				unsigned int new_timeout)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	wdog->timeout = new_timeout;

	regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
			   WDOG_SEC_TO_COUNT(new_timeout));
	return 0;
}

static int imx2_wdt_start(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev)) {
		/* delete the timer that pings the watchdog after close */
		del_timer_sync(&wdev->timer);
		imx2_wdt_set_timeout(wdog, wdog->timeout);
	} else
		imx2_wdt_setup(wdog);

	return imx2_wdt_ping(wdog);
}

static int imx2_wdt_stop(struct watchdog_device *wdog)
{
	/*
	 * We don't need a clk_disable, it cannot be disabled once started.
	 * We use a timer to ping the watchdog while /dev/watchdog is closed
	 */
	imx2_wdt_timer_ping((unsigned long)wdog);
	return 0;
}

static inline void imx2_wdt_ping_if_active(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev)) {
		imx2_wdt_set_timeout(wdog, wdog->timeout);
		imx2_wdt_timer_ping((unsigned long)wdog);
	}
}

static const struct watchdog_ops imx2_wdt_ops = {
	.owner = THIS_MODULE,
	.start = imx2_wdt_start,
	.stop = imx2_wdt_stop,
	.ping = imx2_wdt_ping,
	.set_timeout = imx2_wdt_set_timeout,
	.restart = imx2_wdt_restart,
};

static const struct regmap_config imx2_wdt_regmap_config = {
	.reg_bits = 16,
	.reg_stride = 2,
	.val_bits = 16,
	.max_register = 0x8,
};

static int __init imx2_wdt_probe(struct platform_device *pdev)
{
	struct imx2_wdt_device *wdev;
	struct watchdog_device *wdog;
	struct resource *res;
	void __iomem *base;
	int ret;
	u32 val;

	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	if (!wdev)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
						 &imx2_wdt_regmap_config);
	if (IS_ERR(wdev->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		return PTR_ERR(wdev->regmap);
	}

	wdev->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(wdev->clk)) {
		dev_err(&pdev->dev, "can't get Watchdog clock\n");
		return PTR_ERR(wdev->clk);
	}

	wdog			= &wdev->wdog;
	wdog->info		= &imx2_wdt_info;
	wdog->ops		= &imx2_wdt_ops;
	wdog->min_timeout	= 1;
	wdog->max_timeout	= IMX2_WDT_MAX_TIME;
	wdog->parent		= &pdev->dev;

	ret = clk_prepare_enable(wdev->clk);
	if (ret)
		return ret;

	regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
	wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;

	wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
	if (wdog->timeout != timeout)
		dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
			 timeout, wdog->timeout);

	platform_set_drvdata(pdev, wdog);
	watchdog_set_drvdata(wdog, wdev);
	watchdog_set_nowayout(wdog, nowayout);
	watchdog_set_restart_priority(wdog, 128);
	watchdog_init_timeout(wdog, timeout, &pdev->dev);

	setup_timer(&wdev->timer, imx2_wdt_timer_ping, (unsigned long)wdog);

	imx2_wdt_ping_if_active(wdog);

	/*
	 * Disable the watchdog power down counter at boot. Otherwise the power
	 * down counter will pull down the #WDOG interrupt line for one clock
	 * cycle.
	 */
	regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);

	ret = watchdog_register_device(wdog);
	if (ret) {
		dev_err(&pdev->dev, "cannot register watchdog device\n");
		goto disable_clk;
	}

	dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
		 wdog->timeout, nowayout);

	return 0;

disable_clk:
	clk_disable_unprepare(wdev->clk);
	return ret;
}

static int __exit imx2_wdt_remove(struct platform_device *pdev)
{
	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	watchdog_unregister_device(wdog);

	if (imx2_wdt_is_running(wdev)) {
		del_timer_sync(&wdev->timer);
		imx2_wdt_ping(wdog);
		dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
	}
	return 0;
}

static void imx2_wdt_shutdown(struct platform_device *pdev)
{
	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev)) {
		/*
		 * We are running, we need to delete the timer but will
		 * give max timeout before reboot will take place
		 */
		del_timer_sync(&wdev->timer);
		imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
		imx2_wdt_ping(wdog);
		dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
	}
}

#ifdef CONFIG_PM_SLEEP
/* Disable watchdog if it is active or non-active but still running */
static int imx2_wdt_suspend(struct device *dev)
{
	struct watchdog_device *wdog = dev_get_drvdata(dev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	/* The watchdog IP block is running */
	if (imx2_wdt_is_running(wdev)) {
		imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
		imx2_wdt_ping(wdog);

		/* The watchdog is not active */
		if (!watchdog_active(wdog))
			del_timer_sync(&wdev->timer);
	}

	clk_disable_unprepare(wdev->clk);

	return 0;
}

/* Enable watchdog and configure it if necessary */
static int imx2_wdt_resume(struct device *dev)
{
	struct watchdog_device *wdog = dev_get_drvdata(dev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	int ret;

	ret = clk_prepare_enable(wdev->clk);
	if (ret)
		return ret;

	if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
		/*
		 * If the watchdog is still active and resumes
		 * from deep sleep state, need to restart the
		 * watchdog again.
		 */
		imx2_wdt_setup(wdog);
		imx2_wdt_set_timeout(wdog, wdog->timeout);
		imx2_wdt_ping(wdog);
	} else if (imx2_wdt_is_running(wdev)) {
		/* Resuming from non-deep sleep state. */
		imx2_wdt_set_timeout(wdog, wdog->timeout);
		imx2_wdt_ping(wdog);
		/*
		 * But the watchdog is not active, then start
		 * the timer again.
		 */
		if (!watchdog_active(wdog))
			mod_timer(&wdev->timer,
				  jiffies + wdog->timeout * HZ / 2);
	}

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
			 imx2_wdt_resume);

static const struct of_device_id imx2_wdt_dt_ids[] = {
	{ .compatible = "fsl,imx21-wdt", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);

static struct platform_driver imx2_wdt_driver = {
	.remove		= __exit_p(imx2_wdt_remove),
	.shutdown	= imx2_wdt_shutdown,
	.driver		= {
		.name	= DRIVER_NAME,
		.pm     = &imx2_wdt_pm_ops,
		.of_match_table = imx2_wdt_dt_ids,
	},
};

module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);

MODULE_AUTHOR("Wolfram Sang");
MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
bb2fd8a8 WS	1	/*
	2	* Watchdog driver for IMX2 and later processors
	3	*
	4	* Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <[email protected]>
1a9c5efa	5	* Copyright (C) 2014 Freescale Semiconductor, Inc.
bb2fd8a8 WS	6	*
	7	* some parts adapted by similar drivers from Darius Augulis and Vladimir
	8	* Zapolskiy, additional improvements by Wim Van Sebroeck.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published by
	12	* the Free Software Foundation.
	13	*
	14	* NOTE: MX1 has a slightly different Watchdog than MX2 and later:
	15	*
	16	* MX1: MX2+:
	17	* ---- -----
	18	* Registers: 32-bit 16-bit
	19	* Stopable timer: Yes No
	20	* Need to enable clk: No Yes
	21	* Halt on suspend: Manual Can be automatic
	22	*/
	23
30cb042a	24	#include <linux/clk.h>
334a9d81	25	#include <linux/delay.h>
bb2fd8a8	26	#include <linux/init.h>
30cb042a XL	27	#include <linux/io.h>
30cb042a XL	28	#include <linux/jiffies.h>
bb2fd8a8	29	#include <linux/kernel.h>
bb2fd8a8 WS	30	#include <linux/module.h>
bb2fd8a8 WS	31	#include <linux/moduleparam.h>
f728f4bf	32	#include <linux/of_address.h>
bb2fd8a8	33	#include <linux/platform_device.h>
a7977003	34	#include <linux/regmap.h>
bb2fd8a8	35	#include <linux/timer.h>
30cb042a	36	#include <linux/watchdog.h>
bb2fd8a8 WS	37
	38	#define DRIVER_NAME "imx2-wdt"
	39
	40	#define IMX2_WDT_WCR 0x00 /* Control Register */
	41	#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
	42	#define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
	43	#define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */
1a9c5efa	44	#define IMX2_WDT_WCR_WDZST (1 << 0) /* -> Watchdog timer Suspend */
bb2fd8a8 WS	45
	46	#define IMX2_WDT_WSR 0x02 /* Service Register */
	47	#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
	48	#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
	49
474ef121 OS	50	#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
	51	#define IMX2_WDT_WRSR_TOUT (1 << 1) /* -> Reset due to Timeout */
	52
5fe65ce7 MSP	53	#define IMX2_WDT_WMCR 0x08 /* Misc Register */
5fe65ce7 MSP	54
bb2fd8a8 WS	55	#define IMX2_WDT_MAX_TIME 128
	56	#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
	57
	58	#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
	59
faad5de0	60	struct imx2_wdt_device {
bb2fd8a8	61	struct clk *clk;
a7977003	62	struct regmap *regmap;
bb2fd8a8	63	struct timer_list timer; /* Pings the watchdog when closed */
faad5de0 AG	64	struct watchdog_device wdog;
faad5de0 AG	65	};
bb2fd8a8	66
86a1e189 WVS	67	static bool nowayout = WATCHDOG_NOWAYOUT;
86a1e189 WVS	68	module_param(nowayout, bool, 0);
bb2fd8a8 WS	69	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
	70	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	71
	72
	73	static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
	74	module_param(timeout, uint, 0);
	75	MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
	76	__MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
	77
	78	static const struct watchdog_info imx2_wdt_info = {
	79	.identity = "imx2+ watchdog",
	80	.options = WDIOF_KEEPALIVEPING \| WDIOF_SETTIMEOUT \| WDIOF_MAGICCLOSE,
	81	};
	82
2d9d2475	83	static int imx2_wdt_restart(struct watchdog_device *wdog)
334a9d81	84	{
2d9d2475	85	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
334a9d81	86	unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
2d9d2475	87
334a9d81	88	/* Assert SRS signal */
9493c0d8	89	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
334a9d81 JL	90	/*
	91	* Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
	92	* written twice), we add another two writes to ensure there must be at
	93	* least two writes happen in the same one 32kHz clock period. We save
	94	* the target check here, since the writes shouldn't be a huge burden
	95	* for other platforms.
	96	*/
9493c0d8 FE	97	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
9493c0d8 FE	98	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
334a9d81 JL	99
	100	/* wait for reset to assert... */
	101	mdelay(500);
	102
2d9d2475	103	return 0;
334a9d81 JL	104	}
334a9d81 JL	105
faad5de0	106	static inline void imx2_wdt_setup(struct watchdog_device *wdog)
bb2fd8a8	107	{
faad5de0	108	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
a7977003 XL	109	u32 val;
a7977003 XL	110
faad5de0	111	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
bb2fd8a8	112
1a9c5efa AH	113	/* Suspend timer in low power mode, write once-only */
1a9c5efa AH	114	val \|= IMX2_WDT_WCR_WDZST;
bb2fd8a8 WS	115	/* Strip the old watchdog Time-Out value */
	116	val &= ~IMX2_WDT_WCR_WT;
	117	/* Generate reset if WDOG times out */
	118	val &= ~IMX2_WDT_WCR_WRE;
	119	/* Keep Watchdog Disabled */
	120	val &= ~IMX2_WDT_WCR_WDE;
	121	/* Set the watchdog's Time-Out value */
faad5de0	122	val \|= WDOG_SEC_TO_COUNT(wdog->timeout);
bb2fd8a8	123
faad5de0	124	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
bb2fd8a8 WS	125
	126	/* enable the watchdog */
	127	val \|= IMX2_WDT_WCR_WDE;
faad5de0	128	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
bb2fd8a8 WS	129	}
bb2fd8a8 WS	130
faad5de0	131	static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
bb2fd8a8	132	{
faad5de0	133	u32 val;
bb2fd8a8	134
faad5de0 AG	135	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
	136
	137	return val & IMX2_WDT_WCR_WDE;
bb2fd8a8 WS	138	}
bb2fd8a8 WS	139
faad5de0	140	static int imx2_wdt_ping(struct watchdog_device *wdog)
bb2fd8a8	141	{
faad5de0	142	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	143
faad5de0 AG	144	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
	145	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
	146	return 0;
bb2fd8a8 WS	147	}
bb2fd8a8 WS	148
faad5de0	149	static void imx2_wdt_timer_ping(unsigned long arg)
bb2fd8a8	150	{
faad5de0 AG	151	struct watchdog_device wdog = (struct watchdog_device )arg;
	152	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	153
	154	/* ping it every wdog->timeout / 2 seconds to prevent reboot */
	155	imx2_wdt_ping(wdog);
	156	mod_timer(&wdev->timer, jiffies + wdog->timeout * HZ / 2);
bb2fd8a8 WS	157	}
bb2fd8a8 WS	158
faad5de0 AG	159	static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
faad5de0 AG	160	unsigned int new_timeout)
bb2fd8a8	161	{
faad5de0 AG	162	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
faad5de0 AG	163
30dd4a8f MG	164	wdog->timeout = new_timeout;
30dd4a8f MG	165
faad5de0	166	regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
a7977003	167	WDOG_SEC_TO_COUNT(new_timeout));
faad5de0	168	return 0;
bb2fd8a8 WS	169	}
bb2fd8a8 WS	170
faad5de0	171	static int imx2_wdt_start(struct watchdog_device *wdog)
bb2fd8a8	172	{
faad5de0	173	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	174
faad5de0 AG	175	if (imx2_wdt_is_running(wdev)) {
	176	/* delete the timer that pings the watchdog after close */
	177	del_timer_sync(&wdev->timer);
	178	imx2_wdt_set_timeout(wdog, wdog->timeout);
	179	} else
	180	imx2_wdt_setup(wdog);
	181
	182	return imx2_wdt_ping(wdog);
bb2fd8a8 WS	183	}
bb2fd8a8 WS	184
faad5de0	185	static int imx2_wdt_stop(struct watchdog_device *wdog)
bb2fd8a8	186	{
faad5de0 AG	187	/*
	188	* We don't need a clk_disable, it cannot be disabled once started.
	189	* We use a timer to ping the watchdog while /dev/watchdog is closed
	190	*/
	191	imx2_wdt_timer_ping((unsigned long)wdog);
bb2fd8a8 WS	192	return 0;
	193	}
	194
faad5de0	195	static inline void imx2_wdt_ping_if_active(struct watchdog_device *wdog)
bb2fd8a8	196	{
faad5de0	197	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	198
faad5de0 AG	199	if (imx2_wdt_is_running(wdev)) {
	200	imx2_wdt_set_timeout(wdog, wdog->timeout);
	201	imx2_wdt_timer_ping((unsigned long)wdog);
bb2fd8a8 WS	202	}
	203	}
	204
4bd8ce33	205	static const struct watchdog_ops imx2_wdt_ops = {
bb2fd8a8	206	.owner = THIS_MODULE,
faad5de0 AG	207	.start = imx2_wdt_start,
	208	.stop = imx2_wdt_stop,
	209	.ping = imx2_wdt_ping,
	210	.set_timeout = imx2_wdt_set_timeout,
2d9d2475	211	.restart = imx2_wdt_restart,
bb2fd8a8 WS	212	};
bb2fd8a8 WS	213
4bd8ce33	214	static const struct regmap_config imx2_wdt_regmap_config = {
a7977003 XL	215	.reg_bits = 16,
	216	.reg_stride = 2,
	217	.val_bits = 16,
	218	.max_register = 0x8,
	219	};
	220
bb2fd8a8 WS	221	static int __init imx2_wdt_probe(struct platform_device *pdev)
bb2fd8a8 WS	222	{
faad5de0 AG	223	struct imx2_wdt_device *wdev;
faad5de0 AG	224	struct watchdog_device *wdog;
bb2fd8a8	225	struct resource *res;
a7977003 XL	226	void __iomem *base;
a7977003 XL	227	int ret;
faad5de0 AG	228	u32 val;
	229
	230	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	231	if (!wdev)
	232	return -ENOMEM;
bb2fd8a8 WS	233
bb2fd8a8 WS	234	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
a7977003 XL	235	base = devm_ioremap_resource(&pdev->dev, res);
	236	if (IS_ERR(base))
	237	return PTR_ERR(base);
	238
faad5de0 AG	239	wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
	240	&imx2_wdt_regmap_config);
	241	if (IS_ERR(wdev->regmap)) {
a7977003	242	dev_err(&pdev->dev, "regmap init failed\n");
faad5de0	243	return PTR_ERR(wdev->regmap);
a7977003	244	}
bb2fd8a8	245
faad5de0 AG	246	wdev->clk = devm_clk_get(&pdev->dev, NULL);
faad5de0 AG	247	if (IS_ERR(wdev->clk)) {
bb2fd8a8	248	dev_err(&pdev->dev, "can't get Watchdog clock\n");
faad5de0	249	return PTR_ERR(wdev->clk);
bb2fd8a8 WS	250	}
bb2fd8a8 WS	251
faad5de0 AG	252	wdog = &wdev->wdog;
	253	wdog->info = &imx2_wdt_info;
	254	wdog->ops = &imx2_wdt_ops;
	255	wdog->min_timeout = 1;
	256	wdog->max_timeout = IMX2_WDT_MAX_TIME;
8135193c	257	wdog->parent = &pdev->dev;
bb2fd8a8	258
aefb163c FE	259	ret = clk_prepare_enable(wdev->clk);
	260	if (ret)
	261	return ret;
bb2fd8a8	262
faad5de0 AG	263	regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
faad5de0 AG	264	wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
bb2fd8a8	265
faad5de0 AG	266	wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
	267	if (wdog->timeout != timeout)
	268	dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
	269	timeout, wdog->timeout);
	270
	271	platform_set_drvdata(pdev, wdog);
	272	watchdog_set_drvdata(wdog, wdev);
	273	watchdog_set_nowayout(wdog, nowayout);
2d9d2475	274	watchdog_set_restart_priority(wdog, 128);
faad5de0 AG	275	watchdog_init_timeout(wdog, timeout, &pdev->dev);
	276
	277	setup_timer(&wdev->timer, imx2_wdt_timer_ping, (unsigned long)wdog);
bb2fd8a8	278
faad5de0 AG	279	imx2_wdt_ping_if_active(wdog);
faad5de0 AG	280
5fe65ce7 MSP	281	/*
	282	* Disable the watchdog power down counter at boot. Otherwise the power
	283	* down counter will pull down the #WDOG interrupt line for one clock
	284	* cycle.
	285	*/
	286	regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
	287
faad5de0 AG	288	ret = watchdog_register_device(wdog);
	289	if (ret) {
	290	dev_err(&pdev->dev, "cannot register watchdog device\n");
db11cba2	291	goto disable_clk;
faad5de0 AG	292	}
	293
	294	dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
	295	wdog->timeout, nowayout);
	296
	297	return 0;
db11cba2 FE	298
	299	disable_clk:
	300	clk_disable_unprepare(wdev->clk);
	301	return ret;
bb2fd8a8 WS	302	}
	303
	304	static int __exit imx2_wdt_remove(struct platform_device *pdev)
	305	{
faad5de0 AG	306	struct watchdog_device *wdog = platform_get_drvdata(pdev);
faad5de0 AG	307	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	308
faad5de0	309	watchdog_unregister_device(wdog);
bb2fd8a8	310
faad5de0 AG	311	if (imx2_wdt_is_running(wdev)) {
	312	del_timer_sync(&wdev->timer);
	313	imx2_wdt_ping(wdog);
	314	dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
bdf49574	315	}
bb2fd8a8 WS	316	return 0;
	317	}
	318
	319	static void imx2_wdt_shutdown(struct platform_device *pdev)
	320	{
faad5de0 AG	321	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	322	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	323
	324	if (imx2_wdt_is_running(wdev)) {
	325	/*
	326	* We are running, we need to delete the timer but will
	327	* give max timeout before reboot will take place
	328	*/
	329	del_timer_sync(&wdev->timer);
	330	imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
	331	imx2_wdt_ping(wdog);
	332	dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
bb2fd8a8 WS	333	}
	334	}
	335
aefbaf3a	336	#ifdef CONFIG_PM_SLEEP
bbd59009	337	/* Disable watchdog if it is active or non-active but still running */
aefbaf3a XL	338	static int imx2_wdt_suspend(struct device *dev)
	339	{
	340	struct watchdog_device *wdog = dev_get_drvdata(dev);
	341	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	342
bbd59009 XL	343	/* The watchdog IP block is running */
	344	if (imx2_wdt_is_running(wdev)) {
	345	imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
	346	imx2_wdt_ping(wdog);
aefbaf3a	347
bbd59009 XL	348	/* The watchdog is not active */
	349	if (!watchdog_active(wdog))
	350	del_timer_sync(&wdev->timer);
	351	}
aefbaf3a XL	352
	353	clk_disable_unprepare(wdev->clk);
	354
	355	return 0;
	356	}
	357
	358	/* Enable watchdog and configure it if necessary */
	359	static int imx2_wdt_resume(struct device *dev)
	360	{
	361	struct watchdog_device *wdog = dev_get_drvdata(dev);
	362	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
aefb163c	363	int ret;
aefbaf3a	364
aefb163c FE	365	ret = clk_prepare_enable(wdev->clk);
	366	if (ret)
	367	return ret;
aefbaf3a XL	368
aefbaf3a XL	369	if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
bbd59009 XL	370	/*
	371	* If the watchdog is still active and resumes
	372	* from deep sleep state, need to restart the
	373	* watchdog again.
aefbaf3a XL	374	*/
	375	imx2_wdt_setup(wdog);
	376	imx2_wdt_set_timeout(wdog, wdog->timeout);
	377	imx2_wdt_ping(wdog);
	378	} else if (imx2_wdt_is_running(wdev)) {
bbd59009 XL	379	/* Resuming from non-deep sleep state. */
bbd59009 XL	380	imx2_wdt_set_timeout(wdog, wdog->timeout);
aefbaf3a	381	imx2_wdt_ping(wdog);
bbd59009 XL	382	/*
	383	* But the watchdog is not active, then start
	384	* the timer again.
	385	*/
	386	if (!watchdog_active(wdog))
	387	mod_timer(&wdev->timer,
	388	jiffies + wdog->timeout * HZ / 2);
aefbaf3a XL	389	}
	390
	391	return 0;
	392	}
	393	#endif
	394
	395	static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
	396	imx2_wdt_resume);
	397
f5a427ee SG	398	static const struct of_device_id imx2_wdt_dt_ids[] = {
	399	{ .compatible = "fsl,imx21-wdt", },
	400	{ /* sentinel */ }
	401	};
813296a1	402	MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
f5a427ee	403
bb2fd8a8	404	static struct platform_driver imx2_wdt_driver = {
bb2fd8a8 WS	405	.remove = __exit_p(imx2_wdt_remove),
	406	.shutdown = imx2_wdt_shutdown,
	407	.driver = {
	408	.name = DRIVER_NAME,
aefbaf3a	409	.pm = &imx2_wdt_pm_ops,
f5a427ee	410	.of_match_table = imx2_wdt_dt_ids,
bb2fd8a8 WS	411	},
	412	};
	413
1cb9204c	414	module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
bb2fd8a8 WS	415
	416	MODULE_AUTHOR("Wolfram Sang");
	417	MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
	418	MODULE_LICENSE("GPL v2");
bb2fd8a8	419	MODULE_ALIAS("platform:" DRIVER_NAME);