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0376148f | 1 | // SPDX-License-Identifier: GPL-2.0-only |
62579266 RV |
2 | /* |
3 | * Copyright (C) ST-Ericsson SA 2010 | |
4 | * | |
62579266 RV |
5 | * Author: Srinidhi Kasagar <[email protected]> |
6 | * Author: Rabin Vincent <[email protected]> | |
adceed62 | 7 | * Author: Mattias Wallin <[email protected]> |
62579266 RV |
8 | */ |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/irq.h> | |
06e589ef | 14 | #include <linux/irqdomain.h> |
62579266 RV |
15 | #include <linux/delay.h> |
16 | #include <linux/interrupt.h> | |
31cbae22 | 17 | #include <linux/moduleparam.h> |
62579266 RV |
18 | #include <linux/platform_device.h> |
19 | #include <linux/mfd/core.h> | |
47c16975 | 20 | #include <linux/mfd/abx500.h> |
ee66e653 | 21 | #include <linux/mfd/abx500/ab8500.h> |
d28f1db8 | 22 | #include <linux/mfd/dbx500-prcmu.h> |
6bc4a568 | 23 | #include <linux/of.h> |
62579266 RV |
24 | |
25 | /* | |
26 | * Interrupt register offsets | |
27 | * Bank : 0x0E | |
28 | */ | |
47c16975 MW |
29 | #define AB8500_IT_SOURCE1_REG 0x00 |
30 | #define AB8500_IT_SOURCE2_REG 0x01 | |
31 | #define AB8500_IT_SOURCE3_REG 0x02 | |
32 | #define AB8500_IT_SOURCE4_REG 0x03 | |
33 | #define AB8500_IT_SOURCE5_REG 0x04 | |
34 | #define AB8500_IT_SOURCE6_REG 0x05 | |
35 | #define AB8500_IT_SOURCE7_REG 0x06 | |
36 | #define AB8500_IT_SOURCE8_REG 0x07 | |
d6255529 | 37 | #define AB9540_IT_SOURCE13_REG 0x0C |
47c16975 MW |
38 | #define AB8500_IT_SOURCE19_REG 0x12 |
39 | #define AB8500_IT_SOURCE20_REG 0x13 | |
40 | #define AB8500_IT_SOURCE21_REG 0x14 | |
41 | #define AB8500_IT_SOURCE22_REG 0x15 | |
42 | #define AB8500_IT_SOURCE23_REG 0x16 | |
43 | #define AB8500_IT_SOURCE24_REG 0x17 | |
62579266 RV |
44 | |
45 | /* | |
46 | * latch registers | |
47 | */ | |
47c16975 MW |
48 | #define AB8500_IT_LATCH1_REG 0x20 |
49 | #define AB8500_IT_LATCH2_REG 0x21 | |
50 | #define AB8500_IT_LATCH3_REG 0x22 | |
51 | #define AB8500_IT_LATCH4_REG 0x23 | |
52 | #define AB8500_IT_LATCH5_REG 0x24 | |
53 | #define AB8500_IT_LATCH6_REG 0x25 | |
54 | #define AB8500_IT_LATCH7_REG 0x26 | |
55 | #define AB8500_IT_LATCH8_REG 0x27 | |
56 | #define AB8500_IT_LATCH9_REG 0x28 | |
57 | #define AB8500_IT_LATCH10_REG 0x29 | |
92d50a41 | 58 | #define AB8500_IT_LATCH12_REG 0x2B |
d6255529 | 59 | #define AB9540_IT_LATCH13_REG 0x2C |
47c16975 MW |
60 | #define AB8500_IT_LATCH19_REG 0x32 |
61 | #define AB8500_IT_LATCH20_REG 0x33 | |
62 | #define AB8500_IT_LATCH21_REG 0x34 | |
63 | #define AB8500_IT_LATCH22_REG 0x35 | |
64 | #define AB8500_IT_LATCH23_REG 0x36 | |
65 | #define AB8500_IT_LATCH24_REG 0x37 | |
62579266 RV |
66 | |
67 | /* | |
68 | * mask registers | |
69 | */ | |
70 | ||
47c16975 MW |
71 | #define AB8500_IT_MASK1_REG 0x40 |
72 | #define AB8500_IT_MASK2_REG 0x41 | |
73 | #define AB8500_IT_MASK3_REG 0x42 | |
74 | #define AB8500_IT_MASK4_REG 0x43 | |
75 | #define AB8500_IT_MASK5_REG 0x44 | |
76 | #define AB8500_IT_MASK6_REG 0x45 | |
77 | #define AB8500_IT_MASK7_REG 0x46 | |
78 | #define AB8500_IT_MASK8_REG 0x47 | |
79 | #define AB8500_IT_MASK9_REG 0x48 | |
80 | #define AB8500_IT_MASK10_REG 0x49 | |
81 | #define AB8500_IT_MASK11_REG 0x4A | |
82 | #define AB8500_IT_MASK12_REG 0x4B | |
83 | #define AB8500_IT_MASK13_REG 0x4C | |
84 | #define AB8500_IT_MASK14_REG 0x4D | |
85 | #define AB8500_IT_MASK15_REG 0x4E | |
86 | #define AB8500_IT_MASK16_REG 0x4F | |
87 | #define AB8500_IT_MASK17_REG 0x50 | |
88 | #define AB8500_IT_MASK18_REG 0x51 | |
89 | #define AB8500_IT_MASK19_REG 0x52 | |
90 | #define AB8500_IT_MASK20_REG 0x53 | |
91 | #define AB8500_IT_MASK21_REG 0x54 | |
92 | #define AB8500_IT_MASK22_REG 0x55 | |
93 | #define AB8500_IT_MASK23_REG 0x56 | |
94 | #define AB8500_IT_MASK24_REG 0x57 | |
a29264b6 | 95 | #define AB8500_IT_MASK25_REG 0x58 |
47c16975 | 96 | |
7ccfe9b1 MJ |
97 | /* |
98 | * latch hierarchy registers | |
99 | */ | |
100 | #define AB8500_IT_LATCHHIER1_REG 0x60 | |
101 | #define AB8500_IT_LATCHHIER2_REG 0x61 | |
102 | #define AB8500_IT_LATCHHIER3_REG 0x62 | |
3e1a498f | 103 | #define AB8540_IT_LATCHHIER4_REG 0x63 |
7ccfe9b1 MJ |
104 | |
105 | #define AB8500_IT_LATCHHIER_NUM 3 | |
3e1a498f | 106 | #define AB8540_IT_LATCHHIER_NUM 4 |
7ccfe9b1 | 107 | |
47c16975 | 108 | #define AB8500_REV_REG 0x80 |
0f620837 | 109 | #define AB8500_IC_NAME_REG 0x82 |
e5c238c3 | 110 | #define AB8500_SWITCH_OFF_STATUS 0x00 |
62579266 | 111 | |
b4a31037 | 112 | #define AB8500_TURN_ON_STATUS 0x00 |
500e69a1 | 113 | #define AB8505_TURN_ON_STATUS_2 0x04 |
b4a31037 | 114 | |
f04a9d8a RK |
115 | #define AB8500_CH_USBCH_STAT1_REG 0x02 |
116 | #define VBUS_DET_DBNC100 0x02 | |
117 | #define VBUS_DET_DBNC1 0x01 | |
118 | ||
119 | static DEFINE_SPINLOCK(on_stat_lock); | |
120 | static u8 turn_on_stat_mask = 0xFF; | |
121 | static u8 turn_on_stat_set; | |
6ef9418c | 122 | |
d6255529 LW |
123 | #define AB9540_MODEM_CTRL2_REG 0x23 |
124 | #define AB9540_MODEM_CTRL2_SWDBBRSTN_BIT BIT(2) | |
125 | ||
62579266 RV |
126 | /* |
127 | * Map interrupt numbers to the LATCH and MASK register offsets, Interrupt | |
2ced445e LW |
128 | * numbers are indexed into this array with (num / 8). The interupts are |
129 | * defined in linux/mfd/ab8500.h | |
62579266 RV |
130 | * |
131 | * This is one off from the register names, i.e. AB8500_IT_MASK1_REG is at | |
132 | * offset 0. | |
133 | */ | |
2ced445e | 134 | /* AB8500 support */ |
62579266 | 135 | static const int ab8500_irq_regoffset[AB8500_NUM_IRQ_REGS] = { |
92d50a41 | 136 | 0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21, |
62579266 RV |
137 | }; |
138 | ||
a29264b6 | 139 | /* AB9540 / AB8505 support */ |
d6255529 | 140 | static const int ab9540_irq_regoffset[AB9540_NUM_IRQ_REGS] = { |
a29264b6 | 141 | 0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21, 12, 13, 24, 5, 22, 23 |
d6255529 LW |
142 | }; |
143 | ||
3e1a498f LJ |
144 | /* AB8540 support */ |
145 | static const int ab8540_irq_regoffset[AB8540_NUM_IRQ_REGS] = { | |
7ccf40b1 LJ |
146 | 0, 1, 2, 3, 4, -1, -1, -1, -1, 11, 18, 19, 20, 21, 12, 13, 24, 5, 22, |
147 | 23, 25, 26, 27, 28, 29, 30, 31, | |
3e1a498f LJ |
148 | }; |
149 | ||
0f620837 LW |
150 | static const char ab8500_version_str[][7] = { |
151 | [AB8500_VERSION_AB8500] = "AB8500", | |
152 | [AB8500_VERSION_AB8505] = "AB8505", | |
153 | [AB8500_VERSION_AB9540] = "AB9540", | |
154 | [AB8500_VERSION_AB8540] = "AB8540", | |
155 | }; | |
156 | ||
822672a7 | 157 | static int ab8500_prcmu_write(struct ab8500 *ab8500, u16 addr, u8 data) |
d28f1db8 LJ |
158 | { |
159 | int ret; | |
160 | ||
161 | ret = prcmu_abb_write((u8)(addr >> 8), (u8)(addr & 0xFF), &data, 1); | |
162 | if (ret < 0) | |
163 | dev_err(ab8500->dev, "prcmu i2c error %d\n", ret); | |
164 | return ret; | |
165 | } | |
166 | ||
822672a7 | 167 | static int ab8500_prcmu_write_masked(struct ab8500 *ab8500, u16 addr, u8 mask, |
d28f1db8 LJ |
168 | u8 data) |
169 | { | |
170 | int ret; | |
171 | ||
172 | ret = prcmu_abb_write_masked((u8)(addr >> 8), (u8)(addr & 0xFF), &data, | |
173 | &mask, 1); | |
174 | if (ret < 0) | |
175 | dev_err(ab8500->dev, "prcmu i2c error %d\n", ret); | |
176 | return ret; | |
177 | } | |
178 | ||
822672a7 | 179 | static int ab8500_prcmu_read(struct ab8500 *ab8500, u16 addr) |
d28f1db8 LJ |
180 | { |
181 | int ret; | |
182 | u8 data; | |
183 | ||
184 | ret = prcmu_abb_read((u8)(addr >> 8), (u8)(addr & 0xFF), &data, 1); | |
185 | if (ret < 0) { | |
186 | dev_err(ab8500->dev, "prcmu i2c error %d\n", ret); | |
187 | return ret; | |
188 | } | |
189 | return (int)data; | |
190 | } | |
191 | ||
47c16975 MW |
192 | static int ab8500_get_chip_id(struct device *dev) |
193 | { | |
6bce7bf1 MW |
194 | struct ab8500 *ab8500; |
195 | ||
196 | if (!dev) | |
197 | return -EINVAL; | |
198 | ab8500 = dev_get_drvdata(dev->parent); | |
199 | return ab8500 ? (int)ab8500->chip_id : -EINVAL; | |
47c16975 MW |
200 | } |
201 | ||
202 | static int set_register_interruptible(struct ab8500 *ab8500, u8 bank, | |
203 | u8 reg, u8 data) | |
62579266 RV |
204 | { |
205 | int ret; | |
47c16975 MW |
206 | /* |
207 | * Put the u8 bank and u8 register together into a an u16. | |
208 | * The bank on higher 8 bits and register in lower 8 bits. | |
500e69a1 | 209 | */ |
47c16975 | 210 | u16 addr = ((u16)bank) << 8 | reg; |
62579266 RV |
211 | |
212 | dev_vdbg(ab8500->dev, "wr: addr %#x <= %#x\n", addr, data); | |
213 | ||
392cbd1e | 214 | mutex_lock(&ab8500->lock); |
47c16975 | 215 | |
62579266 RV |
216 | ret = ab8500->write(ab8500, addr, data); |
217 | if (ret < 0) | |
218 | dev_err(ab8500->dev, "failed to write reg %#x: %d\n", | |
219 | addr, ret); | |
47c16975 | 220 | mutex_unlock(&ab8500->lock); |
62579266 RV |
221 | |
222 | return ret; | |
223 | } | |
224 | ||
47c16975 MW |
225 | static int ab8500_set_register(struct device *dev, u8 bank, |
226 | u8 reg, u8 value) | |
62579266 | 227 | { |
112a80d2 | 228 | int ret; |
47c16975 | 229 | struct ab8500 *ab8500 = dev_get_drvdata(dev->parent); |
62579266 | 230 | |
112a80d2 JA |
231 | atomic_inc(&ab8500->transfer_ongoing); |
232 | ret = set_register_interruptible(ab8500, bank, reg, value); | |
233 | atomic_dec(&ab8500->transfer_ongoing); | |
234 | return ret; | |
62579266 | 235 | } |
62579266 | 236 | |
47c16975 MW |
237 | static int get_register_interruptible(struct ab8500 *ab8500, u8 bank, |
238 | u8 reg, u8 *value) | |
62579266 RV |
239 | { |
240 | int ret; | |
47c16975 MW |
241 | u16 addr = ((u16)bank) << 8 | reg; |
242 | ||
392cbd1e | 243 | mutex_lock(&ab8500->lock); |
62579266 RV |
244 | |
245 | ret = ab8500->read(ab8500, addr); | |
246 | if (ret < 0) | |
247 | dev_err(ab8500->dev, "failed to read reg %#x: %d\n", | |
248 | addr, ret); | |
47c16975 MW |
249 | else |
250 | *value = ret; | |
62579266 | 251 | |
47c16975 | 252 | mutex_unlock(&ab8500->lock); |
62579266 RV |
253 | dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret); |
254 | ||
10628e3e | 255 | return (ret < 0) ? ret : 0; |
62579266 RV |
256 | } |
257 | ||
47c16975 MW |
258 | static int ab8500_get_register(struct device *dev, u8 bank, |
259 | u8 reg, u8 *value) | |
62579266 | 260 | { |
112a80d2 | 261 | int ret; |
47c16975 | 262 | struct ab8500 *ab8500 = dev_get_drvdata(dev->parent); |
62579266 | 263 | |
112a80d2 JA |
264 | atomic_inc(&ab8500->transfer_ongoing); |
265 | ret = get_register_interruptible(ab8500, bank, reg, value); | |
266 | atomic_dec(&ab8500->transfer_ongoing); | |
267 | return ret; | |
62579266 | 268 | } |
47c16975 MW |
269 | |
270 | static int mask_and_set_register_interruptible(struct ab8500 *ab8500, u8 bank, | |
271 | u8 reg, u8 bitmask, u8 bitvalues) | |
62579266 RV |
272 | { |
273 | int ret; | |
47c16975 | 274 | u16 addr = ((u16)bank) << 8 | reg; |
62579266 | 275 | |
392cbd1e | 276 | mutex_lock(&ab8500->lock); |
62579266 | 277 | |
bc628fd1 MN |
278 | if (ab8500->write_masked == NULL) { |
279 | u8 data; | |
62579266 | 280 | |
bc628fd1 MN |
281 | ret = ab8500->read(ab8500, addr); |
282 | if (ret < 0) { | |
283 | dev_err(ab8500->dev, "failed to read reg %#x: %d\n", | |
284 | addr, ret); | |
285 | goto out; | |
286 | } | |
62579266 | 287 | |
bc628fd1 MN |
288 | data = (u8)ret; |
289 | data = (~bitmask & data) | (bitmask & bitvalues); | |
290 | ||
291 | ret = ab8500->write(ab8500, addr, data); | |
292 | if (ret < 0) | |
293 | dev_err(ab8500->dev, "failed to write reg %#x: %d\n", | |
294 | addr, ret); | |
62579266 | 295 | |
bc628fd1 MN |
296 | dev_vdbg(ab8500->dev, "mask: addr %#x => data %#x\n", addr, |
297 | data); | |
298 | goto out; | |
299 | } | |
300 | ret = ab8500->write_masked(ab8500, addr, bitmask, bitvalues); | |
301 | if (ret < 0) | |
302 | dev_err(ab8500->dev, "failed to modify reg %#x: %d\n", addr, | |
303 | ret); | |
62579266 RV |
304 | out: |
305 | mutex_unlock(&ab8500->lock); | |
306 | return ret; | |
307 | } | |
47c16975 MW |
308 | |
309 | static int ab8500_mask_and_set_register(struct device *dev, | |
310 | u8 bank, u8 reg, u8 bitmask, u8 bitvalues) | |
311 | { | |
112a80d2 | 312 | int ret; |
47c16975 MW |
313 | struct ab8500 *ab8500 = dev_get_drvdata(dev->parent); |
314 | ||
112a80d2 | 315 | atomic_inc(&ab8500->transfer_ongoing); |
7ccf40b1 | 316 | ret = mask_and_set_register_interruptible(ab8500, bank, reg, |
112a80d2 JA |
317 | bitmask, bitvalues); |
318 | atomic_dec(&ab8500->transfer_ongoing); | |
319 | return ret; | |
47c16975 MW |
320 | } |
321 | ||
322 | static struct abx500_ops ab8500_ops = { | |
323 | .get_chip_id = ab8500_get_chip_id, | |
324 | .get_register = ab8500_get_register, | |
325 | .set_register = ab8500_set_register, | |
326 | .get_register_page = NULL, | |
327 | .set_register_page = NULL, | |
328 | .mask_and_set_register = ab8500_mask_and_set_register, | |
329 | .event_registers_startup_state_get = NULL, | |
330 | .startup_irq_enabled = NULL, | |
1d843a6c | 331 | .dump_all_banks = ab8500_dump_all_banks, |
47c16975 | 332 | }; |
62579266 | 333 | |
9505a0a0 | 334 | static void ab8500_irq_lock(struct irq_data *data) |
62579266 | 335 | { |
9505a0a0 | 336 | struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data); |
62579266 RV |
337 | |
338 | mutex_lock(&ab8500->irq_lock); | |
112a80d2 | 339 | atomic_inc(&ab8500->transfer_ongoing); |
62579266 RV |
340 | } |
341 | ||
9505a0a0 | 342 | static void ab8500_irq_sync_unlock(struct irq_data *data) |
62579266 | 343 | { |
9505a0a0 | 344 | struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data); |
62579266 RV |
345 | int i; |
346 | ||
2ced445e | 347 | for (i = 0; i < ab8500->mask_size; i++) { |
62579266 RV |
348 | u8 old = ab8500->oldmask[i]; |
349 | u8 new = ab8500->mask[i]; | |
350 | int reg; | |
351 | ||
352 | if (new == old) | |
353 | continue; | |
354 | ||
0f620837 LW |
355 | /* |
356 | * Interrupt register 12 doesn't exist prior to AB8500 version | |
357 | * 2.0 | |
358 | */ | |
359 | if (ab8500->irq_reg_offset[i] == 11 && | |
360 | is_ab8500_1p1_or_earlier(ab8500)) | |
92d50a41 MW |
361 | continue; |
362 | ||
3e1a498f LJ |
363 | if (ab8500->irq_reg_offset[i] < 0) |
364 | continue; | |
365 | ||
62579266 RV |
366 | ab8500->oldmask[i] = new; |
367 | ||
2ced445e | 368 | reg = AB8500_IT_MASK1_REG + ab8500->irq_reg_offset[i]; |
47c16975 | 369 | set_register_interruptible(ab8500, AB8500_INTERRUPT, reg, new); |
62579266 | 370 | } |
112a80d2 | 371 | atomic_dec(&ab8500->transfer_ongoing); |
62579266 RV |
372 | mutex_unlock(&ab8500->irq_lock); |
373 | } | |
374 | ||
9505a0a0 | 375 | static void ab8500_irq_mask(struct irq_data *data) |
62579266 | 376 | { |
9505a0a0 | 377 | struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data); |
06e589ef | 378 | int offset = data->hwirq; |
62579266 RV |
379 | int index = offset / 8; |
380 | int mask = 1 << (offset % 8); | |
381 | ||
382 | ab8500->mask[index] |= mask; | |
9c677b9b LJ |
383 | |
384 | /* The AB8500 GPIOs have two interrupts each (rising & falling). */ | |
385 | if (offset >= AB8500_INT_GPIO6R && offset <= AB8500_INT_GPIO41R) | |
386 | ab8500->mask[index + 2] |= mask; | |
387 | if (offset >= AB9540_INT_GPIO50R && offset <= AB9540_INT_GPIO54R) | |
388 | ab8500->mask[index + 1] |= mask; | |
389 | if (offset == AB8540_INT_GPIO43R || offset == AB8540_INT_GPIO44R) | |
e2ddf46a LW |
390 | /* Here the falling IRQ is one bit lower */ |
391 | ab8500->mask[index] |= (mask << 1); | |
62579266 RV |
392 | } |
393 | ||
9505a0a0 | 394 | static void ab8500_irq_unmask(struct irq_data *data) |
62579266 | 395 | { |
9505a0a0 | 396 | struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data); |
9c677b9b | 397 | unsigned int type = irqd_get_trigger_type(data); |
06e589ef | 398 | int offset = data->hwirq; |
62579266 RV |
399 | int index = offset / 8; |
400 | int mask = 1 << (offset % 8); | |
401 | ||
9c677b9b LJ |
402 | if (type & IRQ_TYPE_EDGE_RISING) |
403 | ab8500->mask[index] &= ~mask; | |
404 | ||
405 | /* The AB8500 GPIOs have two interrupts each (rising & falling). */ | |
406 | if (type & IRQ_TYPE_EDGE_FALLING) { | |
407 | if (offset >= AB8500_INT_GPIO6R && offset <= AB8500_INT_GPIO41R) | |
408 | ab8500->mask[index + 2] &= ~mask; | |
7ccf40b1 LJ |
409 | else if (offset >= AB9540_INT_GPIO50R && |
410 | offset <= AB9540_INT_GPIO54R) | |
9c677b9b | 411 | ab8500->mask[index + 1] &= ~mask; |
7ccf40b1 LJ |
412 | else if (offset == AB8540_INT_GPIO43R || |
413 | offset == AB8540_INT_GPIO44R) | |
e2ddf46a LW |
414 | /* Here the falling IRQ is one bit lower */ |
415 | ab8500->mask[index] &= ~(mask << 1); | |
9c677b9b LJ |
416 | else |
417 | ab8500->mask[index] &= ~mask; | |
e2ddf46a | 418 | } else { |
9c677b9b LJ |
419 | /* Satisfies the case where type is not set. */ |
420 | ab8500->mask[index] &= ~mask; | |
e2ddf46a | 421 | } |
62579266 RV |
422 | } |
423 | ||
40f6e5a2 LJ |
424 | static int ab8500_irq_set_type(struct irq_data *data, unsigned int type) |
425 | { | |
426 | return 0; | |
62579266 RV |
427 | } |
428 | ||
429 | static struct irq_chip ab8500_irq_chip = { | |
430 | .name = "ab8500", | |
9505a0a0 MB |
431 | .irq_bus_lock = ab8500_irq_lock, |
432 | .irq_bus_sync_unlock = ab8500_irq_sync_unlock, | |
433 | .irq_mask = ab8500_irq_mask, | |
e6f9306e | 434 | .irq_disable = ab8500_irq_mask, |
9505a0a0 | 435 | .irq_unmask = ab8500_irq_unmask, |
40f6e5a2 | 436 | .irq_set_type = ab8500_irq_set_type, |
62579266 RV |
437 | }; |
438 | ||
3e1a498f LJ |
439 | static void update_latch_offset(u8 *offset, int i) |
440 | { | |
441 | /* Fix inconsistent ITFromLatch25 bit mapping... */ | |
442 | if (unlikely(*offset == 17)) | |
500e69a1 | 443 | *offset = 24; |
3e1a498f LJ |
444 | /* Fix inconsistent ab8540 bit mapping... */ |
445 | if (unlikely(*offset == 16)) | |
500e69a1 | 446 | *offset = 25; |
7ccf40b1 | 447 | if ((i == 3) && (*offset >= 24)) |
500e69a1 | 448 | *offset += 2; |
3e1a498f LJ |
449 | } |
450 | ||
7ccfe9b1 MJ |
451 | static int ab8500_handle_hierarchical_line(struct ab8500 *ab8500, |
452 | int latch_offset, u8 latch_val) | |
453 | { | |
7a93fb37 | 454 | int int_bit, line, i; |
7ccfe9b1 | 455 | |
7a93fb37 FB |
456 | for (i = 0; i < ab8500->mask_size; i++) |
457 | if (ab8500->irq_reg_offset[i] == latch_offset) | |
458 | break; | |
7ccfe9b1 | 459 | |
7a93fb37 FB |
460 | if (i >= ab8500->mask_size) { |
461 | dev_err(ab8500->dev, "Register offset 0x%2x not declared\n", | |
462 | latch_offset); | |
463 | return -ENXIO; | |
464 | } | |
7ccfe9b1 | 465 | |
7a93fb37 FB |
466 | /* ignore masked out interrupts */ |
467 | latch_val &= ~ab8500->mask[i]; | |
7ccfe9b1 | 468 | |
7a93fb37 FB |
469 | while (latch_val) { |
470 | int_bit = __ffs(latch_val); | |
7ccfe9b1 MJ |
471 | line = (i << 3) + int_bit; |
472 | latch_val &= ~(1 << int_bit); | |
473 | ||
e2ddf46a LW |
474 | /* |
475 | * This handles the falling edge hwirqs from the GPIO | |
476 | * lines. Route them back to the line registered for the | |
477 | * rising IRQ, as this is merely a flag for the same IRQ | |
478 | * in linux terms. | |
479 | */ | |
480 | if (line >= AB8500_INT_GPIO6F && line <= AB8500_INT_GPIO41F) | |
481 | line -= 16; | |
482 | if (line >= AB9540_INT_GPIO50F && line <= AB9540_INT_GPIO54F) | |
483 | line -= 8; | |
484 | if (line == AB8540_INT_GPIO43F || line == AB8540_INT_GPIO44F) | |
485 | line += 1; | |
486 | ||
9ff80e2d | 487 | handle_nested_irq(irq_find_mapping(ab8500->domain, line)); |
7a93fb37 | 488 | } |
7ccfe9b1 MJ |
489 | |
490 | return 0; | |
491 | } | |
492 | ||
493 | static int ab8500_handle_hierarchical_latch(struct ab8500 *ab8500, | |
494 | int hier_offset, u8 hier_val) | |
495 | { | |
496 | int latch_bit, status; | |
497 | u8 latch_offset, latch_val; | |
498 | ||
499 | do { | |
500 | latch_bit = __ffs(hier_val); | |
501 | latch_offset = (hier_offset << 3) + latch_bit; | |
502 | ||
3e1a498f | 503 | update_latch_offset(&latch_offset, hier_offset); |
7ccfe9b1 MJ |
504 | |
505 | status = get_register_interruptible(ab8500, | |
506 | AB8500_INTERRUPT, | |
507 | AB8500_IT_LATCH1_REG + latch_offset, | |
508 | &latch_val); | |
509 | if (status < 0 || latch_val == 0) | |
510 | goto discard; | |
511 | ||
512 | status = ab8500_handle_hierarchical_line(ab8500, | |
513 | latch_offset, latch_val); | |
514 | if (status < 0) | |
515 | return status; | |
516 | discard: | |
517 | hier_val &= ~(1 << latch_bit); | |
518 | } while (hier_val); | |
519 | ||
520 | return 0; | |
521 | } | |
522 | ||
523 | static irqreturn_t ab8500_hierarchical_irq(int irq, void *dev) | |
524 | { | |
525 | struct ab8500 *ab8500 = dev; | |
526 | u8 i; | |
527 | ||
528 | dev_vdbg(ab8500->dev, "interrupt\n"); | |
529 | ||
530 | /* Hierarchical interrupt version */ | |
3e1a498f | 531 | for (i = 0; i < (ab8500->it_latchhier_num); i++) { |
7ccfe9b1 MJ |
532 | int status; |
533 | u8 hier_val; | |
534 | ||
535 | status = get_register_interruptible(ab8500, AB8500_INTERRUPT, | |
536 | AB8500_IT_LATCHHIER1_REG + i, &hier_val); | |
537 | if (status < 0 || hier_val == 0) | |
538 | continue; | |
539 | ||
540 | status = ab8500_handle_hierarchical_latch(ab8500, i, hier_val); | |
541 | if (status < 0) | |
542 | break; | |
543 | } | |
544 | return IRQ_HANDLED; | |
545 | } | |
546 | ||
06e589ef LJ |
547 | static int ab8500_irq_map(struct irq_domain *d, unsigned int virq, |
548 | irq_hw_number_t hwirq) | |
549 | { | |
550 | struct ab8500 *ab8500 = d->host_data; | |
551 | ||
552 | if (!ab8500) | |
553 | return -EINVAL; | |
554 | ||
555 | irq_set_chip_data(virq, ab8500); | |
556 | irq_set_chip_and_handler(virq, &ab8500_irq_chip, | |
557 | handle_simple_irq); | |
558 | irq_set_nested_thread(virq, 1); | |
06e589ef | 559 | irq_set_noprobe(virq); |
62579266 RV |
560 | |
561 | return 0; | |
562 | } | |
563 | ||
7ce7b26f | 564 | static const struct irq_domain_ops ab8500_irq_ops = { |
7ccf40b1 LJ |
565 | .map = ab8500_irq_map, |
566 | .xlate = irq_domain_xlate_twocell, | |
06e589ef LJ |
567 | }; |
568 | ||
569 | static int ab8500_irq_init(struct ab8500 *ab8500, struct device_node *np) | |
62579266 | 570 | { |
2ced445e LW |
571 | int num_irqs; |
572 | ||
3e1a498f LJ |
573 | if (is_ab8540(ab8500)) |
574 | num_irqs = AB8540_NR_IRQS; | |
575 | else if (is_ab9540(ab8500)) | |
d6255529 | 576 | num_irqs = AB9540_NR_IRQS; |
a982362c BJ |
577 | else if (is_ab8505(ab8500)) |
578 | num_irqs = AB8505_NR_IRQS; | |
d6255529 LW |
579 | else |
580 | num_irqs = AB8500_NR_IRQS; | |
62579266 | 581 | |
f1d11f39 | 582 | /* If ->irq_base is zero this will give a linear mapping */ |
7602e05d | 583 | ab8500->domain = irq_domain_add_simple(ab8500->dev->of_node, |
500e69a1 LJ |
584 | num_irqs, 0, |
585 | &ab8500_irq_ops, ab8500); | |
06e589ef LJ |
586 | |
587 | if (!ab8500->domain) { | |
588 | dev_err(ab8500->dev, "Failed to create irqdomain\n"); | |
500e69a1 | 589 | return -ENODEV; |
06e589ef LJ |
590 | } |
591 | ||
592 | return 0; | |
62579266 RV |
593 | } |
594 | ||
112a80d2 JA |
595 | int ab8500_suspend(struct ab8500 *ab8500) |
596 | { | |
597 | if (atomic_read(&ab8500->transfer_ongoing)) | |
598 | return -EINVAL; | |
f3556302 LJ |
599 | |
600 | return 0; | |
112a80d2 JA |
601 | } |
602 | ||
5ac98553 | 603 | static const struct mfd_cell ab8500_bm_devs[] = { |
417c0fc2 LW |
604 | MFD_CELL_OF("ab8500-charger", NULL, NULL, 0, 0, |
605 | "stericsson,ab8500-charger"), | |
606 | MFD_CELL_OF("ab8500-btemp", NULL, NULL, 0, 0, | |
607 | "stericsson,ab8500-btemp"), | |
608 | MFD_CELL_OF("ab8500-fg", NULL, NULL, 0, 0, | |
609 | "stericsson,ab8500-fg"), | |
610 | MFD_CELL_OF("ab8500-chargalg", NULL, NULL, 0, 0, | |
611 | "stericsson,ab8500-chargalg"), | |
4b106fb9 LJ |
612 | }; |
613 | ||
5ac98553 | 614 | static const struct mfd_cell ab8500_devs[] = { |
db783e76 | 615 | MFD_CELL_OF("ab8500-sysctrl", |
f4d41ad8 | 616 | NULL, NULL, 0, 0, "stericsson,ab8500-sysctrl"), |
db783e76 | 617 | MFD_CELL_OF("ab8500-ext-regulator", |
f4d41ad8 | 618 | NULL, NULL, 0, 0, "stericsson,ab8500-ext-regulator"), |
db783e76 | 619 | MFD_CELL_OF("ab8500-regulator", |
f4d41ad8 | 620 | NULL, NULL, 0, 0, "stericsson,ab8500-regulator"), |
db783e76 | 621 | MFD_CELL_OF("ab8500-clk", |
702204c2 | 622 | NULL, NULL, 0, 0, "stericsson,ab8500-clk"), |
db783e76 | 623 | MFD_CELL_OF("ab8500-gpadc", |
f4d41ad8 | 624 | NULL, NULL, 0, 0, "stericsson,ab8500-gpadc"), |
db783e76 | 625 | MFD_CELL_OF("ab8500-rtc", |
f4d41ad8 | 626 | NULL, NULL, 0, 0, "stericsson,ab8500-rtc"), |
db783e76 | 627 | MFD_CELL_OF("ab8500-acc-det", |
f4d41ad8 | 628 | NULL, NULL, 0, 0, "stericsson,ab8500-acc-det"), |
db783e76 | 629 | MFD_CELL_OF("ab8500-poweron-key", |
f4d41ad8 | 630 | NULL, NULL, 0, 0, "stericsson,ab8500-poweron-key"), |
db783e76 | 631 | MFD_CELL_OF("ab8500-pwm", |
f4d41ad8 | 632 | NULL, NULL, 0, 1, "stericsson,ab8500-pwm"), |
db783e76 | 633 | MFD_CELL_OF("ab8500-pwm", |
f4d41ad8 | 634 | NULL, NULL, 0, 2, "stericsson,ab8500-pwm"), |
db783e76 | 635 | MFD_CELL_OF("ab8500-pwm", |
f4d41ad8 | 636 | NULL, NULL, 0, 3, "stericsson,ab8500-pwm"), |
db783e76 | 637 | MFD_CELL_OF("ab8500-denc", |
f4d41ad8 | 638 | NULL, NULL, 0, 0, "stericsson,ab8500-denc"), |
db783e76 | 639 | MFD_CELL_OF("pinctrl-ab8500", |
f4d41ad8 | 640 | NULL, NULL, 0, 0, "stericsson,ab8500-gpio"), |
db783e76 | 641 | MFD_CELL_OF("abx500-temp", |
f4d41ad8 | 642 | NULL, NULL, 0, 0, "stericsson,abx500-temp"), |
db783e76 | 643 | MFD_CELL_OF("ab8500-usb", |
f4d41ad8 | 644 | NULL, NULL, 0, 0, "stericsson,ab8500-usb"), |
db783e76 | 645 | MFD_CELL_OF("ab8500-codec", |
f4d41ad8 | 646 | NULL, NULL, 0, 0, "stericsson,ab8500-codec"), |
6ef9418c RA |
647 | }; |
648 | ||
5ac98553 | 649 | static const struct mfd_cell ab9540_devs[] = { |
d6255529 | 650 | { |
4b106fb9 | 651 | .name = "ab8500-sysctrl", |
d6255529 | 652 | }, |
53f325be LJ |
653 | { |
654 | .name = "ab8500-ext-regulator", | |
655 | }, | |
44f72e53 | 656 | { |
4b106fb9 | 657 | .name = "ab8500-regulator", |
44f72e53 | 658 | }, |
9ee17676 UH |
659 | { |
660 | .name = "abx500-clk", | |
661 | .of_compatible = "stericsson,abx500-clk", | |
662 | }, | |
c0eda9ae LJ |
663 | { |
664 | .name = "ab8500-gpadc", | |
665 | .of_compatible = "stericsson,ab8500-gpadc", | |
c0eda9ae | 666 | }, |
4b106fb9 LJ |
667 | { |
668 | .name = "ab8500-rtc", | |
4b106fb9 LJ |
669 | }, |
670 | { | |
671 | .name = "ab8500-acc-det", | |
4b106fb9 LJ |
672 | }, |
673 | { | |
674 | .name = "ab8500-poweron-key", | |
4b106fb9 LJ |
675 | }, |
676 | { | |
677 | .name = "ab8500-pwm", | |
678 | .id = 1, | |
679 | }, | |
4b106fb9 LJ |
680 | { |
681 | .name = "abx500-temp", | |
4b106fb9 | 682 | }, |
d6255529 | 683 | { |
e64d905e LJ |
684 | .name = "pinctrl-ab9540", |
685 | .of_compatible = "stericsson,ab9540-gpio", | |
d6255529 LW |
686 | }, |
687 | { | |
688 | .name = "ab9540-usb", | |
d6255529 | 689 | }, |
44f72e53 VS |
690 | { |
691 | .name = "ab9540-codec", | |
692 | }, | |
c0eda9ae LJ |
693 | { |
694 | .name = "ab-iddet", | |
c0eda9ae | 695 | }, |
44f72e53 VS |
696 | }; |
697 | ||
c0eda9ae | 698 | /* Device list for ab8505 */ |
5ac98553 | 699 | static const struct mfd_cell ab8505_devs[] = { |
4b106fb9 LJ |
700 | { |
701 | .name = "ab8500-sysctrl", | |
1c0769d2 | 702 | .of_compatible = "stericsson,ab8500-sysctrl", |
4b106fb9 LJ |
703 | }, |
704 | { | |
705 | .name = "ab8500-regulator", | |
1c0769d2 | 706 | .of_compatible = "stericsson,ab8505-regulator", |
4b106fb9 | 707 | }, |
9ee17676 UH |
708 | { |
709 | .name = "abx500-clk", | |
1c0769d2 | 710 | .of_compatible = "stericsson,ab8500-clk", |
9ee17676 | 711 | }, |
4b106fb9 LJ |
712 | { |
713 | .name = "ab8500-gpadc", | |
955de2ea | 714 | .of_compatible = "stericsson,ab8500-gpadc", |
4b106fb9 LJ |
715 | }, |
716 | { | |
717 | .name = "ab8500-rtc", | |
1c0769d2 | 718 | .of_compatible = "stericsson,ab8500-rtc", |
4b106fb9 LJ |
719 | }, |
720 | { | |
721 | .name = "ab8500-acc-det", | |
1c0769d2 | 722 | .of_compatible = "stericsson,ab8500-acc-det", |
4b106fb9 LJ |
723 | }, |
724 | { | |
725 | .name = "ab8500-poweron-key", | |
1c0769d2 | 726 | .of_compatible = "stericsson,ab8500-poweron-key", |
4b106fb9 LJ |
727 | }, |
728 | { | |
729 | .name = "ab8500-pwm", | |
1c0769d2 | 730 | .of_compatible = "stericsson,ab8500-pwm", |
4b106fb9 LJ |
731 | .id = 1, |
732 | }, | |
4b106fb9 | 733 | { |
eb696c31 | 734 | .name = "pinctrl-ab8505", |
1c0769d2 | 735 | .of_compatible = "stericsson,ab8505-gpio", |
4b106fb9 LJ |
736 | }, |
737 | { | |
738 | .name = "ab8500-usb", | |
1c0769d2 | 739 | .of_compatible = "stericsson,ab8500-usb", |
4b106fb9 LJ |
740 | }, |
741 | { | |
742 | .name = "ab8500-codec", | |
1c0769d2 | 743 | .of_compatible = "stericsson,ab8500-codec", |
4b106fb9 | 744 | }, |
c0eda9ae LJ |
745 | { |
746 | .name = "ab-iddet", | |
c0eda9ae LJ |
747 | }, |
748 | }; | |
749 | ||
5ac98553 | 750 | static const struct mfd_cell ab8540_devs[] = { |
4b106fb9 LJ |
751 | { |
752 | .name = "ab8500-sysctrl", | |
753 | }, | |
53f325be LJ |
754 | { |
755 | .name = "ab8500-ext-regulator", | |
756 | }, | |
4b106fb9 LJ |
757 | { |
758 | .name = "ab8500-regulator", | |
759 | }, | |
9ee17676 UH |
760 | { |
761 | .name = "abx500-clk", | |
762 | .of_compatible = "stericsson,abx500-clk", | |
763 | }, | |
4b106fb9 LJ |
764 | { |
765 | .name = "ab8500-gpadc", | |
955de2ea | 766 | .of_compatible = "stericsson,ab8500-gpadc", |
4b106fb9 | 767 | }, |
4b106fb9 LJ |
768 | { |
769 | .name = "ab8500-acc-det", | |
4b106fb9 LJ |
770 | }, |
771 | { | |
772 | .name = "ab8500-poweron-key", | |
4b106fb9 LJ |
773 | }, |
774 | { | |
775 | .name = "ab8500-pwm", | |
776 | .id = 1, | |
777 | }, | |
4b106fb9 LJ |
778 | { |
779 | .name = "abx500-temp", | |
4b106fb9 | 780 | }, |
c0eda9ae | 781 | { |
eb696c31 | 782 | .name = "pinctrl-ab8540", |
c0eda9ae LJ |
783 | }, |
784 | { | |
785 | .name = "ab8540-usb", | |
c0eda9ae LJ |
786 | }, |
787 | { | |
788 | .name = "ab8540-codec", | |
789 | }, | |
44f72e53 VS |
790 | { |
791 | .name = "ab-iddet", | |
44f72e53 | 792 | }, |
d6255529 LW |
793 | }; |
794 | ||
5ac98553 | 795 | static const struct mfd_cell ab8540_cut1_devs[] = { |
9c717cf3 AT |
796 | { |
797 | .name = "ab8500-rtc", | |
798 | .of_compatible = "stericsson,ab8500-rtc", | |
9c717cf3 AT |
799 | }, |
800 | }; | |
801 | ||
5ac98553 | 802 | static const struct mfd_cell ab8540_cut2_devs[] = { |
9c717cf3 AT |
803 | { |
804 | .name = "ab8540-rtc", | |
805 | .of_compatible = "stericsson,ab8540-rtc", | |
9c717cf3 AT |
806 | }, |
807 | }; | |
808 | ||
afb349c0 ZL |
809 | static ssize_t chip_id_show(struct device *dev, |
810 | struct device_attribute *attr, char *buf) | |
cca69b67 MW |
811 | { |
812 | struct ab8500 *ab8500; | |
813 | ||
814 | ab8500 = dev_get_drvdata(dev); | |
e436ddff | 815 | |
cca69b67 MW |
816 | return sprintf(buf, "%#x\n", ab8500 ? ab8500->chip_id : -EINVAL); |
817 | } | |
818 | ||
e5c238c3 MW |
819 | /* |
820 | * ab8500 has switched off due to (SWITCH_OFF_STATUS): | |
821 | * 0x01 Swoff bit programming | |
822 | * 0x02 Thermal protection activation | |
823 | * 0x04 Vbat lower then BattOk falling threshold | |
824 | * 0x08 Watchdog expired | |
825 | * 0x10 Non presence of 32kHz clock | |
826 | * 0x20 Battery level lower than power on reset threshold | |
827 | * 0x40 Power on key 1 pressed longer than 10 seconds | |
828 | * 0x80 DB8500 thermal shutdown | |
829 | */ | |
afb349c0 ZL |
830 | static ssize_t switch_off_status_show(struct device *dev, |
831 | struct device_attribute *attr, char *buf) | |
e5c238c3 MW |
832 | { |
833 | int ret; | |
834 | u8 value; | |
835 | struct ab8500 *ab8500; | |
836 | ||
837 | ab8500 = dev_get_drvdata(dev); | |
838 | ret = get_register_interruptible(ab8500, AB8500_RTC, | |
839 | AB8500_SWITCH_OFF_STATUS, &value); | |
840 | if (ret < 0) | |
841 | return ret; | |
842 | return sprintf(buf, "%#x\n", value); | |
843 | } | |
844 | ||
f04a9d8a RK |
845 | /* use mask and set to override the register turn_on_stat value */ |
846 | void ab8500_override_turn_on_stat(u8 mask, u8 set) | |
847 | { | |
848 | spin_lock(&on_stat_lock); | |
849 | turn_on_stat_mask = mask; | |
850 | turn_on_stat_set = set; | |
851 | spin_unlock(&on_stat_lock); | |
852 | } | |
853 | ||
b4a31037 AL |
854 | /* |
855 | * ab8500 has turned on due to (TURN_ON_STATUS): | |
856 | * 0x01 PORnVbat | |
857 | * 0x02 PonKey1dbF | |
858 | * 0x04 PonKey2dbF | |
859 | * 0x08 RTCAlarm | |
860 | * 0x10 MainChDet | |
861 | * 0x20 VbusDet | |
862 | * 0x40 UsbIDDetect | |
863 | * 0x80 Reserved | |
864 | */ | |
afb349c0 ZL |
865 | static ssize_t turn_on_status_show(struct device *dev, |
866 | struct device_attribute *attr, char *buf) | |
b4a31037 AL |
867 | { |
868 | int ret; | |
869 | u8 value; | |
870 | struct ab8500 *ab8500; | |
871 | ||
872 | ab8500 = dev_get_drvdata(dev); | |
873 | ret = get_register_interruptible(ab8500, AB8500_SYS_CTRL1_BLOCK, | |
874 | AB8500_TURN_ON_STATUS, &value); | |
875 | if (ret < 0) | |
876 | return ret; | |
f04a9d8a RK |
877 | |
878 | /* | |
879 | * In L9540, turn_on_status register is not updated correctly if | |
880 | * the device is rebooted with AC/USB charger connected. Due to | |
881 | * this, the device boots android instead of entering into charge | |
882 | * only mode. Read the AC/USB status register to detect the charger | |
883 | * presence and update the turn on status manually. | |
884 | */ | |
885 | if (is_ab9540(ab8500)) { | |
886 | spin_lock(&on_stat_lock); | |
887 | value = (value & turn_on_stat_mask) | turn_on_stat_set; | |
888 | spin_unlock(&on_stat_lock); | |
889 | } | |
890 | ||
b4a31037 AL |
891 | return sprintf(buf, "%#x\n", value); |
892 | } | |
893 | ||
afb349c0 ZL |
894 | static ssize_t turn_on_status_2_show(struct device *dev, |
895 | struct device_attribute *attr, char *buf) | |
93ff722e LJ |
896 | { |
897 | int ret; | |
898 | u8 value; | |
899 | struct ab8500 *ab8500; | |
900 | ||
901 | ab8500 = dev_get_drvdata(dev); | |
902 | ret = get_register_interruptible(ab8500, AB8500_SYS_CTRL1_BLOCK, | |
903 | AB8505_TURN_ON_STATUS_2, &value); | |
904 | if (ret < 0) | |
905 | return ret; | |
906 | return sprintf(buf, "%#x\n", (value & 0x1)); | |
907 | } | |
908 | ||
afb349c0 ZL |
909 | static ssize_t dbbrstn_show(struct device *dev, |
910 | struct device_attribute *attr, char *buf) | |
d6255529 LW |
911 | { |
912 | struct ab8500 *ab8500; | |
913 | int ret; | |
914 | u8 value; | |
915 | ||
916 | ab8500 = dev_get_drvdata(dev); | |
917 | ||
918 | ret = get_register_interruptible(ab8500, AB8500_REGU_CTRL2, | |
919 | AB9540_MODEM_CTRL2_REG, &value); | |
920 | if (ret < 0) | |
921 | return ret; | |
922 | ||
923 | return sprintf(buf, "%d\n", | |
924 | (value & AB9540_MODEM_CTRL2_SWDBBRSTN_BIT) ? 1 : 0); | |
925 | } | |
926 | ||
afb349c0 | 927 | static ssize_t dbbrstn_store(struct device *dev, |
d6255529 LW |
928 | struct device_attribute *attr, const char *buf, size_t count) |
929 | { | |
930 | struct ab8500 *ab8500; | |
931 | int ret = count; | |
932 | int err; | |
933 | u8 bitvalues; | |
934 | ||
935 | ab8500 = dev_get_drvdata(dev); | |
936 | ||
937 | if (count > 0) { | |
938 | switch (buf[0]) { | |
939 | case '0': | |
940 | bitvalues = 0; | |
941 | break; | |
942 | case '1': | |
943 | bitvalues = AB9540_MODEM_CTRL2_SWDBBRSTN_BIT; | |
944 | break; | |
945 | default: | |
946 | goto exit; | |
947 | } | |
948 | ||
949 | err = mask_and_set_register_interruptible(ab8500, | |
950 | AB8500_REGU_CTRL2, AB9540_MODEM_CTRL2_REG, | |
951 | AB9540_MODEM_CTRL2_SWDBBRSTN_BIT, bitvalues); | |
952 | if (err) | |
953 | dev_info(ab8500->dev, | |
954 | "Failed to set DBBRSTN %c, err %#x\n", | |
955 | buf[0], err); | |
956 | } | |
957 | ||
958 | exit: | |
959 | return ret; | |
960 | } | |
961 | ||
afb349c0 ZL |
962 | static DEVICE_ATTR_RO(chip_id); |
963 | static DEVICE_ATTR_RO(switch_off_status); | |
964 | static DEVICE_ATTR_RO(turn_on_status); | |
965 | static DEVICE_ATTR_RO(turn_on_status_2); | |
966 | static DEVICE_ATTR_RW(dbbrstn); | |
cca69b67 MW |
967 | |
968 | static struct attribute *ab8500_sysfs_entries[] = { | |
969 | &dev_attr_chip_id.attr, | |
e5c238c3 | 970 | &dev_attr_switch_off_status.attr, |
b4a31037 | 971 | &dev_attr_turn_on_status.attr, |
cca69b67 MW |
972 | NULL, |
973 | }; | |
974 | ||
93ff722e LJ |
975 | static struct attribute *ab8505_sysfs_entries[] = { |
976 | &dev_attr_turn_on_status_2.attr, | |
977 | NULL, | |
978 | }; | |
979 | ||
d6255529 LW |
980 | static struct attribute *ab9540_sysfs_entries[] = { |
981 | &dev_attr_chip_id.attr, | |
982 | &dev_attr_switch_off_status.attr, | |
983 | &dev_attr_turn_on_status.attr, | |
984 | &dev_attr_dbbrstn.attr, | |
985 | NULL, | |
986 | }; | |
987 | ||
52557dc6 | 988 | static const struct attribute_group ab8500_attr_group = { |
cca69b67 MW |
989 | .attrs = ab8500_sysfs_entries, |
990 | }; | |
991 | ||
52557dc6 | 992 | static const struct attribute_group ab8505_attr_group = { |
93ff722e LJ |
993 | .attrs = ab8505_sysfs_entries, |
994 | }; | |
995 | ||
52557dc6 | 996 | static const struct attribute_group ab9540_attr_group = { |
d6255529 LW |
997 | .attrs = ab9540_sysfs_entries, |
998 | }; | |
999 | ||
f791be49 | 1000 | static int ab8500_probe(struct platform_device *pdev) |
62579266 | 1001 | { |
500e69a1 | 1002 | static const char * const switch_off_status[] = { |
b04c530c JA |
1003 | "Swoff bit programming", |
1004 | "Thermal protection activation", | |
1005 | "Vbat lower then BattOk falling threshold", | |
1006 | "Watchdog expired", | |
1007 | "Non presence of 32kHz clock", | |
1008 | "Battery level lower than power on reset threshold", | |
1009 | "Power on key 1 pressed longer than 10 seconds", | |
1010 | "DB8500 thermal shutdown"}; | |
500e69a1 | 1011 | static const char * const turn_on_status[] = { |
abee26cd MW |
1012 | "Battery rising (Vbat)", |
1013 | "Power On Key 1 dbF", | |
1014 | "Power On Key 2 dbF", | |
1015 | "RTC Alarm", | |
1016 | "Main Charger Detect", | |
1017 | "Vbus Detect (USB)", | |
1018 | "USB ID Detect", | |
1019 | "UART Factory Mode Detect"}; | |
d28f1db8 | 1020 | const struct platform_device_id *platid = platform_get_device_id(pdev); |
6bc4a568 LJ |
1021 | enum ab8500_version version = AB8500_VERSION_UNDEFINED; |
1022 | struct device_node *np = pdev->dev.of_node; | |
d28f1db8 | 1023 | struct ab8500 *ab8500; |
62579266 RV |
1024 | int ret; |
1025 | int i; | |
fc832ac9 | 1026 | int irq; |
47c16975 | 1027 | u8 value; |
62579266 | 1028 | |
7ccf40b1 | 1029 | ab8500 = devm_kzalloc(&pdev->dev, sizeof(*ab8500), GFP_KERNEL); |
d28f1db8 LJ |
1030 | if (!ab8500) |
1031 | return -ENOMEM; | |
1032 | ||
d28f1db8 LJ |
1033 | ab8500->dev = &pdev->dev; |
1034 | ||
fc832ac9 MCCZ |
1035 | irq = platform_get_irq(pdev, 0); |
1036 | if (irq < 0) | |
1037 | return irq; | |
d28f1db8 | 1038 | |
fc832ac9 | 1039 | ab8500->irq = irq; |
d28f1db8 | 1040 | |
822672a7 LJ |
1041 | ab8500->read = ab8500_prcmu_read; |
1042 | ab8500->write = ab8500_prcmu_write; | |
1043 | ab8500->write_masked = ab8500_prcmu_write_masked; | |
d28f1db8 | 1044 | |
62579266 RV |
1045 | mutex_init(&ab8500->lock); |
1046 | mutex_init(&ab8500->irq_lock); | |
112a80d2 | 1047 | atomic_set(&ab8500->transfer_ongoing, 0); |
62579266 | 1048 | |
d28f1db8 LJ |
1049 | platform_set_drvdata(pdev, ab8500); |
1050 | ||
6bc4a568 LJ |
1051 | if (platid) |
1052 | version = platid->driver_data; | |
6bc4a568 | 1053 | |
0f620837 LW |
1054 | if (version != AB8500_VERSION_UNDEFINED) |
1055 | ab8500->version = version; | |
1056 | else { | |
1057 | ret = get_register_interruptible(ab8500, AB8500_MISC, | |
1058 | AB8500_IC_NAME_REG, &value); | |
f864c46a LW |
1059 | if (ret < 0) { |
1060 | dev_err(&pdev->dev, "could not probe HW\n"); | |
8c4203cb | 1061 | return ret; |
f864c46a | 1062 | } |
0f620837 LW |
1063 | |
1064 | ab8500->version = value; | |
1065 | } | |
1066 | ||
47c16975 MW |
1067 | ret = get_register_interruptible(ab8500, AB8500_MISC, |
1068 | AB8500_REV_REG, &value); | |
62579266 | 1069 | if (ret < 0) |
8c4203cb | 1070 | return ret; |
62579266 | 1071 | |
47c16975 | 1072 | ab8500->chip_id = value; |
62579266 | 1073 | |
0f620837 LW |
1074 | dev_info(ab8500->dev, "detected chip, %s rev. %1x.%1x\n", |
1075 | ab8500_version_str[ab8500->version], | |
1076 | ab8500->chip_id >> 4, | |
1077 | ab8500->chip_id & 0x0F); | |
1078 | ||
3e1a498f LJ |
1079 | /* Configure AB8540 */ |
1080 | if (is_ab8540(ab8500)) { | |
1081 | ab8500->mask_size = AB8540_NUM_IRQ_REGS; | |
1082 | ab8500->irq_reg_offset = ab8540_irq_regoffset; | |
1083 | ab8500->it_latchhier_num = AB8540_IT_LATCHHIER_NUM; | |
7ccf40b1 | 1084 | } /* Configure AB8500 or AB9540 IRQ */ |
3e1a498f | 1085 | else if (is_ab9540(ab8500) || is_ab8505(ab8500)) { |
d6255529 LW |
1086 | ab8500->mask_size = AB9540_NUM_IRQ_REGS; |
1087 | ab8500->irq_reg_offset = ab9540_irq_regoffset; | |
3e1a498f | 1088 | ab8500->it_latchhier_num = AB8500_IT_LATCHHIER_NUM; |
d6255529 LW |
1089 | } else { |
1090 | ab8500->mask_size = AB8500_NUM_IRQ_REGS; | |
1091 | ab8500->irq_reg_offset = ab8500_irq_regoffset; | |
3e1a498f | 1092 | ab8500->it_latchhier_num = AB8500_IT_LATCHHIER_NUM; |
d6255529 | 1093 | } |
7ccf40b1 LJ |
1094 | ab8500->mask = devm_kzalloc(&pdev->dev, ab8500->mask_size, |
1095 | GFP_KERNEL); | |
2ced445e LW |
1096 | if (!ab8500->mask) |
1097 | return -ENOMEM; | |
7ccf40b1 LJ |
1098 | ab8500->oldmask = devm_kzalloc(&pdev->dev, ab8500->mask_size, |
1099 | GFP_KERNEL); | |
8c4203cb LJ |
1100 | if (!ab8500->oldmask) |
1101 | return -ENOMEM; | |
1102 | ||
e5c238c3 MW |
1103 | /* |
1104 | * ab8500 has switched off due to (SWITCH_OFF_STATUS): | |
1105 | * 0x01 Swoff bit programming | |
1106 | * 0x02 Thermal protection activation | |
1107 | * 0x04 Vbat lower then BattOk falling threshold | |
1108 | * 0x08 Watchdog expired | |
1109 | * 0x10 Non presence of 32kHz clock | |
1110 | * 0x20 Battery level lower than power on reset threshold | |
1111 | * 0x40 Power on key 1 pressed longer than 10 seconds | |
1112 | * 0x80 DB8500 thermal shutdown | |
1113 | */ | |
1114 | ||
1115 | ret = get_register_interruptible(ab8500, AB8500_RTC, | |
1116 | AB8500_SWITCH_OFF_STATUS, &value); | |
1117 | if (ret < 0) | |
1118 | return ret; | |
b04c530c JA |
1119 | dev_info(ab8500->dev, "switch off cause(s) (%#x): ", value); |
1120 | ||
1121 | if (value) { | |
1122 | for (i = 0; i < ARRAY_SIZE(switch_off_status); i++) { | |
1123 | if (value & 1) | |
7ccf40b1 | 1124 | pr_cont(" \"%s\"", switch_off_status[i]); |
b04c530c JA |
1125 | value = value >> 1; |
1126 | ||
1127 | } | |
7ccf40b1 | 1128 | pr_cont("\n"); |
b04c530c | 1129 | } else { |
7ccf40b1 | 1130 | pr_cont(" None\n"); |
b04c530c | 1131 | } |
abee26cd MW |
1132 | ret = get_register_interruptible(ab8500, AB8500_SYS_CTRL1_BLOCK, |
1133 | AB8500_TURN_ON_STATUS, &value); | |
1134 | if (ret < 0) | |
1135 | return ret; | |
1136 | dev_info(ab8500->dev, "turn on reason(s) (%#x): ", value); | |
1137 | ||
1138 | if (value) { | |
1139 | for (i = 0; i < ARRAY_SIZE(turn_on_status); i++) { | |
1140 | if (value & 1) | |
7ccf40b1 | 1141 | pr_cont("\"%s\" ", turn_on_status[i]); |
abee26cd MW |
1142 | value = value >> 1; |
1143 | } | |
7ccf40b1 | 1144 | pr_cont("\n"); |
abee26cd | 1145 | } else { |
7ccf40b1 | 1146 | pr_cont("None\n"); |
abee26cd | 1147 | } |
e5c238c3 | 1148 | |
f04a9d8a RK |
1149 | if (is_ab9540(ab8500)) { |
1150 | ret = get_register_interruptible(ab8500, AB8500_CHARGER, | |
1151 | AB8500_CH_USBCH_STAT1_REG, &value); | |
1152 | if (ret < 0) | |
1153 | return ret; | |
1154 | if ((value & VBUS_DET_DBNC1) && (value & VBUS_DET_DBNC100)) | |
1155 | ab8500_override_turn_on_stat(~AB8500_POW_KEY_1_ON, | |
1156 | AB8500_VBUS_DET); | |
1157 | } | |
62579266 RV |
1158 | |
1159 | /* Clear and mask all interrupts */ | |
2ced445e | 1160 | for (i = 0; i < ab8500->mask_size; i++) { |
0f620837 LW |
1161 | /* |
1162 | * Interrupt register 12 doesn't exist prior to AB8500 version | |
1163 | * 2.0 | |
1164 | */ | |
1165 | if (ab8500->irq_reg_offset[i] == 11 && | |
1166 | is_ab8500_1p1_or_earlier(ab8500)) | |
92d50a41 | 1167 | continue; |
62579266 | 1168 | |
3e1a498f LJ |
1169 | if (ab8500->irq_reg_offset[i] < 0) |
1170 | continue; | |
1171 | ||
47c16975 | 1172 | get_register_interruptible(ab8500, AB8500_INTERRUPT, |
2ced445e | 1173 | AB8500_IT_LATCH1_REG + ab8500->irq_reg_offset[i], |
92d50a41 | 1174 | &value); |
47c16975 | 1175 | set_register_interruptible(ab8500, AB8500_INTERRUPT, |
2ced445e | 1176 | AB8500_IT_MASK1_REG + ab8500->irq_reg_offset[i], 0xff); |
62579266 RV |
1177 | } |
1178 | ||
47c16975 MW |
1179 | ret = abx500_register_ops(ab8500->dev, &ab8500_ops); |
1180 | if (ret) | |
8c4203cb | 1181 | return ret; |
47c16975 | 1182 | |
2ced445e | 1183 | for (i = 0; i < ab8500->mask_size; i++) |
62579266 RV |
1184 | ab8500->mask[i] = ab8500->oldmask[i] = 0xff; |
1185 | ||
06e589ef LJ |
1186 | ret = ab8500_irq_init(ab8500, np); |
1187 | if (ret) | |
8c4203cb | 1188 | return ret; |
62579266 | 1189 | |
f348fefd DS |
1190 | ret = devm_request_threaded_irq(&pdev->dev, ab8500->irq, NULL, |
1191 | ab8500_hierarchical_irq, | |
1192 | IRQF_ONESHOT | IRQF_NO_SUSPEND, | |
1193 | "ab8500", ab8500); | |
1194 | if (ret) | |
1195 | return ret; | |
62579266 | 1196 | |
bad76991 LJ |
1197 | if (is_ab9540(ab8500)) |
1198 | ret = mfd_add_devices(ab8500->dev, 0, ab9540_devs, | |
1199 | ARRAY_SIZE(ab9540_devs), NULL, | |
f864c46a | 1200 | 0, ab8500->domain); |
9c717cf3 | 1201 | else if (is_ab8540(ab8500)) { |
c0eda9ae LJ |
1202 | ret = mfd_add_devices(ab8500->dev, 0, ab8540_devs, |
1203 | ARRAY_SIZE(ab8540_devs), NULL, | |
f864c46a | 1204 | 0, ab8500->domain); |
9c717cf3 AT |
1205 | if (ret) |
1206 | return ret; | |
1207 | ||
1208 | if (is_ab8540_1p2_or_earlier(ab8500)) | |
1209 | ret = mfd_add_devices(ab8500->dev, 0, ab8540_cut1_devs, | |
1210 | ARRAY_SIZE(ab8540_cut1_devs), NULL, | |
f864c46a | 1211 | 0, ab8500->domain); |
9c717cf3 AT |
1212 | else /* ab8540 >= cut2 */ |
1213 | ret = mfd_add_devices(ab8500->dev, 0, ab8540_cut2_devs, | |
1214 | ARRAY_SIZE(ab8540_cut2_devs), NULL, | |
f864c46a | 1215 | 0, ab8500->domain); |
9c717cf3 | 1216 | } else if (is_ab8505(ab8500)) |
c0eda9ae LJ |
1217 | ret = mfd_add_devices(ab8500->dev, 0, ab8505_devs, |
1218 | ARRAY_SIZE(ab8505_devs), NULL, | |
f864c46a | 1219 | 0, ab8500->domain); |
bad76991 LJ |
1220 | else |
1221 | ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs, | |
1222 | ARRAY_SIZE(ab8500_devs), NULL, | |
f864c46a | 1223 | 0, ab8500->domain); |
bad76991 | 1224 | if (ret) |
8c4203cb | 1225 | return ret; |
44f72e53 | 1226 | |
a98688d2 LW |
1227 | /* Add battery management devices */ |
1228 | ret = mfd_add_devices(ab8500->dev, 0, ab8500_bm_devs, | |
1229 | ARRAY_SIZE(ab8500_bm_devs), NULL, | |
1230 | 0, ab8500->domain); | |
1231 | if (ret) | |
1232 | dev_err(ab8500->dev, "error adding bm devices\n"); | |
6ef9418c | 1233 | |
e436ddff LJ |
1234 | if (((is_ab8505(ab8500) || is_ab9540(ab8500)) && |
1235 | ab8500->chip_id >= AB8500_CUT2P0) || is_ab8540(ab8500)) | |
d6255529 LW |
1236 | ret = sysfs_create_group(&ab8500->dev->kobj, |
1237 | &ab9540_attr_group); | |
1238 | else | |
1239 | ret = sysfs_create_group(&ab8500->dev->kobj, | |
1240 | &ab8500_attr_group); | |
93ff722e LJ |
1241 | |
1242 | if ((is_ab8505(ab8500) || is_ab9540(ab8500)) && | |
1243 | ab8500->chip_id >= AB8500_CUT2P0) | |
1244 | ret = sysfs_create_group(&ab8500->dev->kobj, | |
1245 | &ab8505_attr_group); | |
1246 | ||
cca69b67 MW |
1247 | if (ret) |
1248 | dev_err(ab8500->dev, "error creating sysfs entries\n"); | |
06e589ef LJ |
1249 | |
1250 | return ret; | |
62579266 RV |
1251 | } |
1252 | ||
d28f1db8 LJ |
1253 | static const struct platform_device_id ab8500_id[] = { |
1254 | { "ab8500-core", AB8500_VERSION_AB8500 }, | |
1c0769d2 | 1255 | { "ab8505-core", AB8500_VERSION_AB8505 }, |
d28f1db8 LJ |
1256 | { "ab9540-i2c", AB8500_VERSION_AB9540 }, |
1257 | { "ab8540-i2c", AB8500_VERSION_AB8540 }, | |
1258 | { } | |
1259 | }; | |
1260 | ||
1261 | static struct platform_driver ab8500_core_driver = { | |
1262 | .driver = { | |
1263 | .name = "ab8500-core", | |
31cbae22 | 1264 | .suppress_bind_attrs = true, |
d28f1db8 LJ |
1265 | }, |
1266 | .probe = ab8500_probe, | |
d28f1db8 LJ |
1267 | .id_table = ab8500_id, |
1268 | }; | |
1269 | ||
1270 | static int __init ab8500_core_init(void) | |
1271 | { | |
1272 | return platform_driver_register(&ab8500_core_driver); | |
1273 | } | |
ba7cbc3e | 1274 | core_initcall(ab8500_core_init); |