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Merge branch 'iommu/largepages' into amd-iommu/2.6.35
[linux.git] / sound / pci / fm801.c
CommitLineData
1da177e4
LT		 1/*
2 * The driver for the ForteMedia FM801 based soundcards
c1017a4c 3 * Copyright (c) by Jaroslav Kysela <[email protected]>
1da177e4 4 *
e0a5d82a 5 * Support FM only card by Andy Shevchenko <[email protected]>
1da177e4
LT		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
1da177e4
LT		 23#include <linux/delay.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/pci.h>
27#include <linux/slab.h>
28#include <linux/moduleparam.h>
29#include <sound/core.h>
30#include <sound/pcm.h>
666c70ff 31#include <sound/tlv.h>
1da177e4
LT		 32#include <sound/ac97_codec.h>
33#include <sound/mpu401.h>
34#include <sound/opl3.h>
35#include <sound/initval.h>
36
37#include <asm/io.h>
38
efce4bb9 39#ifdef CONFIG_SND_FM801_TEA575X_BOOL
1da177e4
LT		 40#include <sound/tea575x-tuner.h>
41#define TEA575X_RADIO 1
42#endif
43
c1017a4c 44MODULE_AUTHOR("Jaroslav Kysela <[email protected]>");
1da177e4
LT		 45MODULE_DESCRIPTION("ForteMedia FM801");
46MODULE_LICENSE("GPL");
47MODULE_SUPPORTED_DEVICE("{{ForteMedia,FM801},"
48 "{Genius,SoundMaker Live 5.1}}");
49
50static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
51static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
52static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
53/*
54 * Enable TEA575x tuner
55 * 1 = MediaForte 256-PCS
56 * 2 = MediaForte 256-PCPR
57 * 3 = MediaForte 64-PCR
fb716c0b 58 * 16 = setup tuner only (this is additional bit), i.e. SF64-PCR FM card
1da177e4
LT		 59 * High 16-bits are video (radio) device number + 1
60 */
6581f4e7 61static int tea575x_tuner[SNDRV_CARDS];
1da177e4
LT		 62
63module_param_array(index, int, NULL, 0444);
64MODULE_PARM_DESC(index, "Index value for the FM801 soundcard.");
65module_param_array(id, charp, NULL, 0444);
66MODULE_PARM_DESC(id, "ID string for the FM801 soundcard.");
67module_param_array(enable, bool, NULL, 0444);
68MODULE_PARM_DESC(enable, "Enable FM801 soundcard.");
69module_param_array(tea575x_tuner, int, NULL, 0444);
fb716c0b
OZ		 70MODULE_PARM_DESC(tea575x_tuner, "TEA575x tuner access method (1 = SF256-PCS, 2=SF256-PCPR, 3=SF64-PCR, +16=tuner-only).");
71
72#define TUNER_ONLY (1<<4)
73#define TUNER_TYPE_MASK (~TUNER_ONLY & 0xFFFF)
1da177e4
LT		 74
75/*
76 * Direct registers
77 */
78
79#define FM801_REG(chip, reg) (chip->port + FM801_##reg)
80
81#define FM801_PCM_VOL 0x00 /* PCM Output Volume */
82#define FM801_FM_VOL 0x02 /* FM Output Volume */
83#define FM801_I2S_VOL 0x04 /* I2S Volume */
84#define FM801_REC_SRC 0x06 /* Record Source */
85#define FM801_PLY_CTRL 0x08 /* Playback Control */
86#define FM801_PLY_COUNT 0x0a /* Playback Count */
87#define FM801_PLY_BUF1 0x0c /* Playback Bufer I */
88#define FM801_PLY_BUF2 0x10 /* Playback Buffer II */
89#define FM801_CAP_CTRL 0x14 /* Capture Control */
90#define FM801_CAP_COUNT 0x16 /* Capture Count */
91#define FM801_CAP_BUF1 0x18 /* Capture Buffer I */
92#define FM801_CAP_BUF2 0x1c /* Capture Buffer II */
93#define FM801_CODEC_CTRL 0x22 /* Codec Control */
94#define FM801_I2S_MODE 0x24 /* I2S Mode Control */
95#define FM801_VOLUME 0x26 /* Volume Up/Down/Mute Status */
96#define FM801_I2C_CTRL 0x29 /* I2C Control */
97#define FM801_AC97_CMD 0x2a /* AC'97 Command */
98#define FM801_AC97_DATA 0x2c /* AC'97 Data */
99#define FM801_MPU401_DATA 0x30 /* MPU401 Data */
100#define FM801_MPU401_CMD 0x31 /* MPU401 Command */
101#define FM801_GPIO_CTRL 0x52 /* General Purpose I/O Control */
102#define FM801_GEN_CTRL 0x54 /* General Control */
103#define FM801_IRQ_MASK 0x56 /* Interrupt Mask */
104#define FM801_IRQ_STATUS 0x5a /* Interrupt Status */
105#define FM801_OPL3_BANK0 0x68 /* OPL3 Status Read / Bank 0 Write */
106#define FM801_OPL3_DATA0 0x69 /* OPL3 Data 0 Write */
107#define FM801_OPL3_BANK1 0x6a /* OPL3 Bank 1 Write */
108#define FM801_OPL3_DATA1 0x6b /* OPL3 Bank 1 Write */
109#define FM801_POWERDOWN 0x70 /* Blocks Power Down Control */
110
b1e9ed26
TI		 111/* codec access */
112#define FM801_AC97_READ (1<<7) /* read=1, write=0 */
113#define FM801_AC97_VALID (1<<8) /* port valid=1 */
114#define FM801_AC97_BUSY (1<<9) /* busy=1 */
115#define FM801_AC97_ADDR_SHIFT 10 /* codec id (2bit) */
1da177e4
LT		 116
117/* playback and record control register bits */
118#define FM801_BUF1_LAST (1<<1)
119#define FM801_BUF2_LAST (1<<2)
120#define FM801_START (1<<5)
121#define FM801_PAUSE (1<<6)
122#define FM801_IMMED_STOP (1<<7)
123#define FM801_RATE_SHIFT 8
124#define FM801_RATE_MASK (15 << FM801_RATE_SHIFT)
125#define FM801_CHANNELS_4 (1<<12) /* playback only */
126#define FM801_CHANNELS_6 (2<<12) /* playback only */
127#define FM801_CHANNELS_6MS (3<<12) /* playback only */
128#define FM801_CHANNELS_MASK (3<<12)
129#define FM801_16BIT (1<<14)
130#define FM801_STEREO (1<<15)
131
132/* IRQ status bits */
133#define FM801_IRQ_PLAYBACK (1<<8)
134#define FM801_IRQ_CAPTURE (1<<9)
135#define FM801_IRQ_VOLUME (1<<14)
136#define FM801_IRQ_MPU (1<<15)
137
138/* GPIO control register */
139#define FM801_GPIO_GP0 (1<<0) /* read/write */
140#define FM801_GPIO_GP1 (1<<1)
141#define FM801_GPIO_GP2 (1<<2)
142#define FM801_GPIO_GP3 (1<<3)
143#define FM801_GPIO_GP(x) (1<<(0+(x)))
144#define FM801_GPIO_GD0 (1<<8) /* directions: 1 = input, 0 = output*/
145#define FM801_GPIO_GD1 (1<<9)
146#define FM801_GPIO_GD2 (1<<10)
147#define FM801_GPIO_GD3 (1<<11)
148#define FM801_GPIO_GD(x) (1<<(8+(x)))
149#define FM801_GPIO_GS0 (1<<12) /* function select: */
150#define FM801_GPIO_GS1 (1<<13) /* 1 = GPIO */
151#define FM801_GPIO_GS2 (1<<14) /* 0 = other (S/PDIF, VOL) */
152#define FM801_GPIO_GS3 (1<<15)
153#define FM801_GPIO_GS(x) (1<<(12+(x)))
154
155/*
156
157 */
158
a5f22156 159struct fm801 {
1da177e4
LT		 160 int irq;
161
162 unsigned long port; /* I/O port number */
163 unsigned int multichannel: 1, /* multichannel support */
164 secondary: 1; /* secondary codec */
165 unsigned char secondary_addr; /* address of the secondary codec */
fb716c0b 166 unsigned int tea575x_tuner; /* tuner access method & flags */
1da177e4
LT		 167
168 unsigned short ply_ctrl; /* playback control */
169 unsigned short cap_ctrl; /* capture control */
170
171 unsigned long ply_buffer;
172 unsigned int ply_buf;
173 unsigned int ply_count;
174 unsigned int ply_size;
175 unsigned int ply_pos;
176
177 unsigned long cap_buffer;
178 unsigned int cap_buf;
179 unsigned int cap_count;
180 unsigned int cap_size;
181 unsigned int cap_pos;
182
a5f22156
TI		 183 struct snd_ac97_bus *ac97_bus;
184 struct snd_ac97 *ac97;
185 struct snd_ac97 *ac97_sec;
1da177e4
LT		 186
187 struct pci_dev *pci;
a5f22156
TI		 188 struct snd_card *card;
189 struct snd_pcm *pcm;
190 struct snd_rawmidi *rmidi;
191 struct snd_pcm_substream *playback_substream;
192 struct snd_pcm_substream *capture_substream;
1da177e4
LT		 193 unsigned int p_dma_size;
194 unsigned int c_dma_size;
195
196 spinlock_t reg_lock;
a5f22156 197 struct snd_info_entry *proc_entry;
1da177e4
LT		 198
199#ifdef TEA575X_RADIO
a5f22156 200 struct snd_tea575x tea;
1da177e4 201#endif
b1e9ed26
TI		 202
203#ifdef CONFIG_PM
204 u16 saved_regs[0x20];
205#endif
1da177e4
LT		 206};
207
cebe41d4 208static DEFINE_PCI_DEVICE_TABLE(snd_fm801_ids) = {
1da177e4 209 { 0x1319, 0x0801, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0, }, /* FM801 */
26be8659 210 { 0x5213, 0x0510, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0, }, /* Gallant Odyssey Sound 4 */
1da177e4
LT		 211 { 0, }
212};
213
214MODULE_DEVICE_TABLE(pci, snd_fm801_ids);
215
216/*
217 * common I/O routines
218 */
219
a5f22156 220static int snd_fm801_update_bits(struct fm801 *chip, unsigned short reg,
1da177e4
LT		 221 unsigned short mask, unsigned short value)
222{
223 int change;
224 unsigned long flags;
225 unsigned short old, new;
226
227 spin_lock_irqsave(&chip->reg_lock, flags);
228 old = inw(chip->port + reg);
229 new = (old & ~mask) | value;
230 change = old != new;
231 if (change)
232 outw(new, chip->port + reg);
233 spin_unlock_irqrestore(&chip->reg_lock, flags);
234 return change;
235}
236
a5f22156 237static void snd_fm801_codec_write(struct snd_ac97 *ac97,
1da177e4
LT		 238 unsigned short reg,
239 unsigned short val)
240{
a5f22156 241 struct fm801 *chip = ac97->private_data;
1da177e4
LT		 242 int idx;
243
244 /*
245 * Wait until the codec interface is not ready..
246 */
247 for (idx = 0; idx < 100; idx++) {
b1e9ed26 248 if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
1da177e4
LT		 249 goto ok1;
250 udelay(10);
251 }
99b359ba 252 snd_printk(KERN_ERR "AC'97 interface is busy (1)\n");
1da177e4
LT		 253 return;
254
255 ok1:
256 /* write data and address */
257 outw(val, FM801_REG(chip, AC97_DATA));
258 outw(reg | (ac97->addr << FM801_AC97_ADDR_SHIFT), FM801_REG(chip, AC97_CMD));
259 /*
260 * Wait until the write command is not completed..
261 */
262 for (idx = 0; idx < 1000; idx++) {
b1e9ed26 263 if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
1da177e4
LT		 264 return;
265 udelay(10);
266 }
99b359ba 267 snd_printk(KERN_ERR "AC'97 interface #%d is busy (2)\n", ac97->num);
1da177e4
LT		 268}
269
a5f22156 270static unsigned short snd_fm801_codec_read(struct snd_ac97 *ac97, unsigned short reg)
1da177e4 271{
a5f22156 272 struct fm801 *chip = ac97->private_data;
1da177e4
LT		 273 int idx;
274
275 /*
276 * Wait until the codec interface is not ready..
277 */
278 for (idx = 0; idx < 100; idx++) {
b1e9ed26 279 if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
1da177e4
LT		 280 goto ok1;
281 udelay(10);
282 }
99b359ba 283 snd_printk(KERN_ERR "AC'97 interface is busy (1)\n");
1da177e4
LT		 284 return 0;
285
286 ok1:
287 /* read command */
b1e9ed26
TI		 288 outw(reg | (ac97->addr << FM801_AC97_ADDR_SHIFT) | FM801_AC97_READ,
289 FM801_REG(chip, AC97_CMD));
1da177e4 290 for (idx = 0; idx < 100; idx++) {
b1e9ed26 291 if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
1da177e4
LT		 292 goto ok2;
293 udelay(10);
294 }
99b359ba 295 snd_printk(KERN_ERR "AC'97 interface #%d is busy (2)\n", ac97->num);
1da177e4
LT		 296 return 0;
297
298 ok2:
299 for (idx = 0; idx < 1000; idx++) {
b1e9ed26 300 if (inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_VALID)
1da177e4
LT		 301 goto ok3;
302 udelay(10);
303 }
99b359ba 304 snd_printk(KERN_ERR "AC'97 interface #%d is not valid (2)\n", ac97->num);
1da177e4
LT		 305 return 0;
306
307 ok3:
308 return inw(FM801_REG(chip, AC97_DATA));
309}
310
311static unsigned int rates[] = {
312 5500, 8000, 9600, 11025,
313 16000, 19200, 22050, 32000,
314 38400, 44100, 48000
315};
316
a5f22156 317static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1da177e4
LT		 318 .count = ARRAY_SIZE(rates),
319 .list = rates,
320 .mask = 0,
321};
322
323static unsigned int channels[] = {
324 2, 4, 6
325};
326
a5f22156 327static struct snd_pcm_hw_constraint_list hw_constraints_channels = {
5e4968e2 328 .count = ARRAY_SIZE(channels),
1da177e4
LT		 329 .list = channels,
330 .mask = 0,
331};
332
333/*
334 * Sample rate routines
335 */
336
337static unsigned short snd_fm801_rate_bits(unsigned int rate)
338{
339 unsigned int idx;
340
341 for (idx = 0; idx < ARRAY_SIZE(rates); idx++)
342 if (rates[idx] == rate)
343 return idx;
344 snd_BUG();
345 return ARRAY_SIZE(rates) - 1;
346}
347
348/*
349 * PCM part
350 */
351
a5f22156 352static int snd_fm801_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 353 int cmd)
354{
a5f22156 355 struct fm801 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 356
357 spin_lock(&chip->reg_lock);
358 switch (cmd) {
359 case SNDRV_PCM_TRIGGER_START:
360 chip->ply_ctrl &= ~(FM801_BUF1_LAST |
361 FM801_BUF2_LAST |
362 FM801_PAUSE);
363 chip->ply_ctrl |= FM801_START |
364 FM801_IMMED_STOP;
365 break;
366 case SNDRV_PCM_TRIGGER_STOP:
367 chip->ply_ctrl &= ~(FM801_START | FM801_PAUSE);
368 break;
369 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
b1e9ed26 370 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT		 371 chip->ply_ctrl |= FM801_PAUSE;
372 break;
373 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
b1e9ed26 374 case SNDRV_PCM_TRIGGER_RESUME:
1da177e4
LT		 375 chip->ply_ctrl &= ~FM801_PAUSE;
376 break;
377 default:
378 spin_unlock(&chip->reg_lock);
379 snd_BUG();
380 return -EINVAL;
381 }
382 outw(chip->ply_ctrl, FM801_REG(chip, PLY_CTRL));
383 spin_unlock(&chip->reg_lock);
384 return 0;
385}
386
a5f22156 387static int snd_fm801_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 388 int cmd)
389{
a5f22156 390 struct fm801 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 391
392 spin_lock(&chip->reg_lock);
393 switch (cmd) {
394 case SNDRV_PCM_TRIGGER_START:
395 chip->cap_ctrl &= ~(FM801_BUF1_LAST |
396 FM801_BUF2_LAST |
397 FM801_PAUSE);
398 chip->cap_ctrl |= FM801_START |
399 FM801_IMMED_STOP;
400 break;
401 case SNDRV_PCM_TRIGGER_STOP:
402 chip->cap_ctrl &= ~(FM801_START | FM801_PAUSE);
403 break;
404 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
b1e9ed26 405 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT		 406 chip->cap_ctrl |= FM801_PAUSE;
407 break;
408 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
b1e9ed26 409 case SNDRV_PCM_TRIGGER_RESUME:
1da177e4
LT		 410 chip->cap_ctrl &= ~FM801_PAUSE;
411 break;
412 default:
413 spin_unlock(&chip->reg_lock);
414 snd_BUG();
415 return -EINVAL;
416 }
417 outw(chip->cap_ctrl, FM801_REG(chip, CAP_CTRL));
418 spin_unlock(&chip->reg_lock);
419 return 0;
420}
421
a5f22156
TI		 422static int snd_fm801_hw_params(struct snd_pcm_substream *substream,
423 struct snd_pcm_hw_params *hw_params)
1da177e4
LT		 424{
425 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
426}
427
a5f22156 428static int snd_fm801_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 429{
430 return snd_pcm_lib_free_pages(substream);
431}
432
a5f22156 433static int snd_fm801_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 434{
a5f22156
TI		 435 struct fm801 *chip = snd_pcm_substream_chip(substream);
436 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 437
438 chip->ply_size = snd_pcm_lib_buffer_bytes(substream);
439 chip->ply_count = snd_pcm_lib_period_bytes(substream);
440 spin_lock_irq(&chip->reg_lock);
441 chip->ply_ctrl &= ~(FM801_START | FM801_16BIT |
442 FM801_STEREO | FM801_RATE_MASK |
443 FM801_CHANNELS_MASK);
444 if (snd_pcm_format_width(runtime->format) == 16)
445 chip->ply_ctrl |= FM801_16BIT;
446 if (runtime->channels > 1) {
447 chip->ply_ctrl |= FM801_STEREO;
448 if (runtime->channels == 4)
449 chip->ply_ctrl |= FM801_CHANNELS_4;
450 else if (runtime->channels == 6)
451 chip->ply_ctrl |= FM801_CHANNELS_6;
452 }
453 chip->ply_ctrl |= snd_fm801_rate_bits(runtime->rate) << FM801_RATE_SHIFT;
454 chip->ply_buf = 0;
455 outw(chip->ply_ctrl, FM801_REG(chip, PLY_CTRL));
456 outw(chip->ply_count - 1, FM801_REG(chip, PLY_COUNT));
457 chip->ply_buffer = runtime->dma_addr;
458 chip->ply_pos = 0;
459 outl(chip->ply_buffer, FM801_REG(chip, PLY_BUF1));
460 outl(chip->ply_buffer + (chip->ply_count % chip->ply_size), FM801_REG(chip, PLY_BUF2));
461 spin_unlock_irq(&chip->reg_lock);
462 return 0;
463}
464
a5f22156 465static int snd_fm801_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 466{
a5f22156
TI		 467 struct fm801 *chip = snd_pcm_substream_chip(substream);
468 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 469
470 chip->cap_size = snd_pcm_lib_buffer_bytes(substream);
471 chip->cap_count = snd_pcm_lib_period_bytes(substream);
472 spin_lock_irq(&chip->reg_lock);
473 chip->cap_ctrl &= ~(FM801_START | FM801_16BIT |
474 FM801_STEREO | FM801_RATE_MASK);
475 if (snd_pcm_format_width(runtime->format) == 16)
476 chip->cap_ctrl |= FM801_16BIT;
477 if (runtime->channels > 1)
478 chip->cap_ctrl |= FM801_STEREO;
479 chip->cap_ctrl |= snd_fm801_rate_bits(runtime->rate) << FM801_RATE_SHIFT;
480 chip->cap_buf = 0;
481 outw(chip->cap_ctrl, FM801_REG(chip, CAP_CTRL));
482 outw(chip->cap_count - 1, FM801_REG(chip, CAP_COUNT));
483 chip->cap_buffer = runtime->dma_addr;
484 chip->cap_pos = 0;
485 outl(chip->cap_buffer, FM801_REG(chip, CAP_BUF1));
486 outl(chip->cap_buffer + (chip->cap_count % chip->cap_size), FM801_REG(chip, CAP_BUF2));
487 spin_unlock_irq(&chip->reg_lock);
488 return 0;
489}
490
a5f22156 491static snd_pcm_uframes_t snd_fm801_playback_pointer(struct snd_pcm_substream *substream)
1da177e4 492{
a5f22156 493 struct fm801 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 494 size_t ptr;
495
496 if (!(chip->ply_ctrl & FM801_START))
497 return 0;
498 spin_lock(&chip->reg_lock);
499 ptr = chip->ply_pos + (chip->ply_count - 1) - inw(FM801_REG(chip, PLY_COUNT));
500 if (inw(FM801_REG(chip, IRQ_STATUS)) & FM801_IRQ_PLAYBACK) {
501 ptr += chip->ply_count;
502 ptr %= chip->ply_size;
503 }
504 spin_unlock(&chip->reg_lock);
505 return bytes_to_frames(substream->runtime, ptr);
506}
507
a5f22156 508static snd_pcm_uframes_t snd_fm801_capture_pointer(struct snd_pcm_substream *substream)
1da177e4 509{
a5f22156 510 struct fm801 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 511 size_t ptr;
512
513 if (!(chip->cap_ctrl & FM801_START))
514 return 0;
515 spin_lock(&chip->reg_lock);
516 ptr = chip->cap_pos + (chip->cap_count - 1) - inw(FM801_REG(chip, CAP_COUNT));
517 if (inw(FM801_REG(chip, IRQ_STATUS)) & FM801_IRQ_CAPTURE) {
518 ptr += chip->cap_count;
519 ptr %= chip->cap_size;
520 }
521 spin_unlock(&chip->reg_lock);
522 return bytes_to_frames(substream->runtime, ptr);
523}
524
7d12e780 525static irqreturn_t snd_fm801_interrupt(int irq, void *dev_id)
1da177e4 526{
a5f22156 527 struct fm801 *chip = dev_id;
1da177e4
LT		 528 unsigned short status;
529 unsigned int tmp;
530
531 status = inw(FM801_REG(chip, IRQ_STATUS));
532 status &= FM801_IRQ_PLAYBACK|FM801_IRQ_CAPTURE|FM801_IRQ_MPU|FM801_IRQ_VOLUME;
533 if (! status)
534 return IRQ_NONE;
535 /* ack first */
536 outw(status, FM801_REG(chip, IRQ_STATUS));
537 if (chip->pcm && (status & FM801_IRQ_PLAYBACK) && chip->playback_substream) {
538 spin_lock(&chip->reg_lock);
539 chip->ply_buf++;
540 chip->ply_pos += chip->ply_count;
541 chip->ply_pos %= chip->ply_size;
542 tmp = chip->ply_pos + chip->ply_count;
543 tmp %= chip->ply_size;
544 outl(chip->ply_buffer + tmp,
545 (chip->ply_buf & 1) ?
546 FM801_REG(chip, PLY_BUF1) :
547 FM801_REG(chip, PLY_BUF2));
548 spin_unlock(&chip->reg_lock);
549 snd_pcm_period_elapsed(chip->playback_substream);
550 }
551 if (chip->pcm && (status & FM801_IRQ_CAPTURE) && chip->capture_substream) {
552 spin_lock(&chip->reg_lock);
553 chip->cap_buf++;
554 chip->cap_pos += chip->cap_count;
555 chip->cap_pos %= chip->cap_size;
556 tmp = chip->cap_pos + chip->cap_count;
557 tmp %= chip->cap_size;
558 outl(chip->cap_buffer + tmp,
559 (chip->cap_buf & 1) ?
560 FM801_REG(chip, CAP_BUF1) :
561 FM801_REG(chip, CAP_BUF2));
562 spin_unlock(&chip->reg_lock);
563 snd_pcm_period_elapsed(chip->capture_substream);
564 }
565 if (chip->rmidi && (status & FM801_IRQ_MPU))
7d12e780 566 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
1da177e4
LT		 567 if (status & FM801_IRQ_VOLUME)
568 ;/* TODO */
569
570 return IRQ_HANDLED;
571}
572
a5f22156 573static struct snd_pcm_hardware snd_fm801_playback =
1da177e4
LT		 574{
575 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
576 SNDRV_PCM_INFO_BLOCK_TRANSFER |
b1e9ed26 577 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 578 SNDRV_PCM_INFO_MMAP_VALID),
579 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
580 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
581 .rate_min = 5500,
582 .rate_max = 48000,
583 .channels_min = 1,
584 .channels_max = 2,
585 .buffer_bytes_max = (128*1024),
586 .period_bytes_min = 64,
587 .period_bytes_max = (128*1024),
588 .periods_min = 1,
589 .periods_max = 1024,
590 .fifo_size = 0,
591};
592
a5f22156 593static struct snd_pcm_hardware snd_fm801_capture =
1da177e4
LT		 594{
595 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
596 SNDRV_PCM_INFO_BLOCK_TRANSFER |
b1e9ed26 597 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 598 SNDRV_PCM_INFO_MMAP_VALID),
599 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
600 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
601 .rate_min = 5500,
602 .rate_max = 48000,
603 .channels_min = 1,
604 .channels_max = 2,
605 .buffer_bytes_max = (128*1024),
606 .period_bytes_min = 64,
607 .period_bytes_max = (128*1024),
608 .periods_min = 1,
609 .periods_max = 1024,
610 .fifo_size = 0,
611};
612
a5f22156 613static int snd_fm801_playback_open(struct snd_pcm_substream *substream)
1da177e4 614{
a5f22156
TI		 615 struct fm801 *chip = snd_pcm_substream_chip(substream);
616 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 617 int err;
618
619 chip->playback_substream = substream;
620 runtime->hw = snd_fm801_playback;
a5f22156
TI		 621 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
622 &hw_constraints_rates);
1da177e4
LT		 623 if (chip->multichannel) {
624 runtime->hw.channels_max = 6;
a5f22156
TI		 625 snd_pcm_hw_constraint_list(runtime, 0,
626 SNDRV_PCM_HW_PARAM_CHANNELS,
627 &hw_constraints_channels);
1da177e4
LT		 628 }
629 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
630 return err;
631 return 0;
632}
633
a5f22156 634static int snd_fm801_capture_open(struct snd_pcm_substream *substream)
1da177e4 635{
a5f22156
TI		 636 struct fm801 *chip = snd_pcm_substream_chip(substream);
637 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 638 int err;
639
640 chip->capture_substream = substream;
641 runtime->hw = snd_fm801_capture;
a5f22156
TI		 642 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
643 &hw_constraints_rates);
1da177e4
LT		 644 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
645 return err;
646 return 0;
647}
648
a5f22156 649static int snd_fm801_playback_close(struct snd_pcm_substream *substream)
1da177e4 650{
a5f22156 651 struct fm801 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 652
653 chip->playback_substream = NULL;
654 return 0;
655}
656
a5f22156 657static int snd_fm801_capture_close(struct snd_pcm_substream *substream)
1da177e4 658{
a5f22156 659 struct fm801 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 660
661 chip->capture_substream = NULL;
662 return 0;
663}
664
a5f22156 665static struct snd_pcm_ops snd_fm801_playback_ops = {
1da177e4
LT		 666 .open = snd_fm801_playback_open,
667 .close = snd_fm801_playback_close,
668 .ioctl = snd_pcm_lib_ioctl,
669 .hw_params = snd_fm801_hw_params,
670 .hw_free = snd_fm801_hw_free,
671 .prepare = snd_fm801_playback_prepare,
672 .trigger = snd_fm801_playback_trigger,
673 .pointer = snd_fm801_playback_pointer,
674};
675
a5f22156 676static struct snd_pcm_ops snd_fm801_capture_ops = {
1da177e4
LT		 677 .open = snd_fm801_capture_open,
678 .close = snd_fm801_capture_close,
679 .ioctl = snd_pcm_lib_ioctl,
680 .hw_params = snd_fm801_hw_params,
681 .hw_free = snd_fm801_hw_free,
682 .prepare = snd_fm801_capture_prepare,
683 .trigger = snd_fm801_capture_trigger,
684 .pointer = snd_fm801_capture_pointer,
685};
686
a5f22156 687static int __devinit snd_fm801_pcm(struct fm801 *chip, int device, struct snd_pcm ** rpcm)
1da177e4 688{
a5f22156 689 struct snd_pcm *pcm;
1da177e4
LT		 690 int err;
691
692 if (rpcm)
693 *rpcm = NULL;
694 if ((err = snd_pcm_new(chip->card, "FM801", device, 1, 1, &pcm)) < 0)
695 return err;
696
697 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_fm801_playback_ops);
698 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_fm801_capture_ops);
699
700 pcm->private_data = chip;
1da177e4
LT		 701 pcm->info_flags = 0;
702 strcpy(pcm->name, "FM801");
703 chip->pcm = pcm;
704
705 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
706 snd_dma_pci_data(chip->pci),
707 chip->multichannel ? 128*1024 : 64*1024, 128*1024);
708
709 if (rpcm)
710 *rpcm = pcm;
711 return 0;
712}
713
714/*
715 * TEA5757 radio
716 */
717
718#ifdef TEA575X_RADIO
719
720/* 256PCS GPIO numbers */
721#define TEA_256PCS_DATA 1
722#define TEA_256PCS_WRITE_ENABLE 2 /* inverted */
723#define TEA_256PCS_BUS_CLOCK 3
724
a5f22156 725static void snd_fm801_tea575x_256pcs_write(struct snd_tea575x *tea, unsigned int val)
1da177e4 726{
a5f22156 727 struct fm801 *chip = tea->private_data;
1da177e4
LT		 728 unsigned short reg;
729 int i = 25;
730
731 spin_lock_irq(&chip->reg_lock);
732 reg = inw(FM801_REG(chip, GPIO_CTRL));
733 /* use GPIO lines and set write enable bit */
734 reg |= FM801_GPIO_GS(TEA_256PCS_DATA) |
735 FM801_GPIO_GS(TEA_256PCS_WRITE_ENABLE) |
736 FM801_GPIO_GS(TEA_256PCS_BUS_CLOCK);
737 /* all of lines are in the write direction */
738 /* clear data and clock lines */
739 reg &= ~(FM801_GPIO_GD(TEA_256PCS_DATA) |
740 FM801_GPIO_GD(TEA_256PCS_WRITE_ENABLE) |
741 FM801_GPIO_GD(TEA_256PCS_BUS_CLOCK) |
742 FM801_GPIO_GP(TEA_256PCS_DATA) |
743 FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK) |
744 FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE));
745 outw(reg, FM801_REG(chip, GPIO_CTRL));
746 udelay(1);
747
748 while (i--) {
749 if (val & (1 << i))
750 reg |= FM801_GPIO_GP(TEA_256PCS_DATA);
751 else
752 reg &= ~FM801_GPIO_GP(TEA_256PCS_DATA);
753 outw(reg, FM801_REG(chip, GPIO_CTRL));
754 udelay(1);
755 reg |= FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
756 outw(reg, FM801_REG(chip, GPIO_CTRL));
757 reg &= ~FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
758 outw(reg, FM801_REG(chip, GPIO_CTRL));
759 udelay(1);
760 }
761
762 /* and reset the write enable bit */
763 reg |= FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE) |
764 FM801_GPIO_GP(TEA_256PCS_DATA);
765 outw(reg, FM801_REG(chip, GPIO_CTRL));
766 spin_unlock_irq(&chip->reg_lock);
767}
768
a5f22156 769static unsigned int snd_fm801_tea575x_256pcs_read(struct snd_tea575x *tea)
1da177e4 770{
a5f22156 771 struct fm801 *chip = tea->private_data;
1da177e4
LT		 772 unsigned short reg;
773 unsigned int val = 0;
774 int i;
775
776 spin_lock_irq(&chip->reg_lock);
777 reg = inw(FM801_REG(chip, GPIO_CTRL));
778 /* use GPIO lines, set data direction to input */
779 reg |= FM801_GPIO_GS(TEA_256PCS_DATA) |
780 FM801_GPIO_GS(TEA_256PCS_WRITE_ENABLE) |
781 FM801_GPIO_GS(TEA_256PCS_BUS_CLOCK) |
782 FM801_GPIO_GD(TEA_256PCS_DATA) |
783 FM801_GPIO_GP(TEA_256PCS_DATA) |
784 FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE);
785 /* all of lines are in the write direction, except data */
786 /* clear data, write enable and clock lines */
787 reg &= ~(FM801_GPIO_GD(TEA_256PCS_WRITE_ENABLE) |
788 FM801_GPIO_GD(TEA_256PCS_BUS_CLOCK) |
789 FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK));
790
791 for (i = 0; i < 24; i++) {
792 reg &= ~FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
793 outw(reg, FM801_REG(chip, GPIO_CTRL));
794 udelay(1);
795 reg |= FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
796 outw(reg, FM801_REG(chip, GPIO_CTRL));
797 udelay(1);
798 val <<= 1;
799 if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_256PCS_DATA))
800 val |= 1;
801 }
802
803 spin_unlock_irq(&chip->reg_lock);
804
805 return val;
806}
807
808/* 256PCPR GPIO numbers */
809#define TEA_256PCPR_BUS_CLOCK 0
810#define TEA_256PCPR_DATA 1
811#define TEA_256PCPR_WRITE_ENABLE 2 /* inverted */
812
a5f22156 813static void snd_fm801_tea575x_256pcpr_write(struct snd_tea575x *tea, unsigned int val)
1da177e4 814{
a5f22156 815 struct fm801 *chip = tea->private_data;
1da177e4
LT		 816 unsigned short reg;
817 int i = 25;
818
819 spin_lock_irq(&chip->reg_lock);
820 reg = inw(FM801_REG(chip, GPIO_CTRL));
821 /* use GPIO lines and set write enable bit */
822 reg |= FM801_GPIO_GS(TEA_256PCPR_DATA) |
823 FM801_GPIO_GS(TEA_256PCPR_WRITE_ENABLE) |
824 FM801_GPIO_GS(TEA_256PCPR_BUS_CLOCK);
825 /* all of lines are in the write direction */
826 /* clear data and clock lines */
827 reg &= ~(FM801_GPIO_GD(TEA_256PCPR_DATA) |
828 FM801_GPIO_GD(TEA_256PCPR_WRITE_ENABLE) |
829 FM801_GPIO_GD(TEA_256PCPR_BUS_CLOCK) |
830 FM801_GPIO_GP(TEA_256PCPR_DATA) |
831 FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK) |
832 FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE));
833 outw(reg, FM801_REG(chip, GPIO_CTRL));
834 udelay(1);
835
836 while (i--) {
837 if (val & (1 << i))
838 reg |= FM801_GPIO_GP(TEA_256PCPR_DATA);
839 else
840 reg &= ~FM801_GPIO_GP(TEA_256PCPR_DATA);
841 outw(reg, FM801_REG(chip, GPIO_CTRL));
842 udelay(1);
843 reg |= FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
844 outw(reg, FM801_REG(chip, GPIO_CTRL));
845 reg &= ~FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
846 outw(reg, FM801_REG(chip, GPIO_CTRL));
847 udelay(1);
848 }
849
850 /* and reset the write enable bit */
851 reg |= FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE) |
852 FM801_GPIO_GP(TEA_256PCPR_DATA);
853 outw(reg, FM801_REG(chip, GPIO_CTRL));
854 spin_unlock_irq(&chip->reg_lock);
855}
856
a5f22156 857static unsigned int snd_fm801_tea575x_256pcpr_read(struct snd_tea575x *tea)
1da177e4 858{
a5f22156 859 struct fm801 *chip = tea->private_data;
1da177e4
LT		 860 unsigned short reg;
861 unsigned int val = 0;
862 int i;
863
864 spin_lock_irq(&chip->reg_lock);
865 reg = inw(FM801_REG(chip, GPIO_CTRL));
866 /* use GPIO lines, set data direction to input */
867 reg |= FM801_GPIO_GS(TEA_256PCPR_DATA) |
868 FM801_GPIO_GS(TEA_256PCPR_WRITE_ENABLE) |
869 FM801_GPIO_GS(TEA_256PCPR_BUS_CLOCK) |
870 FM801_GPIO_GD(TEA_256PCPR_DATA) |
871 FM801_GPIO_GP(TEA_256PCPR_DATA) |
872 FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE);
873 /* all of lines are in the write direction, except data */
874 /* clear data, write enable and clock lines */
875 reg &= ~(FM801_GPIO_GD(TEA_256PCPR_WRITE_ENABLE) |
876 FM801_GPIO_GD(TEA_256PCPR_BUS_CLOCK) |
877 FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK));
878
879 for (i = 0; i < 24; i++) {
880 reg &= ~FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
881 outw(reg, FM801_REG(chip, GPIO_CTRL));
882 udelay(1);
883 reg |= FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
884 outw(reg, FM801_REG(chip, GPIO_CTRL));
885 udelay(1);
886 val <<= 1;
887 if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_256PCPR_DATA))
888 val |= 1;
889 }
890
891 spin_unlock_irq(&chip->reg_lock);
892
893 return val;
894}
895
896/* 64PCR GPIO numbers */
897#define TEA_64PCR_BUS_CLOCK 0
898#define TEA_64PCR_WRITE_ENABLE 1 /* inverted */
899#define TEA_64PCR_DATA 2
900
a5f22156 901static void snd_fm801_tea575x_64pcr_write(struct snd_tea575x *tea, unsigned int val)
1da177e4 902{
a5f22156 903 struct fm801 *chip = tea->private_data;
1da177e4
LT		 904 unsigned short reg;
905 int i = 25;
906
907 spin_lock_irq(&chip->reg_lock);
908 reg = inw(FM801_REG(chip, GPIO_CTRL));
909 /* use GPIO lines and set write enable bit */
910 reg |= FM801_GPIO_GS(TEA_64PCR_DATA) |
911 FM801_GPIO_GS(TEA_64PCR_WRITE_ENABLE) |
912 FM801_GPIO_GS(TEA_64PCR_BUS_CLOCK);
913 /* all of lines are in the write direction */
914 /* clear data and clock lines */
915 reg &= ~(FM801_GPIO_GD(TEA_64PCR_DATA) |
916 FM801_GPIO_GD(TEA_64PCR_WRITE_ENABLE) |
917 FM801_GPIO_GD(TEA_64PCR_BUS_CLOCK) |
918 FM801_GPIO_GP(TEA_64PCR_DATA) |
919 FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK) |
920 FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE));
921 outw(reg, FM801_REG(chip, GPIO_CTRL));
922 udelay(1);
923
924 while (i--) {
925 if (val & (1 << i))
926 reg |= FM801_GPIO_GP(TEA_64PCR_DATA);
927 else
928 reg &= ~FM801_GPIO_GP(TEA_64PCR_DATA);
929 outw(reg, FM801_REG(chip, GPIO_CTRL));
930 udelay(1);
931 reg |= FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
932 outw(reg, FM801_REG(chip, GPIO_CTRL));
933 reg &= ~FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
934 outw(reg, FM801_REG(chip, GPIO_CTRL));
935 udelay(1);
936 }
937
938 /* and reset the write enable bit */
939 reg |= FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE) |
940 FM801_GPIO_GP(TEA_64PCR_DATA);
941 outw(reg, FM801_REG(chip, GPIO_CTRL));
942 spin_unlock_irq(&chip->reg_lock);
943}
944
a5f22156 945static unsigned int snd_fm801_tea575x_64pcr_read(struct snd_tea575x *tea)
1da177e4 946{
a5f22156 947 struct fm801 *chip = tea->private_data;
1da177e4
LT		 948 unsigned short reg;
949 unsigned int val = 0;
950 int i;
951
952 spin_lock_irq(&chip->reg_lock);
953 reg = inw(FM801_REG(chip, GPIO_CTRL));
954 /* use GPIO lines, set data direction to input */
955 reg |= FM801_GPIO_GS(TEA_64PCR_DATA) |
956 FM801_GPIO_GS(TEA_64PCR_WRITE_ENABLE) |
957 FM801_GPIO_GS(TEA_64PCR_BUS_CLOCK) |
958 FM801_GPIO_GD(TEA_64PCR_DATA) |
959 FM801_GPIO_GP(TEA_64PCR_DATA) |
960 FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE);
961 /* all of lines are in the write direction, except data */
962 /* clear data, write enable and clock lines */
963 reg &= ~(FM801_GPIO_GD(TEA_64PCR_WRITE_ENABLE) |
964 FM801_GPIO_GD(TEA_64PCR_BUS_CLOCK) |
965 FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK));
966
967 for (i = 0; i < 24; i++) {
968 reg &= ~FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
969 outw(reg, FM801_REG(chip, GPIO_CTRL));
970 udelay(1);
971 reg |= FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
972 outw(reg, FM801_REG(chip, GPIO_CTRL));
973 udelay(1);
974 val <<= 1;
975 if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_64PCR_DATA))
976 val |= 1;
977 }
978
979 spin_unlock_irq(&chip->reg_lock);
980
981 return val;
982}
983
69252128
AS		 984static void snd_fm801_tea575x_64pcr_mute(struct snd_tea575x *tea,
985 unsigned int mute)
986{
987 struct fm801 *chip = tea->private_data;
988 unsigned short reg;
989
990 spin_lock_irq(&chip->reg_lock);
991
992 reg = inw(FM801_REG(chip, GPIO_CTRL));
993 if (mute)
994 /* 0xf800 (mute) */
995 reg &= ~FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE);
996 else
997 /* 0xf802 (unmute) */
998 reg |= FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE);
999 outw(reg, FM801_REG(chip, GPIO_CTRL));
1000 udelay(1);
1001
1002 spin_unlock_irq(&chip->reg_lock);
1003}
1004
1da177e4
LT		 1005static struct snd_tea575x_ops snd_fm801_tea_ops[3] = {
1006 {
1007 /* 1 = MediaForte 256-PCS */
1008 .write = snd_fm801_tea575x_256pcs_write,
1009 .read = snd_fm801_tea575x_256pcs_read,
1010 },
1011 {
1012 /* 2 = MediaForte 256-PCPR */
1013 .write = snd_fm801_tea575x_256pcpr_write,
1014 .read = snd_fm801_tea575x_256pcpr_read,
1015 },
1016 {
1017 /* 3 = MediaForte 64-PCR */
1018 .write = snd_fm801_tea575x_64pcr_write,
1019 .read = snd_fm801_tea575x_64pcr_read,
69252128 1020 .mute = snd_fm801_tea575x_64pcr_mute,
1da177e4
LT		 1021 }
1022};
1023#endif
1024
1025/*
1026 * Mixer routines
1027 */
1028
1029#define FM801_SINGLE(xname, reg, shift, mask, invert) \
1030{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_fm801_info_single, \
1031 .get = snd_fm801_get_single, .put = snd_fm801_put_single, \
1032 .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
1033
a5f22156
TI		 1034static int snd_fm801_info_single(struct snd_kcontrol *kcontrol,
1035 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1036{
1037 int mask = (kcontrol->private_value >> 16) & 0xff;
1038
1039 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1040 uinfo->count = 1;
1041 uinfo->value.integer.min = 0;
1042 uinfo->value.integer.max = mask;
1043 return 0;
1044}
1045
a5f22156
TI		 1046static int snd_fm801_get_single(struct snd_kcontrol *kcontrol,
1047 struct snd_ctl_elem_value *ucontrol)
1da177e4 1048{
a5f22156 1049 struct fm801 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1050 int reg = kcontrol->private_value & 0xff;
1051 int shift = (kcontrol->private_value >> 8) & 0xff;
1052 int mask = (kcontrol->private_value >> 16) & 0xff;
1053 int invert = (kcontrol->private_value >> 24) & 0xff;
1054
1055 ucontrol->value.integer.value[0] = (inw(chip->port + reg) >> shift) & mask;
1056 if (invert)
1057 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
1058 return 0;
1059}
1060
a5f22156
TI		 1061static int snd_fm801_put_single(struct snd_kcontrol *kcontrol,
1062 struct snd_ctl_elem_value *ucontrol)
1da177e4 1063{
a5f22156 1064 struct fm801 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1065 int reg = kcontrol->private_value & 0xff;
1066 int shift = (kcontrol->private_value >> 8) & 0xff;
1067 int mask = (kcontrol->private_value >> 16) & 0xff;
1068 int invert = (kcontrol->private_value >> 24) & 0xff;
1069 unsigned short val;
1070
1071 val = (ucontrol->value.integer.value[0] & mask);
1072 if (invert)
1073 val = mask - val;
1074 return snd_fm801_update_bits(chip, reg, mask << shift, val << shift);
1075}
1076
1077#define FM801_DOUBLE(xname, reg, shift_left, shift_right, mask, invert) \
1078{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_fm801_info_double, \
1079 .get = snd_fm801_get_double, .put = snd_fm801_put_double, \
1080 .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24) }
666c70ff
TI		 1081#define FM801_DOUBLE_TLV(xname, reg, shift_left, shift_right, mask, invert, xtlv) \
1082{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1083 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
1084 .name = xname, .info = snd_fm801_info_double, \
1085 .get = snd_fm801_get_double, .put = snd_fm801_put_double, \
1086 .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24), \
1087 .tlv = { .p = (xtlv) } }
1da177e4 1088
a5f22156
TI		 1089static int snd_fm801_info_double(struct snd_kcontrol *kcontrol,
1090 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1091{
1092 int mask = (kcontrol->private_value >> 16) & 0xff;
1093
1094 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1095 uinfo->count = 2;
1096 uinfo->value.integer.min = 0;
1097 uinfo->value.integer.max = mask;
1098 return 0;
1099}
1100
a5f22156
TI		 1101static int snd_fm801_get_double(struct snd_kcontrol *kcontrol,
1102 struct snd_ctl_elem_value *ucontrol)
1da177e4 1103{
a5f22156 1104 struct fm801 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1105 int reg = kcontrol->private_value & 0xff;
1106 int shift_left = (kcontrol->private_value >> 8) & 0x0f;
1107 int shift_right = (kcontrol->private_value >> 12) & 0x0f;
1108 int mask = (kcontrol->private_value >> 16) & 0xff;
1109 int invert = (kcontrol->private_value >> 24) & 0xff;
1110
1111 spin_lock_irq(&chip->reg_lock);
1112 ucontrol->value.integer.value[0] = (inw(chip->port + reg) >> shift_left) & mask;
1113 ucontrol->value.integer.value[1] = (inw(chip->port + reg) >> shift_right) & mask;
1114 spin_unlock_irq(&chip->reg_lock);
1115 if (invert) {
1116 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
1117 ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
1118 }
1119 return 0;
1120}
1121
a5f22156
TI		 1122static int snd_fm801_put_double(struct snd_kcontrol *kcontrol,
1123 struct snd_ctl_elem_value *ucontrol)
1da177e4 1124{
a5f22156 1125 struct fm801 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1126 int reg = kcontrol->private_value & 0xff;
1127 int shift_left = (kcontrol->private_value >> 8) & 0x0f;
1128 int shift_right = (kcontrol->private_value >> 12) & 0x0f;
1129 int mask = (kcontrol->private_value >> 16) & 0xff;
1130 int invert = (kcontrol->private_value >> 24) & 0xff;
1131 unsigned short val1, val2;
1132
1133 val1 = ucontrol->value.integer.value[0] & mask;
1134 val2 = ucontrol->value.integer.value[1] & mask;
1135 if (invert) {
1136 val1 = mask - val1;
1137 val2 = mask - val2;
1138 }
1139 return snd_fm801_update_bits(chip, reg,
1140 (mask << shift_left) | (mask << shift_right),
1141 (val1 << shift_left ) | (val2 << shift_right));
1142}
1143
a5f22156
TI		 1144static int snd_fm801_info_mux(struct snd_kcontrol *kcontrol,
1145 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1146{
1147 static char *texts[5] = {
1148 "AC97 Primary", "FM", "I2S", "PCM", "AC97 Secondary"
1149 };
1150
1151 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1152 uinfo->count = 1;
1153 uinfo->value.enumerated.items = 5;
1154 if (uinfo->value.enumerated.item > 4)
1155 uinfo->value.enumerated.item = 4;
1156 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1157 return 0;
1158}
1159
a5f22156
TI		 1160static int snd_fm801_get_mux(struct snd_kcontrol *kcontrol,
1161 struct snd_ctl_elem_value *ucontrol)
1da177e4 1162{
a5f22156 1163 struct fm801 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1164 unsigned short val;
1165
1166 val = inw(FM801_REG(chip, REC_SRC)) & 7;
1167 if (val > 4)
1168 val = 4;
1169 ucontrol->value.enumerated.item[0] = val;
1170 return 0;
1171}
1172
a5f22156
TI		 1173static int snd_fm801_put_mux(struct snd_kcontrol *kcontrol,
1174 struct snd_ctl_elem_value *ucontrol)
1da177e4 1175{
a5f22156 1176 struct fm801 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1177 unsigned short val;
1178
1179 if ((val = ucontrol->value.enumerated.item[0]) > 4)
1180 return -EINVAL;
1181 return snd_fm801_update_bits(chip, FM801_REC_SRC, 7, val);
1182}
1183
0cb29ea0 1184static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -3450, 150, 0);
666c70ff 1185
a5f22156 1186#define FM801_CONTROLS ARRAY_SIZE(snd_fm801_controls)
1da177e4 1187
a5f22156 1188static struct snd_kcontrol_new snd_fm801_controls[] __devinitdata = {
666c70ff
TI		 1189FM801_DOUBLE_TLV("Wave Playback Volume", FM801_PCM_VOL, 0, 8, 31, 1,
1190 db_scale_dsp),
1da177e4 1191FM801_SINGLE("Wave Playback Switch", FM801_PCM_VOL, 15, 1, 1),
666c70ff
TI		 1192FM801_DOUBLE_TLV("I2S Playback Volume", FM801_I2S_VOL, 0, 8, 31, 1,
1193 db_scale_dsp),
1da177e4 1194FM801_SINGLE("I2S Playback Switch", FM801_I2S_VOL, 15, 1, 1),
666c70ff
TI		 1195FM801_DOUBLE_TLV("FM Playback Volume", FM801_FM_VOL, 0, 8, 31, 1,
1196 db_scale_dsp),
1da177e4
LT		 1197FM801_SINGLE("FM Playback Switch", FM801_FM_VOL, 15, 1, 1),
1198{
1199 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1200 .name = "Digital Capture Source",
1201 .info = snd_fm801_info_mux,
1202 .get = snd_fm801_get_mux,
1203 .put = snd_fm801_put_mux,
1204}
1205};
1206
a5f22156 1207#define FM801_CONTROLS_MULTI ARRAY_SIZE(snd_fm801_controls_multi)
1da177e4 1208
a5f22156 1209static struct snd_kcontrol_new snd_fm801_controls_multi[] __devinitdata = {
1da177e4
LT		 1210FM801_SINGLE("AC97 2ch->4ch Copy Switch", FM801_CODEC_CTRL, 7, 1, 0),
1211FM801_SINGLE("AC97 18-bit Switch", FM801_CODEC_CTRL, 10, 1, 0),
10e8d78a
CL		 1212FM801_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), FM801_I2S_MODE, 8, 1, 0),
1213FM801_SINGLE(SNDRV_CTL_NAME_IEC958("Raw Data ",PLAYBACK,SWITCH), FM801_I2S_MODE, 9, 1, 0),
1214FM801_SINGLE(SNDRV_CTL_NAME_IEC958("Raw Data ",CAPTURE,SWITCH), FM801_I2S_MODE, 10, 1, 0),
1215FM801_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), FM801_GEN_CTRL, 2, 1, 0),
1da177e4
LT		 1216};
1217
a5f22156 1218static void snd_fm801_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1da177e4 1219{
a5f22156 1220 struct fm801 *chip = bus->private_data;
1da177e4
LT		 1221 chip->ac97_bus = NULL;
1222}
1223
a5f22156 1224static void snd_fm801_mixer_free_ac97(struct snd_ac97 *ac97)
1da177e4 1225{
a5f22156 1226 struct fm801 *chip = ac97->private_data;
1da177e4
LT		 1227 if (ac97->num == 0) {
1228 chip->ac97 = NULL;
1229 } else {
1230 chip->ac97_sec = NULL;
1231 }
1232}
1233
a5f22156 1234static int __devinit snd_fm801_mixer(struct fm801 *chip)
1da177e4 1235{
a5f22156 1236 struct snd_ac97_template ac97;
1da177e4
LT		 1237 unsigned int i;
1238 int err;
a5f22156 1239 static struct snd_ac97_bus_ops ops = {
1da177e4
LT		 1240 .write = snd_fm801_codec_write,
1241 .read = snd_fm801_codec_read,
1242 };
1243
1244 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1245 return err;
1246 chip->ac97_bus->private_free = snd_fm801_mixer_free_ac97_bus;
1247
1248 memset(&ac97, 0, sizeof(ac97));
1249 ac97.private_data = chip;
1250 ac97.private_free = snd_fm801_mixer_free_ac97;
1251 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1252 return err;
1253 if (chip->secondary) {
1254 ac97.num = 1;
1255 ac97.addr = chip->secondary_addr;
1256 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_sec)) < 0)
1257 return err;
1258 }
1259 for (i = 0; i < FM801_CONTROLS; i++)
1260 snd_ctl_add(chip->card, snd_ctl_new1(&snd_fm801_controls[i], chip));
1261 if (chip->multichannel) {
1262 for (i = 0; i < FM801_CONTROLS_MULTI; i++)
1263 snd_ctl_add(chip->card, snd_ctl_new1(&snd_fm801_controls_multi[i], chip));
1264 }
1265 return 0;
1266}
1267
1268/*
1269 * initialization routines
1270 */
1271
b1e9ed26
TI		 1272static int wait_for_codec(struct fm801 *chip, unsigned int codec_id,
1273 unsigned short reg, unsigned long waits)
1274{
1275 unsigned long timeout = jiffies + waits;
1276
1277 outw(FM801_AC97_READ | (codec_id << FM801_AC97_ADDR_SHIFT) | reg,
1278 FM801_REG(chip, AC97_CMD));
1279 udelay(5);
1280 do {
1281 if ((inw(FM801_REG(chip, AC97_CMD)) & (FM801_AC97_VALID|FM801_AC97_BUSY))
1282 == FM801_AC97_VALID)
1283 return 0;
1284 schedule_timeout_uninterruptible(1);
1285 } while (time_after(timeout, jiffies));
1286 return -EIO;
1287}
1288
1289static int snd_fm801_chip_init(struct fm801 *chip, int resume)
1290{
b1e9ed26
TI		 1291 unsigned short cmdw;
1292
fb716c0b 1293 if (chip->tea575x_tuner & TUNER_ONLY)
e0a5d82a
AS		 1294 goto __ac97_ok;
1295
b1e9ed26
TI		 1296 /* codec cold reset + AC'97 warm reset */
1297 outw((1<<5) | (1<<6), FM801_REG(chip, CODEC_CTRL));
1298 inw(FM801_REG(chip, CODEC_CTRL)); /* flush posting data */
1299 udelay(100);
1300 outw(0, FM801_REG(chip, CODEC_CTRL));
1301
fb716c0b
OZ		 1302 if (wait_for_codec(chip, 0, AC97_RESET, msecs_to_jiffies(750)) < 0)
1303 if (!resume) {
1304 snd_printk(KERN_INFO "Primary AC'97 codec not found, "
1305 "assume SF64-PCR (tuner-only)\n");
1306 chip->tea575x_tuner = 3 | TUNER_ONLY;
1307 goto __ac97_ok;
1308 }
b1e9ed26
TI		 1309
1310 if (chip->multichannel) {
1311 if (chip->secondary_addr) {
1312 wait_for_codec(chip, chip->secondary_addr,
1313 AC97_VENDOR_ID1, msecs_to_jiffies(50));
1314 } else {
1315 /* my card has the secondary codec */
1316 /* at address #3, so the loop is inverted */
58e4334e
HH		 1317 int i;
1318 for (i = 3; i > 0; i--) {
1319 if (!wait_for_codec(chip, i, AC97_VENDOR_ID1,
b1e9ed26
TI		 1320 msecs_to_jiffies(50))) {
1321 cmdw = inw(FM801_REG(chip, AC97_DATA));
1322 if (cmdw != 0xffff && cmdw != 0) {
1323 chip->secondary = 1;
58e4334e 1324 chip->secondary_addr = i;
b1e9ed26
TI		 1325 break;
1326 }
1327 }
1328 }
1329 }
1330
1331 /* the recovery phase, it seems that probing for non-existing codec might */
1332 /* cause timeout problems */
1333 wait_for_codec(chip, 0, AC97_VENDOR_ID1, msecs_to_jiffies(750));
1334 }
1335
6bbe13ec
JK		 1336 __ac97_ok:
1337
b1e9ed26
TI		 1338 /* init volume */
1339 outw(0x0808, FM801_REG(chip, PCM_VOL));
1340 outw(0x9f1f, FM801_REG(chip, FM_VOL));
1341 outw(0x8808, FM801_REG(chip, I2S_VOL));
1342
1343 /* I2S control - I2S mode */
1344 outw(0x0003, FM801_REG(chip, I2S_MODE));
1345
6bbe13ec 1346 /* interrupt setup */
b1e9ed26 1347 cmdw = inw(FM801_REG(chip, IRQ_MASK));
6bbe13ec
JK		 1348 if (chip->irq < 0)
1349 cmdw |= 0x00c3; /* mask everything, no PCM nor MPU */
1350 else
1351 cmdw &= ~0x0083; /* unmask MPU, PLAYBACK & CAPTURE */
b1e9ed26
TI		 1352 outw(cmdw, FM801_REG(chip, IRQ_MASK));
1353
1354 /* interrupt clear */
1355 outw(FM801_IRQ_PLAYBACK|FM801_IRQ_CAPTURE|FM801_IRQ_MPU, FM801_REG(chip, IRQ_STATUS));
1356
1357 return 0;
1358}
1359
1360
a5f22156 1361static int snd_fm801_free(struct fm801 *chip)
1da177e4
LT		 1362{
1363 unsigned short cmdw;
1364
1365 if (chip->irq < 0)
1366 goto __end_hw;
1367
1368 /* interrupt setup - mask everything */
1369 cmdw = inw(FM801_REG(chip, IRQ_MASK));
1370 cmdw |= 0x00c3;
1371 outw(cmdw, FM801_REG(chip, IRQ_MASK));
1372
1373 __end_hw:
1374#ifdef TEA575X_RADIO
1375 snd_tea575x_exit(&chip->tea);
1376#endif
1377 if (chip->irq >= 0)
a5f22156 1378 free_irq(chip->irq, chip);
1da177e4
LT		 1379 pci_release_regions(chip->pci);
1380 pci_disable_device(chip->pci);
1381
1382 kfree(chip);
1383 return 0;
1384}
1385
a5f22156 1386static int snd_fm801_dev_free(struct snd_device *device)
1da177e4 1387{
a5f22156 1388 struct fm801 *chip = device->device_data;
1da177e4
LT		 1389 return snd_fm801_free(chip);
1390}
1391
a5f22156 1392static int __devinit snd_fm801_create(struct snd_card *card,
1da177e4
LT		 1393 struct pci_dev * pci,
1394 int tea575x_tuner,
a5f22156 1395 struct fm801 ** rchip)
1da177e4 1396{
a5f22156 1397 struct fm801 *chip;
1da177e4 1398 int err;
a5f22156 1399 static struct snd_device_ops ops = {
1da177e4
LT		 1400 .dev_free = snd_fm801_dev_free,
1401 };
1402
1403 *rchip = NULL;
1404 if ((err = pci_enable_device(pci)) < 0)
1405 return err;
e560d8d8 1406 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 1407 if (chip == NULL) {
1408 pci_disable_device(pci);
1409 return -ENOMEM;
1410 }
1411 spin_lock_init(&chip->reg_lock);
1412 chip->card = card;
1413 chip->pci = pci;
1414 chip->irq = -1;
6bbe13ec 1415 chip->tea575x_tuner = tea575x_tuner;
1da177e4
LT		 1416 if ((err = pci_request_regions(pci, "FM801")) < 0) {
1417 kfree(chip);
1418 pci_disable_device(pci);
1419 return err;
1420 }
1421 chip->port = pci_resource_start(pci, 0);
fb716c0b 1422 if ((tea575x_tuner & TUNER_ONLY) == 0) {
437a5a46 1423 if (request_irq(pci->irq, snd_fm801_interrupt, IRQF_SHARED,
6bbe13ec
JK		 1424 "FM801", chip)) {
1425 snd_printk(KERN_ERR "unable to grab IRQ %d\n", chip->irq);
1426 snd_fm801_free(chip);
1427 return -EBUSY;
1428 }
1429 chip->irq = pci->irq;
1430 pci_set_master(pci);
1da177e4 1431 }
1da177e4 1432
44c10138 1433 if (pci->revision >= 0xb1) /* FM801-AU */
1da177e4
LT		 1434 chip->multichannel = 1;
1435
b1e9ed26 1436 snd_fm801_chip_init(chip, 0);
fb716c0b
OZ		 1437 /* init might set tuner access method */
1438 tea575x_tuner = chip->tea575x_tuner;
1439
1440 if (chip->irq >= 0 && (tea575x_tuner & TUNER_ONLY)) {
1441 pci_clear_master(pci);
1442 free_irq(chip->irq, chip);
1443 chip->irq = -1;
1444 }
1da177e4
LT		 1445
1446 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1447 snd_fm801_free(chip);
1448 return err;
1449 }
1450
1451 snd_card_set_dev(card, &pci->dev);
1452
1453#ifdef TEA575X_RADIO
fb716c0b
OZ		 1454 if ((tea575x_tuner & TUNER_TYPE_MASK) > 0 &&
1455 (tea575x_tuner & TUNER_TYPE_MASK) < 4) {
1da177e4
LT		 1456 chip->tea.dev_nr = tea575x_tuner >> 16;
1457 chip->tea.card = card;
1458 chip->tea.freq_fixup = 10700;
1459 chip->tea.private_data = chip;
fb716c0b 1460 chip->tea.ops = &snd_fm801_tea_ops[(tea575x_tuner & TUNER_TYPE_MASK) - 1];
1da177e4
LT		 1461 snd_tea575x_init(&chip->tea);
1462 }
1463#endif
1464
1465 *rchip = chip;
1466 return 0;
1467}
1468
1469static int __devinit snd_card_fm801_probe(struct pci_dev *pci,
1470 const struct pci_device_id *pci_id)
1471{
1472 static int dev;
a5f22156
TI		 1473 struct snd_card *card;
1474 struct fm801 *chip;
1475 struct snd_opl3 *opl3;
1da177e4
LT		 1476 int err;
1477
1478 if (dev >= SNDRV_CARDS)
1479 return -ENODEV;
1480 if (!enable[dev]) {
1481 dev++;
1482 return -ENOENT;
1483 }
1484
e58de7ba
TI		 1485 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
1486 if (err < 0)
1487 return err;
1da177e4
LT		 1488 if ((err = snd_fm801_create(card, pci, tea575x_tuner[dev], &chip)) < 0) {
1489 snd_card_free(card);
1490 return err;
1491 }
b1e9ed26 1492 card->private_data = chip;
1da177e4
LT		 1493
1494 strcpy(card->driver, "FM801");
1495 strcpy(card->shortname, "ForteMedia FM801-");
1496 strcat(card->shortname, chip->multichannel ? "AU" : "AS");
1497 sprintf(card->longname, "%s at 0x%lx, irq %i",
1498 card->shortname, chip->port, chip->irq);
1499
fb716c0b 1500 if (chip->tea575x_tuner & TUNER_ONLY)
e0a5d82a
AS		 1501 goto __fm801_tuner_only;
1502
1da177e4
LT		 1503 if ((err = snd_fm801_pcm(chip, 0, NULL)) < 0) {
1504 snd_card_free(card);
1505 return err;
1506 }
1507 if ((err = snd_fm801_mixer(chip)) < 0) {
1508 snd_card_free(card);
1509 return err;
1510 }
1511 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_FM801,
302e4c2f
TI		 1512 FM801_REG(chip, MPU401_DATA),
1513 MPU401_INFO_INTEGRATED,
1da177e4
LT		 1514 chip->irq, 0, &chip->rmidi)) < 0) {
1515 snd_card_free(card);
1516 return err;
1517 }
1518 if ((err = snd_opl3_create(card, FM801_REG(chip, OPL3_BANK0),
1519 FM801_REG(chip, OPL3_BANK1),
1520 OPL3_HW_OPL3_FM801, 1, &opl3)) < 0) {
1521 snd_card_free(card);
1522 return err;
1523 }
1524 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1525 snd_card_free(card);
1526 return err;
1527 }
1528
e0a5d82a 1529 __fm801_tuner_only:
1da177e4
LT		 1530 if ((err = snd_card_register(card)) < 0) {
1531 snd_card_free(card);
1532 return err;
1533 }
1534 pci_set_drvdata(pci, card);
1535 dev++;
1536 return 0;
1537}
1538
1539static void __devexit snd_card_fm801_remove(struct pci_dev *pci)
1540{
1541 snd_card_free(pci_get_drvdata(pci));
1542 pci_set_drvdata(pci, NULL);
1543}
1544
b1e9ed26
TI		 1545#ifdef CONFIG_PM
1546static unsigned char saved_regs[] = {
1547 FM801_PCM_VOL, FM801_I2S_VOL, FM801_FM_VOL, FM801_REC_SRC,
1548 FM801_PLY_CTRL, FM801_PLY_COUNT, FM801_PLY_BUF1, FM801_PLY_BUF2,
1549 FM801_CAP_CTRL, FM801_CAP_COUNT, FM801_CAP_BUF1, FM801_CAP_BUF2,
1550 FM801_CODEC_CTRL, FM801_I2S_MODE, FM801_VOLUME, FM801_GEN_CTRL,
1551};
1552
1553static int snd_fm801_suspend(struct pci_dev *pci, pm_message_t state)
1554{
1555 struct snd_card *card = pci_get_drvdata(pci);
1556 struct fm801 *chip = card->private_data;
1557 int i;
1558
1559 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1560 snd_pcm_suspend_all(chip->pcm);
1561 snd_ac97_suspend(chip->ac97);
1562 snd_ac97_suspend(chip->ac97_sec);
1563 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
1564 chip->saved_regs[i] = inw(chip->port + saved_regs[i]);
1565 /* FIXME: tea575x suspend */
1566
b1e9ed26
TI		 1567 pci_disable_device(pci);
1568 pci_save_state(pci);
30b35399 1569 pci_set_power_state(pci, pci_choose_state(pci, state));
b1e9ed26
TI		 1570 return 0;
1571}
1572
1573static int snd_fm801_resume(struct pci_dev *pci)
1574{
1575 struct snd_card *card = pci_get_drvdata(pci);
1576 struct fm801 *chip = card->private_data;
1577 int i;
1578
b1e9ed26 1579 pci_set_power_state(pci, PCI_D0);
30b35399
TI		 1580 pci_restore_state(pci);
1581 if (pci_enable_device(pci) < 0) {
1582 printk(KERN_ERR "fm801: pci_enable_device failed, "
1583 "disabling device\n");
1584 snd_card_disconnect(card);
1585 return -EIO;
1586 }
b1e9ed26
TI		 1587 pci_set_master(pci);
1588
1589 snd_fm801_chip_init(chip, 1);
1590 snd_ac97_resume(chip->ac97);
1591 snd_ac97_resume(chip->ac97_sec);
1592 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
1593 outw(chip->saved_regs[i], chip->port + saved_regs[i]);
1594
1595 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1596 return 0;
1597}
1598#endif
1599
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LT		 1600static struct pci_driver driver = {
1601 .name = "FM801",
1602 .id_table = snd_fm801_ids,
1603 .probe = snd_card_fm801_probe,
1604 .remove = __devexit_p(snd_card_fm801_remove),
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TI		 1605#ifdef CONFIG_PM
1606 .suspend = snd_fm801_suspend,
1607 .resume = snd_fm801_resume,
1608#endif
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LT		 1609};
1610
1611static int __init alsa_card_fm801_init(void)
1612{
01d25d46 1613 return pci_register_driver(&driver);
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LT		 1614}
1615
1616static void __exit alsa_card_fm801_exit(void)
1617{
1618 pci_unregister_driver(&driver);
1619}
1620
1621module_init(alsa_card_fm801_init)
1622module_exit(alsa_card_fm801_exit)
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