[linux.git] / drivers / spi / spi-bcm63xx.c

/*
 * Broadcom BCM63xx SPI controller support
 *
 * Copyright (C) 2009-2012 Florian Fainelli <[email protected]>
 * Copyright (C) 2010 Tanguy Bouzeloc <[email protected]>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the
 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
 */

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/spi/spi.h>
#include <linux/completion.h>
#include <linux/err.h>
#include <linux/pm_runtime.h>

#include <bcm63xx_dev_spi.h>

#define BCM63XX_SPI_MAX_PREPEND		15

struct bcm63xx_spi {
	struct completion	done;

	void __iomem		*regs;
	int			irq;

	/* Platform data */
	unsigned		fifo_size;
	unsigned int		msg_type_shift;
	unsigned int		msg_ctl_width;

	/* data iomem */
	u8 __iomem		*tx_io;
	const u8 __iomem	*rx_io;

	struct clk		*clk;
	struct platform_device	*pdev;
};

static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
				unsigned int offset)
{
	return bcm_readb(bs->regs + bcm63xx_spireg(offset));
}

static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
				unsigned int offset)
{
	return bcm_readw(bs->regs + bcm63xx_spireg(offset));
}

static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
				  u8 value, unsigned int offset)
{
	bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
}

static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
				  u16 value, unsigned int offset)
{
	bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
}

static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
	{ 20000000, SPI_CLK_20MHZ },
	{ 12500000, SPI_CLK_12_50MHZ },
	{  6250000, SPI_CLK_6_250MHZ },
	{  3125000, SPI_CLK_3_125MHZ },
	{  1563000, SPI_CLK_1_563MHZ },
	{   781000, SPI_CLK_0_781MHZ },
	{   391000, SPI_CLK_0_391MHZ }
};

static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
				      struct spi_transfer *t)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	u8 clk_cfg, reg;
	int i;

	/* Find the closest clock configuration */
	for (i = 0; i < SPI_CLK_MASK; i++) {
		if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
			clk_cfg = bcm63xx_spi_freq_table[i][1];
			break;
		}
	}

	/* No matching configuration found, default to lowest */
	if (i == SPI_CLK_MASK)
		clk_cfg = SPI_CLK_0_391MHZ;

	/* clear existing clock configuration bits of the register */
	reg = bcm_spi_readb(bs, SPI_CLK_CFG);
	reg &= ~SPI_CLK_MASK;
	reg |= clk_cfg;

	bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
	dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
		clk_cfg, t->speed_hz);
}

/* the spi->mode bits understood by this driver: */
#define MODEBITS (SPI_CPOL | SPI_CPHA)

static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
				unsigned int num_transfers)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	u16 msg_ctl;
	u16 cmd;
	u8 rx_tail;
	unsigned int i, timeout = 0, prepend_len = 0, len = 0;
	struct spi_transfer *t = first;
	bool do_rx = false;
	bool do_tx = false;

	/* Disable the CMD_DONE interrupt */
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
		t->tx_buf, t->rx_buf, t->len);

	if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
		prepend_len = t->len;

	/* prepare the buffer */
	for (i = 0; i < num_transfers; i++) {
		if (t->tx_buf) {
			do_tx = true;
			memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);

			/* don't prepend more than one tx */
			if (t != first)
				prepend_len = 0;
		}

		if (t->rx_buf) {
			do_rx = true;
			/* prepend is half-duplex write only */
			if (t == first)
				prepend_len = 0;
		}

		len += t->len;

		t = list_entry(t->transfer_list.next, struct spi_transfer,
			       transfer_list);
	}

	reinit_completion(&bs->done);

	/* Fill in the Message control register */
	msg_ctl = (len << SPI_BYTE_CNT_SHIFT);

	if (do_rx && do_tx && prepend_len == 0)
		msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
	else if (do_rx)
		msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
	else if (do_tx)
		msg_ctl |= (SPI_HD_W << bs->msg_type_shift);

	switch (bs->msg_ctl_width) {
	case 8:
		bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
		break;
	case 16:
		bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
		break;
	}

	/* Issue the transfer */
	cmd = SPI_CMD_START_IMMEDIATE;
	cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
	cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
	bcm_spi_writew(bs, cmd, SPI_CMD);

	/* Enable the CMD_DONE interrupt */
	bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);

	timeout = wait_for_completion_timeout(&bs->done, HZ);
	if (!timeout)
		return -ETIMEDOUT;

	if (!do_rx)
		return 0;

	len = 0;
	t = first;
	/* Read out all the data */
	for (i = 0; i < num_transfers; i++) {
		if (t->rx_buf)
			memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);

		if (t != first || prepend_len == 0)
			len += t->len;

		t = list_entry(t->transfer_list.next, struct spi_transfer,
			       transfer_list);
	}

	return 0;
}

static int bcm63xx_spi_transfer_one(struct spi_master *master,
					struct spi_message *m)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	struct spi_transfer *t, *first = NULL;
	struct spi_device *spi = m->spi;
	int status = 0;
	unsigned int n_transfers = 0, total_len = 0;
	bool can_use_prepend = false;

	/*
	 * This SPI controller does not support keeping CS active after a
	 * transfer.
	 * Work around this by merging as many transfers we can into one big
	 * full-duplex transfers.
	 */
	list_for_each_entry(t, &m->transfers, transfer_list) {
		if (!first)
			first = t;

		n_transfers++;
		total_len += t->len;

		if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
		    first->len <= BCM63XX_SPI_MAX_PREPEND)
			can_use_prepend = true;
		else if (can_use_prepend && t->tx_buf)
			can_use_prepend = false;

		/* we can only transfer one fifo worth of data */
		if ((can_use_prepend &&
		     total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
		    (!can_use_prepend && total_len > bs->fifo_size)) {
			dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
				total_len, bs->fifo_size);
			status = -EINVAL;
			goto exit;
		}

		/* all combined transfers have to have the same speed */
		if (t->speed_hz != first->speed_hz) {
			dev_err(&spi->dev, "unable to change speed between transfers\n");
			status = -EINVAL;
			goto exit;
		}

		/* CS will be deasserted directly after transfer */
		if (t->delay_usecs) {
			dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
			status = -EINVAL;
			goto exit;
		}

		if (t->cs_change ||
		    list_is_last(&t->transfer_list, &m->transfers)) {
			/* configure adapter for a new transfer */
			bcm63xx_spi_setup_transfer(spi, first);

			/* send the data */
			status = bcm63xx_txrx_bufs(spi, first, n_transfers);
			if (status)
				goto exit;

			m->actual_length += total_len;

			first = NULL;
			n_transfers = 0;
			total_len = 0;
			can_use_prepend = false;
		}
	}
exit:
	m->status = status;
	spi_finalize_current_message(master);

	return 0;
}

/* This driver supports single master mode only. Hence
 * CMD_DONE is the only interrupt we care about
 */
static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
{
	struct spi_master *master = (struct spi_master *)dev_id;
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	u8 intr;

	/* Read interupts and clear them immediately */
	intr = bcm_spi_readb(bs, SPI_INT_STATUS);
	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	/* A transfer completed */
	if (intr & SPI_INTR_CMD_DONE)
		complete(&bs->done);

	return IRQ_HANDLED;
}


static int bcm63xx_spi_probe(struct platform_device *pdev)
{
	struct resource *r;
	struct device *dev = &pdev->dev;
	struct bcm63xx_spi_pdata *pdata = dev_get_platdata(&pdev->dev);
	int irq;
	struct spi_master *master;
	struct clk *clk;
	struct bcm63xx_spi *bs;
	int ret;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "no irq\n");
		return -ENXIO;
	}

	clk = devm_clk_get(dev, "spi");
	if (IS_ERR(clk)) {
		dev_err(dev, "no clock for device\n");
		return PTR_ERR(clk);
	}

	master = spi_alloc_master(dev, sizeof(*bs));
	if (!master) {
		dev_err(dev, "out of memory\n");
		return -ENOMEM;
	}

	bs = spi_master_get_devdata(master);
	init_completion(&bs->done);

	platform_set_drvdata(pdev, master);
	bs->pdev = pdev;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	bs->regs = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(bs->regs)) {
		ret = PTR_ERR(bs->regs);
		goto out_err;
	}

	bs->irq = irq;
	bs->clk = clk;
	bs->fifo_size = pdata->fifo_size;

	ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
							pdev->name, master);
	if (ret) {
		dev_err(dev, "unable to request irq\n");
		goto out_err;
	}

	master->bus_num = pdata->bus_num;
	master->num_chipselect = pdata->num_chipselect;
	master->transfer_one_message = bcm63xx_spi_transfer_one;
	master->mode_bits = MODEBITS;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->auto_runtime_pm = true;
	bs->msg_type_shift = pdata->msg_type_shift;
	bs->msg_ctl_width = pdata->msg_ctl_width;
	bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
	bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));

	switch (bs->msg_ctl_width) {
	case 8:
	case 16:
		break;
	default:
		dev_err(dev, "unsupported MSG_CTL width: %d\n",
			 bs->msg_ctl_width);
		goto out_err;
	}

	/* Initialize hardware */
	ret = clk_prepare_enable(bs->clk);
	if (ret)
		goto out_err;

	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);

	/* register and we are done */
	ret = devm_spi_register_master(dev, master);
	if (ret) {
		dev_err(dev, "spi register failed\n");
		goto out_clk_disable;
	}

	dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
		 r->start, irq, bs->fifo_size);

	return 0;

out_clk_disable:
	clk_disable_unprepare(clk);
out_err:
	spi_master_put(master);
	return ret;
}

static int bcm63xx_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	/* reset spi block */
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	/* HW shutdown */
	clk_disable_unprepare(bs->clk);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int bcm63xx_spi_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	spi_master_suspend(master);

	clk_disable_unprepare(bs->clk);

	return 0;
}

static int bcm63xx_spi_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	int ret;

	ret = clk_prepare_enable(bs->clk);
	if (ret)
		return ret;

	spi_master_resume(master);

	return 0;
}
#endif

static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
};

static struct platform_driver bcm63xx_spi_driver = {
	.driver = {
		.name	= "bcm63xx-spi",
		.owner	= THIS_MODULE,
		.pm	= &bcm63xx_spi_pm_ops,
	},
	.probe		= bcm63xx_spi_probe,
	.remove		= bcm63xx_spi_remove,
};

module_platform_driver(bcm63xx_spi_driver);

MODULE_ALIAS("platform:bcm63xx_spi");
MODULE_AUTHOR("Florian Fainelli <[email protected]>");
MODULE_AUTHOR("Tanguy Bouzeloc <[email protected]>");
MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
b42dfed8 FF	1	/*
	2	* Broadcom BCM63xx SPI controller support
	3	*
cde4384e	4	* Copyright (C) 2009-2012 Florian Fainelli <[email protected]>
b42dfed8 FF	5	* Copyright (C) 2010 Tanguy Bouzeloc <[email protected]>
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; either version 2
	10	* of the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the
	19	* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
	20	*/
	21
	22	#include <linux/kernel.h>
b42dfed8 FF	23	#include <linux/clk.h>
	24	#include <linux/io.h>
	25	#include <linux/module.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/delay.h>
	28	#include <linux/interrupt.h>
	29	#include <linux/spi/spi.h>
	30	#include <linux/completion.h>
	31	#include <linux/err.h>
cde4384e	32	#include <linux/pm_runtime.h>
b42dfed8 FF	33
	34	#include <bcm63xx_dev_spi.h>
	35
b17de076 JG	36	#define BCM63XX_SPI_MAX_PREPEND 15
b17de076 JG	37
b42dfed8	38	struct bcm63xx_spi {
b42dfed8 FF	39	struct completion done;
	40
	41	void __iomem *regs;
	42	int irq;
	43
	44	/* Platform data */
b42dfed8	45	unsigned fifo_size;
5a670445 FF	46	unsigned int msg_type_shift;
5a670445 FF	47	unsigned int msg_ctl_width;
b42dfed8	48
b42dfed8 FF	49	/* data iomem */
	50	u8 __iomem *tx_io;
	51	const u8 __iomem *rx_io;
	52
b42dfed8 FF	53	struct clk *clk;
	54	struct platform_device *pdev;
	55	};
	56
	57	static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
	58	unsigned int offset)
	59	{
	60	return bcm_readb(bs->regs + bcm63xx_spireg(offset));
	61	}
	62
	63	static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
	64	unsigned int offset)
	65	{
	66	return bcm_readw(bs->regs + bcm63xx_spireg(offset));
	67	}
	68
	69	static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
	70	u8 value, unsigned int offset)
	71	{
	72	bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
	73	}
	74
	75	static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
	76	u16 value, unsigned int offset)
	77	{
	78	bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
	79	}
	80
	81	static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
	82	{ 20000000, SPI_CLK_20MHZ },
	83	{ 12500000, SPI_CLK_12_50MHZ },
	84	{ 6250000, SPI_CLK_6_250MHZ },
	85	{ 3125000, SPI_CLK_3_125MHZ },
	86	{ 1563000, SPI_CLK_1_563MHZ },
	87	{ 781000, SPI_CLK_0_781MHZ },
	88	{ 391000, SPI_CLK_0_391MHZ }
	89	};
	90
cde4384e FF	91	static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
	92	struct spi_transfer *t)
	93	{
	94	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
cde4384e FF	95	u8 clk_cfg, reg;
	96	int i;
	97
b42dfed8 FF	98	/* Find the closest clock configuration */
b42dfed8 FF	99	for (i = 0; i < SPI_CLK_MASK; i++) {
68792e2a	100	if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
b42dfed8 FF	101	clk_cfg = bcm63xx_spi_freq_table[i][1];
	102	break;
	103	}
	104	}
	105
	106	/* No matching configuration found, default to lowest */
	107	if (i == SPI_CLK_MASK)
	108	clk_cfg = SPI_CLK_0_391MHZ;
	109
	110	/* clear existing clock configuration bits of the register */
	111	reg = bcm_spi_readb(bs, SPI_CLK_CFG);
	112	reg &= ~SPI_CLK_MASK;
	113	reg \|= clk_cfg;
	114
	115	bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
	116	dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
68792e2a	117	clk_cfg, t->speed_hz);
b42dfed8 FF	118	}
	119
	120	/* the spi->mode bits understood by this driver: */
	121	#define MODEBITS (SPI_CPOL \| SPI_CPHA)
	122
b17de076 JG	123	static int bcm63xx_txrx_bufs(struct spi_device spi, struct spi_transfer first,
b17de076 JG	124	unsigned int num_transfers)
b42dfed8 FF	125	{
	126	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	127	u16 msg_ctl;
	128	u16 cmd;
c0fde3ba	129	u8 rx_tail;
b17de076 JG	130	unsigned int i, timeout = 0, prepend_len = 0, len = 0;
	131	struct spi_transfer *t = first;
	132	bool do_rx = false;
	133	bool do_tx = false;
b42dfed8	134
cde4384e FF	135	/* Disable the CMD_DONE interrupt */
	136	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
	137
b42dfed8 FF	138	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
	139	t->tx_buf, t->rx_buf, t->len);
	140
b17de076 JG	141	if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
	142	prepend_len = t->len;
	143
	144	/* prepare the buffer */
	145	for (i = 0; i < num_transfers; i++) {
	146	if (t->tx_buf) {
	147	do_tx = true;
	148	memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
	149
	150	/* don't prepend more than one tx */
	151	if (t != first)
	152	prepend_len = 0;
	153	}
	154
	155	if (t->rx_buf) {
	156	do_rx = true;
	157	/* prepend is half-duplex write only */
	158	if (t == first)
	159	prepend_len = 0;
	160	}
	161
	162	len += t->len;
	163
	164	t = list_entry(t->transfer_list.next, struct spi_transfer,
	165	transfer_list);
	166	}
	167
aa0fe826	168	reinit_completion(&bs->done);
b42dfed8 FF	169
b42dfed8 FF	170	/* Fill in the Message control register */
b17de076	171	msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
b42dfed8	172
b17de076	173	if (do_rx && do_tx && prepend_len == 0)
5a670445	174	msg_ctl \|= (SPI_FD_RW << bs->msg_type_shift);
b17de076	175	else if (do_rx)
5a670445	176	msg_ctl \|= (SPI_HD_R << bs->msg_type_shift);
b17de076	177	else if (do_tx)
5a670445 FF	178	msg_ctl \|= (SPI_HD_W << bs->msg_type_shift);
	179
	180	switch (bs->msg_ctl_width) {
	181	case 8:
	182	bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
	183	break;
	184	case 16:
	185	bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
	186	break;
	187	}
b42dfed8 FF	188
	189	/* Issue the transfer */
	190	cmd = SPI_CMD_START_IMMEDIATE;
b17de076	191	cmd \|= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
b42dfed8 FF	192	cmd \|= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
b42dfed8 FF	193	bcm_spi_writew(bs, cmd, SPI_CMD);
b42dfed8	194
cde4384e FF	195	/* Enable the CMD_DONE interrupt */
cde4384e FF	196	bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
b42dfed8	197
c0fde3ba JG	198	timeout = wait_for_completion_timeout(&bs->done, HZ);
	199	if (!timeout)
	200	return -ETIMEDOUT;
	201
20e9e78f	202	if (!do_rx)
b17de076 JG	203	return 0;
	204
	205	len = 0;
	206	t = first;
c0fde3ba	207	/* Read out all the data */
b17de076 JG	208	for (i = 0; i < num_transfers; i++) {
	209	if (t->rx_buf)
	210	memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
	211
	212	if (t != first \|\| prepend_len == 0)
	213	len += t->len;
	214
	215	t = list_entry(t->transfer_list.next, struct spi_transfer,
	216	transfer_list);
	217	}
c0fde3ba JG	218
c0fde3ba JG	219	return 0;
b42dfed8 FF	220	}
b42dfed8 FF	221
cde4384e FF	222	static int bcm63xx_spi_transfer_one(struct spi_master *master,
	223	struct spi_message *m)
	224	{
	225	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
b17de076	226	struct spi_transfer t, first = NULL;
cde4384e FF	227	struct spi_device *spi = m->spi;
cde4384e FF	228	int status = 0;
b17de076 JG	229	unsigned int n_transfers = 0, total_len = 0;
	230	bool can_use_prepend = false;
	231
	232	/*
	233	* This SPI controller does not support keeping CS active after a
	234	* transfer.
	235	* Work around this by merging as many transfers we can into one big
	236	* full-duplex transfers.
	237	*/
b42dfed8	238	list_for_each_entry(t, &m->transfers, transfer_list) {
b17de076 JG	239	if (!first)
	240	first = t;
	241
	242	n_transfers++;
	243	total_len += t->len;
	244
	245	if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
	246	first->len <= BCM63XX_SPI_MAX_PREPEND)
	247	can_use_prepend = true;
	248	else if (can_use_prepend && t->tx_buf)
	249	can_use_prepend = false;
	250
c0fde3ba	251	/* we can only transfer one fifo worth of data */
b17de076 JG	252	if ((can_use_prepend &&
	253	total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) \|\|
	254	(!can_use_prepend && total_len > bs->fifo_size)) {
c0fde3ba	255	dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
b17de076	256	total_len, bs->fifo_size);
c0fde3ba JG	257	status = -EINVAL;
	258	goto exit;
	259	}
cde4384e	260
b17de076 JG	261	/* all combined transfers have to have the same speed */
	262	if (t->speed_hz != first->speed_hz) {
	263	dev_err(&spi->dev, "unable to change speed between transfers\n");
c0fde3ba JG	264	status = -EINVAL;
	265	goto exit;
	266	}
cde4384e	267
b17de076 JG	268	/* CS will be deasserted directly after transfer */
	269	if (t->delay_usecs) {
	270	dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
c0fde3ba JG	271	status = -EINVAL;
	272	goto exit;
	273	}
cde4384e	274
b17de076 JG	275	if (t->cs_change \|\|
	276	list_is_last(&t->transfer_list, &m->transfers)) {
	277	/* configure adapter for a new transfer */
	278	bcm63xx_spi_setup_transfer(spi, first);
cde4384e	279
b17de076 JG	280	/* send the data */
	281	status = bcm63xx_txrx_bufs(spi, first, n_transfers);
	282	if (status)
	283	goto exit;
	284
	285	m->actual_length += total_len;
b42dfed8	286
b17de076 JG	287	first = NULL;
	288	n_transfers = 0;
	289	total_len = 0;
	290	can_use_prepend = false;
	291	}
cde4384e FF	292	}
	293	exit:
	294	m->status = status;
	295	spi_finalize_current_message(master);
b42dfed8	296
cde4384e	297	return 0;
b42dfed8 FF	298	}
	299
	300	/* This driver supports single master mode only. Hence
	301	* CMD_DONE is the only interrupt we care about
	302	*/
	303	static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
	304	{
	305	struct spi_master master = (struct spi_master )dev_id;
	306	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	307	u8 intr;
b42dfed8 FF	308
	309	/* Read interupts and clear them immediately */
	310	intr = bcm_spi_readb(bs, SPI_INT_STATUS);
	311	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	312	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
	313
cde4384e FF	314	/* A transfer completed */
	315	if (intr & SPI_INTR_CMD_DONE)
	316	complete(&bs->done);
b42dfed8 FF	317
	318	return IRQ_HANDLED;
	319	}
	320
	321
fd4a319b	322	static int bcm63xx_spi_probe(struct platform_device *pdev)
b42dfed8 FF	323	{
	324	struct resource *r;
	325	struct device *dev = &pdev->dev;
8074cf06	326	struct bcm63xx_spi_pdata *pdata = dev_get_platdata(&pdev->dev);
b42dfed8 FF	327	int irq;
	328	struct spi_master *master;
	329	struct clk *clk;
	330	struct bcm63xx_spi *bs;
	331	int ret;
	332
b42dfed8 FF	333	irq = platform_get_irq(pdev, 0);
	334	if (irq < 0) {
	335	dev_err(dev, "no irq\n");
acf4fc6f	336	return -ENXIO;
b42dfed8 FF	337	}
b42dfed8 FF	338
acf4fc6f	339	clk = devm_clk_get(dev, "spi");
b42dfed8 FF	340	if (IS_ERR(clk)) {
b42dfed8 FF	341	dev_err(dev, "no clock for device\n");
acf4fc6f	342	return PTR_ERR(clk);
b42dfed8 FF	343	}
	344
	345	master = spi_alloc_master(dev, sizeof(*bs));
	346	if (!master) {
	347	dev_err(dev, "out of memory\n");
acf4fc6f	348	return -ENOMEM;
b42dfed8 FF	349	}
	350
	351	bs = spi_master_get_devdata(master);
aa0fe826	352	init_completion(&bs->done);
b42dfed8 FF	353
	354	platform_set_drvdata(pdev, master);
	355	bs->pdev = pdev;
	356
de0fa83c	357	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b66c7730 JG	358	bs->regs = devm_ioremap_resource(&pdev->dev, r);
	359	if (IS_ERR(bs->regs)) {
	360	ret = PTR_ERR(bs->regs);
b42dfed8 FF	361	goto out_err;
	362	}
	363
	364	bs->irq = irq;
	365	bs->clk = clk;
	366	bs->fifo_size = pdata->fifo_size;
	367
	368	ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
	369	pdev->name, master);
	370	if (ret) {
	371	dev_err(dev, "unable to request irq\n");
	372	goto out_err;
	373	}
	374
	375	master->bus_num = pdata->bus_num;
	376	master->num_chipselect = pdata->num_chipselect;
cde4384e	377	master->transfer_one_message = bcm63xx_spi_transfer_one;
88a3a255	378	master->mode_bits = MODEBITS;
24778be2	379	master->bits_per_word_mask = SPI_BPW_MASK(8);
5355d96d	380	master->auto_runtime_pm = true;
5a670445 FF	381	bs->msg_type_shift = pdata->msg_type_shift;
5a670445 FF	382	bs->msg_ctl_width = pdata->msg_ctl_width;
b42dfed8 FF	383	bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
b42dfed8 FF	384	bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
b42dfed8	385
5a670445 FF	386	switch (bs->msg_ctl_width) {
	387	case 8:
	388	case 16:
	389	break;
	390	default:
	391	dev_err(dev, "unsupported MSG_CTL width: %d\n",
	392	bs->msg_ctl_width);
b435ff21	393	goto out_err;
5a670445 FF	394	}
5a670445 FF	395
b42dfed8	396	/* Initialize hardware */
ea01e8a4 JG	397	ret = clk_prepare_enable(bs->clk);
	398	if (ret)
	399	goto out_err;
	400
b42dfed8 FF	401	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	402
	403	/* register and we are done */
bca76931	404	ret = devm_spi_register_master(dev, master);
b42dfed8 FF	405	if (ret) {
	406	dev_err(dev, "spi register failed\n");
	407	goto out_clk_disable;
	408	}
	409
61d15963 FF	410	dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
61d15963 FF	411	r->start, irq, bs->fifo_size);
b42dfed8 FF	412
	413	return 0;
	414
	415	out_clk_disable:
4fbb82a7	416	clk_disable_unprepare(clk);
b42dfed8	417	out_err:
b42dfed8	418	spi_master_put(master);
b42dfed8 FF	419	return ret;
	420	}
	421
fd4a319b	422	static int bcm63xx_spi_remove(struct platform_device *pdev)
b42dfed8	423	{
9637b86f	424	struct spi_master *master = platform_get_drvdata(pdev);
b42dfed8 FF	425	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	426
	427	/* reset spi block */
	428	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
b42dfed8 FF	429
b42dfed8 FF	430	/* HW shutdown */
4fbb82a7	431	clk_disable_unprepare(bs->clk);
b42dfed8	432
b42dfed8 FF	433	return 0;
	434	}
	435
1bae2028	436	#ifdef CONFIG_PM_SLEEP
b42dfed8 FF	437	static int bcm63xx_spi_suspend(struct device *dev)
b42dfed8 FF	438	{
a1216394	439	struct spi_master *master = dev_get_drvdata(dev);
b42dfed8 FF	440	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
b42dfed8 FF	441
96519957 FF	442	spi_master_suspend(master);
96519957 FF	443
4fbb82a7	444	clk_disable_unprepare(bs->clk);
b42dfed8 FF	445
	446	return 0;
	447	}
	448
	449	static int bcm63xx_spi_resume(struct device *dev)
	450	{
a1216394	451	struct spi_master *master = dev_get_drvdata(dev);
b42dfed8	452	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
ea01e8a4	453	int ret;
b42dfed8	454
ea01e8a4 JG	455	ret = clk_prepare_enable(bs->clk);
	456	if (ret)
	457	return ret;
b42dfed8	458
96519957 FF	459	spi_master_resume(master);
96519957 FF	460
b42dfed8 FF	461	return 0;
b42dfed8 FF	462	}
1bae2028	463	#endif
b42dfed8 FF	464
b42dfed8 FF	465	static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
1bae2028	466	SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
b42dfed8 FF	467	};
b42dfed8 FF	468
b42dfed8 FF	469	static struct platform_driver bcm63xx_spi_driver = {
	470	.driver = {
	471	.name = "bcm63xx-spi",
	472	.owner = THIS_MODULE,
1bae2028	473	.pm = &bcm63xx_spi_pm_ops,
b42dfed8 FF	474	},
b42dfed8 FF	475	.probe = bcm63xx_spi_probe,
fd4a319b	476	.remove = bcm63xx_spi_remove,
b42dfed8 FF	477	};
	478
	479	module_platform_driver(bcm63xx_spi_driver);
	480
	481	MODULE_ALIAS("platform:bcm63xx_spi");
	482	MODULE_AUTHOR("Florian Fainelli <[email protected]>");
	483	MODULE_AUTHOR("Tanguy Bouzeloc <[email protected]>");
	484	MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
	485	MODULE_LICENSE("GPL");