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ASoC: wm_adsp: Fixup some minor formatting and checkpatch errors
[linux.git] / sound / soc / codecs / wm_adsp.c
CommitLineData
2159ad93
MB		 1/*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/firmware.h>
cf17c83c 18#include <linux/list.h>
2159ad93
MB		 19#include <linux/pm.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
973838a0 22#include <linux/regulator/consumer.h>
2159ad93 23#include <linux/slab.h>
cdcd7f72 24#include <linux/vmalloc.h>
6ab2b7b4 25#include <linux/workqueue.h>
f9f55e31 26#include <linux/debugfs.h>
2159ad93
MB		 27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/jack.h>
32#include <sound/initval.h>
33#include <sound/tlv.h>
34
35#include <linux/mfd/arizona/registers.h>
36
dc91428a 37#include "arizona.h"
2159ad93
MB		 38#include "wm_adsp.h"
39
40#define adsp_crit(_dsp, fmt, ...) \
41 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
42#define adsp_err(_dsp, fmt, ...) \
43 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
44#define adsp_warn(_dsp, fmt, ...) \
45 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
46#define adsp_info(_dsp, fmt, ...) \
47 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
48#define adsp_dbg(_dsp, fmt, ...) \
49 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
50
51#define ADSP1_CONTROL_1 0x00
52#define ADSP1_CONTROL_2 0x02
53#define ADSP1_CONTROL_3 0x03
54#define ADSP1_CONTROL_4 0x04
55#define ADSP1_CONTROL_5 0x06
56#define ADSP1_CONTROL_6 0x07
57#define ADSP1_CONTROL_7 0x08
58#define ADSP1_CONTROL_8 0x09
59#define ADSP1_CONTROL_9 0x0A
60#define ADSP1_CONTROL_10 0x0B
61#define ADSP1_CONTROL_11 0x0C
62#define ADSP1_CONTROL_12 0x0D
63#define ADSP1_CONTROL_13 0x0F
64#define ADSP1_CONTROL_14 0x10
65#define ADSP1_CONTROL_15 0x11
66#define ADSP1_CONTROL_16 0x12
67#define ADSP1_CONTROL_17 0x13
68#define ADSP1_CONTROL_18 0x14
69#define ADSP1_CONTROL_19 0x16
70#define ADSP1_CONTROL_20 0x17
71#define ADSP1_CONTROL_21 0x18
72#define ADSP1_CONTROL_22 0x1A
73#define ADSP1_CONTROL_23 0x1B
74#define ADSP1_CONTROL_24 0x1C
75#define ADSP1_CONTROL_25 0x1E
76#define ADSP1_CONTROL_26 0x20
77#define ADSP1_CONTROL_27 0x21
78#define ADSP1_CONTROL_28 0x22
79#define ADSP1_CONTROL_29 0x23
80#define ADSP1_CONTROL_30 0x24
81#define ADSP1_CONTROL_31 0x26
82
83/*
84 * ADSP1 Control 19
85 */
86#define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
87#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
88#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
89
90
91/*
92 * ADSP1 Control 30
93 */
94#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
95#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
96#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
97#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
98#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
99#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
100#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
101#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
102#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
103#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
104#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
105#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
106#define ADSP1_START 0x0001 /* DSP1_START */
107#define ADSP1_START_MASK 0x0001 /* DSP1_START */
108#define ADSP1_START_SHIFT 0 /* DSP1_START */
109#define ADSP1_START_WIDTH 1 /* DSP1_START */
110
94e205bf
CR		 111/*
112 * ADSP1 Control 31
113 */
114#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
115#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
116#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
117
2d30b575
MB		 118#define ADSP2_CONTROL 0x0
119#define ADSP2_CLOCKING 0x1
120#define ADSP2_STATUS1 0x4
121#define ADSP2_WDMA_CONFIG_1 0x30
122#define ADSP2_WDMA_CONFIG_2 0x31
123#define ADSP2_RDMA_CONFIG_1 0x34
2159ad93 124
10337b07
RF		 125#define ADSP2_SCRATCH0 0x40
126#define ADSP2_SCRATCH1 0x41
127#define ADSP2_SCRATCH2 0x42
128#define ADSP2_SCRATCH3 0x43
129
2159ad93
MB		 130/*
131 * ADSP2 Control
132 */
133
134#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
135#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
136#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
137#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
138#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
139#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
140#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
141#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
142#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
143#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
144#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
145#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
146#define ADSP2_START 0x0001 /* DSP1_START */
147#define ADSP2_START_MASK 0x0001 /* DSP1_START */
148#define ADSP2_START_SHIFT 0 /* DSP1_START */
149#define ADSP2_START_WIDTH 1 /* DSP1_START */
150
973838a0
MB		 151/*
152 * ADSP2 clocking
153 */
154#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
155#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
156#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
157
2159ad93
MB		 158/*
159 * ADSP2 Status 1
160 */
161#define ADSP2_RAM_RDY 0x0001
162#define ADSP2_RAM_RDY_MASK 0x0001
163#define ADSP2_RAM_RDY_SHIFT 0
164#define ADSP2_RAM_RDY_WIDTH 1
165
cf17c83c
MB		 166struct wm_adsp_buf {
167 struct list_head list;
168 void *buf;
169};
170
171static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
172 struct list_head *list)
173{
174 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
175
176 if (buf == NULL)
177 return NULL;
178
cdcd7f72 179 buf->buf = vmalloc(len);
cf17c83c 180 if (!buf->buf) {
cdcd7f72 181 vfree(buf);
cf17c83c
MB		 182 return NULL;
183 }
cdcd7f72 184 memcpy(buf->buf, src, len);
cf17c83c
MB		 185
186 if (list)
187 list_add_tail(&buf->list, list);
188
189 return buf;
190}
191
192static void wm_adsp_buf_free(struct list_head *list)
193{
194 while (!list_empty(list)) {
195 struct wm_adsp_buf *buf = list_first_entry(list,
196 struct wm_adsp_buf,
197 list);
198 list_del(&buf->list);
cdcd7f72 199 vfree(buf->buf);
cf17c83c
MB		 200 kfree(buf);
201 }
202}
203
04d1300f
CK		 204#define WM_ADSP_FW_MBC_VSS 0
205#define WM_ADSP_FW_HIFI 1
206#define WM_ADSP_FW_TX 2
207#define WM_ADSP_FW_TX_SPK 3
208#define WM_ADSP_FW_RX 4
209#define WM_ADSP_FW_RX_ANC 5
210#define WM_ADSP_FW_CTRL 6
211#define WM_ADSP_FW_ASR 7
212#define WM_ADSP_FW_TRACE 8
213#define WM_ADSP_FW_SPK_PROT 9
214#define WM_ADSP_FW_MISC 10
215
216#define WM_ADSP_NUM_FW 11
dd84f925 217
1023dbd9 218static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
04d1300f
CK		 219 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
220 [WM_ADSP_FW_HIFI] = "MasterHiFi",
221 [WM_ADSP_FW_TX] = "Tx",
222 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
223 [WM_ADSP_FW_RX] = "Rx",
224 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
225 [WM_ADSP_FW_CTRL] = "Voice Ctrl",
226 [WM_ADSP_FW_ASR] = "ASR Assist",
227 [WM_ADSP_FW_TRACE] = "Dbg Trace",
228 [WM_ADSP_FW_SPK_PROT] = "Protection",
229 [WM_ADSP_FW_MISC] = "Misc",
1023dbd9
MB		 230};
231
232static struct {
233 const char *file;
234} wm_adsp_fw[WM_ADSP_NUM_FW] = {
04d1300f
CK		 235 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
236 [WM_ADSP_FW_HIFI] = { .file = "hifi" },
237 [WM_ADSP_FW_TX] = { .file = "tx" },
238 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
239 [WM_ADSP_FW_RX] = { .file = "rx" },
240 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
241 [WM_ADSP_FW_CTRL] = { .file = "ctrl" },
242 [WM_ADSP_FW_ASR] = { .file = "asr" },
243 [WM_ADSP_FW_TRACE] = { .file = "trace" },
244 [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
245 [WM_ADSP_FW_MISC] = { .file = "misc" },
1023dbd9
MB		 246};
247
6ab2b7b4
DP		 248struct wm_coeff_ctl_ops {
249 int (*xget)(struct snd_kcontrol *kcontrol,
250 struct snd_ctl_elem_value *ucontrol);
251 int (*xput)(struct snd_kcontrol *kcontrol,
252 struct snd_ctl_elem_value *ucontrol);
253 int (*xinfo)(struct snd_kcontrol *kcontrol,
254 struct snd_ctl_elem_info *uinfo);
255};
256
6ab2b7b4
DP		 257struct wm_coeff_ctl {
258 const char *name;
2323736d 259 const char *fw_name;
3809f001 260 struct wm_adsp_alg_region alg_region;
6ab2b7b4 261 struct wm_coeff_ctl_ops ops;
3809f001 262 struct wm_adsp *dsp;
6ab2b7b4
DP		 263 unsigned int enabled:1;
264 struct list_head list;
265 void *cache;
2323736d 266 unsigned int offset;
6ab2b7b4 267 size_t len;
0c2e3f34 268 unsigned int set:1;
6ab2b7b4 269 struct snd_kcontrol *kcontrol;
26c22a19 270 unsigned int flags;
6ab2b7b4
DP		 271};
272
f9f55e31
RF		 273#ifdef CONFIG_DEBUG_FS
274static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
275{
276 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
277
f9f55e31
RF		 278 kfree(dsp->wmfw_file_name);
279 dsp->wmfw_file_name = tmp;
f9f55e31
RF		 280}
281
282static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
283{
284 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
285
f9f55e31
RF		 286 kfree(dsp->bin_file_name);
287 dsp->bin_file_name = tmp;
f9f55e31
RF		 288}
289
290static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
291{
f9f55e31
RF		 292 kfree(dsp->wmfw_file_name);
293 kfree(dsp->bin_file_name);
294 dsp->wmfw_file_name = NULL;
295 dsp->bin_file_name = NULL;
f9f55e31
RF		 296}
297
298static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
299 char __user *user_buf,
300 size_t count, loff_t *ppos)
301{
302 struct wm_adsp *dsp = file->private_data;
303 ssize_t ret;
304
078e7183 305 mutex_lock(&dsp->pwr_lock);
f9f55e31
RF		 306
307 if (!dsp->wmfw_file_name || !dsp->running)
308 ret = 0;
309 else
310 ret = simple_read_from_buffer(user_buf, count, ppos,
311 dsp->wmfw_file_name,
312 strlen(dsp->wmfw_file_name));
313
078e7183 314 mutex_unlock(&dsp->pwr_lock);
f9f55e31
RF		 315 return ret;
316}
317
318static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
319 char __user *user_buf,
320 size_t count, loff_t *ppos)
321{
322 struct wm_adsp *dsp = file->private_data;
323 ssize_t ret;
324
078e7183 325 mutex_lock(&dsp->pwr_lock);
f9f55e31
RF		 326
327 if (!dsp->bin_file_name || !dsp->running)
328 ret = 0;
329 else
330 ret = simple_read_from_buffer(user_buf, count, ppos,
331 dsp->bin_file_name,
332 strlen(dsp->bin_file_name));
333
078e7183 334 mutex_unlock(&dsp->pwr_lock);
f9f55e31
RF		 335 return ret;
336}
337
338static const struct {
339 const char *name;
340 const struct file_operations fops;
341} wm_adsp_debugfs_fops[] = {
342 {
343 .name = "wmfw_file_name",
344 .fops = {
345 .open = simple_open,
346 .read = wm_adsp_debugfs_wmfw_read,
347 },
348 },
349 {
350 .name = "bin_file_name",
351 .fops = {
352 .open = simple_open,
353 .read = wm_adsp_debugfs_bin_read,
354 },
355 },
356};
357
358static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
359 struct snd_soc_codec *codec)
360{
361 struct dentry *root = NULL;
362 char *root_name;
363 int i;
364
365 if (!codec->component.debugfs_root) {
366 adsp_err(dsp, "No codec debugfs root\n");
367 goto err;
368 }
369
370 root_name = kmalloc(PAGE_SIZE, GFP_KERNEL);
371 if (!root_name)
372 goto err;
373
374 snprintf(root_name, PAGE_SIZE, "dsp%d", dsp->num);
375 root = debugfs_create_dir(root_name, codec->component.debugfs_root);
376 kfree(root_name);
377
378 if (!root)
379 goto err;
380
381 if (!debugfs_create_bool("running", S_IRUGO, root, &dsp->running))
382 goto err;
383
384 if (!debugfs_create_x32("fw_id", S_IRUGO, root, &dsp->fw_id))
385 goto err;
386
387 if (!debugfs_create_x32("fw_version", S_IRUGO, root,
388 &dsp->fw_id_version))
389 goto err;
390
391 for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) {
392 if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name,
393 S_IRUGO, root, dsp,
394 &wm_adsp_debugfs_fops[i].fops))
395 goto err;
396 }
397
398 dsp->debugfs_root = root;
399 return;
400
401err:
402 debugfs_remove_recursive(root);
403 adsp_err(dsp, "Failed to create debugfs\n");
404}
405
406static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
407{
408 wm_adsp_debugfs_clear(dsp);
409 debugfs_remove_recursive(dsp->debugfs_root);
410}
411#else
412static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
413 struct snd_soc_codec *codec)
414{
415}
416
417static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
418{
419}
420
421static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
422 const char *s)
423{
424}
425
426static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
427 const char *s)
428{
429}
430
431static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
432{
433}
434#endif
435
1023dbd9
MB		 436static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
437 struct snd_ctl_elem_value *ucontrol)
438{
ea53bf77 439 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1023dbd9 440 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3809f001 441 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
1023dbd9 442
3809f001 443 ucontrol->value.integer.value[0] = dsp[e->shift_l].fw;
1023dbd9
MB		 444
445 return 0;
446}
447
448static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
449 struct snd_ctl_elem_value *ucontrol)
450{
ea53bf77 451 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1023dbd9 452 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3809f001 453 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
d27c5e15 454 int ret = 0;
1023dbd9 455
3809f001 456 if (ucontrol->value.integer.value[0] == dsp[e->shift_l].fw)
1023dbd9
MB		 457 return 0;
458
459 if (ucontrol->value.integer.value[0] >= WM_ADSP_NUM_FW)
460 return -EINVAL;
461
d27c5e15
CK		 462 mutex_lock(&dsp[e->shift_l].pwr_lock);
463
3809f001 464 if (dsp[e->shift_l].running)
d27c5e15
CK		 465 ret = -EBUSY;
466 else
467 dsp[e->shift_l].fw = ucontrol->value.integer.value[0];
1023dbd9 468
d27c5e15 469 mutex_unlock(&dsp[e->shift_l].pwr_lock);
1023dbd9 470
d27c5e15 471 return ret;
1023dbd9
MB		 472}
473
474static const struct soc_enum wm_adsp_fw_enum[] = {
475 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
476 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
477 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
478 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
479};
480
336d0442 481const struct snd_kcontrol_new wm_adsp_fw_controls[] = {
1023dbd9
MB		 482 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
483 wm_adsp_fw_get, wm_adsp_fw_put),
484 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
485 wm_adsp_fw_get, wm_adsp_fw_put),
486 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
487 wm_adsp_fw_get, wm_adsp_fw_put),
336d0442
RF		 488 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
489 wm_adsp_fw_get, wm_adsp_fw_put),
b6ed61cf 490};
336d0442 491EXPORT_SYMBOL_GPL(wm_adsp_fw_controls);
2159ad93
MB		 492
493static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
494 int type)
495{
496 int i;
497
498 for (i = 0; i < dsp->num_mems; i++)
499 if (dsp->mem[i].type == type)
500 return &dsp->mem[i];
501
502 return NULL;
503}
504
3809f001 505static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
45b9ee72
MB		 506 unsigned int offset)
507{
3809f001 508 if (WARN_ON(!mem))
6c452bda 509 return offset;
3809f001 510 switch (mem->type) {
45b9ee72 511 case WMFW_ADSP1_PM:
3809f001 512 return mem->base + (offset * 3);
45b9ee72 513 case WMFW_ADSP1_DM:
3809f001 514 return mem->base + (offset * 2);
45b9ee72 515 case WMFW_ADSP2_XM:
3809f001 516 return mem->base + (offset * 2);
45b9ee72 517 case WMFW_ADSP2_YM:
3809f001 518 return mem->base + (offset * 2);
45b9ee72 519 case WMFW_ADSP1_ZM:
3809f001 520 return mem->base + (offset * 2);
45b9ee72 521 default:
6c452bda 522 WARN(1, "Unknown memory region type");
45b9ee72
MB		 523 return offset;
524 }
525}
526
10337b07
RF		 527static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
528{
529 u16 scratch[4];
530 int ret;
531
532 ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2_SCRATCH0,
533 scratch, sizeof(scratch));
534 if (ret) {
535 adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret);
536 return;
537 }
538
539 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
540 be16_to_cpu(scratch[0]),
541 be16_to_cpu(scratch[1]),
542 be16_to_cpu(scratch[2]),
543 be16_to_cpu(scratch[3]));
544}
545
7585a5b0 546static int wm_coeff_info(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 547 struct snd_ctl_elem_info *uinfo)
548{
7585a5b0 549 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kctl->private_value;
6ab2b7b4
DP		 550
551 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
552 uinfo->count = ctl->len;
553 return 0;
554}
555
c9f8dd71 556static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
6ab2b7b4
DP		 557 const void *buf, size_t len)
558{
3809f001 559 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
6ab2b7b4 560 const struct wm_adsp_region *mem;
3809f001 561 struct wm_adsp *dsp = ctl->dsp;
6ab2b7b4
DP		 562 void *scratch;
563 int ret;
564 unsigned int reg;
565
3809f001 566 mem = wm_adsp_find_region(dsp, alg_region->type);
6ab2b7b4 567 if (!mem) {
3809f001
CK		 568 adsp_err(dsp, "No base for region %x\n",
569 alg_region->type);
6ab2b7b4
DP		 570 return -EINVAL;
571 }
572
2323736d 573 reg = ctl->alg_region.base + ctl->offset;
6ab2b7b4
DP		 574 reg = wm_adsp_region_to_reg(mem, reg);
575
576 scratch = kmemdup(buf, ctl->len, GFP_KERNEL | GFP_DMA);
577 if (!scratch)
578 return -ENOMEM;
579
3809f001 580 ret = regmap_raw_write(dsp->regmap, reg, scratch,
6ab2b7b4
DP		 581 ctl->len);
582 if (ret) {
3809f001 583 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
43bc3bf6 584 ctl->len, reg, ret);
6ab2b7b4
DP		 585 kfree(scratch);
586 return ret;
587 }
3809f001 588 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", ctl->len, reg);
6ab2b7b4
DP		 589
590 kfree(scratch);
591
592 return 0;
593}
594
7585a5b0 595static int wm_coeff_put(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 596 struct snd_ctl_elem_value *ucontrol)
597{
7585a5b0 598 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kctl->private_value;
6ab2b7b4
DP		 599 char *p = ucontrol->value.bytes.data;
600
601 memcpy(ctl->cache, p, ctl->len);
602
65d17a9c
NO		 603 ctl->set = 1;
604 if (!ctl->enabled)
6ab2b7b4 605 return 0;
6ab2b7b4 606
c9f8dd71 607 return wm_coeff_write_control(ctl, p, ctl->len);
6ab2b7b4
DP		 608}
609
c9f8dd71 610static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
6ab2b7b4
DP		 611 void *buf, size_t len)
612{
3809f001 613 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
6ab2b7b4 614 const struct wm_adsp_region *mem;
3809f001 615 struct wm_adsp *dsp = ctl->dsp;
6ab2b7b4
DP		 616 void *scratch;
617 int ret;
618 unsigned int reg;
619
3809f001 620 mem = wm_adsp_find_region(dsp, alg_region->type);
6ab2b7b4 621 if (!mem) {
3809f001
CK		 622 adsp_err(dsp, "No base for region %x\n",
623 alg_region->type);
6ab2b7b4
DP		 624 return -EINVAL;
625 }
626
2323736d 627 reg = ctl->alg_region.base + ctl->offset;
6ab2b7b4
DP		 628 reg = wm_adsp_region_to_reg(mem, reg);
629
630 scratch = kmalloc(ctl->len, GFP_KERNEL | GFP_DMA);
631 if (!scratch)
632 return -ENOMEM;
633
3809f001 634 ret = regmap_raw_read(dsp->regmap, reg, scratch, ctl->len);
6ab2b7b4 635 if (ret) {
3809f001 636 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
43bc3bf6 637 ctl->len, reg, ret);
6ab2b7b4
DP		 638 kfree(scratch);
639 return ret;
640 }
3809f001 641 adsp_dbg(dsp, "Read %zu bytes from %x\n", ctl->len, reg);
6ab2b7b4
DP		 642
643 memcpy(buf, scratch, ctl->len);
644 kfree(scratch);
645
646 return 0;
647}
648
7585a5b0 649static int wm_coeff_get(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 650 struct snd_ctl_elem_value *ucontrol)
651{
7585a5b0 652 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kctl->private_value;
6ab2b7b4
DP		 653 char *p = ucontrol->value.bytes.data;
654
26c22a19
CK		 655 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
656 if (ctl->enabled)
657 return wm_coeff_read_control(ctl, p, ctl->len);
658 else
659 return -EPERM;
660 }
661
6ab2b7b4 662 memcpy(p, ctl->cache, ctl->len);
26c22a19 663
6ab2b7b4
DP		 664 return 0;
665}
666
6ab2b7b4 667struct wmfw_ctl_work {
3809f001 668 struct wm_adsp *dsp;
6ab2b7b4
DP		 669 struct wm_coeff_ctl *ctl;
670 struct work_struct work;
671};
672
3809f001 673static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
6ab2b7b4
DP		 674{
675 struct snd_kcontrol_new *kcontrol;
676 int ret;
677
92bb4c32 678 if (!ctl || !ctl->name)
6ab2b7b4
DP		 679 return -EINVAL;
680
681 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
682 if (!kcontrol)
683 return -ENOMEM;
684 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
685
686 kcontrol->name = ctl->name;
687 kcontrol->info = wm_coeff_info;
688 kcontrol->get = wm_coeff_get;
689 kcontrol->put = wm_coeff_put;
690 kcontrol->private_value = (unsigned long)ctl;
691
26c22a19
CK		 692 if (ctl->flags) {
693 if (ctl->flags & WMFW_CTL_FLAG_WRITEABLE)
694 kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
695 if (ctl->flags & WMFW_CTL_FLAG_READABLE)
696 kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_READ;
697 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
698 kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_VOLATILE;
699 }
700
3809f001 701 ret = snd_soc_add_card_controls(dsp->card,
81ad93ec 702 kcontrol, 1);
6ab2b7b4
DP		 703 if (ret < 0)
704 goto err_kcontrol;
705
706 kfree(kcontrol);
707
3809f001 708 ctl->kcontrol = snd_soc_card_get_kcontrol(dsp->card,
81ad93ec
DP		 709 ctl->name);
710
6ab2b7b4
DP		 711 return 0;
712
713err_kcontrol:
714 kfree(kcontrol);
715 return ret;
716}
717
b21acc1c
CK		 718static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
719{
720 struct wm_coeff_ctl *ctl;
721 int ret;
722
723 list_for_each_entry(ctl, &dsp->ctl_list, list) {
724 if (!ctl->enabled || ctl->set)
725 continue;
26c22a19
CK		 726 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
727 continue;
728
b21acc1c
CK		 729 ret = wm_coeff_read_control(ctl,
730 ctl->cache,
731 ctl->len);
732 if (ret < 0)
733 return ret;
734 }
735
736 return 0;
737}
738
739static int wm_coeff_sync_controls(struct wm_adsp *dsp)
740{
741 struct wm_coeff_ctl *ctl;
742 int ret;
743
744 list_for_each_entry(ctl, &dsp->ctl_list, list) {
745 if (!ctl->enabled)
746 continue;
26c22a19 747 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
b21acc1c
CK		 748 ret = wm_coeff_write_control(ctl,
749 ctl->cache,
750 ctl->len);
751 if (ret < 0)
752 return ret;
753 }
754 }
755
756 return 0;
757}
758
759static void wm_adsp_ctl_work(struct work_struct *work)
760{
761 struct wmfw_ctl_work *ctl_work = container_of(work,
762 struct wmfw_ctl_work,
763 work);
764
765 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
766 kfree(ctl_work);
767}
768
769static int wm_adsp_create_control(struct wm_adsp *dsp,
770 const struct wm_adsp_alg_region *alg_region,
2323736d 771 unsigned int offset, unsigned int len,
26c22a19
CK		 772 const char *subname, unsigned int subname_len,
773 unsigned int flags)
b21acc1c
CK		 774{
775 struct wm_coeff_ctl *ctl;
776 struct wmfw_ctl_work *ctl_work;
777 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
778 char *region_name;
779 int ret;
780
26c22a19
CK		 781 if (flags & WMFW_CTL_FLAG_SYS)
782 return 0;
783
b21acc1c
CK		 784 switch (alg_region->type) {
785 case WMFW_ADSP1_PM:
786 region_name = "PM";
787 break;
788 case WMFW_ADSP1_DM:
789 region_name = "DM";
790 break;
791 case WMFW_ADSP2_XM:
792 region_name = "XM";
793 break;
794 case WMFW_ADSP2_YM:
795 region_name = "YM";
796 break;
797 case WMFW_ADSP1_ZM:
798 region_name = "ZM";
799 break;
800 default:
2323736d 801 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
b21acc1c
CK		 802 return -EINVAL;
803 }
804
cb5b57a9
CK		 805 switch (dsp->fw_ver) {
806 case 0:
807 case 1:
808 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "DSP%d %s %x",
809 dsp->num, region_name, alg_region->alg);
810 break;
811 default:
812 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
813 "DSP%d%c %.12s %x", dsp->num, *region_name,
814 wm_adsp_fw_text[dsp->fw], alg_region->alg);
815
816 /* Truncate the subname from the start if it is too long */
817 if (subname) {
818 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
819 int skip = 0;
820
821 if (subname_len > avail)
822 skip = subname_len - avail;
823
824 snprintf(name + ret,
825 SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s",
826 subname_len - skip, subname + skip);
827 }
828 break;
829 }
b21acc1c 830
7585a5b0 831 list_for_each_entry(ctl, &dsp->ctl_list, list) {
b21acc1c
CK		 832 if (!strcmp(ctl->name, name)) {
833 if (!ctl->enabled)
834 ctl->enabled = 1;
835 return 0;
836 }
837 }
838
839 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
840 if (!ctl)
841 return -ENOMEM;
2323736d 842 ctl->fw_name = wm_adsp_fw_text[dsp->fw];
b21acc1c
CK		 843 ctl->alg_region = *alg_region;
844 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
845 if (!ctl->name) {
846 ret = -ENOMEM;
847 goto err_ctl;
848 }
849 ctl->enabled = 1;
850 ctl->set = 0;
851 ctl->ops.xget = wm_coeff_get;
852 ctl->ops.xput = wm_coeff_put;
853 ctl->dsp = dsp;
854
26c22a19 855 ctl->flags = flags;
2323736d 856 ctl->offset = offset;
b21acc1c
CK		 857 if (len > 512) {
858 adsp_warn(dsp, "Truncating control %s from %d\n",
859 ctl->name, len);
860 len = 512;
861 }
862 ctl->len = len;
863 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
864 if (!ctl->cache) {
865 ret = -ENOMEM;
866 goto err_ctl_name;
867 }
868
2323736d
CK		 869 list_add(&ctl->list, &dsp->ctl_list);
870
b21acc1c
CK		 871 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
872 if (!ctl_work) {
873 ret = -ENOMEM;
874 goto err_ctl_cache;
875 }
876
877 ctl_work->dsp = dsp;
878 ctl_work->ctl = ctl;
879 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
880 schedule_work(&ctl_work->work);
881
882 return 0;
883
884err_ctl_cache:
885 kfree(ctl->cache);
886err_ctl_name:
887 kfree(ctl->name);
888err_ctl:
889 kfree(ctl);
890
891 return ret;
892}
893
2323736d
CK		 894struct wm_coeff_parsed_alg {
895 int id;
896 const u8 *name;
897 int name_len;
898 int ncoeff;
899};
900
901struct wm_coeff_parsed_coeff {
902 int offset;
903 int mem_type;
904 const u8 *name;
905 int name_len;
906 int ctl_type;
907 int flags;
908 int len;
909};
910
cb5b57a9
CK		 911static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
912{
913 int length;
914
915 switch (bytes) {
916 case 1:
917 length = **pos;
918 break;
919 case 2:
8299ee81 920 length = le16_to_cpu(*((__le16 *)*pos));
cb5b57a9
CK		 921 break;
922 default:
923 return 0;
924 }
925
926 if (str)
927 *str = *pos + bytes;
928
929 *pos += ((length + bytes) + 3) & ~0x03;
930
931 return length;
932}
933
934static int wm_coeff_parse_int(int bytes, const u8 **pos)
935{
936 int val = 0;
937
938 switch (bytes) {
939 case 2:
8299ee81 940 val = le16_to_cpu(*((__le16 *)*pos));
cb5b57a9
CK		 941 break;
942 case 4:
8299ee81 943 val = le32_to_cpu(*((__le32 *)*pos));
cb5b57a9
CK		 944 break;
945 default:
946 break;
947 }
948
949 *pos += bytes;
950
951 return val;
952}
953
2323736d
CK		 954static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
955 struct wm_coeff_parsed_alg *blk)
956{
957 const struct wmfw_adsp_alg_data *raw;
958
cb5b57a9
CK		 959 switch (dsp->fw_ver) {
960 case 0:
961 case 1:
962 raw = (const struct wmfw_adsp_alg_data *)*data;
963 *data = raw->data;
2323736d 964
cb5b57a9
CK		 965 blk->id = le32_to_cpu(raw->id);
966 blk->name = raw->name;
967 blk->name_len = strlen(raw->name);
968 blk->ncoeff = le32_to_cpu(raw->ncoeff);
969 break;
970 default:
971 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
972 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
973 &blk->name);
974 wm_coeff_parse_string(sizeof(u16), data, NULL);
975 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
976 break;
977 }
2323736d
CK		 978
979 adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
980 adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
981 adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
982}
983
984static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
985 struct wm_coeff_parsed_coeff *blk)
986{
987 const struct wmfw_adsp_coeff_data *raw;
cb5b57a9
CK		 988 const u8 *tmp;
989 int length;
2323736d 990
cb5b57a9
CK		 991 switch (dsp->fw_ver) {
992 case 0:
993 case 1:
994 raw = (const struct wmfw_adsp_coeff_data *)*data;
995 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
996
997 blk->offset = le16_to_cpu(raw->hdr.offset);
998 blk->mem_type = le16_to_cpu(raw->hdr.type);
999 blk->name = raw->name;
1000 blk->name_len = strlen(raw->name);
1001 blk->ctl_type = le16_to_cpu(raw->ctl_type);
1002 blk->flags = le16_to_cpu(raw->flags);
1003 blk->len = le32_to_cpu(raw->len);
1004 break;
1005 default:
1006 tmp = *data;
1007 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1008 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1009 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1010 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
1011 &blk->name);
1012 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
1013 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
1014 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
1015 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
1016 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
1017
1018 *data = *data + sizeof(raw->hdr) + length;
1019 break;
1020 }
2323736d
CK		 1021
1022 adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1023 adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1024 adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1025 adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1026 adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1027 adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1028}
1029
1030static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
1031 const struct wmfw_region *region)
1032{
1033 struct wm_adsp_alg_region alg_region = {};
1034 struct wm_coeff_parsed_alg alg_blk;
1035 struct wm_coeff_parsed_coeff coeff_blk;
1036 const u8 *data = region->data;
1037 int i, ret;
1038
1039 wm_coeff_parse_alg(dsp, &data, &alg_blk);
1040 for (i = 0; i < alg_blk.ncoeff; i++) {
1041 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
1042
1043 switch (coeff_blk.ctl_type) {
1044 case SNDRV_CTL_ELEM_TYPE_BYTES:
1045 break;
1046 default:
1047 adsp_err(dsp, "Unknown control type: %d\n",
1048 coeff_blk.ctl_type);
1049 return -EINVAL;
1050 }
1051
1052 alg_region.type = coeff_blk.mem_type;
1053 alg_region.alg = alg_blk.id;
1054
1055 ret = wm_adsp_create_control(dsp, &alg_region,
1056 coeff_blk.offset,
1057 coeff_blk.len,
1058 coeff_blk.name,
26c22a19
CK		 1059 coeff_blk.name_len,
1060 coeff_blk.flags);
2323736d
CK		 1061 if (ret < 0)
1062 adsp_err(dsp, "Failed to create control: %.*s, %d\n",
1063 coeff_blk.name_len, coeff_blk.name, ret);
1064 }
1065
1066 return 0;
1067}
1068
2159ad93
MB		 1069static int wm_adsp_load(struct wm_adsp *dsp)
1070{
cf17c83c 1071 LIST_HEAD(buf_list);
2159ad93
MB		 1072 const struct firmware *firmware;
1073 struct regmap *regmap = dsp->regmap;
1074 unsigned int pos = 0;
1075 const struct wmfw_header *header;
1076 const struct wmfw_adsp1_sizes *adsp1_sizes;
1077 const struct wmfw_adsp2_sizes *adsp2_sizes;
1078 const struct wmfw_footer *footer;
1079 const struct wmfw_region *region;
1080 const struct wm_adsp_region *mem;
1081 const char *region_name;
1082 char *file, *text;
cf17c83c 1083 struct wm_adsp_buf *buf;
2159ad93
MB		 1084 unsigned int reg;
1085 int regions = 0;
1086 int ret, offset, type, sizes;
1087
1088 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1089 if (file == NULL)
1090 return -ENOMEM;
1091
1023dbd9
MB		 1092 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
1093 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 1094 file[PAGE_SIZE - 1] = '\0';
1095
1096 ret = request_firmware(&firmware, file, dsp->dev);
1097 if (ret != 0) {
1098 adsp_err(dsp, "Failed to request '%s'\n", file);
1099 goto out;
1100 }
1101 ret = -EINVAL;
1102
1103 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1104 if (pos >= firmware->size) {
1105 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1106 file, firmware->size);
1107 goto out_fw;
1108 }
1109
7585a5b0 1110 header = (void *)&firmware->data[0];
2159ad93
MB		 1111
1112 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1113 adsp_err(dsp, "%s: invalid magic\n", file);
1114 goto out_fw;
1115 }
1116
2323736d
CK		 1117 switch (header->ver) {
1118 case 0:
c61e59fe
CK		 1119 adsp_warn(dsp, "%s: Depreciated file format %d\n",
1120 file, header->ver);
1121 break;
2323736d 1122 case 1:
cb5b57a9 1123 case 2:
2323736d
CK		 1124 break;
1125 default:
2159ad93
MB		 1126 adsp_err(dsp, "%s: unknown file format %d\n",
1127 file, header->ver);
1128 goto out_fw;
1129 }
2323736d 1130
3626992a 1131 adsp_info(dsp, "Firmware version: %d\n", header->ver);
2323736d 1132 dsp->fw_ver = header->ver;
2159ad93
MB		 1133
1134 if (header->core != dsp->type) {
1135 adsp_err(dsp, "%s: invalid core %d != %d\n",
1136 file, header->core, dsp->type);
1137 goto out_fw;
1138 }
1139
1140 switch (dsp->type) {
1141 case WMFW_ADSP1:
1142 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1143 adsp1_sizes = (void *)&(header[1]);
1144 footer = (void *)&(adsp1_sizes[1]);
1145 sizes = sizeof(*adsp1_sizes);
1146
1147 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
1148 file, le32_to_cpu(adsp1_sizes->dm),
1149 le32_to_cpu(adsp1_sizes->pm),
1150 le32_to_cpu(adsp1_sizes->zm));
1151 break;
1152
1153 case WMFW_ADSP2:
1154 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
1155 adsp2_sizes = (void *)&(header[1]);
1156 footer = (void *)&(adsp2_sizes[1]);
1157 sizes = sizeof(*adsp2_sizes);
1158
1159 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
1160 file, le32_to_cpu(adsp2_sizes->xm),
1161 le32_to_cpu(adsp2_sizes->ym),
1162 le32_to_cpu(adsp2_sizes->pm),
1163 le32_to_cpu(adsp2_sizes->zm));
1164 break;
1165
1166 default:
6c452bda 1167 WARN(1, "Unknown DSP type");
2159ad93
MB		 1168 goto out_fw;
1169 }
1170
1171 if (le32_to_cpu(header->len) != sizeof(*header) +
1172 sizes + sizeof(*footer)) {
1173 adsp_err(dsp, "%s: unexpected header length %d\n",
1174 file, le32_to_cpu(header->len));
1175 goto out_fw;
1176 }
1177
1178 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1179 le64_to_cpu(footer->timestamp));
1180
1181 while (pos < firmware->size &&
1182 pos - firmware->size > sizeof(*region)) {
1183 region = (void *)&(firmware->data[pos]);
1184 region_name = "Unknown";
1185 reg = 0;
1186 text = NULL;
1187 offset = le32_to_cpu(region->offset) & 0xffffff;
1188 type = be32_to_cpu(region->type) & 0xff;
1189 mem = wm_adsp_find_region(dsp, type);
7585a5b0 1190
2159ad93
MB		 1191 switch (type) {
1192 case WMFW_NAME_TEXT:
1193 region_name = "Firmware name";
1194 text = kzalloc(le32_to_cpu(region->len) + 1,
1195 GFP_KERNEL);
1196 break;
2323736d
CK		 1197 case WMFW_ALGORITHM_DATA:
1198 region_name = "Algorithm";
1199 ret = wm_adsp_parse_coeff(dsp, region);
1200 if (ret != 0)
1201 goto out_fw;
1202 break;
2159ad93
MB		 1203 case WMFW_INFO_TEXT:
1204 region_name = "Information";
1205 text = kzalloc(le32_to_cpu(region->len) + 1,
1206 GFP_KERNEL);
1207 break;
1208 case WMFW_ABSOLUTE:
1209 region_name = "Absolute";
1210 reg = offset;
1211 break;
1212 case WMFW_ADSP1_PM:
2159ad93 1213 region_name = "PM";
45b9ee72 1214 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1215 break;
1216 case WMFW_ADSP1_DM:
2159ad93 1217 region_name = "DM";
45b9ee72 1218 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1219 break;
1220 case WMFW_ADSP2_XM:
2159ad93 1221 region_name = "XM";
45b9ee72 1222 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1223 break;
1224 case WMFW_ADSP2_YM:
2159ad93 1225 region_name = "YM";
45b9ee72 1226 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1227 break;
1228 case WMFW_ADSP1_ZM:
2159ad93 1229 region_name = "ZM";
45b9ee72 1230 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1231 break;
1232 default:
1233 adsp_warn(dsp,
1234 "%s.%d: Unknown region type %x at %d(%x)\n",
1235 file, regions, type, pos, pos);
1236 break;
1237 }
1238
1239 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1240 regions, le32_to_cpu(region->len), offset,
1241 region_name);
1242
1243 if (text) {
1244 memcpy(text, region->data, le32_to_cpu(region->len));
1245 adsp_info(dsp, "%s: %s\n", file, text);
1246 kfree(text);
1247 }
1248
1249 if (reg) {
cdcd7f72
CK		 1250 buf = wm_adsp_buf_alloc(region->data,
1251 le32_to_cpu(region->len),
1252 &buf_list);
1253 if (!buf) {
1254 adsp_err(dsp, "Out of memory\n");
1255 ret = -ENOMEM;
1256 goto out_fw;
1257 }
c1a7898d 1258
cdcd7f72
CK		 1259 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1260 le32_to_cpu(region->len));
1261 if (ret != 0) {
1262 adsp_err(dsp,
1263 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1264 file, regions,
1265 le32_to_cpu(region->len), offset,
1266 region_name, ret);
1267 goto out_fw;
2159ad93
MB		 1268 }
1269 }
1270
1271 pos += le32_to_cpu(region->len) + sizeof(*region);
1272 regions++;
1273 }
cf17c83c
MB		 1274
1275 ret = regmap_async_complete(regmap);
1276 if (ret != 0) {
1277 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1278 goto out_fw;
1279 }
1280
2159ad93
MB		 1281 if (pos > firmware->size)
1282 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1283 file, regions, pos - firmware->size);
1284
f9f55e31
RF		 1285 wm_adsp_debugfs_save_wmfwname(dsp, file);
1286
2159ad93 1287out_fw:
cf17c83c
MB		 1288 regmap_async_complete(regmap);
1289 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 1290 release_firmware(firmware);
1291out:
1292 kfree(file);
1293
1294 return ret;
1295}
1296
2323736d
CK		 1297static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
1298 const struct wm_adsp_alg_region *alg_region)
1299{
1300 struct wm_coeff_ctl *ctl;
1301
1302 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1303 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
1304 alg_region->alg == ctl->alg_region.alg &&
1305 alg_region->type == ctl->alg_region.type) {
1306 ctl->alg_region.base = alg_region->base;
1307 }
1308 }
1309}
1310
3809f001 1311static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
b618a185 1312 unsigned int pos, unsigned int len)
db40517c 1313{
b618a185
CK		 1314 void *alg;
1315 int ret;
db40517c 1316 __be32 val;
db40517c 1317
3809f001 1318 if (n_algs == 0) {
b618a185
CK		 1319 adsp_err(dsp, "No algorithms\n");
1320 return ERR_PTR(-EINVAL);
db40517c
MB		 1321 }
1322
3809f001
CK		 1323 if (n_algs > 1024) {
1324 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
b618a185
CK		 1325 return ERR_PTR(-EINVAL);
1326 }
db40517c 1327
b618a185
CK		 1328 /* Read the terminator first to validate the length */
1329 ret = regmap_raw_read(dsp->regmap, pos + len, &val, sizeof(val));
1330 if (ret != 0) {
1331 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1332 ret);
1333 return ERR_PTR(ret);
1334 }
db40517c 1335
b618a185
CK		 1336 if (be32_to_cpu(val) != 0xbedead)
1337 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
1338 pos + len, be32_to_cpu(val));
d62f4bc6 1339
b618a185
CK		 1340 alg = kzalloc(len * 2, GFP_KERNEL | GFP_DMA);
1341 if (!alg)
1342 return ERR_PTR(-ENOMEM);
db40517c 1343
b618a185
CK		 1344 ret = regmap_raw_read(dsp->regmap, pos, alg, len * 2);
1345 if (ret != 0) {
1346 adsp_err(dsp, "Failed to read algorithm list: %d\n",
1347 ret);
1348 kfree(alg);
1349 return ERR_PTR(ret);
1350 }
ac50009f 1351
b618a185
CK		 1352 return alg;
1353}
ac50009f 1354
d9d20e17
CK		 1355static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
1356 int type, __be32 id,
1357 __be32 base)
1358{
1359 struct wm_adsp_alg_region *alg_region;
1360
1361 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
1362 if (!alg_region)
1363 return ERR_PTR(-ENOMEM);
1364
1365 alg_region->type = type;
1366 alg_region->alg = be32_to_cpu(id);
1367 alg_region->base = be32_to_cpu(base);
1368
1369 list_add_tail(&alg_region->list, &dsp->alg_regions);
1370
2323736d
CK		 1371 if (dsp->fw_ver > 0)
1372 wm_adsp_ctl_fixup_base(dsp, alg_region);
1373
d9d20e17
CK		 1374 return alg_region;
1375}
1376
b618a185
CK		 1377static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
1378{
1379 struct wmfw_adsp1_id_hdr adsp1_id;
1380 struct wmfw_adsp1_alg_hdr *adsp1_alg;
3809f001 1381 struct wm_adsp_alg_region *alg_region;
b618a185
CK		 1382 const struct wm_adsp_region *mem;
1383 unsigned int pos, len;
3809f001 1384 size_t n_algs;
b618a185 1385 int i, ret;
db40517c 1386
b618a185
CK		 1387 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
1388 if (WARN_ON(!mem))
1389 return -EINVAL;
1390
1391 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
1392 sizeof(adsp1_id));
1393 if (ret != 0) {
1394 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1395 ret);
1396 return ret;
1397 }
db40517c 1398
3809f001 1399 n_algs = be32_to_cpu(adsp1_id.n_algs);
b618a185
CK		 1400 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
1401 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1402 dsp->fw_id,
1403 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
1404 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
1405 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
3809f001 1406 n_algs);
b618a185 1407
d9d20e17
CK		 1408 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1409 adsp1_id.fw.id, adsp1_id.zm);
1410 if (IS_ERR(alg_region))
1411 return PTR_ERR(alg_region);
d62f4bc6 1412
d9d20e17
CK		 1413 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1414 adsp1_id.fw.id, adsp1_id.dm);
1415 if (IS_ERR(alg_region))
1416 return PTR_ERR(alg_region);
db40517c 1417
b618a185 1418 pos = sizeof(adsp1_id) / 2;
3809f001 1419 len = (sizeof(*adsp1_alg) * n_algs) / 2;
b618a185 1420
3809f001 1421 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
b618a185
CK		 1422 if (IS_ERR(adsp1_alg))
1423 return PTR_ERR(adsp1_alg);
1424
3809f001 1425 for (i = 0; i < n_algs; i++) {
b618a185
CK		 1426 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
1427 i, be32_to_cpu(adsp1_alg[i].alg.id),
1428 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
1429 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
1430 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
1431 be32_to_cpu(adsp1_alg[i].dm),
1432 be32_to_cpu(adsp1_alg[i].zm));
ac50009f 1433
d9d20e17
CK		 1434 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1435 adsp1_alg[i].alg.id,
1436 adsp1_alg[i].dm);
1437 if (IS_ERR(alg_region)) {
1438 ret = PTR_ERR(alg_region);
b618a185
CK		 1439 goto out;
1440 }
2323736d
CK		 1441 if (dsp->fw_ver == 0) {
1442 if (i + 1 < n_algs) {
1443 len = be32_to_cpu(adsp1_alg[i + 1].dm);
1444 len -= be32_to_cpu(adsp1_alg[i].dm);
1445 len *= 4;
1446 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1447 len, NULL, 0, 0);
2323736d
CK		 1448 } else {
1449 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
1450 be32_to_cpu(adsp1_alg[i].alg.id));
1451 }
b618a185 1452 }
ac50009f 1453
d9d20e17
CK		 1454 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1455 adsp1_alg[i].alg.id,
1456 adsp1_alg[i].zm);
1457 if (IS_ERR(alg_region)) {
1458 ret = PTR_ERR(alg_region);
b618a185
CK		 1459 goto out;
1460 }
2323736d
CK		 1461 if (dsp->fw_ver == 0) {
1462 if (i + 1 < n_algs) {
1463 len = be32_to_cpu(adsp1_alg[i + 1].zm);
1464 len -= be32_to_cpu(adsp1_alg[i].zm);
1465 len *= 4;
1466 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1467 len, NULL, 0, 0);
2323736d
CK		 1468 } else {
1469 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1470 be32_to_cpu(adsp1_alg[i].alg.id));
1471 }
b618a185 1472 }
db40517c
MB		 1473 }
1474
b618a185
CK		 1475out:
1476 kfree(adsp1_alg);
1477 return ret;
1478}
db40517c 1479
b618a185
CK		 1480static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
1481{
1482 struct wmfw_adsp2_id_hdr adsp2_id;
1483 struct wmfw_adsp2_alg_hdr *adsp2_alg;
3809f001 1484 struct wm_adsp_alg_region *alg_region;
b618a185
CK		 1485 const struct wm_adsp_region *mem;
1486 unsigned int pos, len;
3809f001 1487 size_t n_algs;
b618a185
CK		 1488 int i, ret;
1489
1490 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
1491 if (WARN_ON(!mem))
d62f4bc6 1492 return -EINVAL;
d62f4bc6 1493
b618a185
CK		 1494 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
1495 sizeof(adsp2_id));
db40517c 1496 if (ret != 0) {
b618a185
CK		 1497 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1498 ret);
db40517c
MB		 1499 return ret;
1500 }
1501
3809f001 1502 n_algs = be32_to_cpu(adsp2_id.n_algs);
b618a185 1503 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
f9f55e31 1504 dsp->fw_id_version = be32_to_cpu(adsp2_id.fw.ver);
b618a185
CK		 1505 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1506 dsp->fw_id,
f9f55e31
RF		 1507 (dsp->fw_id_version & 0xff0000) >> 16,
1508 (dsp->fw_id_version & 0xff00) >> 8,
1509 dsp->fw_id_version & 0xff,
3809f001 1510 n_algs);
b618a185 1511
d9d20e17
CK		 1512 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1513 adsp2_id.fw.id, adsp2_id.xm);
1514 if (IS_ERR(alg_region))
1515 return PTR_ERR(alg_region);
db40517c 1516
d9d20e17
CK		 1517 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1518 adsp2_id.fw.id, adsp2_id.ym);
1519 if (IS_ERR(alg_region))
1520 return PTR_ERR(alg_region);
db40517c 1521
d9d20e17
CK		 1522 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
1523 adsp2_id.fw.id, adsp2_id.zm);
1524 if (IS_ERR(alg_region))
1525 return PTR_ERR(alg_region);
db40517c 1526
b618a185 1527 pos = sizeof(adsp2_id) / 2;
3809f001 1528 len = (sizeof(*adsp2_alg) * n_algs) / 2;
db40517c 1529
3809f001 1530 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
b618a185
CK		 1531 if (IS_ERR(adsp2_alg))
1532 return PTR_ERR(adsp2_alg);
471f4885 1533
3809f001 1534 for (i = 0; i < n_algs; i++) {
b618a185
CK		 1535 adsp_info(dsp,
1536 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
1537 i, be32_to_cpu(adsp2_alg[i].alg.id),
1538 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
1539 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
1540 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
1541 be32_to_cpu(adsp2_alg[i].xm),
1542 be32_to_cpu(adsp2_alg[i].ym),
1543 be32_to_cpu(adsp2_alg[i].zm));
db40517c 1544
d9d20e17
CK		 1545 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1546 adsp2_alg[i].alg.id,
1547 adsp2_alg[i].xm);
1548 if (IS_ERR(alg_region)) {
1549 ret = PTR_ERR(alg_region);
b618a185
CK		 1550 goto out;
1551 }
2323736d
CK		 1552 if (dsp->fw_ver == 0) {
1553 if (i + 1 < n_algs) {
1554 len = be32_to_cpu(adsp2_alg[i + 1].xm);
1555 len -= be32_to_cpu(adsp2_alg[i].xm);
1556 len *= 4;
1557 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1558 len, NULL, 0, 0);
2323736d
CK		 1559 } else {
1560 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
1561 be32_to_cpu(adsp2_alg[i].alg.id));
1562 }
b618a185 1563 }
471f4885 1564
d9d20e17
CK		 1565 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1566 adsp2_alg[i].alg.id,
1567 adsp2_alg[i].ym);
1568 if (IS_ERR(alg_region)) {
1569 ret = PTR_ERR(alg_region);
b618a185
CK		 1570 goto out;
1571 }
2323736d
CK		 1572 if (dsp->fw_ver == 0) {
1573 if (i + 1 < n_algs) {
1574 len = be32_to_cpu(adsp2_alg[i + 1].ym);
1575 len -= be32_to_cpu(adsp2_alg[i].ym);
1576 len *= 4;
1577 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1578 len, NULL, 0, 0);
2323736d
CK		 1579 } else {
1580 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
1581 be32_to_cpu(adsp2_alg[i].alg.id));
1582 }
b618a185 1583 }
471f4885 1584
d9d20e17
CK		 1585 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
1586 adsp2_alg[i].alg.id,
1587 adsp2_alg[i].zm);
1588 if (IS_ERR(alg_region)) {
1589 ret = PTR_ERR(alg_region);
b618a185
CK		 1590 goto out;
1591 }
2323736d
CK		 1592 if (dsp->fw_ver == 0) {
1593 if (i + 1 < n_algs) {
1594 len = be32_to_cpu(adsp2_alg[i + 1].zm);
1595 len -= be32_to_cpu(adsp2_alg[i].zm);
1596 len *= 4;
1597 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1598 len, NULL, 0, 0);
2323736d
CK		 1599 } else {
1600 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1601 be32_to_cpu(adsp2_alg[i].alg.id));
1602 }
db40517c
MB		 1603 }
1604 }
1605
1606out:
b618a185 1607 kfree(adsp2_alg);
db40517c
MB		 1608 return ret;
1609}
1610
2159ad93
MB		 1611static int wm_adsp_load_coeff(struct wm_adsp *dsp)
1612{
cf17c83c 1613 LIST_HEAD(buf_list);
2159ad93
MB		 1614 struct regmap *regmap = dsp->regmap;
1615 struct wmfw_coeff_hdr *hdr;
1616 struct wmfw_coeff_item *blk;
1617 const struct firmware *firmware;
471f4885
MB		 1618 const struct wm_adsp_region *mem;
1619 struct wm_adsp_alg_region *alg_region;
2159ad93
MB		 1620 const char *region_name;
1621 int ret, pos, blocks, type, offset, reg;
1622 char *file;
cf17c83c 1623 struct wm_adsp_buf *buf;
2159ad93
MB		 1624
1625 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1626 if (file == NULL)
1627 return -ENOMEM;
1628
1023dbd9
MB		 1629 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
1630 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 1631 file[PAGE_SIZE - 1] = '\0';
1632
1633 ret = request_firmware(&firmware, file, dsp->dev);
1634 if (ret != 0) {
1635 adsp_warn(dsp, "Failed to request '%s'\n", file);
1636 ret = 0;
1637 goto out;
1638 }
1639 ret = -EINVAL;
1640
1641 if (sizeof(*hdr) >= firmware->size) {
1642 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1643 file, firmware->size);
1644 goto out_fw;
1645 }
1646
7585a5b0 1647 hdr = (void *)&firmware->data[0];
2159ad93
MB		 1648 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
1649 adsp_err(dsp, "%s: invalid magic\n", file);
a4cdbec7 1650 goto out_fw;
2159ad93
MB		 1651 }
1652
c712326d
MB		 1653 switch (be32_to_cpu(hdr->rev) & 0xff) {
1654 case 1:
1655 break;
1656 default:
1657 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
1658 file, be32_to_cpu(hdr->rev) & 0xff);
1659 ret = -EINVAL;
1660 goto out_fw;
1661 }
1662
2159ad93
MB		 1663 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
1664 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
1665 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
1666 le32_to_cpu(hdr->ver) & 0xff);
1667
1668 pos = le32_to_cpu(hdr->len);
1669
1670 blocks = 0;
1671 while (pos < firmware->size &&
1672 pos - firmware->size > sizeof(*blk)) {
7585a5b0 1673 blk = (void *)(&firmware->data[pos]);
2159ad93 1674
c712326d
MB		 1675 type = le16_to_cpu(blk->type);
1676 offset = le16_to_cpu(blk->offset);
2159ad93
MB		 1677
1678 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
1679 file, blocks, le32_to_cpu(blk->id),
1680 (le32_to_cpu(blk->ver) >> 16) & 0xff,
1681 (le32_to_cpu(blk->ver) >> 8) & 0xff,
1682 le32_to_cpu(blk->ver) & 0xff);
1683 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
1684 file, blocks, le32_to_cpu(blk->len), offset, type);
1685
1686 reg = 0;
1687 region_name = "Unknown";
1688 switch (type) {
c712326d
MB		 1689 case (WMFW_NAME_TEXT << 8):
1690 case (WMFW_INFO_TEXT << 8):
2159ad93 1691 break;
c712326d 1692 case (WMFW_ABSOLUTE << 8):
f395a218
MB		 1693 /*
1694 * Old files may use this for global
1695 * coefficients.
1696 */
1697 if (le32_to_cpu(blk->id) == dsp->fw_id &&
1698 offset == 0) {
1699 region_name = "global coefficients";
1700 mem = wm_adsp_find_region(dsp, type);
1701 if (!mem) {
1702 adsp_err(dsp, "No ZM\n");
1703 break;
1704 }
1705 reg = wm_adsp_region_to_reg(mem, 0);
1706
1707 } else {
1708 region_name = "register";
1709 reg = offset;
1710 }
2159ad93 1711 break;
471f4885
MB		 1712
1713 case WMFW_ADSP1_DM:
1714 case WMFW_ADSP1_ZM:
1715 case WMFW_ADSP2_XM:
1716 case WMFW_ADSP2_YM:
1717 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
1718 file, blocks, le32_to_cpu(blk->len),
1719 type, le32_to_cpu(blk->id));
1720
1721 mem = wm_adsp_find_region(dsp, type);
1722 if (!mem) {
1723 adsp_err(dsp, "No base for region %x\n", type);
1724 break;
1725 }
1726
1727 reg = 0;
1728 list_for_each_entry(alg_region,
1729 &dsp->alg_regions, list) {
1730 if (le32_to_cpu(blk->id) == alg_region->alg &&
1731 type == alg_region->type) {
338c5188 1732 reg = alg_region->base;
471f4885
MB		 1733 reg = wm_adsp_region_to_reg(mem,
1734 reg);
338c5188 1735 reg += offset;
d733dc08 1736 break;
471f4885
MB		 1737 }
1738 }
1739
1740 if (reg == 0)
1741 adsp_err(dsp, "No %x for algorithm %x\n",
1742 type, le32_to_cpu(blk->id));
1743 break;
1744
2159ad93 1745 default:
25c62f7e
MB		 1746 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
1747 file, blocks, type, pos);
2159ad93
MB		 1748 break;
1749 }
1750
1751 if (reg) {
cf17c83c
MB		 1752 buf = wm_adsp_buf_alloc(blk->data,
1753 le32_to_cpu(blk->len),
1754 &buf_list);
a76fefab
MB		 1755 if (!buf) {
1756 adsp_err(dsp, "Out of memory\n");
f4b82812
WY		 1757 ret = -ENOMEM;
1758 goto out_fw;
a76fefab
MB		 1759 }
1760
20da6d5a
MB		 1761 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
1762 file, blocks, le32_to_cpu(blk->len),
1763 reg);
cf17c83c
MB		 1764 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1765 le32_to_cpu(blk->len));
2159ad93
MB		 1766 if (ret != 0) {
1767 adsp_err(dsp,
43bc3bf6
DP		 1768 "%s.%d: Failed to write to %x in %s: %d\n",
1769 file, blocks, reg, region_name, ret);
2159ad93
MB		 1770 }
1771 }
1772
be951017 1773 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
2159ad93
MB		 1774 blocks++;
1775 }
1776
cf17c83c
MB		 1777 ret = regmap_async_complete(regmap);
1778 if (ret != 0)
1779 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1780
2159ad93
MB		 1781 if (pos > firmware->size)
1782 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1783 file, blocks, pos - firmware->size);
1784
f9f55e31
RF		 1785 wm_adsp_debugfs_save_binname(dsp, file);
1786
2159ad93 1787out_fw:
9da7a5a9 1788 regmap_async_complete(regmap);
2159ad93 1789 release_firmware(firmware);
cf17c83c 1790 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 1791out:
1792 kfree(file);
f4b82812 1793 return ret;
2159ad93
MB		 1794}
1795
3809f001 1796int wm_adsp1_init(struct wm_adsp *dsp)
5e7a7a22 1797{
3809f001 1798 INIT_LIST_HEAD(&dsp->alg_regions);
5e7a7a22 1799
078e7183
CK		 1800 mutex_init(&dsp->pwr_lock);
1801
5e7a7a22
MB		 1802 return 0;
1803}
1804EXPORT_SYMBOL_GPL(wm_adsp1_init);
1805
2159ad93
MB		 1806int wm_adsp1_event(struct snd_soc_dapm_widget *w,
1807 struct snd_kcontrol *kcontrol,
1808 int event)
1809{
72718517 1810 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2159ad93
MB		 1811 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1812 struct wm_adsp *dsp = &dsps[w->shift];
b0101b4f 1813 struct wm_adsp_alg_region *alg_region;
6ab2b7b4 1814 struct wm_coeff_ctl *ctl;
2159ad93 1815 int ret;
7585a5b0 1816 unsigned int val;
2159ad93 1817
00200107 1818 dsp->card = codec->component.card;
92bb4c32 1819
078e7183
CK		 1820 mutex_lock(&dsp->pwr_lock);
1821
2159ad93
MB		 1822 switch (event) {
1823 case SND_SOC_DAPM_POST_PMU:
1824 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1825 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
1826
94e205bf
CR		 1827 /*
1828 * For simplicity set the DSP clock rate to be the
1829 * SYSCLK rate rather than making it configurable.
1830 */
7585a5b0 1831 if (dsp->sysclk_reg) {
94e205bf
CR		 1832 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
1833 if (ret != 0) {
1834 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
1835 ret);
078e7183 1836 goto err_mutex;
94e205bf
CR		 1837 }
1838
1839 val = (val & dsp->sysclk_mask)
1840 >> dsp->sysclk_shift;
1841
1842 ret = regmap_update_bits(dsp->regmap,
1843 dsp->base + ADSP1_CONTROL_31,
1844 ADSP1_CLK_SEL_MASK, val);
1845 if (ret != 0) {
1846 adsp_err(dsp, "Failed to set clock rate: %d\n",
1847 ret);
078e7183 1848 goto err_mutex;
94e205bf
CR		 1849 }
1850 }
1851
2159ad93
MB		 1852 ret = wm_adsp_load(dsp);
1853 if (ret != 0)
078e7183 1854 goto err_ena;
2159ad93 1855
b618a185 1856 ret = wm_adsp1_setup_algs(dsp);
db40517c 1857 if (ret != 0)
078e7183 1858 goto err_ena;
db40517c 1859
2159ad93
MB		 1860 ret = wm_adsp_load_coeff(dsp);
1861 if (ret != 0)
078e7183 1862 goto err_ena;
2159ad93 1863
0c2e3f34 1864 /* Initialize caches for enabled and unset controls */
81ad93ec 1865 ret = wm_coeff_init_control_caches(dsp);
6ab2b7b4 1866 if (ret != 0)
078e7183 1867 goto err_ena;
6ab2b7b4 1868
0c2e3f34 1869 /* Sync set controls */
81ad93ec 1870 ret = wm_coeff_sync_controls(dsp);
6ab2b7b4 1871 if (ret != 0)
078e7183 1872 goto err_ena;
6ab2b7b4 1873
2159ad93
MB		 1874 /* Start the core running */
1875 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1876 ADSP1_CORE_ENA | ADSP1_START,
1877 ADSP1_CORE_ENA | ADSP1_START);
1878 break;
1879
1880 case SND_SOC_DAPM_PRE_PMD:
1881 /* Halt the core */
1882 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1883 ADSP1_CORE_ENA | ADSP1_START, 0);
1884
1885 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
1886 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
1887
1888 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1889 ADSP1_SYS_ENA, 0);
6ab2b7b4 1890
81ad93ec 1891 list_for_each_entry(ctl, &dsp->ctl_list, list)
6ab2b7b4 1892 ctl->enabled = 0;
b0101b4f
DP		 1893
1894 while (!list_empty(&dsp->alg_regions)) {
1895 alg_region = list_first_entry(&dsp->alg_regions,
1896 struct wm_adsp_alg_region,
1897 list);
1898 list_del(&alg_region->list);
1899 kfree(alg_region);
1900 }
2159ad93
MB		 1901 break;
1902
1903 default:
1904 break;
1905 }
1906
078e7183
CK		 1907 mutex_unlock(&dsp->pwr_lock);
1908
2159ad93
MB		 1909 return 0;
1910
078e7183 1911err_ena:
2159ad93
MB		 1912 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1913 ADSP1_SYS_ENA, 0);
078e7183
CK		 1914err_mutex:
1915 mutex_unlock(&dsp->pwr_lock);
1916
2159ad93
MB		 1917 return ret;
1918}
1919EXPORT_SYMBOL_GPL(wm_adsp1_event);
1920
1921static int wm_adsp2_ena(struct wm_adsp *dsp)
1922{
1923 unsigned int val;
1924 int ret, count;
1925
1552c325
MB		 1926 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
1927 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2159ad93
MB		 1928 if (ret != 0)
1929 return ret;
1930
1931 /* Wait for the RAM to start, should be near instantaneous */
939fd1e8 1932 for (count = 0; count < 10; ++count) {
2159ad93
MB		 1933 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1,
1934 &val);
1935 if (ret != 0)
1936 return ret;
939fd1e8
CK		 1937
1938 if (val & ADSP2_RAM_RDY)
1939 break;
1940
1941 msleep(1);
1942 }
2159ad93
MB		 1943
1944 if (!(val & ADSP2_RAM_RDY)) {
1945 adsp_err(dsp, "Failed to start DSP RAM\n");
1946 return -EBUSY;
1947 }
1948
1949 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
2159ad93
MB		 1950
1951 return 0;
1952}
1953
18b1a902 1954static void wm_adsp2_boot_work(struct work_struct *work)
2159ad93 1955{
d8a64d6a
CK		 1956 struct wm_adsp *dsp = container_of(work,
1957 struct wm_adsp,
1958 boot_work);
2159ad93 1959 int ret;
d8a64d6a 1960 unsigned int val;
2159ad93 1961
078e7183
CK		 1962 mutex_lock(&dsp->pwr_lock);
1963
d8a64d6a
CK		 1964 /*
1965 * For simplicity set the DSP clock rate to be the
1966 * SYSCLK rate rather than making it configurable.
1967 */
1968 ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
1969 if (ret != 0) {
1970 adsp_err(dsp, "Failed to read SYSCLK state: %d\n", ret);
078e7183 1971 goto err_mutex;
d8a64d6a
CK		 1972 }
1973 val = (val & ARIZONA_SYSCLK_FREQ_MASK)
1974 >> ARIZONA_SYSCLK_FREQ_SHIFT;
92bb4c32 1975
d8a64d6a
CK		 1976 ret = regmap_update_bits_async(dsp->regmap,
1977 dsp->base + ADSP2_CLOCKING,
1978 ADSP2_CLK_SEL_MASK, val);
1979 if (ret != 0) {
1980 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
078e7183 1981 goto err_mutex;
d8a64d6a 1982 }
dd49e2c8 1983
d8a64d6a
CK		 1984 ret = wm_adsp2_ena(dsp);
1985 if (ret != 0)
078e7183 1986 goto err_mutex;
2159ad93 1987
d8a64d6a
CK		 1988 ret = wm_adsp_load(dsp);
1989 if (ret != 0)
078e7183 1990 goto err_ena;
2159ad93 1991
b618a185 1992 ret = wm_adsp2_setup_algs(dsp);
d8a64d6a 1993 if (ret != 0)
078e7183 1994 goto err_ena;
db40517c 1995
d8a64d6a
CK		 1996 ret = wm_adsp_load_coeff(dsp);
1997 if (ret != 0)
078e7183 1998 goto err_ena;
2159ad93 1999
d8a64d6a
CK		 2000 /* Initialize caches for enabled and unset controls */
2001 ret = wm_coeff_init_control_caches(dsp);
2002 if (ret != 0)
078e7183 2003 goto err_ena;
6ab2b7b4 2004
d8a64d6a
CK		 2005 /* Sync set controls */
2006 ret = wm_coeff_sync_controls(dsp);
2007 if (ret != 0)
078e7183 2008 goto err_ena;
d8a64d6a 2009
d8a64d6a
CK		 2010 dsp->running = true;
2011
078e7183
CK		 2012 mutex_unlock(&dsp->pwr_lock);
2013
d8a64d6a 2014 return;
6ab2b7b4 2015
078e7183 2016err_ena:
d8a64d6a
CK		 2017 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2018 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
078e7183
CK		 2019err_mutex:
2020 mutex_unlock(&dsp->pwr_lock);
d8a64d6a
CK		 2021}
2022
12db5edd
CK		 2023int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
2024 struct snd_kcontrol *kcontrol, int event)
2025{
72718517 2026 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
12db5edd
CK		 2027 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2028 struct wm_adsp *dsp = &dsps[w->shift];
2029
00200107 2030 dsp->card = codec->component.card;
12db5edd
CK		 2031
2032 switch (event) {
2033 case SND_SOC_DAPM_PRE_PMU:
2034 queue_work(system_unbound_wq, &dsp->boot_work);
2035 break;
2036 default:
2037 break;
cab27258 2038 }
12db5edd
CK		 2039
2040 return 0;
2041}
2042EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
2043
d8a64d6a
CK		 2044int wm_adsp2_event(struct snd_soc_dapm_widget *w,
2045 struct snd_kcontrol *kcontrol, int event)
2046{
72718517 2047 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
d8a64d6a
CK		 2048 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2049 struct wm_adsp *dsp = &dsps[w->shift];
2050 struct wm_adsp_alg_region *alg_region;
2051 struct wm_coeff_ctl *ctl;
2052 int ret;
2053
d8a64d6a
CK		 2054 switch (event) {
2055 case SND_SOC_DAPM_POST_PMU:
d8a64d6a
CK		 2056 flush_work(&dsp->boot_work);
2057
2058 if (!dsp->running)
2059 return -EIO;
6ab2b7b4 2060
d8a64d6a
CK		 2061 ret = regmap_update_bits(dsp->regmap,
2062 dsp->base + ADSP2_CONTROL,
00e4c3b6
CK		 2063 ADSP2_CORE_ENA | ADSP2_START,
2064 ADSP2_CORE_ENA | ADSP2_START);
2159ad93
MB		 2065 if (ret != 0)
2066 goto err;
2067 break;
2068
2069 case SND_SOC_DAPM_PRE_PMD:
10337b07
RF		 2070 /* Log firmware state, it can be useful for analysis */
2071 wm_adsp2_show_fw_status(dsp);
2072
078e7183
CK		 2073 mutex_lock(&dsp->pwr_lock);
2074
f9f55e31
RF		 2075 wm_adsp_debugfs_clear(dsp);
2076
2077 dsp->fw_id = 0;
2078 dsp->fw_id_version = 0;
1023dbd9
MB		 2079 dsp->running = false;
2080
2159ad93 2081 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e
MB		 2082 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
2083 ADSP2_START, 0);
973838a0 2084
2d30b575
MB		 2085 /* Make sure DMAs are quiesced */
2086 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2087 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
2088 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2089
81ad93ec 2090 list_for_each_entry(ctl, &dsp->ctl_list, list)
6ab2b7b4 2091 ctl->enabled = 0;
6ab2b7b4 2092
471f4885
MB		 2093 while (!list_empty(&dsp->alg_regions)) {
2094 alg_region = list_first_entry(&dsp->alg_regions,
2095 struct wm_adsp_alg_region,
2096 list);
2097 list_del(&alg_region->list);
2098 kfree(alg_region);
2099 }
ddbc5efe 2100
078e7183
CK		 2101 mutex_unlock(&dsp->pwr_lock);
2102
ddbc5efe 2103 adsp_dbg(dsp, "Shutdown complete\n");
2159ad93
MB		 2104 break;
2105
2106 default:
2107 break;
2108 }
2109
2110 return 0;
2111err:
2112 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e 2113 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2159ad93
MB		 2114 return ret;
2115}
2116EXPORT_SYMBOL_GPL(wm_adsp2_event);
973838a0 2117
f5e2ce92
RF		 2118int wm_adsp2_codec_probe(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2119{
f9f55e31
RF		 2120 wm_adsp2_init_debugfs(dsp, codec);
2121
218e5087 2122 return snd_soc_add_codec_controls(codec,
336d0442
RF		 2123 &wm_adsp_fw_controls[dsp->num - 1],
2124 1);
f5e2ce92
RF		 2125}
2126EXPORT_SYMBOL_GPL(wm_adsp2_codec_probe);
2127
2128int wm_adsp2_codec_remove(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2129{
f9f55e31
RF		 2130 wm_adsp2_cleanup_debugfs(dsp);
2131
f5e2ce92
RF		 2132 return 0;
2133}
2134EXPORT_SYMBOL_GPL(wm_adsp2_codec_remove);
2135
81ac58b1 2136int wm_adsp2_init(struct wm_adsp *dsp)
973838a0
MB		 2137{
2138 int ret;
2139
10a2b662
MB		 2140 /*
2141 * Disable the DSP memory by default when in reset for a small
2142 * power saving.
2143 */
3809f001 2144 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
10a2b662
MB		 2145 ADSP2_MEM_ENA, 0);
2146 if (ret != 0) {
3809f001 2147 adsp_err(dsp, "Failed to clear memory retention: %d\n", ret);
10a2b662
MB		 2148 return ret;
2149 }
2150
3809f001
CK		 2151 INIT_LIST_HEAD(&dsp->alg_regions);
2152 INIT_LIST_HEAD(&dsp->ctl_list);
2153 INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work);
6ab2b7b4 2154
078e7183
CK		 2155 mutex_init(&dsp->pwr_lock);
2156
973838a0
MB		 2157 return 0;
2158}
2159EXPORT_SYMBOL_GPL(wm_adsp2_init);
0a37c6ef
PD		 2160
2161MODULE_LICENSE("GPL v2");
Empty description
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