[linux.git] / drivers / char / agp / via-agp.c

/*
 * VIA AGPGART routines.
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/agp_backend.h>
#include "agp.h"

static const struct pci_device_id agp_via_pci_table[];

#define VIA_GARTCTRL	0x80
#define VIA_APSIZE	0x84
#define VIA_ATTBASE	0x88

#define VIA_AGP3_GARTCTRL	0x90
#define VIA_AGP3_APSIZE		0x94
#define VIA_AGP3_ATTBASE	0x98
#define VIA_AGPSEL		0xfd

static int via_fetch_size(void)
{
	int i;
	u8 temp;
	struct aper_size_info_8 *values;

	values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
	pci_read_config_byte(agp_bridge->dev, VIA_APSIZE, &temp);
	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
		if (temp == values[i].size_value) {
			agp_bridge->previous_size =
			    agp_bridge->current_size = (void *) (values + i);
			agp_bridge->aperture_size_idx = i;
			return values[i].size;
		}
	}
	printk(KERN_ERR PFX "Unknown aperture size from AGP bridge (0x%x)\n", temp);
	return 0;
}


static int via_configure(void)
{
	u32 temp;
	struct aper_size_info_8 *current_size;

	current_size = A_SIZE_8(agp_bridge->current_size);
	/* aperture size */
	pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
			      current_size->size_value);
	/* address to map too */
	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);

	/* GART control register */
	pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);

	/* attbase - aperture GATT base */
	pci_write_config_dword(agp_bridge->dev, VIA_ATTBASE,
			    (agp_bridge->gatt_bus_addr & 0xfffff000) | 3);
	return 0;
}


static void via_cleanup(void)
{
	struct aper_size_info_8 *previous_size;

	previous_size = A_SIZE_8(agp_bridge->previous_size);
	pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
			      previous_size->size_value);
	/* Do not disable by writing 0 to VIA_ATTBASE, it screws things up
	 * during reinitialization.
	 */
}


static void via_tlbflush(struct agp_memory *mem)
{
	u32 temp;

	pci_read_config_dword(agp_bridge->dev, VIA_GARTCTRL, &temp);
	temp |= (1<<7);
	pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp);
	temp &= ~(1<<7);
	pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp);
}


static const struct aper_size_info_8 via_generic_sizes[9] =
{
	{256, 65536, 6, 0},
	{128, 32768, 5, 128},
	{64, 16384, 4, 192},
	{32, 8192, 3, 224},
	{16, 4096, 2, 240},
	{8, 2048, 1, 248},
	{4, 1024, 0, 252},
	{2, 512, 0, 254},
	{1, 256, 0, 255}
};


static int via_fetch_size_agp3(void)
{
	int i;
	u16 temp;
	struct aper_size_info_16 *values;

	values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
	pci_read_config_word(agp_bridge->dev, VIA_AGP3_APSIZE, &temp);
	temp &= 0xfff;

	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
		if (temp == values[i].size_value) {
			agp_bridge->previous_size =
				agp_bridge->current_size = (void *) (values + i);
			agp_bridge->aperture_size_idx = i;
			return values[i].size;
		}
	}
	return 0;
}


static int via_configure_agp3(void)
{
	u32 temp;
	struct aper_size_info_16 *current_size;

	current_size = A_SIZE_16(agp_bridge->current_size);

	/* address to map too */
	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);

	/* attbase - aperture GATT base */
	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE,
		agp_bridge->gatt_bus_addr & 0xfffff000);

	/* 1. Enable GTLB in RX90<7>, all AGP aperture access needs to fetch
	 *    translation table first.
	 * 2. Enable AGP aperture in RX91<0>. This bit controls the enabling of the
	 *    graphics AGP aperture for the AGP3.0 port.
	 */
	pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp | (3<<7));
	return 0;
}


static void via_cleanup_agp3(void)
{
	struct aper_size_info_16 *previous_size;

	previous_size = A_SIZE_16(agp_bridge->previous_size);
	pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, previous_size->size_value);
}


static void via_tlbflush_agp3(struct agp_memory *mem)
{
	u32 temp;

	pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7));
	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp);
}


static const struct agp_bridge_driver via_agp3_driver = {
	.owner			= THIS_MODULE,
	.aperture_sizes		= agp3_generic_sizes,
	.size_type		= U8_APER_SIZE,
	.num_aperture_sizes	= 10,
	.configure		= via_configure_agp3,
	.fetch_size		= via_fetch_size_agp3,
	.cleanup		= via_cleanup_agp3,
	.tlb_flush		= via_tlbflush_agp3,
	.mask_memory		= agp_generic_mask_memory,
	.masks			= NULL,
	.agp_enable		= agp_generic_enable,
	.cache_flush		= global_cache_flush,
	.create_gatt_table	= agp_generic_create_gatt_table,
	.free_gatt_table	= agp_generic_free_gatt_table,
	.insert_memory		= agp_generic_insert_memory,
	.remove_memory		= agp_generic_remove_memory,
	.alloc_by_type		= agp_generic_alloc_by_type,
	.free_by_type		= agp_generic_free_by_type,
	.agp_alloc_page		= agp_generic_alloc_page,
	.agp_destroy_page	= agp_generic_destroy_page,
	.agp_type_to_mask_type  = agp_generic_type_to_mask_type,
};

static const struct agp_bridge_driver via_driver = {
	.owner			= THIS_MODULE,
	.aperture_sizes		= via_generic_sizes,
	.size_type		= U8_APER_SIZE,
	.num_aperture_sizes	= 9,
	.configure		= via_configure,
	.fetch_size		= via_fetch_size,
	.cleanup		= via_cleanup,
	.tlb_flush		= via_tlbflush,
	.mask_memory		= agp_generic_mask_memory,
	.masks			= NULL,
	.agp_enable		= agp_generic_enable,
	.cache_flush		= global_cache_flush,
	.create_gatt_table	= agp_generic_create_gatt_table,
	.free_gatt_table	= agp_generic_free_gatt_table,
	.insert_memory		= agp_generic_insert_memory,
	.remove_memory		= agp_generic_remove_memory,
	.alloc_by_type		= agp_generic_alloc_by_type,
	.free_by_type		= agp_generic_free_by_type,
	.agp_alloc_page		= agp_generic_alloc_page,
	.agp_destroy_page	= agp_generic_destroy_page,
	.agp_type_to_mask_type  = agp_generic_type_to_mask_type,
};

static struct agp_device_ids via_agp_device_ids[] __devinitdata =
{
	{
		.device_id	= PCI_DEVICE_ID_VIA_82C597_0,
		.chipset_name	= "Apollo VP3",
	},

	{
		.device_id	= PCI_DEVICE_ID_VIA_82C598_0,
		.chipset_name	= "Apollo MVP3",
	},

	{
		.device_id	= PCI_DEVICE_ID_VIA_8501_0,
		.chipset_name	= "Apollo MVP4",
	},

	/* VT8601 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8601_0,
		.chipset_name	= "Apollo ProMedia/PLE133Ta",
	},

	/* VT82C693A / VT28C694T */
	{
		.device_id	= PCI_DEVICE_ID_VIA_82C691_0,
		.chipset_name	= "Apollo Pro 133",
	},

	{
		.device_id	= PCI_DEVICE_ID_VIA_8371_0,
		.chipset_name	= "KX133",
	},

	/* VT8633 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8633_0,
		.chipset_name	= "Pro 266",
	},

	{
		.device_id	= PCI_DEVICE_ID_VIA_XN266,
		.chipset_name	= "Apollo Pro266",
	},

	/* VT8361 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8361,
		.chipset_name	= "KLE133",
	},

	/* VT8365 / VT8362 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8363_0,
		.chipset_name	= "Twister-K/KT133x/KM133",
	},

	/* VT8753A */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8753_0,
		.chipset_name	= "P4X266",
	},

	/* VT8366 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8367_0,
		.chipset_name	= "KT266/KY266x/KT333",
	},

	/* VT8633 (for CuMine/ Celeron) */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8653_0,
		.chipset_name	= "Pro266T",
	},

	/* KM266 / PM266 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_XM266,
		.chipset_name	= "PM266/KM266",
	},

	/* CLE266 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_862X_0,
		.chipset_name	= "CLE266",
	},

	{
		.device_id	= PCI_DEVICE_ID_VIA_8377_0,
		.chipset_name	= "KT400/KT400A/KT600",
	},

	/* VT8604 / VT8605 / VT8603
	 * (Apollo Pro133A chipset with S3 Savage4) */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8605_0,
		.chipset_name	= "ProSavage PM133/PL133/PN133"
	},

	/* P4M266x/P4N266 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8703_51_0,
		.chipset_name	= "P4M266x/P4N266",
	},

	/* VT8754 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8754C_0,
		.chipset_name	= "PT800",
	},

	/* P4X600 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8763_0,
		.chipset_name	= "P4X600"
	},

	/* KM400 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8378_0,
		.chipset_name	= "KM400/KM400A",
	},

	/* PT880 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_PT880,
		.chipset_name	= "PT880",
	},

	/* PT880 Ultra */
	{
		.device_id	= PCI_DEVICE_ID_VIA_PT880ULTRA,
		.chipset_name	= "PT880 Ultra",
	},

	/* PT890 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_8783_0,
		.chipset_name	= "PT890",
	},

	/* PM800/PN800/PM880/PN880 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_PX8X0_0,
		.chipset_name	= "PM800/PN800/PM880/PN880",
	},
	/* KT880 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_3269_0,
		.chipset_name	= "KT880",
	},
	/* KTxxx/Px8xx */
	{
		.device_id	= PCI_DEVICE_ID_VIA_83_87XX_1,
		.chipset_name	= "VT83xx/VT87xx/KTxxx/Px8xx",
	},
	/* P4M800 */
	{
		.device_id	= PCI_DEVICE_ID_VIA_3296_0,
		.chipset_name	= "P4M800",
	},
	/* P4M800CE */
	{
		.device_id	= PCI_DEVICE_ID_VIA_P4M800CE,
		.chipset_name	= "VT3314",
	},
	/* VT3324 / CX700 */
	{
		.device_id  = PCI_DEVICE_ID_VIA_VT3324,
		.chipset_name   = "CX700",
	},
	/* VT3336 - this is a chipset for AMD Athlon/K8 CPU. Due to K8's unique
	 * architecture, the AGP resource and behavior are different from
	 * the traditional AGP which resides only in chipset. AGP is used
	 * by 3D driver which wasn't available for the VT3336 and VT3364
	 * generation until now.  Unfortunately, by testing, VT3364 works
	 * but VT3336 doesn't. - explaination from via, just leave this as
	 * as a placeholder to avoid future patches adding it back in.
	 */
#if 0
	{
		.device_id  = PCI_DEVICE_ID_VIA_VT3336,
		.chipset_name   = "VT3336",
	},
#endif
	/* P4M890 */
	{
		.device_id  = PCI_DEVICE_ID_VIA_P4M890,
		.chipset_name   = "P4M890",
	},
	/* P4M900 */
	{
		.device_id  = PCI_DEVICE_ID_VIA_VT3364,
		.chipset_name   = "P4M900",
	},
	{ }, /* dummy final entry, always present */
};


/*
 * VIA's AGP3 chipsets do magick to put the AGP bridge compliant
 * with the same standards version as the graphics card.
 */
static void check_via_agp3 (struct agp_bridge_data *bridge)
{
	u8 reg;

	pci_read_config_byte(bridge->dev, VIA_AGPSEL, &reg);
	/* Check AGP 2.0 compatibility mode. */
	if ((reg & (1<<1))==0)
		bridge->driver = &via_agp3_driver;
}


static int __devinit agp_via_probe(struct pci_dev *pdev,
				   const struct pci_device_id *ent)
{
	struct agp_device_ids *devs = via_agp_device_ids;
	struct agp_bridge_data *bridge;
	int j = 0;
	u8 cap_ptr;

	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
	if (!cap_ptr)
		return -ENODEV;

	j = ent - agp_via_pci_table;
	printk (KERN_INFO PFX "Detected VIA %s chipset\n", devs[j].chipset_name);

	bridge = agp_alloc_bridge();
	if (!bridge)
		return -ENOMEM;

	bridge->dev = pdev;
	bridge->capndx = cap_ptr;
	bridge->driver = &via_driver;

	/*
	 * Garg, there are KT400s with KT266 IDs.
	 */
	if (pdev->device == PCI_DEVICE_ID_VIA_8367_0) {
		/* Is there a KT400 subsystem ? */
		if (pdev->subsystem_device == PCI_DEVICE_ID_VIA_8377_0) {
			printk(KERN_INFO PFX "Found KT400 in disguise as a KT266.\n");
			check_via_agp3(bridge);
		}
	}

	/* If this is an AGP3 bridge, check which mode its in and adjust. */
	get_agp_version(bridge);
	if (bridge->major_version >= 3)
		check_via_agp3(bridge);

	/* Fill in the mode register */
	pci_read_config_dword(pdev,
			bridge->capndx+PCI_AGP_STATUS, &bridge->mode);

	pci_set_drvdata(pdev, bridge);
	return agp_add_bridge(bridge);
}

static void __devexit agp_via_remove(struct pci_dev *pdev)
{
	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);

	agp_remove_bridge(bridge);
	agp_put_bridge(bridge);
}

#ifdef CONFIG_PM

static int agp_via_suspend(struct pci_dev *pdev, pm_message_t state)
{
	pci_save_state (pdev);
	pci_set_power_state (pdev, PCI_D3hot);

	return 0;
}

static int agp_via_resume(struct pci_dev *pdev)
{
	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);

	pci_set_power_state (pdev, PCI_D0);
	pci_restore_state(pdev);

	if (bridge->driver == &via_agp3_driver)
		return via_configure_agp3();
	else if (bridge->driver == &via_driver)
		return via_configure();

	return 0;
}

#endif /* CONFIG_PM */

/* must be the same order as name table above */
static const struct pci_device_id agp_via_pci_table[] = {
#define ID(x) \
	{						\
	.class		= (PCI_CLASS_BRIDGE_HOST << 8),	\
	.class_mask	= ~0,				\
	.vendor		= PCI_VENDOR_ID_VIA,		\
	.device		= x,				\
	.subvendor	= PCI_ANY_ID,			\
	.subdevice	= PCI_ANY_ID,			\
	}
	ID(PCI_DEVICE_ID_VIA_82C597_0),
	ID(PCI_DEVICE_ID_VIA_82C598_0),
	ID(PCI_DEVICE_ID_VIA_8501_0),
	ID(PCI_DEVICE_ID_VIA_8601_0),
	ID(PCI_DEVICE_ID_VIA_82C691_0),
	ID(PCI_DEVICE_ID_VIA_8371_0),
	ID(PCI_DEVICE_ID_VIA_8633_0),
	ID(PCI_DEVICE_ID_VIA_XN266),
	ID(PCI_DEVICE_ID_VIA_8361),
	ID(PCI_DEVICE_ID_VIA_8363_0),
	ID(PCI_DEVICE_ID_VIA_8753_0),
	ID(PCI_DEVICE_ID_VIA_8367_0),
	ID(PCI_DEVICE_ID_VIA_8653_0),
	ID(PCI_DEVICE_ID_VIA_XM266),
	ID(PCI_DEVICE_ID_VIA_862X_0),
	ID(PCI_DEVICE_ID_VIA_8377_0),
	ID(PCI_DEVICE_ID_VIA_8605_0),
	ID(PCI_DEVICE_ID_VIA_8703_51_0),
	ID(PCI_DEVICE_ID_VIA_8754C_0),
	ID(PCI_DEVICE_ID_VIA_8763_0),
	ID(PCI_DEVICE_ID_VIA_8378_0),
	ID(PCI_DEVICE_ID_VIA_PT880),
	ID(PCI_DEVICE_ID_VIA_PT880ULTRA),
	ID(PCI_DEVICE_ID_VIA_8783_0),
	ID(PCI_DEVICE_ID_VIA_PX8X0_0),
	ID(PCI_DEVICE_ID_VIA_3269_0),
	ID(PCI_DEVICE_ID_VIA_83_87XX_1),
	ID(PCI_DEVICE_ID_VIA_3296_0),
	ID(PCI_DEVICE_ID_VIA_P4M800CE),
	ID(PCI_DEVICE_ID_VIA_VT3324),
	ID(PCI_DEVICE_ID_VIA_P4M890),
	ID(PCI_DEVICE_ID_VIA_VT3364),
	{ }
};

MODULE_DEVICE_TABLE(pci, agp_via_pci_table);


static struct pci_driver agp_via_pci_driver = {
	.name		= "agpgart-via",
	.id_table	= agp_via_pci_table,
	.probe		= agp_via_probe,
	.remove		= agp_via_remove,
#ifdef CONFIG_PM
	.suspend	= agp_via_suspend,
	.resume		= agp_via_resume,
#endif
};


static int __init agp_via_init(void)
{
	if (agp_off)
		return -EINVAL;
	return pci_register_driver(&agp_via_pci_driver);
}

static void __exit agp_via_cleanup(void)
{
	pci_unregister_driver(&agp_via_pci_driver);
}

module_init(agp_via_init);
module_exit(agp_via_cleanup);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Dave Jones <[email protected]>");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* VIA AGPGART routines.
	3	*/
	4
	5	#include <linux/types.h>
	6	#include <linux/module.h>
	7	#include <linux/pci.h>
	8	#include <linux/init.h>
	9	#include <linux/agp_backend.h>
	10	#include "agp.h"
	11
b53e674a	12	static const struct pci_device_id agp_via_pci_table[];
1da177e4 LT	13
	14	#define VIA_GARTCTRL 0x80
	15	#define VIA_APSIZE 0x84
	16	#define VIA_ATTBASE 0x88
	17
	18	#define VIA_AGP3_GARTCTRL 0x90
	19	#define VIA_AGP3_APSIZE 0x94
	20	#define VIA_AGP3_ATTBASE 0x98
	21	#define VIA_AGPSEL 0xfd
	22
	23	static int via_fetch_size(void)
	24	{
	25	int i;
	26	u8 temp;
	27	struct aper_size_info_8 *values;
	28
	29	values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
	30	pci_read_config_byte(agp_bridge->dev, VIA_APSIZE, &temp);
	31	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
	32	if (temp == values[i].size_value) {
	33	agp_bridge->previous_size =
	34	agp_bridge->current_size = (void *) (values + i);
	35	agp_bridge->aperture_size_idx = i;
	36	return values[i].size;
	37	}
	38	}
	39	printk(KERN_ERR PFX "Unknown aperture size from AGP bridge (0x%x)\n", temp);
	40	return 0;
	41	}
	42
	43
	44	static int via_configure(void)
	45	{
	46	u32 temp;
	47	struct aper_size_info_8 *current_size;
	48
	49	current_size = A_SIZE_8(agp_bridge->current_size);
	50	/* aperture size */
	51	pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
	52	current_size->size_value);
	53	/* address to map too */
	54	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
	55	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
	56
	57	/* GART control register */
	58	pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);
	59
	60	/* attbase - aperture GATT base */
	61	pci_write_config_dword(agp_bridge->dev, VIA_ATTBASE,
	62	(agp_bridge->gatt_bus_addr & 0xfffff000) \| 3);
	63	return 0;
	64	}
	65
	66
	67	static void via_cleanup(void)
	68	{
	69	struct aper_size_info_8 *previous_size;
	70
	71	previous_size = A_SIZE_8(agp_bridge->previous_size);
	72	pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
	73	previous_size->size_value);
	74	/* Do not disable by writing 0 to VIA_ATTBASE, it screws things up
	75	* during reinitialization.
	76	*/
77	}
78
79
80	static void via_tlbflush(struct agp_memory *mem)
81	{
82	u32 temp;
83
84	pci_read_config_dword(agp_bridge->dev, VIA_GARTCTRL, &temp);
85	temp \|= (1<<7);
86	pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp);
87	temp &= ~(1<<7);
88	pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp);
89	}
90
91
e5524f35	92	static const struct aper_size_info_8 via_generic_sizes[9] =
1da177e4 LT	93	{
	94	{256, 65536, 6, 0},
	95	{128, 32768, 5, 128},
	96	{64, 16384, 4, 192},
	97	{32, 8192, 3, 224},
	98	{16, 4096, 2, 240},
	99	{8, 2048, 1, 248},
	100	{4, 1024, 0, 252},
	101	{2, 512, 0, 254},
	102	{1, 256, 0, 255}
	103	};
	104
	105
	106	static int via_fetch_size_agp3(void)
	107	{
	108	int i;
	109	u16 temp;
	110	struct aper_size_info_16 *values;
	111
	112	values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
	113	pci_read_config_word(agp_bridge->dev, VIA_AGP3_APSIZE, &temp);
	114	temp &= 0xfff;
	115
	116	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
	117	if (temp == values[i].size_value) {
	118	agp_bridge->previous_size =
	119	agp_bridge->current_size = (void *) (values + i);
	120	agp_bridge->aperture_size_idx = i;
	121	return values[i].size;
	122	}
	123	}
	124	return 0;
	125	}
	126
	127
	128	static int via_configure_agp3(void)
	129	{
	130	u32 temp;
	131	struct aper_size_info_16 *current_size;
	132
	133	current_size = A_SIZE_16(agp_bridge->current_size);
	134
	135	/* address to map too */
	136	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
	137	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
	138
	139	/* attbase - aperture GATT base */
	140	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE,
	141	agp_bridge->gatt_bus_addr & 0xfffff000);
	142
	143	/* 1. Enable GTLB in RX90<7>, all AGP aperture access needs to fetch
	144	* translation table first.
	145	* 2. Enable AGP aperture in RX91<0>. This bit controls the enabling of the
	146	* graphics AGP aperture for the AGP3.0 port.
	147	*/
	148	pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
	149	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp \| (3<<7));
	150	return 0;
	151	}
	152
	153
	154	static void via_cleanup_agp3(void)
	155	{
	156	struct aper_size_info_16 *previous_size;
157
158	previous_size = A_SIZE_16(agp_bridge->previous_size);
159	pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, previous_size->size_value);
160	}
161
162
163	static void via_tlbflush_agp3(struct agp_memory *mem)
164	{
165	u32 temp;
166
167	pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
168	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7));
169	pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp);
170	}
171
172
e5524f35	173	static const struct agp_bridge_driver via_agp3_driver = {
1da177e4 LT	174	.owner = THIS_MODULE,
	175	.aperture_sizes = agp3_generic_sizes,
	176	.size_type = U8_APER_SIZE,
	177	.num_aperture_sizes = 10,
	178	.configure = via_configure_agp3,
	179	.fetch_size = via_fetch_size_agp3,
	180	.cleanup = via_cleanup_agp3,
	181	.tlb_flush = via_tlbflush_agp3,
	182	.mask_memory = agp_generic_mask_memory,
	183	.masks = NULL,
	184	.agp_enable = agp_generic_enable,
	185	.cache_flush = global_cache_flush,
	186	.create_gatt_table = agp_generic_create_gatt_table,
	187	.free_gatt_table = agp_generic_free_gatt_table,
	188	.insert_memory = agp_generic_insert_memory,
	189	.remove_memory = agp_generic_remove_memory,
	190	.alloc_by_type = agp_generic_alloc_by_type,
	191	.free_by_type = agp_generic_free_by_type,
	192	.agp_alloc_page = agp_generic_alloc_page,
	193	.agp_destroy_page = agp_generic_destroy_page,
a030ce44	194	.agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4 LT	195	};
1da177e4 LT	196
e5524f35	197	static const struct agp_bridge_driver via_driver = {
1da177e4 LT	198	.owner = THIS_MODULE,
	199	.aperture_sizes = via_generic_sizes,
	200	.size_type = U8_APER_SIZE,
	201	.num_aperture_sizes = 9,
	202	.configure = via_configure,
	203	.fetch_size = via_fetch_size,
	204	.cleanup = via_cleanup,
	205	.tlb_flush = via_tlbflush,
	206	.mask_memory = agp_generic_mask_memory,
	207	.masks = NULL,
	208	.agp_enable = agp_generic_enable,
	209	.cache_flush = global_cache_flush,
	210	.create_gatt_table = agp_generic_create_gatt_table,
	211	.free_gatt_table = agp_generic_free_gatt_table,
	212	.insert_memory = agp_generic_insert_memory,
	213	.remove_memory = agp_generic_remove_memory,
	214	.alloc_by_type = agp_generic_alloc_by_type,
	215	.free_by_type = agp_generic_free_by_type,
	216	.agp_alloc_page = agp_generic_alloc_page,
	217	.agp_destroy_page = agp_generic_destroy_page,
a030ce44	218	.agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4 LT	219	};
	220
	221	static struct agp_device_ids via_agp_device_ids[] __devinitdata =
	222	{
	223	{
	224	.device_id = PCI_DEVICE_ID_VIA_82C597_0,
	225	.chipset_name = "Apollo VP3",
	226	},
	227
	228	{
	229	.device_id = PCI_DEVICE_ID_VIA_82C598_0,
	230	.chipset_name = "Apollo MVP3",
	231	},
	232
	233	{
	234	.device_id = PCI_DEVICE_ID_VIA_8501_0,
	235	.chipset_name = "Apollo MVP4",
	236	},
	237
	238	/* VT8601 */
	239	{
	240	.device_id = PCI_DEVICE_ID_VIA_8601_0,
	241	.chipset_name = "Apollo ProMedia/PLE133Ta",
	242	},
	243
	244	/* VT82C693A / VT28C694T */
	245	{
	246	.device_id = PCI_DEVICE_ID_VIA_82C691_0,
	247	.chipset_name = "Apollo Pro 133",
	248	},
	249
	250	{
	251	.device_id = PCI_DEVICE_ID_VIA_8371_0,
	252	.chipset_name = "KX133",
	253	},
	254
	255	/* VT8633 */
	256	{
	257	.device_id = PCI_DEVICE_ID_VIA_8633_0,
	258	.chipset_name = "Pro 266",
	259	},
	260
	261	{
	262	.device_id = PCI_DEVICE_ID_VIA_XN266,
	263	.chipset_name = "Apollo Pro266",
	264	},
	265
	266	/* VT8361 */
	267	{
	268	.device_id = PCI_DEVICE_ID_VIA_8361,
	269	.chipset_name = "KLE133",
	270	},
	271
	272	/* VT8365 / VT8362 */
	273	{
	274	.device_id = PCI_DEVICE_ID_VIA_8363_0,
	275	.chipset_name = "Twister-K/KT133x/KM133",
	276	},
	277
	278	/* VT8753A */
	279	{
	280	.device_id = PCI_DEVICE_ID_VIA_8753_0,
	281	.chipset_name = "P4X266",
	282	},
283
284	/* VT8366 */
285	{
286	.device_id = PCI_DEVICE_ID_VIA_8367_0,
287	.chipset_name = "KT266/KY266x/KT333",
288	},
289
290	/* VT8633 (for CuMine/ Celeron) */
291	{
292	.device_id = PCI_DEVICE_ID_VIA_8653_0,
293	.chipset_name = "Pro266T",
294	},
295
296	/* KM266 / PM266 */
297	{
298	.device_id = PCI_DEVICE_ID_VIA_XM266,
299	.chipset_name = "PM266/KM266",
300	},
301
302	/* CLE266 */
303	{
304	.device_id = PCI_DEVICE_ID_VIA_862X_0,
305	.chipset_name = "CLE266",
306	},
307
308	{
309	.device_id = PCI_DEVICE_ID_VIA_8377_0,
310	.chipset_name = "KT400/KT400A/KT600",
311	},
312
313	/* VT8604 / VT8605 / VT8603
314	* (Apollo Pro133A chipset with S3 Savage4) */
315	{
316	.device_id = PCI_DEVICE_ID_VIA_8605_0,
317	.chipset_name = "ProSavage PM133/PL133/PN133"
318	},
319
320	/* P4M266x/P4N266 */
321	{
322	.device_id = PCI_DEVICE_ID_VIA_8703_51_0,
323	.chipset_name = "P4M266x/P4N266",
324	},
325
326	/* VT8754 */
327	{
328	.device_id = PCI_DEVICE_ID_VIA_8754C_0,
329	.chipset_name = "PT800",
330	},
331
332	/* P4X600 */
333	{
334	.device_id = PCI_DEVICE_ID_VIA_8763_0,
335	.chipset_name = "P4X600"
336	},
337
338	/* KM400 */
339	{
340	.device_id = PCI_DEVICE_ID_VIA_8378_0,
341	.chipset_name = "KM400/KM400A",
342	},
343
344	/* PT880 */
345	{
346	.device_id = PCI_DEVICE_ID_VIA_PT880,
347	.chipset_name = "PT880",
348	},
349
7dd1d9b8 MK	350	/* PT880 Ultra */
	351	{
	352	.device_id = PCI_DEVICE_ID_VIA_PT880ULTRA,
	353	.chipset_name = "PT880 Ultra",
	354	},
	355
1da177e4 LT	356	/* PT890 */
	357	{
	358	.device_id = PCI_DEVICE_ID_VIA_8783_0,
	359	.chipset_name = "PT890",
	360	},
	361
	362	/* PM800/PN800/PM880/PN880 */
	363	{
	364	.device_id = PCI_DEVICE_ID_VIA_PX8X0_0,
	365	.chipset_name = "PM800/PN800/PM880/PN880",
	366	},
	367	/* KT880 */
	368	{
	369	.device_id = PCI_DEVICE_ID_VIA_3269_0,
	370	.chipset_name = "KT880",
	371	},
	372	/* KTxxx/Px8xx */
	373	{
	374	.device_id = PCI_DEVICE_ID_VIA_83_87XX_1,
	375	.chipset_name = "VT83xx/VT87xx/KTxxx/Px8xx",
	376	},
	377	/* P4M800 */
	378	{
	379	.device_id = PCI_DEVICE_ID_VIA_3296_0,
	380	.chipset_name = "P4M800",
	381	},
c243f1f1 DJ	382	/* P4M800CE */
	383	{
	384	.device_id = PCI_DEVICE_ID_VIA_P4M800CE,
43ed41f6 DJ	385	.chipset_name = "VT3314",
43ed41f6 DJ	386	},
bbdfff86	387	/* VT3324 / CX700 */
43ed41f6	388	{
bbdfff86	389	.device_id = PCI_DEVICE_ID_VIA_VT3324,
43ed41f6 DJ	390	.chipset_name = "CX700",
43ed41f6 DJ	391	},
dcd981a7 GKH	392	/* VT3336 - this is a chipset for AMD Athlon/K8 CPU. Due to K8's unique
	393	* architecture, the AGP resource and behavior are different from
	394	* the traditional AGP which resides only in chipset. AGP is used
	395	* by 3D driver which wasn't available for the VT3336 and VT3364
	396	* generation until now. Unfortunately, by testing, VT3364 works
	397	* but VT3336 doesn't. - explaination from via, just leave this as
	398	* as a placeholder to avoid future patches adding it back in.
	399	*/
	400	#if 0
43ed41f6 DJ	401	{
	402	.device_id = PCI_DEVICE_ID_VIA_VT3336,
	403	.chipset_name = "VT3336",
	404	},
dcd981a7	405	#endif
43ed41f6 DJ	406	/* P4M890 */
	407	{
	408	.device_id = PCI_DEVICE_ID_VIA_P4M890,
	409	.chipset_name = "P4M890",
c243f1f1	410	},
32ddef98 XB	411	/* P4M900 */
	412	{
	413	.device_id = PCI_DEVICE_ID_VIA_VT3364,
	414	.chipset_name = "P4M900",
	415	},
1da177e4 LT	416	{ }, /* dummy final entry, always present */
	417	};
	418
	419
	420	/*
	421	* VIA's AGP3 chipsets do magick to put the AGP bridge compliant
	422	* with the same standards version as the graphics card.
	423	*/
	424	static void check_via_agp3 (struct agp_bridge_data *bridge)
	425	{
	426	u8 reg;
	427
	428	pci_read_config_byte(bridge->dev, VIA_AGPSEL, &reg);
	429	/* Check AGP 2.0 compatibility mode. */
	430	if ((reg & (1<<1))==0)
	431	bridge->driver = &via_agp3_driver;
	432	}
	433
	434
	435	static int __devinit agp_via_probe(struct pci_dev *pdev,
	436	const struct pci_device_id *ent)
	437	{
	438	struct agp_device_ids *devs = via_agp_device_ids;
	439	struct agp_bridge_data *bridge;
	440	int j = 0;
	441	u8 cap_ptr;
	442
	443	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
	444	if (!cap_ptr)
	445	return -ENODEV;
	446
	447	j = ent - agp_via_pci_table;
	448	printk (KERN_INFO PFX "Detected VIA %s chipset\n", devs[j].chipset_name);
	449
	450	bridge = agp_alloc_bridge();
	451	if (!bridge)
	452	return -ENOMEM;
	453
	454	bridge->dev = pdev;
	455	bridge->capndx = cap_ptr;
	456	bridge->driver = &via_driver;
	457
	458	/*
	459	* Garg, there are KT400s with KT266 IDs.
	460	*/
	461	if (pdev->device == PCI_DEVICE_ID_VIA_8367_0) {
	462	/* Is there a KT400 subsystem ? */
	463	if (pdev->subsystem_device == PCI_DEVICE_ID_VIA_8377_0) {
	464	printk(KERN_INFO PFX "Found KT400 in disguise as a KT266.\n");
	465	check_via_agp3(bridge);
	466	}
	467	}
	468
	469	/* If this is an AGP3 bridge, check which mode its in and adjust. */
	470	get_agp_version(bridge);
	471	if (bridge->major_version >= 3)
	472	check_via_agp3(bridge);
	473
	474	/* Fill in the mode register */
	475	pci_read_config_dword(pdev,
	476	bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
	477
	478	pci_set_drvdata(pdev, bridge);
	479	return agp_add_bridge(bridge);
480	}
481
482	static void __devexit agp_via_remove(struct pci_dev *pdev)
483	{
484	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
485
486	agp_remove_bridge(bridge);
487	agp_put_bridge(bridge);
488	}
489
490	#ifdef CONFIG_PM
491
492	static int agp_via_suspend(struct pci_dev *pdev, pm_message_t state)
493	{
494	pci_save_state (pdev);
495	pci_set_power_state (pdev, PCI_D3hot);
496
497	return 0;
498	}
499
500	static int agp_via_resume(struct pci_dev *pdev)
501	{
502	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
503
504	pci_set_power_state (pdev, PCI_D0);
505	pci_restore_state(pdev);
506
507	if (bridge->driver == &via_agp3_driver)
508	return via_configure_agp3();
509	else if (bridge->driver == &via_driver)
510	return via_configure();
511
512	return 0;
513	}
514
515	#endif /* CONFIG_PM */
516
517	/* must be the same order as name table above */
b53e674a	518	static const struct pci_device_id agp_via_pci_table[] = {
1da177e4 LT	519	#define ID(x) \
	520	{ \
	521	.class = (PCI_CLASS_BRIDGE_HOST << 8), \
	522	.class_mask = ~0, \
	523	.vendor = PCI_VENDOR_ID_VIA, \
	524	.device = x, \
	525	.subvendor = PCI_ANY_ID, \
	526	.subdevice = PCI_ANY_ID, \
	527	}
	528	ID(PCI_DEVICE_ID_VIA_82C597_0),
	529	ID(PCI_DEVICE_ID_VIA_82C598_0),
	530	ID(PCI_DEVICE_ID_VIA_8501_0),
	531	ID(PCI_DEVICE_ID_VIA_8601_0),
	532	ID(PCI_DEVICE_ID_VIA_82C691_0),
	533	ID(PCI_DEVICE_ID_VIA_8371_0),
	534	ID(PCI_DEVICE_ID_VIA_8633_0),
	535	ID(PCI_DEVICE_ID_VIA_XN266),
	536	ID(PCI_DEVICE_ID_VIA_8361),
	537	ID(PCI_DEVICE_ID_VIA_8363_0),
	538	ID(PCI_DEVICE_ID_VIA_8753_0),
	539	ID(PCI_DEVICE_ID_VIA_8367_0),
	540	ID(PCI_DEVICE_ID_VIA_8653_0),
	541	ID(PCI_DEVICE_ID_VIA_XM266),
	542	ID(PCI_DEVICE_ID_VIA_862X_0),
	543	ID(PCI_DEVICE_ID_VIA_8377_0),
	544	ID(PCI_DEVICE_ID_VIA_8605_0),
	545	ID(PCI_DEVICE_ID_VIA_8703_51_0),
	546	ID(PCI_DEVICE_ID_VIA_8754C_0),
	547	ID(PCI_DEVICE_ID_VIA_8763_0),
	548	ID(PCI_DEVICE_ID_VIA_8378_0),
	549	ID(PCI_DEVICE_ID_VIA_PT880),
7dd1d9b8	550	ID(PCI_DEVICE_ID_VIA_PT880ULTRA),
1da177e4 LT	551	ID(PCI_DEVICE_ID_VIA_8783_0),
	552	ID(PCI_DEVICE_ID_VIA_PX8X0_0),
	553	ID(PCI_DEVICE_ID_VIA_3269_0),
	554	ID(PCI_DEVICE_ID_VIA_83_87XX_1),
	555	ID(PCI_DEVICE_ID_VIA_3296_0),
c243f1f1	556	ID(PCI_DEVICE_ID_VIA_P4M800CE),
bbdfff86	557	ID(PCI_DEVICE_ID_VIA_VT3324),
43ed41f6	558	ID(PCI_DEVICE_ID_VIA_P4M890),
dcd981a7	559	ID(PCI_DEVICE_ID_VIA_VT3364),
1da177e4 LT	560	{ }
	561	};
	562
	563	MODULE_DEVICE_TABLE(pci, agp_via_pci_table);
	564
	565
	566	static struct pci_driver agp_via_pci_driver = {
	567	.name = "agpgart-via",
	568	.id_table = agp_via_pci_table,
	569	.probe = agp_via_probe,
	570	.remove = agp_via_remove,
	571	#ifdef CONFIG_PM
	572	.suspend = agp_via_suspend,
	573	.resume = agp_via_resume,
	574	#endif
	575	};
	576
	577
	578	static int __init agp_via_init(void)
	579	{
	580	if (agp_off)
	581	return -EINVAL;
	582	return pci_register_driver(&agp_via_pci_driver);
	583	}
	584
	585	static void __exit agp_via_cleanup(void)
	586	{
	587	pci_unregister_driver(&agp_via_pci_driver);
	588	}
	589
	590	module_init(agp_via_init);
	591	module_exit(agp_via_cleanup);
	592
	593	MODULE_LICENSE("GPL");
	594	MODULE_AUTHOR("Dave Jones <[email protected]>");