projects / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 23b5e15a SG |
1 | /* |
| 2 | * Copyright 2012 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 4 | * The code contained herein is licensed under the GNU General Public | |
| 5 | * License. You may obtain a copy of the GNU General Public License | |
| 6 | * Version 2 or later at the following locations: | |
| 7 | * | |
| 8 | * http://www.opensource.org/licenses/gpl-license.html | |
| 9 | * http://www.gnu.org/copyleft/gpl.html | |
| 10 | */ | |
| 11 | ||
| 12 | #ifndef __MXS_CLK_H | |
| 13 | #define __MXS_CLK_H | |
| 14 | ||
| bb0bf354 SB |
15 | struct clk; |
| 16 | ||
| 23b5e15a SG |
17 | #include <linux/clk-provider.h> |
| 18 | #include <linux/spinlock.h> | |
| 19 | ||
| 20 | #define SET 0x4 | |
| 21 | #define CLR 0x8 | |
| 22 | ||
| 23 | extern spinlock_t mxs_lock; | |
| 24 | ||
| 25 | int mxs_clk_wait(void __iomem *reg, u8 shift); | |
| 26 | ||
| 27 | struct clk *mxs_clk_pll(const char *name, const char *parent_name, | |
| 28 | void __iomem *base, u8 power, unsigned long rate); | |
| 29 | ||
| 30 | struct clk *mxs_clk_ref(const char *name, const char *parent_name, | |
| 31 | void __iomem *reg, u8 idx); | |
| 32 | ||
| 33 | struct clk *mxs_clk_div(const char *name, const char *parent_name, | |
| 34 | void __iomem *reg, u8 shift, u8 width, u8 busy); | |
| 35 | ||
| 36 | struct clk *mxs_clk_frac(const char *name, const char *parent_name, | |
| 37 | void __iomem *reg, u8 shift, u8 width, u8 busy); | |
| 38 | ||
| 39 | static inline struct clk *mxs_clk_fixed(const char *name, int rate) | |
| 40 | { | |
| 41 | return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); | |
| 42 | } | |
| 43 | ||
| 44 | static inline struct clk *mxs_clk_gate(const char *name, | |
| 45 | const char *parent_name, void __iomem *reg, u8 shift) | |
| 46 | { | |
| 47 | return clk_register_gate(NULL, name, parent_name, CLK_SET_RATE_PARENT, | |
| 48 | reg, shift, CLK_GATE_SET_TO_DISABLE, | |
| 49 | &mxs_lock); | |
| 50 | } | |
| 51 | ||
| 52 | static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg, | |
| 4a1caed3 | 53 | u8 shift, u8 width, const char *const *parent_names, int num_parents) |
| 23b5e15a SG |
54 | { |
| 55 | return clk_register_mux(NULL, name, parent_names, num_parents, | |
| 819c1de3 JH |
56 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
| 57 | reg, shift, width, 0, &mxs_lock); | |
| 23b5e15a SG |
58 | } |
| 59 | ||
| 60 | static inline struct clk *mxs_clk_fixed_factor(const char *name, | |
| 61 | const char *parent_name, unsigned int mult, unsigned int div) | |
| 62 | { | |
| 63 | return clk_register_fixed_factor(NULL, name, parent_name, | |
| 64 | CLK_SET_RATE_PARENT, mult, div); | |
| 65 | } | |
| 66 | ||
| 67 | #endif /* __MXS_CLK_H */ |