[linux.git] / include / drm / drm_dp_helper.h

/*
 * Copyright © 2008 Keith Packard
 *
 * Permission to use, copy, modify, distribute, and sell this software and its
 * documentation for any purpose is hereby granted without fee, provided that
 * the above copyright notice appear in all copies and that both that copyright
 * notice and this permission notice appear in supporting documentation, and
 * that the name of the copyright holders not be used in advertising or
 * publicity pertaining to distribution of the software without specific,
 * written prior permission.  The copyright holders make no representations
 * about the suitability of this software for any purpose.  It is provided "as
 * is" without express or implied warranty.
 *
 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
 * OF THIS SOFTWARE.
 */

#ifndef _DRM_DP_HELPER_H_
#define _DRM_DP_HELPER_H_

/* From the VESA DisplayPort spec */

#define AUX_NATIVE_WRITE	0x8
#define AUX_NATIVE_READ		0x9
#define AUX_I2C_WRITE		0x0
#define AUX_I2C_READ		0x1
#define AUX_I2C_STATUS		0x2
#define AUX_I2C_MOT		0x4

#define AUX_NATIVE_REPLY_ACK	(0x0 << 4)
#define AUX_NATIVE_REPLY_NACK	(0x1 << 4)
#define AUX_NATIVE_REPLY_DEFER	(0x2 << 4)
#define AUX_NATIVE_REPLY_MASK	(0x3 << 4)

#define AUX_I2C_REPLY_ACK	(0x0 << 6)
#define AUX_I2C_REPLY_NACK	(0x1 << 6)
#define AUX_I2C_REPLY_DEFER	(0x2 << 6)
#define AUX_I2C_REPLY_MASK	(0x3 << 6)

/* AUX CH addresses */
#define DP_DPCP_REV 0x0

#define	DP_LINK_BW_SET		0x100
# define DP_LINK_BW_1_62		    0x06
# define DP_LINK_BW_2_7			    0x0a

#define DP_LANE_COUNT_SET	0x101
# define DP_LANE_COUNT_MASK		    0x0f
# define DP_LANE_COUNT_ENHANCED_FRAME_EN    (1 << 7)

#define DP_TRAINING_PATTERN_SET	0x102

# define DP_TRAINING_PATTERN_DISABLE	    0
# define DP_TRAINING_PATTERN_1		    1
# define DP_TRAINING_PATTERN_2		    2
# define DP_TRAINING_PATTERN_MASK	    0x3

# define DP_LINK_QUAL_PATTERN_DISABLE	    (0 << 2)
# define DP_LINK_QUAL_PATTERN_D10_2	    (1 << 2)
# define DP_LINK_QUAL_PATTERN_ERROR_RATE    (2 << 2)
# define DP_LINK_QUAL_PATTERN_PRBS7	    (3 << 2)
# define DP_LINK_QUAL_PATTERN_MASK	    (3 << 2)

# define DP_RECOVERED_CLOCK_OUT_EN	    (1 << 4)
# define DP_LINK_SCRAMBLING_DISABLE	    (1 << 5)

# define DP_SYMBOL_ERROR_COUNT_BOTH	    (0 << 6)
# define DP_SYMBOL_ERROR_COUNT_DISPARITY    (1 << 6)
# define DP_SYMBOL_ERROR_COUNT_SYMBOL	    (2 << 6)
# define DP_SYMBOL_ERROR_COUNT_MASK	    (3 << 6)

#define DP_TRAINING_LANE0_SET		    0x103
#define DP_TRAINING_LANE1_SET		    0x104
#define DP_TRAINING_LANE2_SET		    0x105
#define DP_TRAINING_LANE3_SET		    0x106

# define DP_TRAIN_VOLTAGE_SWING_MASK	    0x3
# define DP_TRAIN_VOLTAGE_SWING_SHIFT	    0
# define DP_TRAIN_MAX_SWING_REACHED	    (1 << 2)
# define DP_TRAIN_VOLTAGE_SWING_400	    (0 << 0)
# define DP_TRAIN_VOLTAGE_SWING_600	    (1 << 0)
# define DP_TRAIN_VOLTAGE_SWING_800	    (2 << 0)
# define DP_TRAIN_VOLTAGE_SWING_1200	    (3 << 0)

# define DP_TRAIN_PRE_EMPHASIS_MASK	    (3 << 3)
# define DP_TRAIN_PRE_EMPHASIS_0	    (0 << 3)
# define DP_TRAIN_PRE_EMPHASIS_3_5	    (1 << 3)
# define DP_TRAIN_PRE_EMPHASIS_6	    (2 << 3)
# define DP_TRAIN_PRE_EMPHASIS_9_5	    (3 << 3)

# define DP_TRAIN_PRE_EMPHASIS_SHIFT	    3
# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED  (1 << 5)

#define DP_DOWNSPREAD_CTRL		    0x107
# define DP_SPREAD_AMP_0_5		    (1 << 4)

#define DP_MAIN_LINK_CHANNEL_CODING_SET	    0x108
# define DP_SET_ANSI_8B10B		    (1 << 0)

#define DP_LANE0_1_STATUS		    0x202
#define DP_LANE2_3_STATUS		    0x203

# define DP_LANE_CR_DONE		    (1 << 0)
# define DP_LANE_CHANNEL_EQ_DONE	    (1 << 1)
# define DP_LANE_SYMBOL_LOCKED		    (1 << 2)

#define DP_LANE_ALIGN_STATUS_UPDATED	    0x204

#define DP_INTERLANE_ALIGN_DONE		    (1 << 0)
#define DP_DOWNSTREAM_PORT_STATUS_CHANGED   (1 << 6)
#define DP_LINK_STATUS_UPDATED		    (1 << 7)

#define DP_SINK_STATUS			    0x205

#define DP_RECEIVE_PORT_0_STATUS	    (1 << 0)
#define DP_RECEIVE_PORT_1_STATUS	    (1 << 1)

#define DP_ADJUST_REQUEST_LANE0_1	    0x206
#define DP_ADJUST_REQUEST_LANE2_3	    0x207

#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK  0x03
#define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK   0x0c
#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT  2
#define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK  0x30
#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK   0xc0
#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT  6

#define MODE_I2C_START	1
#define MODE_I2C_WRITE	2
#define MODE_I2C_READ	4
#define MODE_I2C_STOP	8

struct i2c_algo_dp_aux_data {
	bool running;
	u16 address;
	int (*aux_ch) (struct i2c_adapter *adapter,
		       int mode, uint8_t write_byte,
		       uint8_t *read_byte);
};

int
i2c_dp_aux_add_bus(struct i2c_adapter *adapter);

#endif /* _DRM_DP_HELPER_H_ */
Commit	Line	Data
a4fc5ed6 KP	1	/*
	2	* Copyright © 2008 Keith Packard
	3	*
	4	* Permission to use, copy, modify, distribute, and sell this software and its
	5	* documentation for any purpose is hereby granted without fee, provided that
	6	* the above copyright notice appear in all copies and that both that copyright
	7	* notice and this permission notice appear in supporting documentation, and
	8	* that the name of the copyright holders not be used in advertising or
	9	* publicity pertaining to distribution of the software without specific,
	10	* written prior permission. The copyright holders make no representations
	11	* about the suitability of this software for any purpose. It is provided "as
	12	* is" without express or implied warranty.
	13	*
	14	* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
	15	* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
	16	* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
	17	* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
	18	* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
	19	* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
	20	* OF THIS SOFTWARE.
	21	*/
	22
ab2c0672 DA	23	#ifndef _DRM_DP_HELPER_H_
ab2c0672 DA	24	#define _DRM_DP_HELPER_H_
a4fc5ed6 KP	25
	26	/* From the VESA DisplayPort spec */
	27
	28	#define AUX_NATIVE_WRITE 0x8
	29	#define AUX_NATIVE_READ 0x9
	30	#define AUX_I2C_WRITE 0x0
	31	#define AUX_I2C_READ 0x1
	32	#define AUX_I2C_STATUS 0x2
	33	#define AUX_I2C_MOT 0x4
	34
	35	#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
	36	#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
	37	#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
	38	#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
	39
	40	#define AUX_I2C_REPLY_ACK (0x0 << 6)
	41	#define AUX_I2C_REPLY_NACK (0x1 << 6)
	42	#define AUX_I2C_REPLY_DEFER (0x2 << 6)
	43	#define AUX_I2C_REPLY_MASK (0x3 << 6)
	44
	45	/* AUX CH addresses */
746c1aa4 DA	46	#define DP_DPCP_REV 0x0
746c1aa4 DA	47
a4fc5ed6 KP	48	#define DP_LINK_BW_SET 0x100
	49	# define DP_LINK_BW_1_62 0x06
	50	# define DP_LINK_BW_2_7 0x0a
	51
	52	#define DP_LANE_COUNT_SET 0x101
	53	# define DP_LANE_COUNT_MASK 0x0f
	54	# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
	55
	56	#define DP_TRAINING_PATTERN_SET 0x102
	57
	58	# define DP_TRAINING_PATTERN_DISABLE 0
	59	# define DP_TRAINING_PATTERN_1 1
	60	# define DP_TRAINING_PATTERN_2 2
	61	# define DP_TRAINING_PATTERN_MASK 0x3
	62
	63	# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
	64	# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
	65	# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
	66	# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
	67	# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
	68
	69	# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
	70	# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
	71
	72	# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
	73	# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
	74	# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
	75	# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
	76
	77	#define DP_TRAINING_LANE0_SET 0x103
	78	#define DP_TRAINING_LANE1_SET 0x104
	79	#define DP_TRAINING_LANE2_SET 0x105
	80	#define DP_TRAINING_LANE3_SET 0x106
	81
	82	# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
	83	# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
	84	# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
	85	# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
	86	# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
	87	# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
	88	# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
	89
	90	# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
	91	# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
	92	# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
	93	# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
	94	# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
	95
	96	# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
	97	# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
	98
	99	#define DP_DOWNSPREAD_CTRL 0x107
	100	# define DP_SPREAD_AMP_0_5 (1 << 4)
	101
	102	#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
	103	# define DP_SET_ANSI_8B10B (1 << 0)
	104
	105	#define DP_LANE0_1_STATUS 0x202
	106	#define DP_LANE2_3_STATUS 0x203
	107
	108	# define DP_LANE_CR_DONE (1 << 0)
	109	# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
	110	# define DP_LANE_SYMBOL_LOCKED (1 << 2)
	111
112	#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
113
114	#define DP_INTERLANE_ALIGN_DONE (1 << 0)
115	#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
116	#define DP_LINK_STATUS_UPDATED (1 << 7)
117
118	#define DP_SINK_STATUS 0x205
119
120	#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
121	#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
122
123	#define DP_ADJUST_REQUEST_LANE0_1 0x206
124	#define DP_ADJUST_REQUEST_LANE2_3 0x207
125
126	#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
127	#define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
128	#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
129	#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
130	#define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
131	#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
132	#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
133	#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
134
ab2c0672 DA	135	#define MODE_I2C_START 1
	136	#define MODE_I2C_WRITE 2
	137	#define MODE_I2C_READ 4
	138	#define MODE_I2C_STOP 8
	139
a4fc5ed6 KP	140	struct i2c_algo_dp_aux_data {
	141	bool running;
	142	u16 address;
	143	int (aux_ch) (struct i2c_adapter adapter,
ab2c0672 DA	144	int mode, uint8_t write_byte,
ab2c0672 DA	145	uint8_t *read_byte);
a4fc5ed6 KP	146	};
	147
	148	int
	149	i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
	150
ab2c0672	151	#endif /* _DRM_DP_HELPER_H_ */