[linux.git] / drivers / cpufreq / sa1110-cpufreq.c

/*
 *  linux/arch/arm/mach-sa1100/cpu-sa1110.c
 *
 *  Copyright (C) 2001 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Note: there are two erratas that apply to the SA1110 here:
 *  7 - SDRAM auto-power-up failure (rev A0)
 * 13 - Corruption of internal register reads/writes following
 *      SDRAM reads (rev A0, B0, B1)
 *
 * We ignore rev. A0 and B0 devices; I don't think they're worth supporting.
 *
 * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
 */
#include <linux/cpufreq.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/moduleparam.h>
#include <linux/types.h>

#include <asm/cputype.h>
#include <asm/mach-types.h>

#include <mach/generic.h>
#include <mach/hardware.h>

#undef DEBUG

struct sdram_params {
	const char name[20];
	u_char  rows;		/* bits				 */
	u_char  cas_latency;	/* cycles			 */
	u_char  tck;		/* clock cycle time (ns)	 */
	u_char  trcd;		/* activate to r/w (ns)		 */
	u_char  trp;		/* precharge to activate (ns)	 */
	u_char  twr;		/* write recovery time (ns)	 */
	u_short refresh;	/* refresh time for array (us)	 */
};

struct sdram_info {
	u_int	mdcnfg;
	u_int	mdrefr;
	u_int	mdcas[3];
};

static struct sdram_params sdram_tbl[] __initdata = {
	{	/* Toshiba TC59SM716 CL2 */
		.name		= "TC59SM716-CL2",
		.rows		= 12,
		.tck		= 10,
		.trcd		= 20,
		.trp		= 20,
		.twr		= 10,
		.refresh	= 64000,
		.cas_latency	= 2,
	}, {	/* Toshiba TC59SM716 CL3 */
		.name		= "TC59SM716-CL3",
		.rows		= 12,
		.tck		= 8,
		.trcd		= 20,
		.trp		= 20,
		.twr		= 8,
		.refresh	= 64000,
		.cas_latency	= 3,
	}, {	/* Samsung K4S641632D TC75 */
		.name		= "K4S641632D",
		.rows		= 14,
		.tck		= 9,
		.trcd		= 27,
		.trp		= 20,
		.twr		= 9,
		.refresh	= 64000,
		.cas_latency	= 3,
	}, {	/* Samsung K4S281632B-1H */
		.name           = "K4S281632B-1H",
		.rows		= 12,
		.tck		= 10,
		.trp		= 20,
		.twr		= 10,
		.refresh	= 64000,
		.cas_latency	= 3,
	}, {	/* Samsung KM416S4030CT */
		.name		= "KM416S4030CT",
		.rows		= 13,
		.tck		= 8,
		.trcd		= 24,	/* 3 CLKs */
		.trp		= 24,	/* 3 CLKs */
		.twr		= 16,	/* Trdl: 2 CLKs */
		.refresh	= 64000,
		.cas_latency	= 3,
	}, {	/* Winbond W982516AH75L CL3 */
		.name		= "W982516AH75L",
		.rows		= 16,
		.tck		= 8,
		.trcd		= 20,
		.trp		= 20,
		.twr		= 8,
		.refresh	= 64000,
		.cas_latency	= 3,
	}, {	/* Micron MT48LC8M16A2TG-75 */
		.name		= "MT48LC8M16A2TG-75",
		.rows		= 12,
		.tck		= 8,
		.trcd		= 20,
		.trp		= 20,
		.twr		= 8,
		.refresh	= 64000,
		.cas_latency	= 3,
	},
};

static struct sdram_params sdram_params;

/*
 * Given a period in ns and frequency in khz, calculate the number of
 * cycles of frequency in period.  Note that we round up to the next
 * cycle, even if we are only slightly over.
 */
static inline u_int ns_to_cycles(u_int ns, u_int khz)
{
	return (ns * khz + 999999) / 1000000;
}

/*
 * Create the MDCAS register bit pattern.
 */
static inline void set_mdcas(u_int *mdcas, int delayed, u_int rcd)
{
	u_int shift;

	rcd = 2 * rcd - 1;
	shift = delayed + 1 + rcd;

	mdcas[0]  = (1 << rcd) - 1;
	mdcas[0] |= 0x55555555 << shift;
	mdcas[1]  = mdcas[2] = 0x55555555 << (shift & 1);
}

static void
sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz,
		       struct sdram_params *sdram)
{
	u_int mem_khz, sd_khz, trp, twr;

	mem_khz = cpu_khz / 2;
	sd_khz = mem_khz;

	/*
	 * If SDCLK would invalidate the SDRAM timings,
	 * run SDCLK at half speed.
	 *
	 * CPU steppings prior to B2 must either run the memory at
	 * half speed or use delayed read latching (errata 13).
	 */
	if ((ns_to_cycles(sdram->tck, sd_khz) > 1) ||
	    (CPU_REVISION < CPU_SA1110_B2 && sd_khz < 62000))
		sd_khz /= 2;

	sd->mdcnfg = MDCNFG & 0x007f007f;

	twr = ns_to_cycles(sdram->twr, mem_khz);

	/* trp should always be >1 */
	trp = ns_to_cycles(sdram->trp, mem_khz) - 1;
	if (trp < 1)
		trp = 1;

	sd->mdcnfg |= trp << 8;
	sd->mdcnfg |= trp << 24;
	sd->mdcnfg |= sdram->cas_latency << 12;
	sd->mdcnfg |= sdram->cas_latency << 28;
	sd->mdcnfg |= twr << 14;
	sd->mdcnfg |= twr << 30;

	sd->mdrefr = MDREFR & 0xffbffff0;
	sd->mdrefr |= 7;

	if (sd_khz != mem_khz)
		sd->mdrefr |= MDREFR_K1DB2;

	/* initial number of '1's in MDCAS + 1 */
	set_mdcas(sd->mdcas, sd_khz >= 62000,
		ns_to_cycles(sdram->trcd, mem_khz));

#ifdef DEBUG
	printk(KERN_DEBUG "MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
		sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1],
		sd->mdcas[2]);
#endif
}

/*
 * Set the SDRAM refresh rate.
 */
static inline void sdram_set_refresh(u_int dri)
{
	MDREFR = (MDREFR & 0xffff000f) | (dri << 4);
	(void) MDREFR;
}

/*
 * Update the refresh period.  We do this such that we always refresh
 * the SDRAMs within their permissible period.  The refresh period is
 * always a multiple of the memory clock (fixed at cpu_clock / 2).
 *
 * FIXME: we don't currently take account of burst accesses here,
 * but neither do Intels DM nor Angel.
 */
static void
sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram)
{
	u_int ns_row = (sdram->refresh * 1000) >> sdram->rows;
	u_int dri = ns_to_cycles(ns_row, cpu_khz / 2) / 32;

#ifdef DEBUG
	mdelay(250);
	printk(KERN_DEBUG "new dri value = %d\n", dri);
#endif

	sdram_set_refresh(dri);
}

/*
 * Ok, set the CPU frequency.
 */
static int sa1110_target(struct cpufreq_policy *policy, unsigned int ppcr)
{
	struct sdram_params *sdram = &sdram_params;
	struct sdram_info sd;
	unsigned long flags;
	unsigned int unused;

	sdram_calculate_timing(&sd, sa11x0_freq_table[ppcr].frequency, sdram);

#if 0
	/*
	 * These values are wrong according to the SA1110 documentation
	 * and errata, but they seem to work.  Need to get a storage
	 * scope on to the SDRAM signals to work out why.
	 */
	if (policy->max < 147500) {
		sd.mdrefr |= MDREFR_K1DB2;
		sd.mdcas[0] = 0xaaaaaa7f;
	} else {
		sd.mdrefr &= ~MDREFR_K1DB2;
		sd.mdcas[0] = 0xaaaaaa9f;
	}
	sd.mdcas[1] = 0xaaaaaaaa;
	sd.mdcas[2] = 0xaaaaaaaa;
#endif

	/*
	 * The clock could be going away for some time.  Set the SDRAMs
	 * to refresh rapidly (every 64 memory clock cycles).  To get
	 * through the whole array, we need to wait 262144 mclk cycles.
	 * We wait 20ms to be safe.
	 */
	sdram_set_refresh(2);
	if (!irqs_disabled())
		msleep(20);
	else
		mdelay(20);

	/*
	 * Reprogram the DRAM timings with interrupts disabled, and
	 * ensure that we are doing this within a complete cache line.
	 * This means that we won't access SDRAM for the duration of
	 * the programming.
	 */
	local_irq_save(flags);
	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
	udelay(10);
	__asm__ __volatile__("\n\
		b	2f					\n\
		.align	5					\n\
1:		str	%3, [%1, #0]		@ MDCNFG	\n\
		str	%4, [%1, #28]		@ MDREFR	\n\
		str	%5, [%1, #4]		@ MDCAS0	\n\
		str	%6, [%1, #8]		@ MDCAS1	\n\
		str	%7, [%1, #12]		@ MDCAS2	\n\
		str	%8, [%2, #0]		@ PPCR		\n\
		ldr	%0, [%1, #0]				\n\
		b	3f					\n\
2:		b	1b					\n\
3:		nop						\n\
		nop"
		: "=&r" (unused)
		: "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg),
		  "r" (sd.mdrefr), "r" (sd.mdcas[0]),
		  "r" (sd.mdcas[1]), "r" (sd.mdcas[2]), "r" (ppcr));
	local_irq_restore(flags);

	/*
	 * Now, return the SDRAM refresh back to normal.
	 */
	sdram_update_refresh(sa11x0_freq_table[ppcr].frequency, sdram);

	return 0;
}

static int __init sa1110_cpu_init(struct cpufreq_policy *policy)
{
	return cpufreq_generic_init(policy, sa11x0_freq_table, CPUFREQ_ETERNAL);
}

/* sa1110_driver needs __refdata because it must remain after init registers
 * it with cpufreq_register_driver() */
static struct cpufreq_driver sa1110_driver __refdata = {
	.flags		= CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	.verify		= cpufreq_generic_frequency_table_verify,
	.target_index	= sa1110_target,
	.get		= sa11x0_getspeed,
	.init		= sa1110_cpu_init,
	.name		= "sa1110",
};

static struct sdram_params *sa1110_find_sdram(const char *name)
{
	struct sdram_params *sdram;

	for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl);
	     sdram++)
		if (strcmp(name, sdram->name) == 0)
			return sdram;

	return NULL;
}

static char sdram_name[16];

static int __init sa1110_clk_init(void)
{
	struct sdram_params *sdram;
	const char *name = sdram_name;

	if (!cpu_is_sa1110())
		return -ENODEV;

	if (!name[0]) {
		if (machine_is_assabet())
			name = "TC59SM716-CL3";
		if (machine_is_pt_system3())
			name = "K4S641632D";
		if (machine_is_h3100())
			name = "KM416S4030CT";
		if (machine_is_jornada720() || machine_is_h3600())
			name = "K4S281632B-1H";
		if (machine_is_nanoengine())
			name = "MT48LC8M16A2TG-75";
	}

	sdram = sa1110_find_sdram(name);
	if (sdram) {
		printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d"
			" twr: %d refresh: %d cas_latency: %d\n",
			sdram->tck, sdram->trcd, sdram->trp,
			sdram->twr, sdram->refresh, sdram->cas_latency);

		memcpy(&sdram_params, sdram, sizeof(sdram_params));

		return cpufreq_register_driver(&sa1110_driver);
	}

	return 0;
}

module_param_string(sdram, sdram_name, sizeof(sdram_name), 0);
arch_initcall(sa1110_clk_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-sa1100/cpu-sa1110.c
	3	*
	4	* Copyright (C) 2001 Russell King
	5	*
1da177e4 LT	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Note: there are two erratas that apply to the SA1110 here:
	11	* 7 - SDRAM auto-power-up failure (rev A0)
	12	* 13 - Corruption of internal register reads/writes following
	13	* SDRAM reads (rev A0, B0, B1)
	14	*
	15	* We ignore rev. A0 and B0 devices; I don't think they're worth supporting.
ba532011 RK	16	*
ba532011 RK	17	* The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
1da177e4	18	*/
1da177e4 LT	19	#include <linux/cpufreq.h>
	20	#include <linux/delay.h>
	21	#include <linux/init.h>
3169663a	22	#include <linux/io.h>
9f15d2ca MRJ	23	#include <linux/kernel.h>
	24	#include <linux/moduleparam.h>
	25	#include <linux/types.h>
1da177e4	26
0ba8b9b2	27	#include <asm/cputype.h>
1da177e4	28	#include <asm/mach-types.h>
9f15d2ca	29
59a2e613	30	#include <mach/generic.h>
9f15d2ca	31	#include <mach/hardware.h>
1da177e4	32
1da177e4 LT	33	#undef DEBUG
1da177e4 LT	34
1da177e4	35	struct sdram_params {
9f15d2ca	36	const char name[20];
1da177e4 LT	37	u_char rows; /* bits */
	38	u_char cas_latency; /* cycles */
	39	u_char tck; /* clock cycle time (ns) */
	40	u_char trcd; /* activate to r/w (ns) */
	41	u_char trp; /* precharge to activate (ns) */
	42	u_char twr; /* write recovery time (ns) */
	43	u_short refresh; /* refresh time for array (us) */
	44	};
	45
	46	struct sdram_info {
	47	u_int mdcnfg;
	48	u_int mdrefr;
	49	u_int mdcas[3];
	50	};
	51
ba532011 RK	52	static struct sdram_params sdram_tbl[] __initdata = {
	53	{ /* Toshiba TC59SM716 CL2 */
	54	.name = "TC59SM716-CL2",
	55	.rows = 12,
	56	.tck = 10,
	57	.trcd = 20,
	58	.trp = 20,
	59	.twr = 10,
	60	.refresh = 64000,
	61	.cas_latency = 2,
	62	}, { /* Toshiba TC59SM716 CL3 */
	63	.name = "TC59SM716-CL3",
	64	.rows = 12,
	65	.tck = 8,
	66	.trcd = 20,
	67	.trp = 20,
	68	.twr = 8,
	69	.refresh = 64000,
	70	.cas_latency = 3,
	71	}, { /* Samsung K4S641632D TC75 */
	72	.name = "K4S641632D",
	73	.rows = 14,
	74	.tck = 9,
	75	.trcd = 27,
	76	.trp = 20,
	77	.twr = 9,
	78	.refresh = 64000,
	79	.cas_latency = 3,
93982535 KE	80	}, { /* Samsung K4S281632B-1H */
	81	.name = "K4S281632B-1H",
	82	.rows = 12,
	83	.tck = 10,
	84	.trp = 20,
	85	.twr = 10,
	86	.refresh = 64000,
	87	.cas_latency = 3,
ba532011 RK	88	}, { /* Samsung KM416S4030CT */
	89	.name = "KM416S4030CT",
	90	.rows = 13,
	91	.tck = 8,
	92	.trcd = 24, /* 3 CLKs */
	93	.trp = 24, /* 3 CLKs */
	94	.twr = 16, /* Trdl: 2 CLKs */
	95	.refresh = 64000,
	96	.cas_latency = 3,
	97	}, { /* Winbond W982516AH75L CL3 */
	98	.name = "W982516AH75L",
	99	.rows = 16,
	100	.tck = 8,
	101	.trcd = 20,
	102	.trp = 20,
	103	.twr = 8,
	104	.refresh = 64000,
	105	.cas_latency = 3,
9f15d2ca MRJ	106	}, { /* Micron MT48LC8M16A2TG-75 */
	107	.name = "MT48LC8M16A2TG-75",
	108	.rows = 12,
	109	.tck = 8,
	110	.trcd = 20,
	111	.trp = 20,
	112	.twr = 8,
	113	.refresh = 64000,
	114	.cas_latency = 3,
ba532011	115	},
1da177e4 LT	116	};
	117
	118	static struct sdram_params sdram_params;
	119
	120	/*
	121	* Given a period in ns and frequency in khz, calculate the number of
	122	* cycles of frequency in period. Note that we round up to the next
	123	* cycle, even if we are only slightly over.
	124	*/
	125	static inline u_int ns_to_cycles(u_int ns, u_int khz)
	126	{
	127	return (ns * khz + 999999) / 1000000;
	128	}
	129
	130	/*
	131	* Create the MDCAS register bit pattern.
	132	*/
	133	static inline void set_mdcas(u_int *mdcas, int delayed, u_int rcd)
	134	{
	135	u_int shift;
	136
	137	rcd = 2 * rcd - 1;
	138	shift = delayed + 1 + rcd;
	139
	140	mdcas[0] = (1 << rcd) - 1;
	141	mdcas[0] \|= 0x55555555 << shift;
	142	mdcas[1] = mdcas[2] = 0x55555555 << (shift & 1);
	143	}
	144
	145	static void
	146	sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz,
	147	struct sdram_params *sdram)
	148	{
	149	u_int mem_khz, sd_khz, trp, twr;
	150
	151	mem_khz = cpu_khz / 2;
	152	sd_khz = mem_khz;
	153
	154	/*
	155	* If SDCLK would invalidate the SDRAM timings,
	156	* run SDCLK at half speed.
	157	*
	158	* CPU steppings prior to B2 must either run the memory at
	159	* half speed or use delayed read latching (errata 13).
	160	*/
	161	if ((ns_to_cycles(sdram->tck, sd_khz) > 1) \|\|
	162	(CPU_REVISION < CPU_SA1110_B2 && sd_khz < 62000))
	163	sd_khz /= 2;
	164
	165	sd->mdcnfg = MDCNFG & 0x007f007f;
	166
	167	twr = ns_to_cycles(sdram->twr, mem_khz);
	168
	169	/* trp should always be >1 */
	170	trp = ns_to_cycles(sdram->trp, mem_khz) - 1;
	171	if (trp < 1)
	172	trp = 1;
	173
	174	sd->mdcnfg \|= trp << 8;
	175	sd->mdcnfg \|= trp << 24;
	176	sd->mdcnfg \|= sdram->cas_latency << 12;
	177	sd->mdcnfg \|= sdram->cas_latency << 28;
	178	sd->mdcnfg \|= twr << 14;
	179	sd->mdcnfg \|= twr << 30;
180
181	sd->mdrefr = MDREFR & 0xffbffff0;
182	sd->mdrefr \|= 7;
183
184	if (sd_khz != mem_khz)
185	sd->mdrefr \|= MDREFR_K1DB2;
186
187	/* initial number of '1's in MDCAS + 1 */
47bb3b31 MRJ	188	set_mdcas(sd->mdcas, sd_khz >= 62000,
47bb3b31 MRJ	189	ns_to_cycles(sdram->trcd, mem_khz));
1da177e4 LT	190
1da177e4 LT	191	#ifdef DEBUG
47bb3b31 MRJ	192	printk(KERN_DEBUG "MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
	193	sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1],
	194	sd->mdcas[2]);
1da177e4 LT	195	#endif
	196	}
	197
	198	/*
	199	* Set the SDRAM refresh rate.
	200	*/
	201	static inline void sdram_set_refresh(u_int dri)
	202	{
	203	MDREFR = (MDREFR & 0xffff000f) \| (dri << 4);
	204	(void) MDREFR;
	205	}
	206
	207	/*
	208	* Update the refresh period. We do this such that we always refresh
	209	* the SDRAMs within their permissible period. The refresh period is
	210	* always a multiple of the memory clock (fixed at cpu_clock / 2).
	211	*
	212	* FIXME: we don't currently take account of burst accesses here,
	213	* but neither do Intels DM nor Angel.
	214	*/
	215	static void
	216	sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram)
	217	{
	218	u_int ns_row = (sdram->refresh * 1000) >> sdram->rows;
	219	u_int dri = ns_to_cycles(ns_row, cpu_khz / 2) / 32;
	220
	221	#ifdef DEBUG
	222	mdelay(250);
47bb3b31	223	printk(KERN_DEBUG "new dri value = %d\n", dri);
1da177e4 LT	224	#endif
	225
	226	sdram_set_refresh(dri);
	227	}
	228
	229	/*
93982535	230	* Ok, set the CPU frequency.
1da177e4	231	*/
9c0ebcf7	232	static int sa1110_target(struct cpufreq_policy *policy, unsigned int ppcr)
1da177e4 LT	233	{
1da177e4 LT	234	struct sdram_params *sdram = &sdram_params;
1da177e4 LT	235	struct sdram_info sd;
1da177e4 LT	236	unsigned long flags;
9c0ebcf7	237	unsigned int unused;
1da177e4	238
d4019f0a	239	sdram_calculate_timing(&sd, sa11x0_freq_table[ppcr].frequency, sdram);
1da177e4 LT	240
	241	#if 0
	242	/*
	243	* These values are wrong according to the SA1110 documentation
	244	* and errata, but they seem to work. Need to get a storage
	245	* scope on to the SDRAM signals to work out why.
	246	*/
	247	if (policy->max < 147500) {
	248	sd.mdrefr \|= MDREFR_K1DB2;
	249	sd.mdcas[0] = 0xaaaaaa7f;
	250	} else {
	251	sd.mdrefr &= ~MDREFR_K1DB2;
	252	sd.mdcas[0] = 0xaaaaaa9f;
	253	}
	254	sd.mdcas[1] = 0xaaaaaaaa;
	255	sd.mdcas[2] = 0xaaaaaaaa;
	256	#endif
	257
1da177e4 LT	258	/*
	259	* The clock could be going away for some time. Set the SDRAMs
	260	* to refresh rapidly (every 64 memory clock cycles). To get
	261	* through the whole array, we need to wait 262144 mclk cycles.
	262	* We wait 20ms to be safe.
	263	*/
	264	sdram_set_refresh(2);
47bb3b31	265	if (!irqs_disabled())
db579554	266	msleep(20);
47bb3b31	267	else
1da177e4	268	mdelay(20);
1da177e4 LT	269
	270	/*
	271	* Reprogram the DRAM timings with interrupts disabled, and
	272	* ensure that we are doing this within a complete cache line.
	273	* This means that we won't access SDRAM for the duration of
	274	* the programming.
	275	*/
	276	local_irq_save(flags);
	277	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
	278	udelay(10);
47bb3b31	279	__asm__ __volatile__("\n\
1da177e4 LT	280	b 2f \n\
	281	.align 5 \n\
	282	1: str %3, [%1, #0] @ MDCNFG \n\
	283	str %4, [%1, #28] @ MDREFR \n\
	284	str %5, [%1, #4] @ MDCAS0 \n\
	285	str %6, [%1, #8] @ MDCAS1 \n\
	286	str %7, [%1, #12] @ MDCAS2 \n\
	287	str %8, [%2, #0] @ PPCR \n\
	288	ldr %0, [%1, #0] \n\
	289	b 3f \n\
	290	2: b 1b \n\
	291	3: nop \n\
	292	nop"
	293	: "=&r" (unused)
	294	: "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg),
	295	"r" (sd.mdrefr), "r" (sd.mdcas[0]),
	296	"r" (sd.mdcas[1]), "r" (sd.mdcas[2]), "r" (ppcr));
	297	local_irq_restore(flags);
	298
	299	/*
	300	* Now, return the SDRAM refresh back to normal.
	301	*/
d4019f0a	302	sdram_update_refresh(sa11x0_freq_table[ppcr].frequency, sdram);
1da177e4 LT	303
	304	return 0;
	305	}
	306
	307	static int __init sa1110_cpu_init(struct cpufreq_policy *policy)
	308	{
9b30367b	309	return cpufreq_generic_init(policy, sa11x0_freq_table, CPUFREQ_ETERNAL);
1da177e4 LT	310	}
1da177e4 LT	311
9f15d2ca MRJ	312	/* sa1110_driver needs __refdata because it must remain after init registers
	313	* it with cpufreq_register_driver() */
	314	static struct cpufreq_driver sa1110_driver __refdata = {
ae6b4271	315	.flags = CPUFREQ_STICKY \| CPUFREQ_NEED_INITIAL_FREQ_CHECK,
dd9f2639	316	.verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7	317	.target_index = sa1110_target,
1da177e4 LT	318	.get = sa11x0_getspeed,
	319	.init = sa1110_cpu_init,
	320	.name = "sa1110",
	321	};
	322
ba532011 RK	323	static struct sdram_params sa1110_find_sdram(const char name)
	324	{
	325	struct sdram_params *sdram;
	326
47bb3b31 MRJ	327	for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl);
47bb3b31 MRJ	328	sdram++)
ba532011 RK	329	if (strcmp(name, sdram->name) == 0)
	330	return sdram;
	331
	332	return NULL;
	333	}
	334
	335	static char sdram_name[16];
	336
1da177e4 LT	337	static int __init sa1110_clk_init(void)
1da177e4 LT	338	{
ba532011 RK	339	struct sdram_params *sdram;
ba532011 RK	340	const char *name = sdram_name;
1da177e4	341
e5992c05 DA	342	if (!cpu_is_sa1110())
	343	return -ENODEV;
	344
ba532011 RK	345	if (!name[0]) {
	346	if (machine_is_assabet())
	347	name = "TC59SM716-CL3";
ba532011 RK	348	if (machine_is_pt_system3())
ba532011 RK	349	name = "K4S641632D";
ba532011 RK	350	if (machine_is_h3100())
ba532011 RK	351	name = "KM416S4030CT";
97d496bf	352	if (machine_is_jornada720() \|\| machine_is_h3600())
47bb3b31	353	name = "K4S281632B-1H";
9f15d2ca MRJ	354	if (machine_is_nanoengine())
9f15d2ca MRJ	355	name = "MT48LC8M16A2TG-75";
ba532011	356	}
1da177e4	357
ba532011	358	sdram = sa1110_find_sdram(name);
1da177e4 LT	359	if (sdram) {
	360	printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d"
	361	" twr: %d refresh: %d cas_latency: %d\n",
	362	sdram->tck, sdram->trcd, sdram->trp,
	363	sdram->twr, sdram->refresh, sdram->cas_latency);
	364
	365	memcpy(&sdram_params, sdram, sizeof(sdram_params));
	366
	367	return cpufreq_register_driver(&sa1110_driver);
	368	}
	369
	370	return 0;
	371	}
	372
ba532011	373	module_param_string(sdram, sdram_name, sizeof(sdram_name), 0);
1da177e4	374	arch_initcall(sa1110_clk_init);