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drm/i915/gvt: Add software PTE flag to mark special 64K splited entry
[linux.git] / drivers / gpu / drm / i915 / gvt / gtt.c
CommitLineData
2707e444
ZW		 1/*
2 * GTT virtualization
3 *
4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Zhi Wang <[email protected]>
27 * Zhenyu Wang <[email protected]>
28 * Xiao Zheng <[email protected]>
29 *
30 * Contributors:
31 * Min He <[email protected]>
32 * Bing Niu <[email protected]>
33 *
34 */
35
36#include "i915_drv.h"
feddf6e8
ZW		 37#include "gvt.h"
38#include "i915_pvinfo.h"
2707e444
ZW		 39#include "trace.h"
40
bc37ab56
CD		 41#if defined(VERBOSE_DEBUG)
42#define gvt_vdbg_mm(fmt, args...) gvt_dbg_mm(fmt, ##args)
43#else
44#define gvt_vdbg_mm(fmt, args...)
45#endif
46
2707e444
ZW		 47static bool enable_out_of_sync = false;
48static int preallocated_oos_pages = 8192;
49
50/*
51 * validate a gm address and related range size,
52 * translate it to host gm address
53 */
54bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
55{
56 if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
57 && !vgpu_gmadr_is_valid(vgpu, addr + size - 1))) {
695fbc08
TZ		 58 gvt_vgpu_err("invalid range gmadr 0x%llx size 0x%x\n",
59 addr, size);
2707e444
ZW		 60 return false;
61 }
62 return true;
63}
64
65/* translate a guest gmadr to host gmadr */
66int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
67{
68 if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr),
69 "invalid guest gmadr %llx\n", g_addr))
70 return -EACCES;
71
72 if (vgpu_gmadr_is_aperture(vgpu, g_addr))
73 *h_addr = vgpu_aperture_gmadr_base(vgpu)
74 + (g_addr - vgpu_aperture_offset(vgpu));
75 else
76 *h_addr = vgpu_hidden_gmadr_base(vgpu)
77 + (g_addr - vgpu_hidden_offset(vgpu));
78 return 0;
79}
80
81/* translate a host gmadr to guest gmadr */
82int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
83{
84 if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr),
85 "invalid host gmadr %llx\n", h_addr))
86 return -EACCES;
87
88 if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
89 *g_addr = vgpu_aperture_gmadr_base(vgpu)
90 + (h_addr - gvt_aperture_gmadr_base(vgpu->gvt));
91 else
92 *g_addr = vgpu_hidden_gmadr_base(vgpu)
93 + (h_addr - gvt_hidden_gmadr_base(vgpu->gvt));
94 return 0;
95}
96
97int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
98 unsigned long *h_index)
99{
100 u64 h_addr;
101 int ret;
102
9556e118 103 ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << I915_GTT_PAGE_SHIFT,
2707e444
ZW		 104 &h_addr);
105 if (ret)
106 return ret;
107
9556e118 108 *h_index = h_addr >> I915_GTT_PAGE_SHIFT;
2707e444
ZW		 109 return 0;
110}
111
112int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
113 unsigned long *g_index)
114{
115 u64 g_addr;
116 int ret;
117
9556e118 118 ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << I915_GTT_PAGE_SHIFT,
2707e444
ZW		 119 &g_addr);
120 if (ret)
121 return ret;
122
9556e118 123 *g_index = g_addr >> I915_GTT_PAGE_SHIFT;
2707e444
ZW		 124 return 0;
125}
126
127#define gtt_type_is_entry(type) \
128 (type > GTT_TYPE_INVALID && type < GTT_TYPE_PPGTT_ENTRY \
129 && type != GTT_TYPE_PPGTT_PTE_ENTRY \
130 && type != GTT_TYPE_PPGTT_ROOT_ENTRY)
131
132#define gtt_type_is_pt(type) \
133 (type >= GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX)
134
135#define gtt_type_is_pte_pt(type) \
136 (type == GTT_TYPE_PPGTT_PTE_PT)
137
138#define gtt_type_is_root_pointer(type) \
139 (gtt_type_is_entry(type) && type > GTT_TYPE_PPGTT_ROOT_ENTRY)
140
141#define gtt_init_entry(e, t, p, v) do { \
142 (e)->type = t; \
143 (e)->pdev = p; \
144 memcpy(&(e)->val64, &v, sizeof(v)); \
145} while (0)
146
2707e444
ZW		 147/*
148 * Mappings between GTT_TYPE* enumerations.
149 * Following information can be found according to the given type:
150 * - type of next level page table
151 * - type of entry inside this level page table
152 * - type of entry with PSE set
153 *
154 * If the given type doesn't have such a kind of information,
155 * e.g. give a l4 root entry type, then request to get its PSE type,
156 * give a PTE page table type, then request to get its next level page
157 * table type, as we know l4 root entry doesn't have a PSE bit,
158 * and a PTE page table doesn't have a next level page table type,
159 * GTT_TYPE_INVALID will be returned. This is useful when traversing a
160 * page table.
161 */
162
163struct gtt_type_table_entry {
164 int entry_type;
054f4eba 165 int pt_type;
2707e444
ZW		 166 int next_pt_type;
167 int pse_entry_type;
168};
169
054f4eba 170#define GTT_TYPE_TABLE_ENTRY(type, e_type, cpt_type, npt_type, pse_type) \
2707e444
ZW		 171 [type] = { \
172 .entry_type = e_type, \
054f4eba 173 .pt_type = cpt_type, \
2707e444
ZW		 174 .next_pt_type = npt_type, \
175 .pse_entry_type = pse_type, \
176 }
177
178static struct gtt_type_table_entry gtt_type_table[] = {
179 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
180 GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
054f4eba 181 GTT_TYPE_INVALID,
2707e444
ZW		 182 GTT_TYPE_PPGTT_PML4_PT,
183 GTT_TYPE_INVALID),
184 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_PT,
185 GTT_TYPE_PPGTT_PML4_ENTRY,
054f4eba 186 GTT_TYPE_PPGTT_PML4_PT,
2707e444
ZW		 187 GTT_TYPE_PPGTT_PDP_PT,
188 GTT_TYPE_INVALID),
189 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_ENTRY,
190 GTT_TYPE_PPGTT_PML4_ENTRY,
054f4eba 191 GTT_TYPE_PPGTT_PML4_PT,
2707e444
ZW		 192 GTT_TYPE_PPGTT_PDP_PT,
193 GTT_TYPE_INVALID),
194 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_PT,
195 GTT_TYPE_PPGTT_PDP_ENTRY,
054f4eba 196 GTT_TYPE_PPGTT_PDP_PT,
2707e444
ZW		 197 GTT_TYPE_PPGTT_PDE_PT,
198 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
199 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
200 GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
054f4eba 201 GTT_TYPE_INVALID,
2707e444
ZW		 202 GTT_TYPE_PPGTT_PDE_PT,
203 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
204 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_ENTRY,
205 GTT_TYPE_PPGTT_PDP_ENTRY,
054f4eba 206 GTT_TYPE_PPGTT_PDP_PT,
2707e444
ZW		 207 GTT_TYPE_PPGTT_PDE_PT,
208 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
209 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_PT,
210 GTT_TYPE_PPGTT_PDE_ENTRY,
054f4eba 211 GTT_TYPE_PPGTT_PDE_PT,
2707e444
ZW		 212 GTT_TYPE_PPGTT_PTE_PT,
213 GTT_TYPE_PPGTT_PTE_2M_ENTRY),
214 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_ENTRY,
215 GTT_TYPE_PPGTT_PDE_ENTRY,
054f4eba 216 GTT_TYPE_PPGTT_PDE_PT,
2707e444
ZW		 217 GTT_TYPE_PPGTT_PTE_PT,
218 GTT_TYPE_PPGTT_PTE_2M_ENTRY),
b294657d 219 /* We take IPS bit as 'PSE' for PTE level. */
2707e444
ZW		 220 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_PT,
221 GTT_TYPE_PPGTT_PTE_4K_ENTRY,
054f4eba 222 GTT_TYPE_PPGTT_PTE_PT,
2707e444 223 GTT_TYPE_INVALID,
b294657d 224 GTT_TYPE_PPGTT_PTE_64K_ENTRY),
2707e444
ZW		 225 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_4K_ENTRY,
226 GTT_TYPE_PPGTT_PTE_4K_ENTRY,
054f4eba 227 GTT_TYPE_PPGTT_PTE_PT,
2707e444 228 GTT_TYPE_INVALID,
b294657d
CD		 229 GTT_TYPE_PPGTT_PTE_64K_ENTRY),
230 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_64K_ENTRY,
231 GTT_TYPE_PPGTT_PTE_4K_ENTRY,
232 GTT_TYPE_PPGTT_PTE_PT,
233 GTT_TYPE_INVALID,
234 GTT_TYPE_PPGTT_PTE_64K_ENTRY),
2707e444
ZW		 235 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_2M_ENTRY,
236 GTT_TYPE_PPGTT_PDE_ENTRY,
054f4eba 237 GTT_TYPE_PPGTT_PDE_PT,
2707e444
ZW		 238 GTT_TYPE_INVALID,
239 GTT_TYPE_PPGTT_PTE_2M_ENTRY),
240 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_1G_ENTRY,
241 GTT_TYPE_PPGTT_PDP_ENTRY,
054f4eba 242 GTT_TYPE_PPGTT_PDP_PT,
2707e444
ZW		 243 GTT_TYPE_INVALID,
244 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
245 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_GGTT_PTE,
246 GTT_TYPE_GGTT_PTE,
247 GTT_TYPE_INVALID,
054f4eba 248 GTT_TYPE_INVALID,
2707e444
ZW		 249 GTT_TYPE_INVALID),
250};
251
252static inline int get_next_pt_type(int type)
253{
254 return gtt_type_table[type].next_pt_type;
255}
256
054f4eba
ZW		 257static inline int get_pt_type(int type)
258{
259 return gtt_type_table[type].pt_type;
260}
261
2707e444
ZW		 262static inline int get_entry_type(int type)
263{
264 return gtt_type_table[type].entry_type;
265}
266
267static inline int get_pse_type(int type)
268{
269 return gtt_type_table[type].pse_entry_type;
270}
271
272static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index)
273{
321927db 274 void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
905a5035
CD		 275
276 return readq(addr);
2707e444
ZW		 277}
278
a143cef7 279static void ggtt_invalidate(struct drm_i915_private *dev_priv)
af2c6399
CD		 280{
281 mmio_hw_access_pre(dev_priv);
282 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
283 mmio_hw_access_post(dev_priv);
284}
285
2707e444
ZW		 286static void write_pte64(struct drm_i915_private *dev_priv,
287 unsigned long index, u64 pte)
288{
321927db 289 void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
2707e444 290
2707e444 291 writeq(pte, addr);
2707e444
ZW		 292}
293
4b2dbbc2 294static inline int gtt_get_entry64(void *pt,
2707e444
ZW		 295 struct intel_gvt_gtt_entry *e,
296 unsigned long index, bool hypervisor_access, unsigned long gpa,
297 struct intel_vgpu *vgpu)
298{
299 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
300 int ret;
301
302 if (WARN_ON(info->gtt_entry_size != 8))
4b2dbbc2 303 return -EINVAL;
2707e444
ZW		 304
305 if (hypervisor_access) {
306 ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa +
307 (index << info->gtt_entry_size_shift),
308 &e->val64, 8);
4b2dbbc2
CD		 309 if (WARN_ON(ret))
310 return ret;
2707e444
ZW		 311 } else if (!pt) {
312 e->val64 = read_pte64(vgpu->gvt->dev_priv, index);
313 } else {
314 e->val64 = *((u64 *)pt + index);
315 }
4b2dbbc2 316 return 0;
2707e444
ZW		 317}
318
4b2dbbc2 319static inline int gtt_set_entry64(void *pt,
2707e444
ZW		 320 struct intel_gvt_gtt_entry *e,
321 unsigned long index, bool hypervisor_access, unsigned long gpa,
322 struct intel_vgpu *vgpu)
323{
324 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
325 int ret;
326
327 if (WARN_ON(info->gtt_entry_size != 8))
4b2dbbc2 328 return -EINVAL;
2707e444
ZW		 329
330 if (hypervisor_access) {
331 ret = intel_gvt_hypervisor_write_gpa(vgpu, gpa +
332 (index << info->gtt_entry_size_shift),
333 &e->val64, 8);
4b2dbbc2
CD		 334 if (WARN_ON(ret))
335 return ret;
2707e444
ZW		 336 } else if (!pt) {
337 write_pte64(vgpu->gvt->dev_priv, index, e->val64);
338 } else {
339 *((u64 *)pt + index) = e->val64;
340 }
4b2dbbc2 341 return 0;
2707e444
ZW		 342}
343
344#define GTT_HAW 46
345
420fba78
CD		 346#define ADDR_1G_MASK GENMASK_ULL(GTT_HAW - 1, 30)
347#define ADDR_2M_MASK GENMASK_ULL(GTT_HAW - 1, 21)
b294657d 348#define ADDR_64K_MASK GENMASK_ULL(GTT_HAW - 1, 16)
420fba78 349#define ADDR_4K_MASK GENMASK_ULL(GTT_HAW - 1, 12)
2707e444 350
71634848
CD		 351#define GTT_SPTE_FLAG_MASK GENMASK_ULL(62, 52)
352#define GTT_SPTE_FLAG_64K_SPLITED BIT(52) /* splited 64K gtt entry */
353
2707e444
ZW		 354static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
355{
356 unsigned long pfn;
357
358 if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY)
d861ca23 359 pfn = (e->val64 & ADDR_1G_MASK) >> PAGE_SHIFT;
2707e444 360 else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY)
d861ca23 361 pfn = (e->val64 & ADDR_2M_MASK) >> PAGE_SHIFT;
b294657d
CD		 362 else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY)
363 pfn = (e->val64 & ADDR_64K_MASK) >> PAGE_SHIFT;
2707e444 364 else
d861ca23 365 pfn = (e->val64 & ADDR_4K_MASK) >> PAGE_SHIFT;
2707e444
ZW		 366 return pfn;
367}
368
369static void gen8_gtt_set_pfn(struct intel_gvt_gtt_entry *e, unsigned long pfn)
370{
371 if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) {
372 e->val64 &= ~ADDR_1G_MASK;
d861ca23 373 pfn &= (ADDR_1G_MASK >> PAGE_SHIFT);
2707e444
ZW		 374 } else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY) {
375 e->val64 &= ~ADDR_2M_MASK;
d861ca23 376 pfn &= (ADDR_2M_MASK >> PAGE_SHIFT);
b294657d
CD		 377 } else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY) {
378 e->val64 &= ~ADDR_64K_MASK;
379 pfn &= (ADDR_64K_MASK >> PAGE_SHIFT);
2707e444
ZW		 380 } else {
381 e->val64 &= ~ADDR_4K_MASK;
d861ca23 382 pfn &= (ADDR_4K_MASK >> PAGE_SHIFT);
2707e444
ZW		 383 }
384
d861ca23 385 e->val64 |= (pfn << PAGE_SHIFT);
2707e444
ZW		 386}
387
388static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e)
389{
40b27176 390 return !!(e->val64 & _PAGE_PSE);
2707e444
ZW		 391}
392
6fd79378
CD		 393static bool gen8_gtt_test_ips(struct intel_gvt_gtt_entry *e)
394{
395 if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY))
396 return false;
397
398 return !!(e->val64 & GEN8_PDE_IPS_64K);
399}
400
401static void gen8_gtt_clear_ips(struct intel_gvt_gtt_entry *e)
402{
403 if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY))
404 return;
405
406 e->val64 &= ~GEN8_PDE_IPS_64K;
407}
408
2707e444
ZW		 409static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e)
410{
411 /*
412 * i915 writes PDP root pointer registers without present bit,
413 * it also works, so we need to treat root pointer entry
414 * specifically.
415 */
416 if (e->type == GTT_TYPE_PPGTT_ROOT_L3_ENTRY
417 || e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
418 return (e->val64 != 0);
419 else
d861ca23 420 return (e->val64 & _PAGE_PRESENT);
2707e444
ZW		 421}
422
423static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
424{
d861ca23 425 e->val64 &= ~_PAGE_PRESENT;
2707e444
ZW		 426}
427
655c64ef
ZW		 428static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
429{
d861ca23 430 e->val64 |= _PAGE_PRESENT;
2707e444
ZW		 431}
432
71634848
CD		 433static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e)
434{
435 return !!(e->val64 & GTT_SPTE_FLAG_64K_SPLITED);
436}
437
438static void gen8_gtt_set_64k_splited(struct intel_gvt_gtt_entry *e)
439{
440 e->val64 |= GTT_SPTE_FLAG_64K_SPLITED;
441}
442
443static void gen8_gtt_clear_64k_splited(struct intel_gvt_gtt_entry *e)
444{
445 e->val64 &= ~GTT_SPTE_FLAG_64K_SPLITED;
446}
447
2707e444
ZW		 448/*
449 * Per-platform GMA routines.
450 */
451static unsigned long gma_to_ggtt_pte_index(unsigned long gma)
452{
9556e118 453 unsigned long x = (gma >> I915_GTT_PAGE_SHIFT);
2707e444
ZW		 454
455 trace_gma_index(__func__, gma, x);
456 return x;
457}
458
459#define DEFINE_PPGTT_GMA_TO_INDEX(prefix, ename, exp) \
460static unsigned long prefix##_gma_to_##ename##_index(unsigned long gma) \
461{ \
462 unsigned long x = (exp); \
463 trace_gma_index(__func__, gma, x); \
464 return x; \
465}
466
467DEFINE_PPGTT_GMA_TO_INDEX(gen8, pte, (gma >> 12 & 0x1ff));
468DEFINE_PPGTT_GMA_TO_INDEX(gen8, pde, (gma >> 21 & 0x1ff));
469DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
470DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
471DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));
472
473static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
474 .get_entry = gtt_get_entry64,
475 .set_entry = gtt_set_entry64,
476 .clear_present = gtt_entry_clear_present,
655c64ef 477 .set_present = gtt_entry_set_present,
2707e444
ZW		 478 .test_present = gen8_gtt_test_present,
479 .test_pse = gen8_gtt_test_pse,
6fd79378
CD		 480 .clear_ips = gen8_gtt_clear_ips,
481 .test_ips = gen8_gtt_test_ips,
71634848
CD		 482 .clear_64k_splited = gen8_gtt_clear_64k_splited,
483 .set_64k_splited = gen8_gtt_set_64k_splited,
484 .test_64k_splited = gen8_gtt_test_64k_splited,
2707e444
ZW		 485 .get_pfn = gen8_gtt_get_pfn,
486 .set_pfn = gen8_gtt_set_pfn,
487};
488
489static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
490 .gma_to_ggtt_pte_index = gma_to_ggtt_pte_index,
491 .gma_to_pte_index = gen8_gma_to_pte_index,
492 .gma_to_pde_index = gen8_gma_to_pde_index,
493 .gma_to_l3_pdp_index = gen8_gma_to_l3_pdp_index,
494 .gma_to_l4_pdp_index = gen8_gma_to_l4_pdp_index,
495 .gma_to_pml4_index = gen8_gma_to_pml4_index,
496};
497
40b27176
CD		 498/* Update entry type per pse and ips bit. */
499static void update_entry_type_for_real(struct intel_gvt_gtt_pte_ops *pte_ops,
500 struct intel_gvt_gtt_entry *entry, bool ips)
501{
502 switch (entry->type) {
503 case GTT_TYPE_PPGTT_PDE_ENTRY:
504 case GTT_TYPE_PPGTT_PDP_ENTRY:
505 if (pte_ops->test_pse(entry))
506 entry->type = get_pse_type(entry->type);
507 break;
508 case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
509 if (ips)
510 entry->type = get_pse_type(entry->type);
511 break;
512 default:
513 GEM_BUG_ON(!gtt_type_is_entry(entry->type));
514 }
515
516 GEM_BUG_ON(entry->type == GTT_TYPE_INVALID);
517}
518
2707e444
ZW		 519/*
520 * MM helpers.
521 */
3aff3512
CD		 522static void _ppgtt_get_root_entry(struct intel_vgpu_mm *mm,
523 struct intel_gvt_gtt_entry *entry, unsigned long index,
524 bool guest)
2707e444 525{
3aff3512 526 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
2707e444 527
3aff3512 528 GEM_BUG_ON(mm->type != INTEL_GVT_MM_PPGTT);
2707e444 529
3aff3512
CD		 530 entry->type = mm->ppgtt_mm.root_entry_type;
531 pte_ops->get_entry(guest ? mm->ppgtt_mm.guest_pdps :
532 mm->ppgtt_mm.shadow_pdps,
533 entry, index, false, 0, mm->vgpu);
40b27176 534 update_entry_type_for_real(pte_ops, entry, false);
2707e444
ZW		 535}
536
3aff3512
CD		 537static inline void ppgtt_get_guest_root_entry(struct intel_vgpu_mm *mm,
538 struct intel_gvt_gtt_entry *entry, unsigned long index)
2707e444 539{
3aff3512
CD		 540 _ppgtt_get_root_entry(mm, entry, index, true);
541}
542
543static inline void ppgtt_get_shadow_root_entry(struct intel_vgpu_mm *mm,
544 struct intel_gvt_gtt_entry *entry, unsigned long index)
545{
546 _ppgtt_get_root_entry(mm, entry, index, false);
547}
548
549static void _ppgtt_set_root_entry(struct intel_vgpu_mm *mm,
550 struct intel_gvt_gtt_entry *entry, unsigned long index,
551 bool guest)
552{
553 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
554
555 pte_ops->set_entry(guest ? mm->ppgtt_mm.guest_pdps :
556 mm->ppgtt_mm.shadow_pdps,
557 entry, index, false, 0, mm->vgpu);
558}
559
560static inline void ppgtt_set_guest_root_entry(struct intel_vgpu_mm *mm,
561 struct intel_gvt_gtt_entry *entry, unsigned long index)
562{
563 _ppgtt_set_root_entry(mm, entry, index, true);
564}
565
566static inline void ppgtt_set_shadow_root_entry(struct intel_vgpu_mm *mm,
567 struct intel_gvt_gtt_entry *entry, unsigned long index)
568{
569 _ppgtt_set_root_entry(mm, entry, index, false);
570}
571
572static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
573 struct intel_gvt_gtt_entry *entry, unsigned long index)
574{
575 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
576
577 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
578
579 entry->type = GTT_TYPE_GGTT_PTE;
580 pte_ops->get_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
581 false, 0, mm->vgpu);
582}
583
584static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
585 struct intel_gvt_gtt_entry *entry, unsigned long index)
586{
587 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
588
589 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
590
591 pte_ops->set_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
592 false, 0, mm->vgpu);
593}
594
7598e870
CD		 595static void ggtt_get_host_entry(struct intel_vgpu_mm *mm,
596 struct intel_gvt_gtt_entry *entry, unsigned long index)
597{
598 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
599
600 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
601
602 pte_ops->get_entry(NULL, entry, index, false, 0, mm->vgpu);
603}
604
3aff3512
CD		 605static void ggtt_set_host_entry(struct intel_vgpu_mm *mm,
606 struct intel_gvt_gtt_entry *entry, unsigned long index)
607{
608 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
609
610 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
2707e444 611
3aff3512 612 pte_ops->set_entry(NULL, entry, index, false, 0, mm->vgpu);
2707e444
ZW		 613}
614
615/*
616 * PPGTT shadow page table helpers.
617 */
4b2dbbc2 618static inline int ppgtt_spt_get_entry(
2707e444
ZW		 619 struct intel_vgpu_ppgtt_spt *spt,
620 void *page_table, int type,
621 struct intel_gvt_gtt_entry *e, unsigned long index,
622 bool guest)
623{
624 struct intel_gvt *gvt = spt->vgpu->gvt;
625 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
4b2dbbc2 626 int ret;
2707e444
ZW		 627
628 e->type = get_entry_type(type);
629
630 if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
4b2dbbc2 631 return -EINVAL;
2707e444 632
4b2dbbc2 633 ret = ops->get_entry(page_table, e, index, guest,
e502a2af 634 spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
2707e444 635 spt->vgpu);
4b2dbbc2
CD		 636 if (ret)
637 return ret;
638
40b27176
CD		 639 update_entry_type_for_real(ops, e, guest ?
640 spt->guest_page.pde_ips : false);
bc37ab56
CD		 641
642 gvt_vdbg_mm("read ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
643 type, e->type, index, e->val64);
4b2dbbc2 644 return 0;
2707e444
ZW		 645}
646
4b2dbbc2 647static inline int ppgtt_spt_set_entry(
2707e444
ZW		 648 struct intel_vgpu_ppgtt_spt *spt,
649 void *page_table, int type,
650 struct intel_gvt_gtt_entry *e, unsigned long index,
651 bool guest)
652{
653 struct intel_gvt *gvt = spt->vgpu->gvt;
654 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
655
656 if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
4b2dbbc2 657 return -EINVAL;
2707e444 658
bc37ab56
CD		 659 gvt_vdbg_mm("set ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
660 type, e->type, index, e->val64);
661
2707e444 662 return ops->set_entry(page_table, e, index, guest,
e502a2af 663 spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
2707e444
ZW		 664 spt->vgpu);
665}
666
667#define ppgtt_get_guest_entry(spt, e, index) \
668 ppgtt_spt_get_entry(spt, NULL, \
44b46733 669 spt->guest_page.type, e, index, true)
2707e444
ZW		 670
671#define ppgtt_set_guest_entry(spt, e, index) \
672 ppgtt_spt_set_entry(spt, NULL, \
44b46733 673 spt->guest_page.type, e, index, true)
2707e444
ZW		 674
675#define ppgtt_get_shadow_entry(spt, e, index) \
676 ppgtt_spt_get_entry(spt, spt->shadow_page.vaddr, \
677 spt->shadow_page.type, e, index, false)
678
679#define ppgtt_set_shadow_entry(spt, e, index) \
680 ppgtt_spt_set_entry(spt, spt->shadow_page.vaddr, \
681 spt->shadow_page.type, e, index, false)
682
44b46733 683static void *alloc_spt(gfp_t gfp_mask)
2707e444 684{
44b46733 685 struct intel_vgpu_ppgtt_spt *spt;
2707e444 686
44b46733
CD		 687 spt = kzalloc(sizeof(*spt), gfp_mask);
688 if (!spt)
689 return NULL;
2707e444 690
44b46733
CD		 691 spt->shadow_page.page = alloc_page(gfp_mask);
692 if (!spt->shadow_page.page) {
693 kfree(spt);
694 return NULL;
695 }
696 return spt;
2707e444
ZW		 697}
698
44b46733 699static void free_spt(struct intel_vgpu_ppgtt_spt *spt)
2707e444 700{
44b46733
CD		 701 __free_page(spt->shadow_page.page);
702 kfree(spt);
2707e444
ZW		 703}
704
7d1e5cdf
ZW		 705static int detach_oos_page(struct intel_vgpu *vgpu,
706 struct intel_vgpu_oos_page *oos_page);
707
d87f5ff3 708static void ppgtt_free_spt(struct intel_vgpu_ppgtt_spt *spt)
2707e444 709{
44b46733 710 struct device *kdev = &spt->vgpu->gvt->dev_priv->drm.pdev->dev;
2707e444 711
44b46733 712 trace_spt_free(spt->vgpu->id, spt, spt->guest_page.type);
7d1e5cdf 713
44b46733
CD		 714 dma_unmap_page(kdev, spt->shadow_page.mfn << I915_GTT_PAGE_SHIFT, 4096,
715 PCI_DMA_BIDIRECTIONAL);
b6c126a3
CD		 716
717 radix_tree_delete(&spt->vgpu->gtt.spt_tree, spt->shadow_page.mfn);
2707e444 718
44b46733
CD		 719 if (spt->guest_page.oos_page)
720 detach_oos_page(spt->vgpu, spt->guest_page.oos_page);
2707e444 721
e502a2af 722 intel_vgpu_unregister_page_track(spt->vgpu, spt->guest_page.gfn);
2707e444 723
2707e444 724 list_del_init(&spt->post_shadow_list);
2707e444
ZW		 725 free_spt(spt);
726}
727
d87f5ff3 728static void ppgtt_free_all_spt(struct intel_vgpu *vgpu)
2707e444 729{
44b46733 730 struct intel_vgpu_ppgtt_spt *spt;
b6c126a3
CD		 731 struct radix_tree_iter iter;
732 void **slot;
2707e444 733
b6c126a3
CD		 734 radix_tree_for_each_slot(slot, &vgpu->gtt.spt_tree, &iter, 0) {
735 spt = radix_tree_deref_slot(slot);
d87f5ff3 736 ppgtt_free_spt(spt);
b6c126a3 737 }
2707e444
ZW		 738}
739
7d1e5cdf 740static int ppgtt_handle_guest_write_page_table_bytes(
44b46733 741 struct intel_vgpu_ppgtt_spt *spt,
2707e444
ZW		 742 u64 pa, void *p_data, int bytes);
743
e502a2af
CD		 744static int ppgtt_write_protection_handler(
745 struct intel_vgpu_page_track *page_track,
746 u64 gpa, void *data, int bytes)
2707e444 747{
e502a2af
CD		 748 struct intel_vgpu_ppgtt_spt *spt = page_track->priv_data;
749
2707e444
ZW		 750 int ret;
751
752 if (bytes != 4 && bytes != 8)
753 return -EINVAL;
754
e502a2af 755 ret = ppgtt_handle_guest_write_page_table_bytes(spt, gpa, data, bytes);
2707e444
ZW		 756 if (ret)
757 return ret;
758 return ret;
759}
760
44b46733
CD		 761/* Find a spt by guest gfn. */
762static struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_gfn(
763 struct intel_vgpu *vgpu, unsigned long gfn)
764{
765 struct intel_vgpu_page_track *track;
766
e502a2af
CD		 767 track = intel_vgpu_find_page_track(vgpu, gfn);
768 if (track && track->handler == ppgtt_write_protection_handler)
769 return track->priv_data;
44b46733
CD		 770
771 return NULL;
772}
773
774/* Find the spt by shadow page mfn. */
b6c126a3 775static inline struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_mfn(
44b46733
CD		 776 struct intel_vgpu *vgpu, unsigned long mfn)
777{
b6c126a3 778 return radix_tree_lookup(&vgpu->gtt.spt_tree, mfn);
44b46733
CD		 779}
780
ede9d0cf 781static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt);
2707e444 782
d87f5ff3 783static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt(
40b27176
CD		 784 struct intel_vgpu *vgpu, int type, unsigned long gfn,
785 bool guest_pde_ips)
2707e444 786{
44b46733 787 struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev;
2707e444 788 struct intel_vgpu_ppgtt_spt *spt = NULL;
44b46733 789 dma_addr_t daddr;
e502a2af 790 int ret;
2707e444
ZW		 791
792retry:
793 spt = alloc_spt(GFP_KERNEL | __GFP_ZERO);
794 if (!spt) {
ede9d0cf 795 if (reclaim_one_ppgtt_mm(vgpu->gvt))
2707e444
ZW		 796 goto retry;
797
695fbc08 798 gvt_vgpu_err("fail to allocate ppgtt shadow page\n");
2707e444
ZW		 799 return ERR_PTR(-ENOMEM);
800 }
801
802 spt->vgpu = vgpu;
2707e444
ZW		 803 atomic_set(&spt->refcount, 1);
804 INIT_LIST_HEAD(&spt->post_shadow_list);
805
806 /*
44b46733 807 * Init shadow_page.
2707e444 808 */
44b46733
CD		 809 spt->shadow_page.type = type;
810 daddr = dma_map_page(kdev, spt->shadow_page.page,
811 0, 4096, PCI_DMA_BIDIRECTIONAL);
812 if (dma_mapping_error(kdev, daddr)) {
813 gvt_vgpu_err("fail to map dma addr\n");
b6c126a3
CD		 814 ret = -EINVAL;
815 goto err_free_spt;
2707e444 816 }
44b46733
CD		 817 spt->shadow_page.vaddr = page_address(spt->shadow_page.page);
818 spt->shadow_page.mfn = daddr >> I915_GTT_PAGE_SHIFT;
2707e444 819
44b46733
CD		 820 /*
821 * Init guest_page.
822 */
823 spt->guest_page.type = type;
824 spt->guest_page.gfn = gfn;
40b27176 825 spt->guest_page.pde_ips = guest_pde_ips;
2707e444 826
e502a2af
CD		 827 ret = intel_vgpu_register_page_track(vgpu, spt->guest_page.gfn,
828 ppgtt_write_protection_handler, spt);
b6c126a3
CD		 829 if (ret)
830 goto err_unmap_dma;
2707e444 831
b6c126a3
CD		 832 ret = radix_tree_insert(&vgpu->gtt.spt_tree, spt->shadow_page.mfn, spt);
833 if (ret)
834 goto err_unreg_page_track;
2707e444 835
44b46733
CD		 836 trace_spt_alloc(vgpu->id, spt, type, spt->shadow_page.mfn, gfn);
837 return spt;
b6c126a3
CD		 838
839err_unreg_page_track:
840 intel_vgpu_unregister_page_track(vgpu, spt->guest_page.gfn);
841err_unmap_dma:
842 dma_unmap_page(kdev, daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
843err_free_spt:
844 free_spt(spt);
845 return ERR_PTR(ret);
2707e444
ZW		 846}
847
848#define pt_entry_size_shift(spt) \
849 ((spt)->vgpu->gvt->device_info.gtt_entry_size_shift)
850
851#define pt_entries(spt) \
9556e118 852 (I915_GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
2707e444
ZW		 853
854#define for_each_present_guest_entry(spt, e, i) \
855 for (i = 0; i < pt_entries(spt); i++) \
4b2dbbc2
CD		 856 if (!ppgtt_get_guest_entry(spt, e, i) && \
857 spt->vgpu->gvt->gtt.pte_ops->test_present(e))
2707e444
ZW		 858
859#define for_each_present_shadow_entry(spt, e, i) \
860 for (i = 0; i < pt_entries(spt); i++) \
4b2dbbc2
CD		 861 if (!ppgtt_get_shadow_entry(spt, e, i) && \
862 spt->vgpu->gvt->gtt.pte_ops->test_present(e))
2707e444 863
d87f5ff3 864static void ppgtt_get_spt(struct intel_vgpu_ppgtt_spt *spt)
2707e444
ZW		 865{
866 int v = atomic_read(&spt->refcount);
867
868 trace_spt_refcount(spt->vgpu->id, "inc", spt, v, (v + 1));
869
870 atomic_inc(&spt->refcount);
871}
872
d87f5ff3 873static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt);
2707e444 874
d87f5ff3 875static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
2707e444
ZW		 876 struct intel_gvt_gtt_entry *e)
877{
878 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
879 struct intel_vgpu_ppgtt_spt *s;
3b6411c2 880 intel_gvt_gtt_type_t cur_pt_type;
2707e444 881
72f03d7e 882 GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(e->type)));
2707e444 883
3b6411c2
PG		 884 if (e->type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY
885 && e->type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
886 cur_pt_type = get_next_pt_type(e->type) + 1;
887 if (ops->get_pfn(e) ==
888 vgpu->gtt.scratch_pt[cur_pt_type].page_mfn)
889 return 0;
890 }
44b46733 891 s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
2707e444 892 if (!s) {
695fbc08
TZ		 893 gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n",
894 ops->get_pfn(e));
2707e444
ZW		 895 return -ENXIO;
896 }
d87f5ff3 897 return ppgtt_invalidate_spt(s);
2707e444
ZW		 898}
899
cf4ee73f
CD		 900static inline void ppgtt_invalidate_pte(struct intel_vgpu_ppgtt_spt *spt,
901 struct intel_gvt_gtt_entry *entry)
902{
903 struct intel_vgpu *vgpu = spt->vgpu;
904 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
905 unsigned long pfn;
906 int type;
907
908 pfn = ops->get_pfn(entry);
909 type = spt->shadow_page.type;
910
911 if (pfn == vgpu->gtt.scratch_pt[type].page_mfn)
912 return;
913
914 intel_gvt_hypervisor_dma_unmap_guest_page(vgpu, pfn << PAGE_SHIFT);
915}
916
d87f5ff3 917static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
2707e444 918{
695fbc08 919 struct intel_vgpu *vgpu = spt->vgpu;
2707e444
ZW		 920 struct intel_gvt_gtt_entry e;
921 unsigned long index;
922 int ret;
923 int v = atomic_read(&spt->refcount);
924
925 trace_spt_change(spt->vgpu->id, "die", spt,
44b46733 926 spt->guest_page.gfn, spt->shadow_page.type);
2707e444
ZW		 927
928 trace_spt_refcount(spt->vgpu->id, "dec", spt, v, (v - 1));
929
930 if (atomic_dec_return(&spt->refcount) > 0)
931 return 0;
932
2707e444 933 for_each_present_shadow_entry(spt, &e, index) {
72f03d7e
CD		 934 switch (e.type) {
935 case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
936 gvt_vdbg_mm("invalidate 4K entry\n");
cf4ee73f
CD		 937 ppgtt_invalidate_pte(spt, &e);
938 break;
b294657d 939 case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
72f03d7e
CD		 940 case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
941 case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
b294657d 942 WARN(1, "GVT doesn't support 64K/2M/1GB page\n");
72f03d7e
CD		 943 continue;
944 case GTT_TYPE_PPGTT_PML4_ENTRY:
945 case GTT_TYPE_PPGTT_PDP_ENTRY:
946 case GTT_TYPE_PPGTT_PDE_ENTRY:
947 gvt_vdbg_mm("invalidate PMUL4/PDP/PDE entry\n");
d87f5ff3 948 ret = ppgtt_invalidate_spt_by_shadow_entry(
72f03d7e
CD		 949 spt->vgpu, &e);
950 if (ret)
951 goto fail;
952 break;
953 default:
954 GEM_BUG_ON(1);
2707e444 955 }
2707e444 956 }
cf4ee73f 957
2707e444 958 trace_spt_change(spt->vgpu->id, "release", spt,
44b46733 959 spt->guest_page.gfn, spt->shadow_page.type);
d87f5ff3 960 ppgtt_free_spt(spt);
2707e444
ZW		 961 return 0;
962fail:
695fbc08
TZ		 963 gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
964 spt, e.val64, e.type);
2707e444
ZW		 965 return ret;
966}
967
40b27176
CD		 968static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
969{
970 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
971
972 if (INTEL_GEN(dev_priv) == 9 || INTEL_GEN(dev_priv) == 10) {
973 u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &
974 GAMW_ECO_ENABLE_64K_IPS_FIELD;
975
976 return ips == GAMW_ECO_ENABLE_64K_IPS_FIELD;
977 } else if (INTEL_GEN(dev_priv) >= 11) {
978 /* 64K paging only controlled by IPS bit in PTE now. */
979 return true;
980 } else
981 return false;
982}
983
d87f5ff3 984static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt);
2707e444 985
d87f5ff3 986static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
2707e444
ZW		 987 struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
988{
989 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
44b46733 990 struct intel_vgpu_ppgtt_spt *spt = NULL;
40b27176 991 bool ips = false;
2707e444
ZW		 992 int ret;
993
72f03d7e 994 GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(we->type)));
2707e444 995
44b46733
CD		 996 spt = intel_vgpu_find_spt_by_gfn(vgpu, ops->get_pfn(we));
997 if (spt)
d87f5ff3 998 ppgtt_get_spt(spt);
44b46733 999 else {
2707e444
ZW		 1000 int type = get_next_pt_type(we->type);
1001
40b27176
CD		 1002 if (we->type == GTT_TYPE_PPGTT_PDE_ENTRY)
1003 ips = vgpu_ips_enabled(vgpu) && ops->test_ips(we);
1004
1005 spt = ppgtt_alloc_spt(vgpu, type, ops->get_pfn(we), ips);
44b46733
CD		 1006 if (IS_ERR(spt)) {
1007 ret = PTR_ERR(spt);
2707e444
ZW		 1008 goto fail;
1009 }
1010
e502a2af 1011 ret = intel_vgpu_enable_page_track(vgpu, spt->guest_page.gfn);
2707e444
ZW		 1012 if (ret)
1013 goto fail;
1014
d87f5ff3 1015 ret = ppgtt_populate_spt(spt);
2707e444
ZW		 1016 if (ret)
1017 goto fail;
1018
44b46733
CD		 1019 trace_spt_change(vgpu->id, "new", spt, spt->guest_page.gfn,
1020 spt->shadow_page.type);
2707e444 1021 }
44b46733 1022 return spt;
2707e444 1023fail:
695fbc08 1024 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
44b46733 1025 spt, we->val64, we->type);
2707e444
ZW		 1026 return ERR_PTR(ret);
1027}
1028
1029static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
1030 struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
1031{
1032 struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;
1033
1034 se->type = ge->type;
1035 se->val64 = ge->val64;
1036
1037 ops->set_pfn(se, s->shadow_page.mfn);
1038}
1039
72f03d7e
CD		 1040static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu,
1041 struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
1042 struct intel_gvt_gtt_entry *ge)
1043{
1044 struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
1045 struct intel_gvt_gtt_entry se = *ge;
cf4ee73f
CD		 1046 unsigned long gfn;
1047 dma_addr_t dma_addr;
1048 int ret;
72f03d7e
CD		 1049
1050 if (!pte_ops->test_present(ge))
1051 return 0;
1052
1053 gfn = pte_ops->get_pfn(ge);
1054
1055 switch (ge->type) {
1056 case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
1057 gvt_vdbg_mm("shadow 4K gtt entry\n");
1058 break;
b294657d 1059 case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
72f03d7e
CD		 1060 case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
1061 case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
b294657d 1062 gvt_vgpu_err("GVT doesn't support 64K/2M/1GB entry\n");
72f03d7e
CD		 1063 return -EINVAL;
1064 default:
1065 GEM_BUG_ON(1);
1066 };
1067
1068 /* direct shadow */
cf4ee73f
CD		 1069 ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu, gfn, &dma_addr);
1070 if (ret)
72f03d7e
CD		 1071 return -ENXIO;
1072
cf4ee73f 1073 pte_ops->set_pfn(&se, dma_addr >> PAGE_SHIFT);
72f03d7e
CD		 1074 ppgtt_set_shadow_entry(spt, &se, index);
1075 return 0;
1076}
1077
d87f5ff3 1078static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt)
2707e444
ZW		 1079{
1080 struct intel_vgpu *vgpu = spt->vgpu;
cc753fbe
HY		 1081 struct intel_gvt *gvt = vgpu->gvt;
1082 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
2707e444
ZW		 1083 struct intel_vgpu_ppgtt_spt *s;
1084 struct intel_gvt_gtt_entry se, ge;
cc753fbe 1085 unsigned long gfn, i;
2707e444
ZW		 1086 int ret;
1087
1088 trace_spt_change(spt->vgpu->id, "born", spt,
e502a2af 1089 spt->guest_page.gfn, spt->shadow_page.type);
2707e444 1090
72f03d7e
CD		 1091 for_each_present_guest_entry(spt, &ge, i) {
1092 if (gtt_type_is_pt(get_next_pt_type(ge.type))) {
d87f5ff3 1093 s = ppgtt_populate_spt_by_guest_entry(vgpu, &ge);
72f03d7e
CD		 1094 if (IS_ERR(s)) {
1095 ret = PTR_ERR(s);
1096 goto fail;
1097 }
1098 ppgtt_get_shadow_entry(spt, &se, i);
1099 ppgtt_generate_shadow_entry(&se, s, &ge);
1100 ppgtt_set_shadow_entry(spt, &se, i);
1101 } else {
cc753fbe 1102 gfn = ops->get_pfn(&ge);
72f03d7e 1103 if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
cc753fbe 1104 ops->set_pfn(&se, gvt->gtt.scratch_mfn);
72f03d7e
CD		 1105 ppgtt_set_shadow_entry(spt, &se, i);
1106 continue;
1107 }
2707e444 1108
72f03d7e
CD		 1109 ret = ppgtt_populate_shadow_entry(vgpu, spt, i, &ge);
1110 if (ret)
1111 goto fail;
2707e444 1112 }
2707e444
ZW		 1113 }
1114 return 0;
1115fail:
695fbc08
TZ		 1116 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1117 spt, ge.val64, ge.type);
2707e444
ZW		 1118 return ret;
1119}
1120
44b46733 1121static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_ppgtt_spt *spt,
6b3816d6 1122 struct intel_gvt_gtt_entry *se, unsigned long index)
2707e444 1123{
2707e444
ZW		 1124 struct intel_vgpu *vgpu = spt->vgpu;
1125 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2707e444
ZW		 1126 int ret;
1127
44b46733
CD		 1128 trace_spt_guest_change(spt->vgpu->id, "remove", spt,
1129 spt->shadow_page.type, se->val64, index);
9baf0920 1130
bc37ab56
CD		 1131 gvt_vdbg_mm("destroy old shadow entry, type %d, index %lu, value %llx\n",
1132 se->type, index, se->val64);
1133
6b3816d6 1134 if (!ops->test_present(se))
2707e444
ZW		 1135 return 0;
1136
44b46733
CD		 1137 if (ops->get_pfn(se) ==
1138 vgpu->gtt.scratch_pt[spt->shadow_page.type].page_mfn)
2707e444
ZW		 1139 return 0;
1140
6b3816d6 1141 if (gtt_type_is_pt(get_next_pt_type(se->type))) {
9baf0920 1142 struct intel_vgpu_ppgtt_spt *s =
44b46733 1143 intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(se));
9baf0920 1144 if (!s) {
695fbc08 1145 gvt_vgpu_err("fail to find guest page\n");
2707e444
ZW		 1146 ret = -ENXIO;
1147 goto fail;
1148 }
d87f5ff3 1149 ret = ppgtt_invalidate_spt(s);
2707e444
ZW		 1150 if (ret)
1151 goto fail;
cf4ee73f
CD		 1152 } else
1153 ppgtt_invalidate_pte(spt, se);
1154
2707e444
ZW		 1155 return 0;
1156fail:
695fbc08 1157 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
6b3816d6 1158 spt, se->val64, se->type);
2707e444
ZW		 1159 return ret;
1160}
1161
44b46733 1162static int ppgtt_handle_guest_entry_add(struct intel_vgpu_ppgtt_spt *spt,
2707e444
ZW		 1163 struct intel_gvt_gtt_entry *we, unsigned long index)
1164{
2707e444
ZW		 1165 struct intel_vgpu *vgpu = spt->vgpu;
1166 struct intel_gvt_gtt_entry m;
1167 struct intel_vgpu_ppgtt_spt *s;
1168 int ret;
1169
44b46733
CD		 1170 trace_spt_guest_change(spt->vgpu->id, "add", spt, spt->shadow_page.type,
1171 we->val64, index);
2707e444 1172
bc37ab56
CD		 1173 gvt_vdbg_mm("add shadow entry: type %d, index %lu, value %llx\n",
1174 we->type, index, we->val64);
1175
2707e444 1176 if (gtt_type_is_pt(get_next_pt_type(we->type))) {
d87f5ff3 1177 s = ppgtt_populate_spt_by_guest_entry(vgpu, we);
2707e444
ZW		 1178 if (IS_ERR(s)) {
1179 ret = PTR_ERR(s);
1180 goto fail;
1181 }
1182 ppgtt_get_shadow_entry(spt, &m, index);
1183 ppgtt_generate_shadow_entry(&m, s, we);
1184 ppgtt_set_shadow_entry(spt, &m, index);
1185 } else {
72f03d7e 1186 ret = ppgtt_populate_shadow_entry(vgpu, spt, index, we);
2707e444
ZW		 1187 if (ret)
1188 goto fail;
2707e444
ZW		 1189 }
1190 return 0;
1191fail:
695fbc08
TZ		 1192 gvt_vgpu_err("fail: spt %p guest entry 0x%llx type %d\n",
1193 spt, we->val64, we->type);
2707e444
ZW		 1194 return ret;
1195}
1196
1197static int sync_oos_page(struct intel_vgpu *vgpu,
1198 struct intel_vgpu_oos_page *oos_page)
1199{
1200 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1201 struct intel_gvt *gvt = vgpu->gvt;
1202 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
44b46733 1203 struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
72f03d7e 1204 struct intel_gvt_gtt_entry old, new;
2707e444
ZW		 1205 int index;
1206 int ret;
1207
1208 trace_oos_change(vgpu->id, "sync", oos_page->id,
44b46733 1209 spt, spt->guest_page.type);
2707e444 1210
44b46733 1211 old.type = new.type = get_entry_type(spt->guest_page.type);
2707e444
ZW		 1212 old.val64 = new.val64 = 0;
1213
9556e118
ZW		 1214 for (index = 0; index < (I915_GTT_PAGE_SIZE >>
1215 info->gtt_entry_size_shift); index++) {
2707e444
ZW		 1216 ops->get_entry(oos_page->mem, &old, index, false, 0, vgpu);
1217 ops->get_entry(NULL, &new, index, true,
44b46733 1218 spt->guest_page.gfn << PAGE_SHIFT, vgpu);
2707e444
ZW		 1219
1220 if (old.val64 == new.val64
1221 && !test_and_clear_bit(index, spt->post_shadow_bitmap))
1222 continue;
1223
1224 trace_oos_sync(vgpu->id, oos_page->id,
44b46733 1225 spt, spt->guest_page.type,
2707e444
ZW		 1226 new.val64, index);
1227
72f03d7e 1228 ret = ppgtt_populate_shadow_entry(vgpu, spt, index, &new);
2707e444
ZW		 1229 if (ret)
1230 return ret;
1231
1232 ops->set_entry(oos_page->mem, &new, index, false, 0, vgpu);
2707e444
ZW		 1233 }
1234
44b46733 1235 spt->guest_page.write_cnt = 0;
2707e444
ZW		 1236 list_del_init(&spt->post_shadow_list);
1237 return 0;
1238}
1239
1240static int detach_oos_page(struct intel_vgpu *vgpu,
1241 struct intel_vgpu_oos_page *oos_page)
1242{
1243 struct intel_gvt *gvt = vgpu->gvt;
44b46733 1244 struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
2707e444
ZW		 1245
1246 trace_oos_change(vgpu->id, "detach", oos_page->id,
44b46733 1247 spt, spt->guest_page.type);
2707e444 1248
44b46733
CD		 1249 spt->guest_page.write_cnt = 0;
1250 spt->guest_page.oos_page = NULL;
1251 oos_page->spt = NULL;
2707e444
ZW		 1252
1253 list_del_init(&oos_page->vm_list);
1254 list_move_tail(&oos_page->list, &gvt->gtt.oos_page_free_list_head);
1255
1256 return 0;
1257}
1258
44b46733
CD		 1259static int attach_oos_page(struct intel_vgpu_oos_page *oos_page,
1260 struct intel_vgpu_ppgtt_spt *spt)
2707e444 1261{
44b46733 1262 struct intel_gvt *gvt = spt->vgpu->gvt;
2707e444
ZW		 1263 int ret;
1264
44b46733
CD		 1265 ret = intel_gvt_hypervisor_read_gpa(spt->vgpu,
1266 spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
9556e118 1267 oos_page->mem, I915_GTT_PAGE_SIZE);
2707e444
ZW		 1268 if (ret)
1269 return ret;
1270
44b46733
CD		 1271 oos_page->spt = spt;
1272 spt->guest_page.oos_page = oos_page;
2707e444
ZW		 1273
1274 list_move_tail(&oos_page->list, &gvt->gtt.oos_page_use_list_head);
1275
44b46733
CD		 1276 trace_oos_change(spt->vgpu->id, "attach", oos_page->id,
1277 spt, spt->guest_page.type);
2707e444
ZW		 1278 return 0;
1279}
1280
44b46733 1281static int ppgtt_set_guest_page_sync(struct intel_vgpu_ppgtt_spt *spt)
2707e444 1282{
44b46733 1283 struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
2707e444
ZW		 1284 int ret;
1285
e502a2af 1286 ret = intel_vgpu_enable_page_track(spt->vgpu, spt->guest_page.gfn);
2707e444
ZW		 1287 if (ret)
1288 return ret;
1289
44b46733
CD		 1290 trace_oos_change(spt->vgpu->id, "set page sync", oos_page->id,
1291 spt, spt->guest_page.type);
2707e444 1292
44b46733
CD		 1293 list_del_init(&oos_page->vm_list);
1294 return sync_oos_page(spt->vgpu, oos_page);
2707e444
ZW		 1295}
1296
44b46733 1297static int ppgtt_allocate_oos_page(struct intel_vgpu_ppgtt_spt *spt)
2707e444 1298{
44b46733 1299 struct intel_gvt *gvt = spt->vgpu->gvt;
2707e444 1300 struct intel_gvt_gtt *gtt = &gvt->gtt;
44b46733 1301 struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
2707e444
ZW		 1302 int ret;
1303
1304 WARN(oos_page, "shadow PPGTT page has already has a oos page\n");
1305
1306 if (list_empty(&gtt->oos_page_free_list_head)) {
1307 oos_page = container_of(gtt->oos_page_use_list_head.next,
1308 struct intel_vgpu_oos_page, list);
44b46733 1309 ret = ppgtt_set_guest_page_sync(oos_page->spt);
2707e444
ZW		 1310 if (ret)
1311 return ret;
44b46733 1312 ret = detach_oos_page(spt->vgpu, oos_page);
2707e444
ZW		 1313 if (ret)
1314 return ret;
1315 } else
1316 oos_page = container_of(gtt->oos_page_free_list_head.next,
1317 struct intel_vgpu_oos_page, list);
44b46733 1318 return attach_oos_page(oos_page, spt);
2707e444
ZW		 1319}
1320
44b46733 1321static int ppgtt_set_guest_page_oos(struct intel_vgpu_ppgtt_spt *spt)
2707e444 1322{
44b46733 1323 struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
2707e444
ZW		 1324
1325 if (WARN(!oos_page, "shadow PPGTT page should have a oos page\n"))
1326 return -EINVAL;
1327
44b46733
CD		 1328 trace_oos_change(spt->vgpu->id, "set page out of sync", oos_page->id,
1329 spt, spt->guest_page.type);
2707e444 1330
44b46733 1331 list_add_tail(&oos_page->vm_list, &spt->vgpu->gtt.oos_page_list_head);
e502a2af 1332 return intel_vgpu_disable_page_track(spt->vgpu, spt->guest_page.gfn);
2707e444
ZW		 1333}
1334
1335/**
1336 * intel_vgpu_sync_oos_pages - sync all the out-of-synced shadow for vGPU
1337 * @vgpu: a vGPU
1338 *
1339 * This function is called before submitting a guest workload to host,
1340 * to sync all the out-of-synced shadow for vGPU
1341 *
1342 * Returns:
1343 * Zero on success, negative error code if failed.
1344 */
1345int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu)
1346{
1347 struct list_head *pos, *n;
1348 struct intel_vgpu_oos_page *oos_page;
1349 int ret;
1350
1351 if (!enable_out_of_sync)
1352 return 0;
1353
1354 list_for_each_safe(pos, n, &vgpu->gtt.oos_page_list_head) {
1355 oos_page = container_of(pos,
1356 struct intel_vgpu_oos_page, vm_list);
44b46733 1357 ret = ppgtt_set_guest_page_sync(oos_page->spt);
2707e444
ZW		 1358 if (ret)
1359 return ret;
1360 }
1361 return 0;
1362}
1363
1364/*
1365 * The heart of PPGTT shadow page table.
1366 */
1367static int ppgtt_handle_guest_write_page_table(
44b46733 1368 struct intel_vgpu_ppgtt_spt *spt,
2707e444
ZW		 1369 struct intel_gvt_gtt_entry *we, unsigned long index)
1370{
2707e444 1371 struct intel_vgpu *vgpu = spt->vgpu;
6b3816d6 1372 int type = spt->shadow_page.type;
2707e444 1373 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
72f03d7e 1374 struct intel_gvt_gtt_entry old_se;
9baf0920 1375 int new_present;
72f03d7e 1376 int ret;
2707e444 1377
2707e444
ZW		 1378 new_present = ops->test_present(we);
1379
6b3816d6
TZ		 1380 /*
1381 * Adding the new entry first and then removing the old one, that can
1382 * guarantee the ppgtt table is validated during the window between
1383 * adding and removal.
1384 */
72f03d7e 1385 ppgtt_get_shadow_entry(spt, &old_se, index);
2707e444 1386
2707e444 1387 if (new_present) {
44b46733 1388 ret = ppgtt_handle_guest_entry_add(spt, we, index);
2707e444
ZW		 1389 if (ret)
1390 goto fail;
1391 }
6b3816d6 1392
44b46733 1393 ret = ppgtt_handle_guest_entry_removal(spt, &old_se, index);
6b3816d6
TZ		 1394 if (ret)
1395 goto fail;
1396
1397 if (!new_present) {
72f03d7e
CD		 1398 ops->set_pfn(&old_se, vgpu->gtt.scratch_pt[type].page_mfn);
1399 ppgtt_set_shadow_entry(spt, &old_se, index);
6b3816d6
TZ		 1400 }
1401
2707e444
ZW		 1402 return 0;
1403fail:
695fbc08
TZ		 1404 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d.\n",
1405 spt, we->val64, we->type);
2707e444
ZW		 1406 return ret;
1407}
1408
72f03d7e
CD		 1409
1410
44b46733 1411static inline bool can_do_out_of_sync(struct intel_vgpu_ppgtt_spt *spt)
2707e444
ZW		 1412{
1413 return enable_out_of_sync
44b46733
CD		 1414 && gtt_type_is_pte_pt(spt->guest_page.type)
1415 && spt->guest_page.write_cnt >= 2;
2707e444
ZW		 1416}
1417
1418static void ppgtt_set_post_shadow(struct intel_vgpu_ppgtt_spt *spt,
1419 unsigned long index)
1420{
1421 set_bit(index, spt->post_shadow_bitmap);
1422 if (!list_empty(&spt->post_shadow_list))
1423 return;
1424
1425 list_add_tail(&spt->post_shadow_list,
1426 &spt->vgpu->gtt.post_shadow_list_head);
1427}
1428
1429/**
1430 * intel_vgpu_flush_post_shadow - flush the post shadow transactions
1431 * @vgpu: a vGPU
1432 *
1433 * This function is called before submitting a guest workload to host,
1434 * to flush all the post shadows for a vGPU.
1435 *
1436 * Returns:
1437 * Zero on success, negative error code if failed.
1438 */
1439int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu)
1440{
1441 struct list_head *pos, *n;
1442 struct intel_vgpu_ppgtt_spt *spt;
9baf0920 1443 struct intel_gvt_gtt_entry ge;
2707e444
ZW		 1444 unsigned long index;
1445 int ret;
1446
1447 list_for_each_safe(pos, n, &vgpu->gtt.post_shadow_list_head) {
1448 spt = container_of(pos, struct intel_vgpu_ppgtt_spt,
1449 post_shadow_list);
1450
1451 for_each_set_bit(index, spt->post_shadow_bitmap,
1452 GTT_ENTRY_NUM_IN_ONE_PAGE) {
1453 ppgtt_get_guest_entry(spt, &ge, index);
2707e444 1454
44b46733
CD		 1455 ret = ppgtt_handle_guest_write_page_table(spt,
1456 &ge, index);
2707e444
ZW		 1457 if (ret)
1458 return ret;
1459 clear_bit(index, spt->post_shadow_bitmap);
1460 }
1461 list_del_init(&spt->post_shadow_list);
1462 }
1463 return 0;
1464}
1465
7d1e5cdf 1466static int ppgtt_handle_guest_write_page_table_bytes(
44b46733 1467 struct intel_vgpu_ppgtt_spt *spt,
2707e444
ZW		 1468 u64 pa, void *p_data, int bytes)
1469{
2707e444
ZW		 1470 struct intel_vgpu *vgpu = spt->vgpu;
1471 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1472 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
6b3816d6 1473 struct intel_gvt_gtt_entry we, se;
2707e444
ZW		 1474 unsigned long index;
1475 int ret;
1476
1477 index = (pa & (PAGE_SIZE - 1)) >> info->gtt_entry_size_shift;
1478
1479 ppgtt_get_guest_entry(spt, &we, index);
2707e444 1480
2707e444 1481 if (bytes == info->gtt_entry_size) {
44b46733 1482 ret = ppgtt_handle_guest_write_page_table(spt, &we, index);
2707e444
ZW		 1483 if (ret)
1484 return ret;
1485 } else {
2707e444 1486 if (!test_bit(index, spt->post_shadow_bitmap)) {
121d760d
ZW		 1487 int type = spt->shadow_page.type;
1488
6b3816d6 1489 ppgtt_get_shadow_entry(spt, &se, index);
44b46733 1490 ret = ppgtt_handle_guest_entry_removal(spt, &se, index);
2707e444
ZW		 1491 if (ret)
1492 return ret;
121d760d
ZW		 1493 ops->set_pfn(&se, vgpu->gtt.scratch_pt[type].page_mfn);
1494 ppgtt_set_shadow_entry(spt, &se, index);
2707e444 1495 }
2707e444 1496 ppgtt_set_post_shadow(spt, index);
2707e444
ZW		 1497 }
1498
1499 if (!enable_out_of_sync)
1500 return 0;
1501
44b46733 1502 spt->guest_page.write_cnt++;
2707e444 1503
44b46733
CD		 1504 if (spt->guest_page.oos_page)
1505 ops->set_entry(spt->guest_page.oos_page->mem, &we, index,
2707e444
ZW		 1506 false, 0, vgpu);
1507
44b46733
CD		 1508 if (can_do_out_of_sync(spt)) {
1509 if (!spt->guest_page.oos_page)
1510 ppgtt_allocate_oos_page(spt);
2707e444 1511
44b46733 1512 ret = ppgtt_set_guest_page_oos(spt);
2707e444
ZW		 1513 if (ret < 0)
1514 return ret;
1515 }
1516 return 0;
1517}
1518
ede9d0cf 1519static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
2707e444
ZW		 1520{
1521 struct intel_vgpu *vgpu = mm->vgpu;
1522 struct intel_gvt *gvt = vgpu->gvt;
1523 struct intel_gvt_gtt *gtt = &gvt->gtt;
1524 struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1525 struct intel_gvt_gtt_entry se;
ede9d0cf 1526 int index;
2707e444 1527
ede9d0cf 1528 if (!mm->ppgtt_mm.shadowed)
2707e444
ZW		 1529 return;
1530
ede9d0cf
CD		 1531 for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.shadow_pdps); index++) {
1532 ppgtt_get_shadow_root_entry(mm, &se, index);
1533
2707e444
ZW		 1534 if (!ops->test_present(&se))
1535 continue;
ede9d0cf 1536
d87f5ff3 1537 ppgtt_invalidate_spt_by_shadow_entry(vgpu, &se);
2707e444 1538 se.val64 = 0;
ede9d0cf 1539 ppgtt_set_shadow_root_entry(mm, &se, index);
2707e444 1540
44b46733
CD		 1541 trace_spt_guest_change(vgpu->id, "destroy root pointer",
1542 NULL, se.type, se.val64, index);
2707e444 1543 }
2707e444 1544
ede9d0cf 1545 mm->ppgtt_mm.shadowed = false;
2707e444
ZW		 1546}
1547
ede9d0cf
CD		 1548
1549static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
2707e444
ZW		 1550{
1551 struct intel_vgpu *vgpu = mm->vgpu;
1552 struct intel_gvt *gvt = vgpu->gvt;
1553 struct intel_gvt_gtt *gtt = &gvt->gtt;
1554 struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1555 struct intel_vgpu_ppgtt_spt *spt;
1556 struct intel_gvt_gtt_entry ge, se;
ede9d0cf 1557 int index, ret;
2707e444 1558
ede9d0cf 1559 if (mm->ppgtt_mm.shadowed)
2707e444
ZW		 1560 return 0;
1561
ede9d0cf
CD		 1562 mm->ppgtt_mm.shadowed = true;
1563
1564 for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.guest_pdps); index++) {
1565 ppgtt_get_guest_root_entry(mm, &ge, index);
2707e444 1566
2707e444
ZW		 1567 if (!ops->test_present(&ge))
1568 continue;
1569
44b46733
CD		 1570 trace_spt_guest_change(vgpu->id, __func__, NULL,
1571 ge.type, ge.val64, index);
2707e444 1572
d87f5ff3 1573 spt = ppgtt_populate_spt_by_guest_entry(vgpu, &ge);
2707e444 1574 if (IS_ERR(spt)) {
695fbc08 1575 gvt_vgpu_err("fail to populate guest root pointer\n");
2707e444
ZW		 1576 ret = PTR_ERR(spt);
1577 goto fail;
1578 }
1579 ppgtt_generate_shadow_entry(&se, spt, &ge);
ede9d0cf 1580 ppgtt_set_shadow_root_entry(mm, &se, index);
2707e444 1581
44b46733
CD		 1582 trace_spt_guest_change(vgpu->id, "populate root pointer",
1583 NULL, se.type, se.val64, index);
2707e444 1584 }
ede9d0cf 1585
2707e444
ZW		 1586 return 0;
1587fail:
ede9d0cf 1588 invalidate_ppgtt_mm(mm);
2707e444
ZW		 1589 return ret;
1590}
1591
ede9d0cf
CD		 1592static struct intel_vgpu_mm *vgpu_alloc_mm(struct intel_vgpu *vgpu)
1593{
1594 struct intel_vgpu_mm *mm;
1595
1596 mm = kzalloc(sizeof(*mm), GFP_KERNEL);
1597 if (!mm)
1598 return NULL;
1599
1600 mm->vgpu = vgpu;
1601 kref_init(&mm->ref);
1602 atomic_set(&mm->pincount, 0);
1603
1604 return mm;
1605}
1606
1607static void vgpu_free_mm(struct intel_vgpu_mm *mm)
1608{
1609 kfree(mm);
1610}
1611
2707e444 1612/**
ede9d0cf 1613 * intel_vgpu_create_ppgtt_mm - create a ppgtt mm object for a vGPU
2707e444 1614 * @vgpu: a vGPU
ede9d0cf
CD		 1615 * @root_entry_type: ppgtt root entry type
1616 * @pdps: guest pdps.
2707e444 1617 *
ede9d0cf 1618 * This function is used to create a ppgtt mm object for a vGPU.
2707e444
ZW		 1619 *
1620 * Returns:
1621 * Zero on success, negative error code in pointer if failed.
1622 */
ede9d0cf
CD		 1623struct intel_vgpu_mm *intel_vgpu_create_ppgtt_mm(struct intel_vgpu *vgpu,
1624 intel_gvt_gtt_type_t root_entry_type, u64 pdps[])
2707e444
ZW		 1625{
1626 struct intel_gvt *gvt = vgpu->gvt;
2707e444
ZW		 1627 struct intel_vgpu_mm *mm;
1628 int ret;
1629
ede9d0cf
CD		 1630 mm = vgpu_alloc_mm(vgpu);
1631 if (!mm)
1632 return ERR_PTR(-ENOMEM);
2707e444 1633
ede9d0cf 1634 mm->type = INTEL_GVT_MM_PPGTT;
2707e444 1635
ede9d0cf
CD		 1636 GEM_BUG_ON(root_entry_type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY &&
1637 root_entry_type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY);
1638 mm->ppgtt_mm.root_entry_type = root_entry_type;
2707e444 1639
ede9d0cf
CD		 1640 INIT_LIST_HEAD(&mm->ppgtt_mm.list);
1641 INIT_LIST_HEAD(&mm->ppgtt_mm.lru_list);
2707e444 1642
ede9d0cf
CD		 1643 if (root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
1644 mm->ppgtt_mm.guest_pdps[0] = pdps[0];
1645 else
1646 memcpy(mm->ppgtt_mm.guest_pdps, pdps,
1647 sizeof(mm->ppgtt_mm.guest_pdps));
2707e444 1648
ede9d0cf 1649 ret = shadow_ppgtt_mm(mm);
2707e444 1650 if (ret) {
ede9d0cf
CD		 1651 gvt_vgpu_err("failed to shadow ppgtt mm\n");
1652 vgpu_free_mm(mm);
1653 return ERR_PTR(ret);
2707e444
ZW		 1654 }
1655
ede9d0cf
CD		 1656 list_add_tail(&mm->ppgtt_mm.list, &vgpu->gtt.ppgtt_mm_list_head);
1657 list_add_tail(&mm->ppgtt_mm.lru_list, &gvt->gtt.ppgtt_mm_lru_list_head);
1658 return mm;
1659}
2707e444 1660
ede9d0cf
CD		 1661static struct intel_vgpu_mm *intel_vgpu_create_ggtt_mm(struct intel_vgpu *vgpu)
1662{
1663 struct intel_vgpu_mm *mm;
1664 unsigned long nr_entries;
2707e444 1665
ede9d0cf
CD		 1666 mm = vgpu_alloc_mm(vgpu);
1667 if (!mm)
1668 return ERR_PTR(-ENOMEM);
1669
1670 mm->type = INTEL_GVT_MM_GGTT;
1671
1672 nr_entries = gvt_ggtt_gm_sz(vgpu->gvt) >> I915_GTT_PAGE_SHIFT;
1673 mm->ggtt_mm.virtual_ggtt = vzalloc(nr_entries *
1674 vgpu->gvt->device_info.gtt_entry_size);
1675 if (!mm->ggtt_mm.virtual_ggtt) {
1676 vgpu_free_mm(mm);
1677 return ERR_PTR(-ENOMEM);
2707e444 1678 }
ede9d0cf 1679
2707e444 1680 return mm;
ede9d0cf
CD		 1681}
1682
1683/**
1bc25851 1684 * _intel_vgpu_mm_release - destroy a mm object
ede9d0cf
CD		 1685 * @mm_ref: a kref object
1686 *
1687 * This function is used to destroy a mm object for vGPU
1688 *
1689 */
1bc25851 1690void _intel_vgpu_mm_release(struct kref *mm_ref)
ede9d0cf
CD		 1691{
1692 struct intel_vgpu_mm *mm = container_of(mm_ref, typeof(*mm), ref);
1693
1694 if (GEM_WARN_ON(atomic_read(&mm->pincount)))
1695 gvt_err("vgpu mm pin count bug detected\n");
1696
1697 if (mm->type == INTEL_GVT_MM_PPGTT) {
1698 list_del(&mm->ppgtt_mm.list);
1699 list_del(&mm->ppgtt_mm.lru_list);
1700 invalidate_ppgtt_mm(mm);
1701 } else {
1702 vfree(mm->ggtt_mm.virtual_ggtt);
1703 }
1704
1705 vgpu_free_mm(mm);
2707e444
ZW		 1706}
1707
1708/**
1709 * intel_vgpu_unpin_mm - decrease the pin count of a vGPU mm object
1710 * @mm: a vGPU mm object
1711 *
1712 * This function is called when user doesn't want to use a vGPU mm object
1713 */
1714void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm)
1715{
2707e444
ZW		 1716 atomic_dec(&mm->pincount);
1717}
1718
1719/**
1720 * intel_vgpu_pin_mm - increase the pin count of a vGPU mm object
1721 * @vgpu: a vGPU
1722 *
1723 * This function is called when user wants to use a vGPU mm object. If this
1724 * mm object hasn't been shadowed yet, the shadow will be populated at this
1725 * time.
1726 *
1727 * Returns:
1728 * Zero on success, negative error code if failed.
1729 */
1730int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm)
1731{
1732 int ret;
1733
ede9d0cf 1734 atomic_inc(&mm->pincount);
2707e444 1735
ede9d0cf
CD		 1736 if (mm->type == INTEL_GVT_MM_PPGTT) {
1737 ret = shadow_ppgtt_mm(mm);
2707e444
ZW		 1738 if (ret)
1739 return ret;
ede9d0cf
CD		 1740
1741 list_move_tail(&mm->ppgtt_mm.lru_list,
1742 &mm->vgpu->gvt->gtt.ppgtt_mm_lru_list_head);
1743
2707e444
ZW		 1744 }
1745
2707e444
ZW		 1746 return 0;
1747}
1748
ede9d0cf 1749static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt)
2707e444
ZW		 1750{
1751 struct intel_vgpu_mm *mm;
1752 struct list_head *pos, *n;
1753
ede9d0cf
CD		 1754 list_for_each_safe(pos, n, &gvt->gtt.ppgtt_mm_lru_list_head) {
1755 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.lru_list);
2707e444 1756
2707e444
ZW		 1757 if (atomic_read(&mm->pincount))
1758 continue;
1759
ede9d0cf
CD		 1760 list_del_init(&mm->ppgtt_mm.lru_list);
1761 invalidate_ppgtt_mm(mm);
2707e444
ZW		 1762 return 1;
1763 }
1764 return 0;
1765}
1766
1767/*
1768 * GMA translation APIs.
1769 */
1770static inline int ppgtt_get_next_level_entry(struct intel_vgpu_mm *mm,
1771 struct intel_gvt_gtt_entry *e, unsigned long index, bool guest)
1772{
1773 struct intel_vgpu *vgpu = mm->vgpu;
1774 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1775 struct intel_vgpu_ppgtt_spt *s;
1776
44b46733 1777 s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
2707e444
ZW		 1778 if (!s)
1779 return -ENXIO;
1780
1781 if (!guest)
1782 ppgtt_get_shadow_entry(s, e, index);
1783 else
1784 ppgtt_get_guest_entry(s, e, index);
1785 return 0;
1786}
1787
1788/**
1789 * intel_vgpu_gma_to_gpa - translate a gma to GPA
1790 * @mm: mm object. could be a PPGTT or GGTT mm object
1791 * @gma: graphics memory address in this mm object
1792 *
1793 * This function is used to translate a graphics memory address in specific
1794 * graphics memory space to guest physical address.
1795 *
1796 * Returns:
1797 * Guest physical address on success, INTEL_GVT_INVALID_ADDR if failed.
1798 */
1799unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma)
1800{
1801 struct intel_vgpu *vgpu = mm->vgpu;
1802 struct intel_gvt *gvt = vgpu->gvt;
1803 struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
1804 struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
1805 unsigned long gpa = INTEL_GVT_INVALID_ADDR;
1806 unsigned long gma_index[4];
1807 struct intel_gvt_gtt_entry e;
ede9d0cf 1808 int i, levels = 0;
2707e444
ZW		 1809 int ret;
1810
ede9d0cf
CD		 1811 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT &&
1812 mm->type != INTEL_GVT_MM_PPGTT);
2707e444
ZW		 1813
1814 if (mm->type == INTEL_GVT_MM_GGTT) {
1815 if (!vgpu_gmadr_is_valid(vgpu, gma))
1816 goto err;
1817
ede9d0cf
CD		 1818 ggtt_get_guest_entry(mm, &e,
1819 gma_ops->gma_to_ggtt_pte_index(gma));
1820
9556e118
ZW		 1821 gpa = (pte_ops->get_pfn(&e) << I915_GTT_PAGE_SHIFT)
1822 + (gma & ~I915_GTT_PAGE_MASK);
2707e444
ZW		 1823
1824 trace_gma_translate(vgpu->id, "ggtt", 0, 0, gma, gpa);
ede9d0cf
CD		 1825 } else {
1826 switch (mm->ppgtt_mm.root_entry_type) {
1827 case GTT_TYPE_PPGTT_ROOT_L4_ENTRY:
1828 ppgtt_get_shadow_root_entry(mm, &e, 0);
1829
1830 gma_index[0] = gma_ops->gma_to_pml4_index(gma);
1831 gma_index[1] = gma_ops->gma_to_l4_pdp_index(gma);
1832 gma_index[2] = gma_ops->gma_to_pde_index(gma);
1833 gma_index[3] = gma_ops->gma_to_pte_index(gma);
1834 levels = 4;
1835 break;
1836 case GTT_TYPE_PPGTT_ROOT_L3_ENTRY:
1837 ppgtt_get_shadow_root_entry(mm, &e,
1838 gma_ops->gma_to_l3_pdp_index(gma));
1839
1840 gma_index[0] = gma_ops->gma_to_pde_index(gma);
1841 gma_index[1] = gma_ops->gma_to_pte_index(gma);
1842 levels = 2;
1843 break;
1844 default:
1845 GEM_BUG_ON(1);
1846 }
2707e444 1847
ede9d0cf
CD		 1848 /* walk the shadow page table and get gpa from guest entry */
1849 for (i = 0; i < levels; i++) {
1850 ret = ppgtt_get_next_level_entry(mm, &e, gma_index[i],
1851 (i == levels - 1));
1852 if (ret)
1853 goto err;
4b2dbbc2 1854
ede9d0cf
CD		 1855 if (!pte_ops->test_present(&e)) {
1856 gvt_dbg_core("GMA 0x%lx is not present\n", gma);
1857 goto err;
1858 }
4b2dbbc2 1859 }
2707e444 1860
ede9d0cf
CD		 1861 gpa = (pte_ops->get_pfn(&e) << I915_GTT_PAGE_SHIFT) +
1862 (gma & ~I915_GTT_PAGE_MASK);
1863 trace_gma_translate(vgpu->id, "ppgtt", 0,
1864 mm->ppgtt_mm.root_entry_type, gma, gpa);
1865 }
2707e444 1866
2707e444
ZW		 1867 return gpa;
1868err:
695fbc08 1869 gvt_vgpu_err("invalid mm type: %d gma %lx\n", mm->type, gma);
2707e444
ZW		 1870 return INTEL_GVT_INVALID_ADDR;
1871}
1872
a143cef7 1873static int emulate_ggtt_mmio_read(struct intel_vgpu *vgpu,
2707e444
ZW		 1874 unsigned int off, void *p_data, unsigned int bytes)
1875{
1876 struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
1877 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1878 unsigned long index = off >> info->gtt_entry_size_shift;
1879 struct intel_gvt_gtt_entry e;
1880
1881 if (bytes != 4 && bytes != 8)
1882 return -EINVAL;
1883
1884 ggtt_get_guest_entry(ggtt_mm, &e, index);
1885 memcpy(p_data, (void *)&e.val64 + (off & (info->gtt_entry_size - 1)),
1886 bytes);
1887 return 0;
1888}
1889
1890/**
1891 * intel_vgpu_emulate_gtt_mmio_read - emulate GTT MMIO register read
1892 * @vgpu: a vGPU
1893 * @off: register offset
1894 * @p_data: data will be returned to guest
1895 * @bytes: data length
1896 *
1897 * This function is used to emulate the GTT MMIO register read
1898 *
1899 * Returns:
1900 * Zero on success, error code if failed.
1901 */
a143cef7 1902int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
2707e444
ZW		 1903 void *p_data, unsigned int bytes)
1904{
1905 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1906 int ret;
1907
1908 if (bytes != 4 && bytes != 8)
1909 return -EINVAL;
1910
1911 off -= info->gtt_start_offset;
a143cef7 1912 ret = emulate_ggtt_mmio_read(vgpu, off, p_data, bytes);
2707e444
ZW		 1913 return ret;
1914}
1915
7598e870
CD		 1916static void ggtt_invalidate_pte(struct intel_vgpu *vgpu,
1917 struct intel_gvt_gtt_entry *entry)
1918{
1919 struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
1920 unsigned long pfn;
1921
1922 pfn = pte_ops->get_pfn(entry);
1923 if (pfn != vgpu->gvt->gtt.scratch_mfn)
1924 intel_gvt_hypervisor_dma_unmap_guest_page(vgpu,
1925 pfn << PAGE_SHIFT);
1926}
1927
a143cef7 1928static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
2707e444
ZW		 1929 void *p_data, unsigned int bytes)
1930{
1931 struct intel_gvt *gvt = vgpu->gvt;
1932 const struct intel_gvt_device_info *info = &gvt->device_info;
1933 struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
1934 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1935 unsigned long g_gtt_index = off >> info->gtt_entry_size_shift;
cf4ee73f 1936 unsigned long gma, gfn;
2707e444 1937 struct intel_gvt_gtt_entry e, m;
cf4ee73f
CD		 1938 dma_addr_t dma_addr;
1939 int ret;
2707e444
ZW		 1940
1941 if (bytes != 4 && bytes != 8)
1942 return -EINVAL;
1943
9556e118 1944 gma = g_gtt_index << I915_GTT_PAGE_SHIFT;
2707e444
ZW		 1945
1946 /* the VM may configure the whole GM space when ballooning is used */
7c28135c 1947 if (!vgpu_gmadr_is_valid(vgpu, gma))
2707e444 1948 return 0;
2707e444
ZW		 1949
1950 ggtt_get_guest_entry(ggtt_mm, &e, g_gtt_index);
1951
1952 memcpy((void *)&e.val64 + (off & (info->gtt_entry_size - 1)), p_data,
1953 bytes);
1954
1955 if (ops->test_present(&e)) {
cc753fbe 1956 gfn = ops->get_pfn(&e);
7598e870 1957 m = e;
cc753fbe
HY		 1958
1959 /* one PTE update may be issued in multiple writes and the
1960 * first write may not construct a valid gfn
1961 */
1962 if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
1963 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
1964 goto out;
1965 }
1966
cf4ee73f
CD		 1967 ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu, gfn,
1968 &dma_addr);
1969 if (ret) {
72f03d7e 1970 gvt_vgpu_err("fail to populate guest ggtt entry\n");
359b6931
XC		 1971 /* guest driver may read/write the entry when partial
1972 * update the entry in this situation p2m will fail
1973 * settting the shadow entry to point to a scratch page
1974 */
22115cef 1975 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
72f03d7e 1976 } else
cf4ee73f 1977 ops->set_pfn(&m, dma_addr >> PAGE_SHIFT);
7598e870
CD		 1978 } else {
1979 ggtt_get_host_entry(ggtt_mm, &m, g_gtt_index);
1980 ggtt_invalidate_pte(vgpu, &m);
22115cef 1981 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
7598e870
CD		 1982 ops->clear_present(&m);
1983 }
2707e444 1984
cc753fbe 1985out:
3aff3512 1986 ggtt_set_host_entry(ggtt_mm, &m, g_gtt_index);
a143cef7 1987 ggtt_invalidate(gvt->dev_priv);
2707e444
ZW		 1988 ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
1989 return 0;
1990}
1991
1992/*
a143cef7 1993 * intel_vgpu_emulate_ggtt_mmio_write - emulate GTT MMIO register write
2707e444
ZW		 1994 * @vgpu: a vGPU
1995 * @off: register offset
1996 * @p_data: data from guest write
1997 * @bytes: data length
1998 *
1999 * This function is used to emulate the GTT MMIO register write
2000 *
2001 * Returns:
2002 * Zero on success, error code if failed.
2003 */
a143cef7
CD		 2004int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
2005 unsigned int off, void *p_data, unsigned int bytes)
2707e444
ZW		 2006{
2007 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2008 int ret;
2009
2010 if (bytes != 4 && bytes != 8)
2011 return -EINVAL;
2012
2013 off -= info->gtt_start_offset;
a143cef7 2014 ret = emulate_ggtt_mmio_write(vgpu, off, p_data, bytes);
2707e444
ZW		 2015 return ret;
2016}
2017
3b6411c2
PG		 2018static int alloc_scratch_pages(struct intel_vgpu *vgpu,
2019 intel_gvt_gtt_type_t type)
2707e444
ZW		 2020{
2021 struct intel_vgpu_gtt *gtt = &vgpu->gtt;
3b6411c2 2022 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
5c35258d 2023 int page_entry_num = I915_GTT_PAGE_SIZE >>
3b6411c2 2024 vgpu->gvt->device_info.gtt_entry_size_shift;
9631739f 2025 void *scratch_pt;
3b6411c2 2026 int i;
5de6bd4c
CD		 2027 struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
2028 dma_addr_t daddr;
2707e444 2029
3b6411c2
PG		 2030 if (WARN_ON(type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX))
2031 return -EINVAL;
2032
9631739f 2033 scratch_pt = (void *)get_zeroed_page(GFP_KERNEL);
3b6411c2 2034 if (!scratch_pt) {
695fbc08 2035 gvt_vgpu_err("fail to allocate scratch page\n");
2707e444
ZW		 2036 return -ENOMEM;
2037 }
2038
5de6bd4c
CD		 2039 daddr = dma_map_page(dev, virt_to_page(scratch_pt), 0,
2040 4096, PCI_DMA_BIDIRECTIONAL);
2041 if (dma_mapping_error(dev, daddr)) {
695fbc08 2042 gvt_vgpu_err("fail to dmamap scratch_pt\n");
5de6bd4c
CD		 2043 __free_page(virt_to_page(scratch_pt));
2044 return -ENOMEM;
3b6411c2 2045 }
5de6bd4c 2046 gtt->scratch_pt[type].page_mfn =
5c35258d 2047 (unsigned long)(daddr >> I915_GTT_PAGE_SHIFT);
9631739f 2048 gtt->scratch_pt[type].page = virt_to_page(scratch_pt);
3b6411c2 2049 gvt_dbg_mm("vgpu%d create scratch_pt: type %d mfn=0x%lx\n",
5de6bd4c 2050 vgpu->id, type, gtt->scratch_pt[type].page_mfn);
3b6411c2
PG		 2051
2052 /* Build the tree by full filled the scratch pt with the entries which
2053 * point to the next level scratch pt or scratch page. The
2054 * scratch_pt[type] indicate the scratch pt/scratch page used by the
2055 * 'type' pt.
2056 * e.g. scratch_pt[GTT_TYPE_PPGTT_PDE_PT] is used by
9631739f 2057 * GTT_TYPE_PPGTT_PDE_PT level pt, that means this scratch_pt it self
3b6411c2
PG		 2058 * is GTT_TYPE_PPGTT_PTE_PT, and full filled by scratch page mfn.
2059 */
65957195 2060 if (type > GTT_TYPE_PPGTT_PTE_PT) {
3b6411c2
PG		 2061 struct intel_gvt_gtt_entry se;
2062
2063 memset(&se, 0, sizeof(struct intel_gvt_gtt_entry));
2064 se.type = get_entry_type(type - 1);
2065 ops->set_pfn(&se, gtt->scratch_pt[type - 1].page_mfn);
2066
2067 /* The entry parameters like present/writeable/cache type
2068 * set to the same as i915's scratch page tree.
2069 */
2070 se.val64 |= _PAGE_PRESENT | _PAGE_RW;
2071 if (type == GTT_TYPE_PPGTT_PDE_PT)
c095b97c 2072 se.val64 |= PPAT_CACHED;
3b6411c2
PG		 2073
2074 for (i = 0; i < page_entry_num; i++)
9631739f 2075 ops->set_entry(scratch_pt, &se, i, false, 0, vgpu);
3b6411c2
PG		 2076 }
2077
3b6411c2
PG		 2078 return 0;
2079}
2707e444 2080
3b6411c2
PG		 2081static int release_scratch_page_tree(struct intel_vgpu *vgpu)
2082{
2083 int i;
5de6bd4c
CD		 2084 struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
2085 dma_addr_t daddr;
3b6411c2
PG		 2086
2087 for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
2088 if (vgpu->gtt.scratch_pt[i].page != NULL) {
5de6bd4c 2089 daddr = (dma_addr_t)(vgpu->gtt.scratch_pt[i].page_mfn <<
5c35258d 2090 I915_GTT_PAGE_SHIFT);
5de6bd4c 2091 dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
3b6411c2
PG		 2092 __free_page(vgpu->gtt.scratch_pt[i].page);
2093 vgpu->gtt.scratch_pt[i].page = NULL;
2094 vgpu->gtt.scratch_pt[i].page_mfn = 0;
2095 }
2707e444
ZW		 2096 }
2097
2707e444
ZW		 2098 return 0;
2099}
2100
3b6411c2 2101static int create_scratch_page_tree(struct intel_vgpu *vgpu)
2707e444 2102{
3b6411c2
PG		 2103 int i, ret;
2104
2105 for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
2106 ret = alloc_scratch_pages(vgpu, i);
2107 if (ret)
2108 goto err;
2707e444 2109 }
3b6411c2
PG		 2110
2111 return 0;
2112
2113err:
2114 release_scratch_page_tree(vgpu);
2115 return ret;
2707e444
ZW		 2116}
2117
2118/**
2119 * intel_vgpu_init_gtt - initialize per-vGPU graphics memory virulization
2120 * @vgpu: a vGPU
2121 *
2122 * This function is used to initialize per-vGPU graphics memory virtualization
2123 * components.
2124 *
2125 * Returns:
2126 * Zero on success, error code if failed.
2127 */
2128int intel_vgpu_init_gtt(struct intel_vgpu *vgpu)
2129{
2130 struct intel_vgpu_gtt *gtt = &vgpu->gtt;
2707e444 2131
b6c126a3 2132 INIT_RADIX_TREE(&gtt->spt_tree, GFP_KERNEL);
2707e444 2133
ede9d0cf 2134 INIT_LIST_HEAD(&gtt->ppgtt_mm_list_head);
2707e444
ZW		 2135 INIT_LIST_HEAD(&gtt->oos_page_list_head);
2136 INIT_LIST_HEAD(&gtt->post_shadow_list_head);
2137
ede9d0cf
CD		 2138 gtt->ggtt_mm = intel_vgpu_create_ggtt_mm(vgpu);
2139 if (IS_ERR(gtt->ggtt_mm)) {
695fbc08 2140 gvt_vgpu_err("fail to create mm for ggtt.\n");
ede9d0cf 2141 return PTR_ERR(gtt->ggtt_mm);
2707e444
ZW		 2142 }
2143
f4c43db3 2144 intel_vgpu_reset_ggtt(vgpu, false);
2707e444 2145
3b6411c2 2146 return create_scratch_page_tree(vgpu);
2707e444
ZW		 2147}
2148
ede9d0cf 2149static void intel_vgpu_destroy_all_ppgtt_mm(struct intel_vgpu *vgpu)
da9cc8de
PG		 2150{
2151 struct list_head *pos, *n;
2152 struct intel_vgpu_mm *mm;
2153
ede9d0cf
CD		 2154 list_for_each_safe(pos, n, &vgpu->gtt.ppgtt_mm_list_head) {
2155 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
1bc25851 2156 intel_vgpu_destroy_mm(mm);
da9cc8de 2157 }
ede9d0cf
CD		 2158
2159 if (GEM_WARN_ON(!list_empty(&vgpu->gtt.ppgtt_mm_list_head)))
84f69ba0 2160 gvt_err("vgpu ppgtt mm is not fully destroyed\n");
ede9d0cf 2161
b6c126a3 2162 if (GEM_WARN_ON(!radix_tree_empty(&vgpu->gtt.spt_tree))) {
ede9d0cf 2163 gvt_err("Why we still has spt not freed?\n");
d87f5ff3 2164 ppgtt_free_all_spt(vgpu);
ede9d0cf
CD		 2165 }
2166}
2167
2168static void intel_vgpu_destroy_ggtt_mm(struct intel_vgpu *vgpu)
2169{
1bc25851 2170 intel_vgpu_destroy_mm(vgpu->gtt.ggtt_mm);
ede9d0cf 2171 vgpu->gtt.ggtt_mm = NULL;
da9cc8de
PG		 2172}
2173
2707e444
ZW		 2174/**
2175 * intel_vgpu_clean_gtt - clean up per-vGPU graphics memory virulization
2176 * @vgpu: a vGPU
2177 *
2178 * This function is used to clean up per-vGPU graphics memory virtualization
2179 * components.
2180 *
2181 * Returns:
2182 * Zero on success, error code if failed.
2183 */
2184void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu)
2185{
ede9d0cf
CD		 2186 intel_vgpu_destroy_all_ppgtt_mm(vgpu);
2187 intel_vgpu_destroy_ggtt_mm(vgpu);
3b6411c2 2188 release_scratch_page_tree(vgpu);
2707e444
ZW		 2189}
2190
2191static void clean_spt_oos(struct intel_gvt *gvt)
2192{
2193 struct intel_gvt_gtt *gtt = &gvt->gtt;
2194 struct list_head *pos, *n;
2195 struct intel_vgpu_oos_page *oos_page;
2196
2197 WARN(!list_empty(&gtt->oos_page_use_list_head),
2198 "someone is still using oos page\n");
2199
2200 list_for_each_safe(pos, n, &gtt->oos_page_free_list_head) {
2201 oos_page = container_of(pos, struct intel_vgpu_oos_page, list);
2202 list_del(&oos_page->list);
2203 kfree(oos_page);
2204 }
2205}
2206
2207static int setup_spt_oos(struct intel_gvt *gvt)
2208{
2209 struct intel_gvt_gtt *gtt = &gvt->gtt;
2210 struct intel_vgpu_oos_page *oos_page;
2211 int i;
2212 int ret;
2213
2214 INIT_LIST_HEAD(&gtt->oos_page_free_list_head);
2215 INIT_LIST_HEAD(&gtt->oos_page_use_list_head);
2216
2217 for (i = 0; i < preallocated_oos_pages; i++) {
2218 oos_page = kzalloc(sizeof(*oos_page), GFP_KERNEL);
2219 if (!oos_page) {
2707e444
ZW		 2220 ret = -ENOMEM;
2221 goto fail;
2222 }
2223
2224 INIT_LIST_HEAD(&oos_page->list);
2225 INIT_LIST_HEAD(&oos_page->vm_list);
2226 oos_page->id = i;
2227 list_add_tail(&oos_page->list, &gtt->oos_page_free_list_head);
2228 }
2229
2230 gvt_dbg_mm("%d oos pages preallocated\n", i);
2231
2232 return 0;
2233fail:
2234 clean_spt_oos(gvt);
2235 return ret;
2236}
2237
2238/**
2239 * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
2240 * @vgpu: a vGPU
2241 * @page_table_level: PPGTT page table level
2242 * @root_entry: PPGTT page table root pointers
2243 *
2244 * This function is used to find a PPGTT mm object from mm object pool
2245 *
2246 * Returns:
2247 * pointer to mm object on success, NULL if failed.
2248 */
2249struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu,
ede9d0cf 2250 u64 pdps[])
2707e444 2251{
2707e444 2252 struct intel_vgpu_mm *mm;
ede9d0cf 2253 struct list_head *pos;
2707e444 2254
ede9d0cf
CD		 2255 list_for_each(pos, &vgpu->gtt.ppgtt_mm_list_head) {
2256 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
2707e444 2257
ede9d0cf
CD		 2258 switch (mm->ppgtt_mm.root_entry_type) {
2259 case GTT_TYPE_PPGTT_ROOT_L4_ENTRY:
2260 if (pdps[0] == mm->ppgtt_mm.guest_pdps[0])
2707e444 2261 return mm;
ede9d0cf
CD		 2262 break;
2263 case GTT_TYPE_PPGTT_ROOT_L3_ENTRY:
2264 if (!memcmp(pdps, mm->ppgtt_mm.guest_pdps,
2265 sizeof(mm->ppgtt_mm.guest_pdps)))
2707e444 2266 return mm;
ede9d0cf
CD		 2267 break;
2268 default:
2269 GEM_BUG_ON(1);
2707e444
ZW		 2270 }
2271 }
2272 return NULL;
2273}
2274
2275/**
e6e9c46f 2276 * intel_vgpu_get_ppgtt_mm - get or create a PPGTT mm object.
2707e444 2277 * @vgpu: a vGPU
ede9d0cf
CD		 2278 * @root_entry_type: ppgtt root entry type
2279 * @pdps: guest pdps
2707e444 2280 *
e6e9c46f 2281 * This function is used to find or create a PPGTT mm object from a guest.
2707e444
ZW		 2282 *
2283 * Returns:
2284 * Zero on success, negative error code if failed.
2285 */
e6e9c46f 2286struct intel_vgpu_mm *intel_vgpu_get_ppgtt_mm(struct intel_vgpu *vgpu,
ede9d0cf 2287 intel_gvt_gtt_type_t root_entry_type, u64 pdps[])
2707e444 2288{
2707e444
ZW		 2289 struct intel_vgpu_mm *mm;
2290
ede9d0cf 2291 mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
2707e444 2292 if (mm) {
1bc25851 2293 intel_vgpu_mm_get(mm);
2707e444 2294 } else {
ede9d0cf 2295 mm = intel_vgpu_create_ppgtt_mm(vgpu, root_entry_type, pdps);
e6e9c46f 2296 if (IS_ERR(mm))
695fbc08 2297 gvt_vgpu_err("fail to create mm\n");
2707e444 2298 }
e6e9c46f 2299 return mm;
2707e444
ZW		 2300}
2301
2302/**
e6e9c46f 2303 * intel_vgpu_put_ppgtt_mm - find and put a PPGTT mm object.
2707e444 2304 * @vgpu: a vGPU
ede9d0cf 2305 * @pdps: guest pdps
2707e444 2306 *
e6e9c46f 2307 * This function is used to find a PPGTT mm object from a guest and destroy it.
2707e444
ZW		 2308 *
2309 * Returns:
2310 * Zero on success, negative error code if failed.
2311 */
e6e9c46f 2312int intel_vgpu_put_ppgtt_mm(struct intel_vgpu *vgpu, u64 pdps[])
2707e444 2313{
2707e444
ZW		 2314 struct intel_vgpu_mm *mm;
2315
ede9d0cf 2316 mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
2707e444 2317 if (!mm) {
695fbc08 2318 gvt_vgpu_err("fail to find ppgtt instance.\n");
2707e444
ZW		 2319 return -EINVAL;
2320 }
1bc25851 2321 intel_vgpu_mm_put(mm);
2707e444
ZW		 2322 return 0;
2323}
2324
2325/**
2326 * intel_gvt_init_gtt - initialize mm components of a GVT device
2327 * @gvt: GVT device
2328 *
2329 * This function is called at the initialization stage, to initialize
2330 * the mm components of a GVT device.
2331 *
2332 * Returns:
2333 * zero on success, negative error code if failed.
2334 */
2335int intel_gvt_init_gtt(struct intel_gvt *gvt)
2336{
2337 int ret;
9631739f 2338 void *page;
5de6bd4c
CD		 2339 struct device *dev = &gvt->dev_priv->drm.pdev->dev;
2340 dma_addr_t daddr;
2707e444
ZW		 2341
2342 gvt_dbg_core("init gtt\n");
2343
665004b8
CX		 2344 gvt->gtt.pte_ops = &gen8_gtt_pte_ops;
2345 gvt->gtt.gma_ops = &gen8_gtt_gma_ops;
2707e444 2346
9631739f
JS		 2347 page = (void *)get_zeroed_page(GFP_KERNEL);
2348 if (!page) {
d650ac06
PG		 2349 gvt_err("fail to allocate scratch ggtt page\n");
2350 return -ENOMEM;
2351 }
2352
5de6bd4c
CD		 2353 daddr = dma_map_page(dev, virt_to_page(page), 0,
2354 4096, PCI_DMA_BIDIRECTIONAL);
2355 if (dma_mapping_error(dev, daddr)) {
2356 gvt_err("fail to dmamap scratch ggtt page\n");
2357 __free_page(virt_to_page(page));
2358 return -ENOMEM;
d650ac06 2359 }
22115cef
ZW		 2360
2361 gvt->gtt.scratch_page = virt_to_page(page);
2362 gvt->gtt.scratch_mfn = (unsigned long)(daddr >> I915_GTT_PAGE_SHIFT);
d650ac06 2363
2707e444
ZW		 2364 if (enable_out_of_sync) {
2365 ret = setup_spt_oos(gvt);
2366 if (ret) {
2367 gvt_err("fail to initialize SPT oos\n");
0de98709 2368 dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
22115cef 2369 __free_page(gvt->gtt.scratch_page);
2707e444
ZW		 2370 return ret;
2371 }
2372 }
ede9d0cf 2373 INIT_LIST_HEAD(&gvt->gtt.ppgtt_mm_lru_list_head);
2707e444
ZW		 2374 return 0;
2375}
2376
2377/**
2378 * intel_gvt_clean_gtt - clean up mm components of a GVT device
2379 * @gvt: GVT device
2380 *
2381 * This function is called at the driver unloading stage, to clean up the
2382 * the mm components of a GVT device.
2383 *
2384 */
2385void intel_gvt_clean_gtt(struct intel_gvt *gvt)
2386{
5de6bd4c 2387 struct device *dev = &gvt->dev_priv->drm.pdev->dev;
22115cef 2388 dma_addr_t daddr = (dma_addr_t)(gvt->gtt.scratch_mfn <<
9556e118 2389 I915_GTT_PAGE_SHIFT);
5de6bd4c
CD		 2390
2391 dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
2392
22115cef 2393 __free_page(gvt->gtt.scratch_page);
d650ac06 2394
2707e444
ZW		 2395 if (enable_out_of_sync)
2396 clean_spt_oos(gvt);
2397}
d650ac06 2398
730c8ead
ZW		 2399/**
2400 * intel_vgpu_invalidate_ppgtt - invalidate PPGTT instances
2401 * @vgpu: a vGPU
2402 *
2403 * This function is called when invalidate all PPGTT instances of a vGPU.
2404 *
2405 */
2406void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu)
2407{
2408 struct list_head *pos, *n;
2409 struct intel_vgpu_mm *mm;
2410
2411 list_for_each_safe(pos, n, &vgpu->gtt.ppgtt_mm_list_head) {
2412 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
2413 if (mm->type == INTEL_GVT_MM_PPGTT) {
2414 list_del_init(&mm->ppgtt_mm.lru_list);
2415 if (mm->ppgtt_mm.shadowed)
2416 invalidate_ppgtt_mm(mm);
2417 }
2418 }
2419}
2420
d650ac06
PG		 2421/**
2422 * intel_vgpu_reset_ggtt - reset the GGTT entry
2423 * @vgpu: a vGPU
f4c43db3 2424 * @invalidate_old: invalidate old entries
d650ac06
PG		 2425 *
2426 * This function is called at the vGPU create stage
2427 * to reset all the GGTT entries.
2428 *
2429 */
f4c43db3 2430void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old)
d650ac06
PG		 2431{
2432 struct intel_gvt *gvt = vgpu->gvt;
5ad59bf0 2433 struct drm_i915_private *dev_priv = gvt->dev_priv;
b0c766bf
CD		 2434 struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2435 struct intel_gvt_gtt_entry entry = {.type = GTT_TYPE_GGTT_PTE};
f4c43db3 2436 struct intel_gvt_gtt_entry old_entry;
d650ac06 2437 u32 index;
d650ac06 2438 u32 num_entries;
d650ac06 2439
b0c766bf
CD		 2440 pte_ops->set_pfn(&entry, gvt->gtt.scratch_mfn);
2441 pte_ops->set_present(&entry);
d650ac06
PG		 2442
2443 index = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT;
2444 num_entries = vgpu_aperture_sz(vgpu) >> PAGE_SHIFT;
f4c43db3
CD		 2445 while (num_entries--) {
2446 if (invalidate_old) {
2447 ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index);
2448 ggtt_invalidate_pte(vgpu, &old_entry);
2449 }
b0c766bf 2450 ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
f4c43db3 2451 }
d650ac06
PG		 2452
2453 index = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT;
2454 num_entries = vgpu_hidden_sz(vgpu) >> PAGE_SHIFT;
f4c43db3
CD		 2455 while (num_entries--) {
2456 if (invalidate_old) {
2457 ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index);
2458 ggtt_invalidate_pte(vgpu, &old_entry);
2459 }
b0c766bf 2460 ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
f4c43db3 2461 }
5ad59bf0 2462
a143cef7 2463 ggtt_invalidate(dev_priv);
d650ac06 2464}
b611581b
CD		 2465
2466/**
2467 * intel_vgpu_reset_gtt - reset the all GTT related status
2468 * @vgpu: a vGPU
b611581b
CD		 2469 *
2470 * This function is called from vfio core to reset reset all
2471 * GTT related status, including GGTT, PPGTT, scratch page.
2472 *
2473 */
4d3e67bb 2474void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu)
b611581b 2475{
da9cc8de
PG		 2476 /* Shadow pages are only created when there is no page
2477 * table tracking data, so remove page tracking data after
2478 * removing the shadow pages.
2479 */
ede9d0cf 2480 intel_vgpu_destroy_all_ppgtt_mm(vgpu);
f4c43db3 2481 intel_vgpu_reset_ggtt(vgpu, true);
b611581b 2482}
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