[linux.git] / arch / arm / mach-imx / pm-imx5.c

/*
 *  Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */
#include <linux/suspend.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/export.h>

#include <linux/genalloc.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>

#include <asm/cacheflush.h>
#include <asm/fncpy.h>
#include <asm/system_misc.h>
#include <asm/tlbflush.h>

#include "common.h"
#include "cpuidle.h"
#include "hardware.h"

#define MXC_CCM_CLPCR			0x54
#define MXC_CCM_CLPCR_LPM_OFFSET	0
#define MXC_CCM_CLPCR_LPM_MASK		0x3
#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET	9
#define MXC_CCM_CLPCR_VSTBY		(0x1 << 8)
#define MXC_CCM_CLPCR_SBYOS		(0x1 << 6)

#define MXC_CORTEXA8_PLAT_LPC		0xc
#define MXC_CORTEXA8_PLAT_LPC_DSM	(1 << 0)
#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM	(1 << 1)

#define MXC_SRPG_NEON_SRPGCR		0x280
#define MXC_SRPG_ARM_SRPGCR		0x2a0
#define MXC_SRPG_EMPGC0_SRPGCR		0x2c0
#define MXC_SRPG_EMPGC1_SRPGCR		0x2d0

#define MXC_SRPGCR_PCR			1

/*
 * The WAIT_UNCLOCKED_POWER_OFF state only requires <= 500ns to exit.
 * This is also the lowest power state possible without affecting
 * non-cpu parts of the system.  For these reasons, imx5 should default
 * to always using this state for cpu idling.  The PM_SUSPEND_STANDBY also
 * uses this state and needs to take no action when registers remain confgiured
 * for this state.
 */
#define IMX5_DEFAULT_CPU_IDLE_STATE WAIT_UNCLOCKED_POWER_OFF

struct imx5_suspend_io_state {
	u32	offset;
	u32	clear;
	u32	set;
	u32	saved_value;
};

struct imx5_pm_data {
	phys_addr_t ccm_addr;
	phys_addr_t cortex_addr;
	phys_addr_t gpc_addr;
	phys_addr_t m4if_addr;
	phys_addr_t iomuxc_addr;
	void (*suspend_asm)(void __iomem *ocram_vbase);
	const u32 *suspend_asm_sz;
	const struct imx5_suspend_io_state *suspend_io_config;
	int suspend_io_count;
};

static const struct imx5_suspend_io_state imx53_suspend_io_config[] = {
#define MX53_DSE_HIGHZ_MASK (0x7 << 19)
	{.offset = 0x584, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM0 */
	{.offset = 0x594, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM1 */
	{.offset = 0x560, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM2 */
	{.offset = 0x554, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM3 */
	{.offset = 0x574, .clear = MX53_DSE_HIGHZ_MASK}, /* CAS */
	{.offset = 0x588, .clear = MX53_DSE_HIGHZ_MASK}, /* RAS */
	{.offset = 0x578, .clear = MX53_DSE_HIGHZ_MASK}, /* SDCLK_0 */
	{.offset = 0x570, .clear = MX53_DSE_HIGHZ_MASK}, /* SDCLK_1 */

	{.offset = 0x580, .clear = MX53_DSE_HIGHZ_MASK}, /* SDODT0 */
	{.offset = 0x564, .clear = MX53_DSE_HIGHZ_MASK}, /* SDODT1 */
	{.offset = 0x57c, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS0 */
	{.offset = 0x590, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS1 */
	{.offset = 0x568, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS2 */
	{.offset = 0x558, .clear = MX53_DSE_HIGHZ_MASK}, /* SDSQ3 */
	{.offset = 0x6f0, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_ADDS */
	{.offset = 0x718, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_BODS */
	{.offset = 0x71c, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B1DS */
	{.offset = 0x728, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B2DS */
	{.offset = 0x72c, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B3DS */

	/* Controls the CKE signal which is required to leave self refresh */
	{.offset = 0x720, .clear = MX53_DSE_HIGHZ_MASK, .set = 1 << 19}, /* CTLDS */
};

static const struct imx5_pm_data imx51_pm_data __initconst = {
	.ccm_addr = 0x73fd4000,
	.cortex_addr = 0x83fa0000,
	.gpc_addr = 0x73fd8000,
};

static const struct imx5_pm_data imx53_pm_data __initconst = {
	.ccm_addr = 0x53fd4000,
	.cortex_addr = 0x63fa0000,
	.gpc_addr = 0x53fd8000,
	.m4if_addr = 0x63fd8000,
	.iomuxc_addr = 0x53fa8000,
	.suspend_asm = &imx53_suspend,
	.suspend_asm_sz = &imx53_suspend_sz,
	.suspend_io_config = imx53_suspend_io_config,
	.suspend_io_count = ARRAY_SIZE(imx53_suspend_io_config),
};

#define MX5_MAX_SUSPEND_IOSTATE ARRAY_SIZE(imx53_suspend_io_config)

/*
 * This structure is for passing necessary data for low level ocram
 * suspend code(arch/arm/mach-imx/suspend-imx53.S), if this struct
 * definition is changed, the offset definition in that file
 * must be also changed accordingly otherwise, the suspend to ocram
 * function will be broken!
 */
struct imx5_cpu_suspend_info {
	void __iomem	*m4if_base;
	void __iomem	*iomuxc_base;
	u32		io_count;
	struct imx5_suspend_io_state io_state[MX5_MAX_SUSPEND_IOSTATE];
} __aligned(8);

static void __iomem *ccm_base;
static void __iomem *cortex_base;
static void __iomem *gpc_base;
static void __iomem *suspend_ocram_base;
static void (*imx5_suspend_in_ocram_fn)(void __iomem *ocram_vbase);

/*
 * set cpu low power mode before WFI instruction. This function is called
 * mx5 because it can be used for mx51, and mx53.
 */
static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
{
	u32 plat_lpc, arm_srpgcr, ccm_clpcr;
	u32 empgc0, empgc1;
	int stop_mode = 0;

	/* always allow platform to issue a deep sleep mode request */
	plat_lpc = __raw_readl(cortex_base + MXC_CORTEXA8_PLAT_LPC) &
	    ~(MXC_CORTEXA8_PLAT_LPC_DSM);
	ccm_clpcr = __raw_readl(ccm_base + MXC_CCM_CLPCR) &
		    ~(MXC_CCM_CLPCR_LPM_MASK);
	arm_srpgcr = __raw_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) &
		     ~(MXC_SRPGCR_PCR);
	empgc0 = __raw_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) &
		 ~(MXC_SRPGCR_PCR);
	empgc1 = __raw_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) &
		 ~(MXC_SRPGCR_PCR);

	switch (mode) {
	case WAIT_CLOCKED:
		break;
	case WAIT_UNCLOCKED:
		ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
		break;
	case WAIT_UNCLOCKED_POWER_OFF:
	case STOP_POWER_OFF:
		plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM
			    | MXC_CORTEXA8_PLAT_LPC_DBG_DSM;
		if (mode == WAIT_UNCLOCKED_POWER_OFF) {
			ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
			ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY;
			ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS;
			stop_mode = 0;
		} else {
			ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
			ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET;
			ccm_clpcr |= MXC_CCM_CLPCR_VSTBY;
			ccm_clpcr |= MXC_CCM_CLPCR_SBYOS;
			stop_mode = 1;
		}
		arm_srpgcr |= MXC_SRPGCR_PCR;
		break;
	case STOP_POWER_ON:
		ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
		break;
	default:
		printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode);
		return;
	}

	__raw_writel(plat_lpc, cortex_base + MXC_CORTEXA8_PLAT_LPC);
	__raw_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR);
	__raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR);
	__raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR);

	if (stop_mode) {
		empgc0 |= MXC_SRPGCR_PCR;
		empgc1 |= MXC_SRPGCR_PCR;

		__raw_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
		__raw_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);
	}
}

static int mx5_suspend_enter(suspend_state_t state)
{
	switch (state) {
	case PM_SUSPEND_MEM:
		mx5_cpu_lp_set(STOP_POWER_OFF);
		break;
	case PM_SUSPEND_STANDBY:
		/* DEFAULT_IDLE_STATE already configured */
		break;
	default:
		return -EINVAL;
	}

	if (state == PM_SUSPEND_MEM) {
		local_flush_tlb_all();
		flush_cache_all();

		/*clear the EMPGC0/1 bits */
		__raw_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
		__raw_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);

		if (imx5_suspend_in_ocram_fn)
			imx5_suspend_in_ocram_fn(suspend_ocram_base);
		else
			cpu_do_idle();

	} else {
		cpu_do_idle();
	}

	/* return registers to default idle state */
	mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE);
	return 0;
}

static int mx5_pm_valid(suspend_state_t state)
{
	return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
}

static const struct platform_suspend_ops mx5_suspend_ops = {
	.valid = mx5_pm_valid,
	.enter = mx5_suspend_enter,
};

static inline int imx5_cpu_do_idle(void)
{
	int ret = tzic_enable_wake();

	if (likely(!ret))
		cpu_do_idle();

	return ret;
}

static void imx5_pm_idle(void)
{
	imx5_cpu_do_idle();
}

static int __init imx_suspend_alloc_ocram(
				size_t size,
				void __iomem **virt_out,
				phys_addr_t *phys_out)
{
	struct device_node *node;
	struct platform_device *pdev;
	struct gen_pool *ocram_pool;
	unsigned long ocram_base;
	void __iomem *virt;
	phys_addr_t phys;
	int ret = 0;

	/* Copied from imx6: TODO factorize */
	node = of_find_compatible_node(NULL, NULL, "mmio-sram");
	if (!node) {
		pr_warn("%s: failed to find ocram node!\n", __func__);
		return -ENODEV;
	}

	pdev = of_find_device_by_node(node);
	if (!pdev) {
		pr_warn("%s: failed to find ocram device!\n", __func__);
		ret = -ENODEV;
		goto put_node;
	}

	ocram_pool = gen_pool_get(&pdev->dev, NULL);
	if (!ocram_pool) {
		pr_warn("%s: ocram pool unavailable!\n", __func__);
		ret = -ENODEV;
		goto put_node;
	}

	ocram_base = gen_pool_alloc(ocram_pool, size);
	if (!ocram_base) {
		pr_warn("%s: unable to alloc ocram!\n", __func__);
		ret = -ENOMEM;
		goto put_node;
	}

	phys = gen_pool_virt_to_phys(ocram_pool, ocram_base);
	virt = __arm_ioremap_exec(phys, size, false);
	if (phys_out)
		*phys_out = phys;
	if (virt_out)
		*virt_out = virt;

put_node:
	of_node_put(node);

	return ret;
}

static int __init imx5_suspend_init(const struct imx5_pm_data *soc_data)
{
	struct imx5_cpu_suspend_info *suspend_info;
	int ret;
	/* Need this to avoid compile error due to const typeof in fncpy.h */
	void (*suspend_asm)(void __iomem *) = soc_data->suspend_asm;

	if (!suspend_asm)
		return 0;

	if (!soc_data->suspend_asm_sz || !*soc_data->suspend_asm_sz)
		return -EINVAL;

	ret = imx_suspend_alloc_ocram(
		*soc_data->suspend_asm_sz + sizeof(*suspend_info),
		&suspend_ocram_base, NULL);
	if (ret)
		return ret;

	suspend_info = suspend_ocram_base;

	suspend_info->io_count = soc_data->suspend_io_count;
	memcpy(suspend_info->io_state, soc_data->suspend_io_config,
	       sizeof(*suspend_info->io_state) * soc_data->suspend_io_count);

	suspend_info->m4if_base = ioremap(soc_data->m4if_addr, SZ_16K);
	if (!suspend_info->m4if_base) {
		ret = -ENOMEM;
		goto failed_map_m4if;
	}

	suspend_info->iomuxc_base = ioremap(soc_data->iomuxc_addr, SZ_16K);
	if (!suspend_info->iomuxc_base) {
		ret = -ENOMEM;
		goto failed_map_iomuxc;
	}

	imx5_suspend_in_ocram_fn = fncpy(
		suspend_ocram_base + sizeof(*suspend_info),
		suspend_asm,
		*soc_data->suspend_asm_sz);

	return 0;

failed_map_iomuxc:
	iounmap(suspend_info->m4if_base);

failed_map_m4if:
	return ret;
}

static int __init imx5_pm_common_init(const struct imx5_pm_data *data)
{
	int ret;
	struct clk *gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");

	if (IS_ERR(gpc_dvfs_clk))
		return PTR_ERR(gpc_dvfs_clk);

	ret = clk_prepare_enable(gpc_dvfs_clk);
	if (ret)
		return ret;

	arm_pm_idle = imx5_pm_idle;

	ccm_base = ioremap(data->ccm_addr, SZ_16K);
	cortex_base = ioremap(data->cortex_addr, SZ_16K);
	gpc_base = ioremap(data->gpc_addr, SZ_16K);
	WARN_ON(!ccm_base || !cortex_base || !gpc_base);

	/* Set the registers to the default cpu idle state. */
	mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE);

	ret = imx5_cpuidle_init();
	if (ret)
		pr_warn("%s: cpuidle init failed %d\n", __func__, ret);

	ret = imx5_suspend_init(data);
	if (ret)
		pr_warn("%s: No DDR LPM support with suspend %d!\n",
			__func__, ret);

	suspend_set_ops(&mx5_suspend_ops);

	return 0;
}

void __init imx51_pm_init(void)
{
	if (IS_ENABLED(CONFIG_SOC_IMX51))
		imx5_pm_common_init(&imx51_pm_data);
}

void __init imx53_pm_init(void)
{
	if (IS_ENABLED(CONFIG_SOC_IMX53))
		imx5_pm_common_init(&imx53_pm_data);
}
Commit	Line	Data
0adf882b	1	/*
784a90c0 SH	2	* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
784a90c0 SH	3	*
0adf882b DN	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
784a90c0 SH	11	#include <linux/suspend.h>
784a90c0 SH	12	#include <linux/clk.h>
0adf882b	13	#include <linux/io.h>
784a90c0	14	#include <linux/err.h>
ccc12b32	15	#include <linux/export.h>
1579c7b9 MF	16
	17	#include <linux/genalloc.h>
	18	#include <linux/of.h>
	19	#include <linux/of_address.h>
	20	#include <linux/of_platform.h>
	21
784a90c0	22	#include <asm/cacheflush.h>
1579c7b9	23	#include <asm/fncpy.h>
565fa91f	24	#include <asm/system_misc.h>
784a90c0	25	#include <asm/tlbflush.h>
e3372474 SG	26
e3372474 SG	27	#include "common.h"
e29248c9	28	#include "cpuidle.h"
50f2de61	29	#include "hardware.h"
784a90c0	30
4ef5e387	31	#define MXC_CCM_CLPCR 0x54
e7d5eb3c SG	32	#define MXC_CCM_CLPCR_LPM_OFFSET 0
	33	#define MXC_CCM_CLPCR_LPM_MASK 0x3
	34	#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
	35	#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
	36	#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
	37
36b66c3f	38	#define MXC_CORTEXA8_PLAT_LPC 0xc
e7d5eb3c SG	39	#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
	40	#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
	41
36b66c3f SG	42	#define MXC_SRPG_NEON_SRPGCR 0x280
	43	#define MXC_SRPG_ARM_SRPGCR 0x2a0
	44	#define MXC_SRPG_EMPGC0_SRPGCR 0x2c0
	45	#define MXC_SRPG_EMPGC1_SRPGCR 0x2d0
e7d5eb3c SG	46
	47	#define MXC_SRPGCR_PCR 1
	48
565fa91f RL	49	/*
	50	* The WAIT_UNCLOCKED_POWER_OFF state only requires <= 500ns to exit.
	51	* This is also the lowest power state possible without affecting
	52	* non-cpu parts of the system. For these reasons, imx5 should default
	53	* to always using this state for cpu idling. The PM_SUSPEND_STANDBY also
	54	* uses this state and needs to take no action when registers remain confgiured
	55	* for this state.
	56	*/
	57	#define IMX5_DEFAULT_CPU_IDLE_STATE WAIT_UNCLOCKED_POWER_OFF
0adf882b	58
1579c7b9 MF	59	struct imx5_suspend_io_state {
	60	u32 offset;
	61	u32 clear;
	62	u32 set;
	63	u32 saved_value;
	64	};
	65
36b66c3f	66	struct imx5_pm_data {
f3a9249d	67	phys_addr_t ccm_addr;
36b66c3f SG	68	phys_addr_t cortex_addr;
36b66c3f SG	69	phys_addr_t gpc_addr;
1579c7b9 MF	70	phys_addr_t m4if_addr;
	71	phys_addr_t iomuxc_addr;
	72	void (suspend_asm)(void __iomem ocram_vbase);
	73	const u32 *suspend_asm_sz;
	74	const struct imx5_suspend_io_state *suspend_io_config;
	75	int suspend_io_count;
	76	};
	77
	78	static const struct imx5_suspend_io_state imx53_suspend_io_config[] = {
	79	#define MX53_DSE_HIGHZ_MASK (0x7 << 19)
	80	{.offset = 0x584, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM0 */
	81	{.offset = 0x594, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM1 */
	82	{.offset = 0x560, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM2 */
	83	{.offset = 0x554, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM3 */
	84	{.offset = 0x574, .clear = MX53_DSE_HIGHZ_MASK}, /* CAS */
	85	{.offset = 0x588, .clear = MX53_DSE_HIGHZ_MASK}, /* RAS */
	86	{.offset = 0x578, .clear = MX53_DSE_HIGHZ_MASK}, /* SDCLK_0 */
	87	{.offset = 0x570, .clear = MX53_DSE_HIGHZ_MASK}, /* SDCLK_1 */
	88
	89	{.offset = 0x580, .clear = MX53_DSE_HIGHZ_MASK}, /* SDODT0 */
	90	{.offset = 0x564, .clear = MX53_DSE_HIGHZ_MASK}, /* SDODT1 */
	91	{.offset = 0x57c, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS0 */
	92	{.offset = 0x590, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS1 */
	93	{.offset = 0x568, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS2 */
	94	{.offset = 0x558, .clear = MX53_DSE_HIGHZ_MASK}, /* SDSQ3 */
	95	{.offset = 0x6f0, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_ADDS */
	96	{.offset = 0x718, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_BODS */
	97	{.offset = 0x71c, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B1DS */
	98	{.offset = 0x728, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B2DS */
	99	{.offset = 0x72c, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B3DS */
	100
	101	/* Controls the CKE signal which is required to leave self refresh */
	102	{.offset = 0x720, .clear = MX53_DSE_HIGHZ_MASK, .set = 1 << 19}, /* CTLDS */
36b66c3f SG	103	};
	104
	105	static const struct imx5_pm_data imx51_pm_data __initconst = {
f3a9249d	106	.ccm_addr = 0x73fd4000,
36b66c3f SG	107	.cortex_addr = 0x83fa0000,
	108	.gpc_addr = 0x73fd8000,
	109	};
	110
	111	static const struct imx5_pm_data imx53_pm_data __initconst = {
f3a9249d	112	.ccm_addr = 0x53fd4000,
36b66c3f SG	113	.cortex_addr = 0x63fa0000,
36b66c3f SG	114	.gpc_addr = 0x53fd8000,
1579c7b9 MF	115	.m4if_addr = 0x63fd8000,
	116	.iomuxc_addr = 0x53fa8000,
	117	.suspend_asm = &imx53_suspend,
	118	.suspend_asm_sz = &imx53_suspend_sz,
	119	.suspend_io_config = imx53_suspend_io_config,
	120	.suspend_io_count = ARRAY_SIZE(imx53_suspend_io_config),
36b66c3f SG	121	};
36b66c3f SG	122
1579c7b9 MF	123	#define MX5_MAX_SUSPEND_IOSTATE ARRAY_SIZE(imx53_suspend_io_config)
	124
	125	/*
	126	* This structure is for passing necessary data for low level ocram
	127	* suspend code(arch/arm/mach-imx/suspend-imx53.S), if this struct
	128	* definition is changed, the offset definition in that file
	129	* must be also changed accordingly otherwise, the suspend to ocram
	130	* function will be broken!
	131	*/
	132	struct imx5_cpu_suspend_info {
	133	void __iomem *m4if_base;
	134	void __iomem *iomuxc_base;
	135	u32 io_count;
	136	struct imx5_suspend_io_state io_state[MX5_MAX_SUSPEND_IOSTATE];
	137	} __aligned(8);
	138
4ef5e387	139	static void __iomem *ccm_base;
36b66c3f SG	140	static void __iomem *cortex_base;
36b66c3f SG	141	static void __iomem *gpc_base;
1579c7b9 MF	142	static void __iomem *suspend_ocram_base;
1579c7b9 MF	143	static void (imx5_suspend_in_ocram_fn)(void __iomem ocram_vbase);
4ef5e387	144
784a90c0 SH	145	/*
784a90c0 SH	146	* set cpu low power mode before WFI instruction. This function is called
7356420c	147	* mx5 because it can be used for mx51, and mx53.
784a90c0	148	*/
565fa91f	149	static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
0adf882b DN	150	{
	151	u32 plat_lpc, arm_srpgcr, ccm_clpcr;
	152	u32 empgc0, empgc1;
	153	int stop_mode = 0;
	154
	155	/* always allow platform to issue a deep sleep mode request */
36b66c3f	156	plat_lpc = __raw_readl(cortex_base + MXC_CORTEXA8_PLAT_LPC) &
0adf882b	157	~(MXC_CORTEXA8_PLAT_LPC_DSM);
4ef5e387 SG	158	ccm_clpcr = __raw_readl(ccm_base + MXC_CCM_CLPCR) &
4ef5e387 SG	159	~(MXC_CCM_CLPCR_LPM_MASK);
36b66c3f SG	160	arm_srpgcr = __raw_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) &
	161	~(MXC_SRPGCR_PCR);
	162	empgc0 = __raw_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) &
	163	~(MXC_SRPGCR_PCR);
	164	empgc1 = __raw_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) &
	165	~(MXC_SRPGCR_PCR);
0adf882b DN	166
	167	switch (mode) {
	168	case WAIT_CLOCKED:
	169	break;
	170	case WAIT_UNCLOCKED:
	171	ccm_clpcr \|= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
	172	break;
	173	case WAIT_UNCLOCKED_POWER_OFF:
	174	case STOP_POWER_OFF:
	175	plat_lpc \|= MXC_CORTEXA8_PLAT_LPC_DSM
	176	\| MXC_CORTEXA8_PLAT_LPC_DBG_DSM;
	177	if (mode == WAIT_UNCLOCKED_POWER_OFF) {
	178	ccm_clpcr \|= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
	179	ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY;
	180	ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS;
	181	stop_mode = 0;
	182	} else {
	183	ccm_clpcr \|= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
	184	ccm_clpcr \|= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET;
	185	ccm_clpcr \|= MXC_CCM_CLPCR_VSTBY;
	186	ccm_clpcr \|= MXC_CCM_CLPCR_SBYOS;
	187	stop_mode = 1;
	188	}
	189	arm_srpgcr \|= MXC_SRPGCR_PCR;
0adf882b DN	190	break;
	191	case STOP_POWER_ON:
	192	ccm_clpcr \|= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
	193	break;
	194	default:
	195	printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode);
	196	return;
	197	}
	198
36b66c3f	199	__raw_writel(plat_lpc, cortex_base + MXC_CORTEXA8_PLAT_LPC);
4ef5e387	200	__raw_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR);
36b66c3f SG	201	__raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR);
36b66c3f SG	202	__raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR);
0adf882b DN	203
	204	if (stop_mode) {
	205	empgc0 \|= MXC_SRPGCR_PCR;
	206	empgc1 \|= MXC_SRPGCR_PCR;
	207
36b66c3f SG	208	__raw_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
36b66c3f SG	209	__raw_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);
0adf882b DN	210	}
0adf882b DN	211	}
784a90c0	212
784a90c0 SH	213	static int mx5_suspend_enter(suspend_state_t state)
	214	{
	215	switch (state) {
	216	case PM_SUSPEND_MEM:
	217	mx5_cpu_lp_set(STOP_POWER_OFF);
	218	break;
	219	case PM_SUSPEND_STANDBY:
565fa91f	220	/* DEFAULT_IDLE_STATE already configured */
784a90c0 SH	221	break;
	222	default:
	223	return -EINVAL;
	224	}
	225
	226	if (state == PM_SUSPEND_MEM) {
	227	local_flush_tlb_all();
	228	flush_cache_all();
	229
	230	/clear the EMPGC0/1 bits /
36b66c3f SG	231	__raw_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
36b66c3f SG	232	__raw_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);
1579c7b9 MF	233
	234	if (imx5_suspend_in_ocram_fn)
	235	imx5_suspend_in_ocram_fn(suspend_ocram_base);
	236	else
	237	cpu_do_idle();
	238
	239	} else {
	240	cpu_do_idle();
784a90c0	241	}
784a90c0	242
565fa91f RL	243	/* return registers to default idle state */
	244	mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE);
	245	return 0;
784a90c0 SH	246	}
	247
	248	static int mx5_pm_valid(suspend_state_t state)
	249	{
	250	return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
	251	}
	252
	253	static const struct platform_suspend_ops mx5_suspend_ops = {
	254	.valid = mx5_pm_valid,
784a90c0	255	.enter = mx5_suspend_enter,
784a90c0 SH	256	};
784a90c0 SH	257
ccc12b32	258	static inline int imx5_cpu_do_idle(void)
784a90c0	259	{
ccc12b32 RL	260	int ret = tzic_enable_wake();
	261
	262	if (likely(!ret))
565fa91f	263	cpu_do_idle();
ccc12b32 RL	264
	265	return ret;
	266	}
	267
	268	static void imx5_pm_idle(void)
	269	{
	270	imx5_cpu_do_idle();
	271	}
	272
1579c7b9 MF	273	static int __init imx_suspend_alloc_ocram(
	274	size_t size,
	275	void __iomem **virt_out,
	276	phys_addr_t *phys_out)
	277	{
	278	struct device_node *node;
	279	struct platform_device *pdev;
	280	struct gen_pool *ocram_pool;
	281	unsigned long ocram_base;
	282	void __iomem *virt;
	283	phys_addr_t phys;
	284	int ret = 0;
	285
	286	/* Copied from imx6: TODO factorize */
	287	node = of_find_compatible_node(NULL, NULL, "mmio-sram");
	288	if (!node) {
	289	pr_warn("%s: failed to find ocram node!\n", __func__);
	290	return -ENODEV;
	291	}
	292
	293	pdev = of_find_device_by_node(node);
	294	if (!pdev) {
	295	pr_warn("%s: failed to find ocram device!\n", __func__);
	296	ret = -ENODEV;
	297	goto put_node;
	298	}
	299
73858173	300	ocram_pool = gen_pool_get(&pdev->dev, NULL);
1579c7b9 MF	301	if (!ocram_pool) {
	302	pr_warn("%s: ocram pool unavailable!\n", __func__);
	303	ret = -ENODEV;
	304	goto put_node;
	305	}
	306
	307	ocram_base = gen_pool_alloc(ocram_pool, size);
	308	if (!ocram_base) {
	309	pr_warn("%s: unable to alloc ocram!\n", __func__);
	310	ret = -ENOMEM;
	311	goto put_node;
	312	}
	313
	314	phys = gen_pool_virt_to_phys(ocram_pool, ocram_base);
	315	virt = __arm_ioremap_exec(phys, size, false);
	316	if (phys_out)
	317	*phys_out = phys;
	318	if (virt_out)
	319	*virt_out = virt;
	320
	321	put_node:
	322	of_node_put(node);
	323
	324	return ret;
	325	}
	326
	327	static int __init imx5_suspend_init(const struct imx5_pm_data *soc_data)
	328	{
	329	struct imx5_cpu_suspend_info *suspend_info;
	330	int ret;
	331	/* Need this to avoid compile error due to const typeof in fncpy.h */
	332	void (suspend_asm)(void __iomem ) = soc_data->suspend_asm;
	333
	334	if (!suspend_asm)
	335	return 0;
	336
	337	if (!soc_data->suspend_asm_sz \|\| !*soc_data->suspend_asm_sz)
	338	return -EINVAL;
	339
	340	ret = imx_suspend_alloc_ocram(
	341	soc_data->suspend_asm_sz + sizeof(suspend_info),
	342	&suspend_ocram_base, NULL);
	343	if (ret)
	344	return ret;
	345
	346	suspend_info = suspend_ocram_base;
	347
	348	suspend_info->io_count = soc_data->suspend_io_count;
	349	memcpy(suspend_info->io_state, soc_data->suspend_io_config,
	350	sizeof(suspend_info->io_state) soc_data->suspend_io_count);
	351
	352	suspend_info->m4if_base = ioremap(soc_data->m4if_addr, SZ_16K);
	353	if (!suspend_info->m4if_base) {
	354	ret = -ENOMEM;
	355	goto failed_map_m4if;
	356	}
	357
	358	suspend_info->iomuxc_base = ioremap(soc_data->iomuxc_addr, SZ_16K);
	359	if (!suspend_info->iomuxc_base) {
	360	ret = -ENOMEM;
	361	goto failed_map_iomuxc;
	362	}
	363
	364	imx5_suspend_in_ocram_fn = fncpy(
365	suspend_ocram_base + sizeof(*suspend_info),
366	suspend_asm,
367	*soc_data->suspend_asm_sz);
368
369	return 0;
370
371	failed_map_iomuxc:
372	iounmap(suspend_info->m4if_base);
373
374	failed_map_m4if:
375	return ret;
376	}
377
36b66c3f	378	static int __init imx5_pm_common_init(const struct imx5_pm_data *data)
565fa91f RL	379	{
	380	int ret;
	381	struct clk *gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
	382
	383	if (IS_ERR(gpc_dvfs_clk))
	384	return PTR_ERR(gpc_dvfs_clk);
784a90c0	385
565fa91f RL	386	ret = clk_prepare_enable(gpc_dvfs_clk);
	387	if (ret)
	388	return ret;
784a90c0	389
565fa91f RL	390	arm_pm_idle = imx5_pm_idle;
565fa91f RL	391
f3a9249d	392	ccm_base = ioremap(data->ccm_addr, SZ_16K);
36b66c3f SG	393	cortex_base = ioremap(data->cortex_addr, SZ_16K);
	394	gpc_base = ioremap(data->gpc_addr, SZ_16K);
	395	WARN_ON(!ccm_base \|\| !cortex_base \|\| !gpc_base);
4ef5e387	396
565fa91f RL	397	/* Set the registers to the default cpu idle state. */
565fa91f RL	398	mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE);
784a90c0	399
36b66c3f SG	400	ret = imx5_cpuidle_init();
	401	if (ret)
	402	pr_warn("%s: cpuidle init failed %d\n", __func__, ret);
	403
1579c7b9 MF	404	ret = imx5_suspend_init(data);
	405	if (ret)
	406	pr_warn("%s: No DDR LPM support with suspend %d!\n",
	407	__func__, ret);
	408
36b66c3f SG	409	suspend_set_ops(&mx5_suspend_ops);
	410
	411	return 0;
	412	}
	413
	414	void __init imx51_pm_init(void)
	415	{
e20d7b52 AB	416	if (IS_ENABLED(CONFIG_SOC_IMX51))
e20d7b52 AB	417	imx5_pm_common_init(&imx51_pm_data);
784a90c0	418	}
565fa91f	419
36b66c3f	420	void __init imx53_pm_init(void)
565fa91f	421	{
e20d7b52 AB	422	if (IS_ENABLED(CONFIG_SOC_IMX53))
e20d7b52 AB	423	imx5_pm_common_init(&imx53_pm_data);
565fa91f	424	}