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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
4dc28134 BS |
2 | #ifndef __NOUVEAU_DRV_H__ |
3 | #define __NOUVEAU_DRV_H__ | |
94580299 | 4 | |
77145f1c BS |
5 | #define DRIVER_AUTHOR "Nouveau Project" |
6 | #define DRIVER_EMAIL "[email protected]" | |
7 | ||
8 | #define DRIVER_NAME "nouveau" | |
451b58d2 | 9 | #define DRIVER_DESC "nVidia Riva/TNT/GeForce/Quadro/Tesla/Tegra K1+" |
77145f1c BS |
10 | #define DRIVER_DATE "20120801" |
11 | ||
12 | #define DRIVER_MAJOR 1 | |
a3c1ff87 | 13 | #define DRIVER_MINOR 3 |
79ef5dca | 14 | #define DRIVER_PATCHLEVEL 1 |
142c21b8 CB |
15 | |
16 | /* | |
17 | * 1.1.1: | |
18 | * - added support for tiled system memory buffer objects | |
19 | * - added support for NOUVEAU_GETPARAM_GRAPH_UNITS on [nvc0,nve0]. | |
20 | * - added support for compressed memory storage types on [nvc0,nve0]. | |
21 | * - added support for software methods 0x600,0x644,0x6ac on nvc0 | |
22 | * to control registers on the MPs to enable performance counters, | |
23 | * and to control the warp error enable mask (OpenGL requires out of | |
24 | * bounds access to local memory to be silently ignored / return 0). | |
7820e5ee MK |
25 | * 1.1.2: |
26 | * - fixes multiple bugs in flip completion events and timestamping | |
27111a23 BS |
27 | * 1.2.0: |
28 | * - object api exposed to userspace | |
29 | * - fermi,kepler,maxwell zbc | |
055dffdf ML |
30 | * 1.2.1: |
31 | * - allow concurrent access to bo's mapped read/write. | |
82452755 BS |
32 | * 1.2.2: |
33 | * - add NOUVEAU_GEM_DOMAIN_COHERENT flag | |
a3c1ff87 BS |
34 | * 1.3.0: |
35 | * - NVIF ABI modified, safe because only (current) users are test | |
36 | * programs that get directly linked with NVKM. | |
79ef5dca BS |
37 | * 1.3.1: |
38 | * - implemented limited ABI16/NVIF interop | |
142c21b8 | 39 | */ |
77145f1c | 40 | |
3a6536c5 HG |
41 | #include <linux/notifier.h> |
42 | ||
0ad72863 BS |
43 | #include <nvif/client.h> |
44 | #include <nvif/device.h> | |
f5e55187 | 45 | #include <nvif/ioctl.h> |
01670a79 | 46 | #include <nvif/mmu.h> |
96da0bcd | 47 | #include <nvif/vmm.h> |
0ad72863 | 48 | |
ae95621b | 49 | #include <drm/drmP.h> |
94580299 | 50 | |
612a9aab LT |
51 | #include <drm/ttm/ttm_bo_api.h> |
52 | #include <drm/ttm/ttm_bo_driver.h> | |
53 | #include <drm/ttm/ttm_placement.h> | |
54 | #include <drm/ttm/ttm_memory.h> | |
55 | #include <drm/ttm/ttm_module.h> | |
56 | #include <drm/ttm/ttm_page_alloc.h> | |
ebb945a9 | 57 | |
a4e610b5 BS |
58 | #include "uapi/drm/nouveau_drm.h" |
59 | ||
ebb945a9 | 60 | struct nouveau_channel; |
8ba9ff11 | 61 | struct platform_device; |
ebb945a9 BS |
62 | |
63 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) | |
64 | ||
ebb945a9 | 65 | #include "nouveau_fence.h" |
77145f1c | 66 | #include "nouveau_bios.h" |
24e8375b | 67 | #include "nouveau_vmm.h" |
ebb945a9 BS |
68 | |
69 | struct nouveau_drm_tile { | |
70 | struct nouveau_fence *fence; | |
71 | bool used; | |
72 | }; | |
73 | ||
0ad72863 | 74 | enum nouveau_drm_object_route { |
f5e55187 | 75 | NVDRM_OBJECT_NVIF = NVIF_IOCTL_V0_OWNER_NVIF, |
0ad72863 BS |
76 | NVDRM_OBJECT_USIF, |
77 | NVDRM_OBJECT_ABI16, | |
f5e55187 | 78 | NVDRM_OBJECT_ANY = NVIF_IOCTL_V0_OWNER_ANY, |
0ad72863 BS |
79 | }; |
80 | ||
81 | enum nouveau_drm_notify_route { | |
82 | NVDRM_NOTIFY_NVIF = 0, | |
83 | NVDRM_NOTIFY_USIF | |
84 | }; | |
85 | ||
94580299 | 86 | enum nouveau_drm_handle { |
26fdd78c | 87 | NVDRM_CHAN = 0xcccc0000, /* |= client chid */ |
69a6146d | 88 | NVDRM_NVSW = 0x55550000, |
94580299 BS |
89 | }; |
90 | ||
91 | struct nouveau_cli { | |
0ad72863 | 92 | struct nvif_client base; |
e75c091b | 93 | struct nouveau_drm *drm; |
20d8a88e BS |
94 | struct mutex mutex; |
95 | ||
1167c6bc | 96 | struct nvif_device device; |
01670a79 | 97 | struct nvif_mmu mmu; |
24e8375b | 98 | struct nouveau_vmm vmm; |
7f507624 | 99 | const struct nvif_mclass *mem; |
1167c6bc | 100 | |
94580299 | 101 | struct list_head head; |
ebb945a9 | 102 | void *abi16; |
27111a23 BS |
103 | struct list_head objects; |
104 | struct list_head notifys; | |
9ad97ede | 105 | char name[32]; |
cb7e88e7 | 106 | |
814a2324 BS |
107 | struct work_struct work; |
108 | struct list_head worker; | |
cb7e88e7 | 109 | struct mutex lock; |
94580299 BS |
110 | }; |
111 | ||
814a2324 BS |
112 | struct nouveau_cli_work { |
113 | void (*func)(struct nouveau_cli_work *); | |
114 | struct nouveau_cli *cli; | |
115 | struct list_head head; | |
116 | ||
117 | struct dma_fence *fence; | |
118 | struct dma_fence_cb cb; | |
119 | }; | |
120 | ||
121 | void nouveau_cli_work_queue(struct nouveau_cli *, struct dma_fence *, | |
122 | struct nouveau_cli_work *); | |
123 | ||
ebb945a9 BS |
124 | static inline struct nouveau_cli * |
125 | nouveau_cli(struct drm_file *fpriv) | |
126 | { | |
127 | return fpriv ? fpriv->driver_priv : NULL; | |
128 | } | |
129 | ||
967e7bde | 130 | #include <nvif/object.h> |
967e7bde | 131 | #include <nvif/device.h> |
db2bec18 | 132 | |
94580299 | 133 | struct nouveau_drm { |
cb7e88e7 | 134 | struct nouveau_cli master; |
94580299 BS |
135 | struct nouveau_cli client; |
136 | struct drm_device *dev; | |
137 | ||
94580299 | 138 | struct list_head clients; |
cb75d97e BS |
139 | |
140 | struct { | |
340b0e7c | 141 | struct agp_bridge_data *bridge; |
cb75d97e BS |
142 | u32 base; |
143 | u32 size; | |
340b0e7c | 144 | bool cma; |
cb75d97e | 145 | } agp; |
ebb945a9 BS |
146 | |
147 | /* TTM interface support */ | |
148 | struct { | |
149 | struct drm_global_reference mem_global_ref; | |
150 | struct ttm_bo_global_ref bo_global_ref; | |
151 | struct ttm_bo_device bdev; | |
152 | atomic_t validate_sequence; | |
153 | int (*move)(struct nouveau_channel *, | |
154 | struct ttm_buffer_object *, | |
155 | struct ttm_mem_reg *, struct ttm_mem_reg *); | |
1bb3f6a2 | 156 | struct nouveau_channel *chan; |
0ad72863 | 157 | struct nvif_object copy; |
ebb945a9 | 158 | int mtrr; |
658c71f4 | 159 | int type_vram; |
74a39954 BS |
160 | int type_host[2]; |
161 | int type_ncoh[2]; | |
ebb945a9 BS |
162 | } ttm; |
163 | ||
164 | /* GEM interface support */ | |
165 | struct { | |
166 | u64 vram_available; | |
167 | u64 gart_available; | |
168 | } gem; | |
169 | ||
170 | /* synchronisation */ | |
171 | void *fence; | |
172 | ||
eb47db4f BS |
173 | /* Global channel management. */ |
174 | struct { | |
175 | int nr; | |
176 | u64 context_base; | |
177 | } chan; | |
178 | ||
ebb945a9 | 179 | /* context for accelerated drm-internal operations */ |
49981046 | 180 | struct nouveau_channel *cechan; |
ebb945a9 | 181 | struct nouveau_channel *channel; |
be83cd4e | 182 | struct nvkm_gpuobj *notify; |
ebb945a9 | 183 | struct nouveau_fbdev *fbcon; |
0ad72863 BS |
184 | struct nvif_object nvsw; |
185 | struct nvif_object ntfy; | |
898a2b32 | 186 | struct nvif_notify flip; |
ebb945a9 BS |
187 | |
188 | /* nv10-nv40 tiling regions */ | |
189 | struct { | |
190 | struct nouveau_drm_tile reg[15]; | |
191 | spinlock_t lock; | |
192 | } tile; | |
51a3d342 | 193 | |
77145f1c BS |
194 | /* modesetting */ |
195 | struct nvbios vbios; | |
196 | struct nouveau_display *display; | |
81280d0e | 197 | struct work_struct hpd_work; |
15266ae3 LP |
198 | struct work_struct fbcon_work; |
199 | int fbcon_new_state; | |
3a6536c5 HG |
200 | #ifdef CONFIG_ACPI |
201 | struct notifier_block acpi_nb; | |
3a6536c5 | 202 | #endif |
77145f1c BS |
203 | |
204 | /* power management */ | |
b9ed919f | 205 | struct nouveau_hwmon *hwmon; |
b126a200 | 206 | struct nouveau_debugfs *debugfs; |
5addcf0a | 207 | |
8d021d71 MP |
208 | /* led management */ |
209 | struct nouveau_led *led; | |
210 | ||
5addcf0a DA |
211 | /* display power reference */ |
212 | bool have_disp_power_ref; | |
213 | ||
214 | struct dev_pm_domain vga_pm_domain; | |
94580299 BS |
215 | }; |
216 | ||
ebb945a9 BS |
217 | static inline struct nouveau_drm * |
218 | nouveau_drm(struct drm_device *dev) | |
219 | { | |
77145f1c BS |
220 | return dev->dev_private; |
221 | } | |
222 | ||
74a39954 BS |
223 | static inline bool |
224 | nouveau_drm_use_coherent_gpu_mapping(struct nouveau_drm *drm) | |
225 | { | |
226 | struct nvif_mmu *mmu = &drm->client.mmu; | |
227 | return !(mmu->type[drm->ttm.type_host[0]].type & NVIF_MEM_UNCACHED); | |
228 | } | |
229 | ||
2d8b9ccb DA |
230 | int nouveau_pmops_suspend(struct device *); |
231 | int nouveau_pmops_resume(struct device *); | |
321f5c5f | 232 | bool nouveau_pmops_runtime(void); |
94580299 | 233 | |
e396ecd1 AC |
234 | #include <nvkm/core/tegra.h> |
235 | ||
8ba9ff11 | 236 | struct drm_device * |
e396ecd1 AC |
237 | nouveau_platform_device_create(const struct nvkm_device_tegra_func *, |
238 | struct platform_device *, struct nvkm_device **); | |
8ba9ff11 AC |
239 | void nouveau_drm_device_remove(struct drm_device *dev); |
240 | ||
fa2bade9 BS |
241 | #define NV_PRINTK(l,c,f,a...) do { \ |
242 | struct nouveau_cli *_cli = (c); \ | |
e75c091b | 243 | dev_##l(_cli->drm->dev->dev, "%s: "f, _cli->name, ##a); \ |
fa2bade9 | 244 | } while(0) |
4c497075 | 245 | |
9ad97ede BS |
246 | #define NV_FATAL(drm,f,a...) NV_PRINTK(crit, &(drm)->client, f, ##a) |
247 | #define NV_ERROR(drm,f,a...) NV_PRINTK(err, &(drm)->client, f, ##a) | |
fa2bade9 BS |
248 | #define NV_WARN(drm,f,a...) NV_PRINTK(warn, &(drm)->client, f, ##a) |
249 | #define NV_INFO(drm,f,a...) NV_PRINTK(info, &(drm)->client, f, ##a) | |
4c497075 | 250 | |
9ad97ede BS |
251 | #define NV_DEBUG(drm,f,a...) do { \ |
252 | if (unlikely(drm_debug & DRM_UT_DRIVER)) \ | |
253 | NV_PRINTK(info, &(drm)->client, f, ##a); \ | |
254 | } while(0) | |
3dbd036b BS |
255 | #define NV_ATOMIC(drm,f,a...) do { \ |
256 | if (unlikely(drm_debug & DRM_UT_ATOMIC)) \ | |
257 | NV_PRINTK(info, &(drm)->client, f, ##a); \ | |
258 | } while(0) | |
94580299 | 259 | |
4c497075 LP |
260 | #define NV_PRINTK_ONCE(l,c,f,a...) NV_PRINTK(l##_once,c,f, ##a) |
261 | ||
262 | #define NV_ERROR_ONCE(drm,f,a...) NV_PRINTK_ONCE(err, &(drm)->client, f, ##a) | |
263 | #define NV_WARN_ONCE(drm,f,a...) NV_PRINTK_ONCE(warn, &(drm)->client, f, ##a) | |
264 | #define NV_INFO_ONCE(drm,f,a...) NV_PRINTK_ONCE(info, &(drm)->client, f, ##a) | |
265 | ||
9430738d BS |
266 | extern int nouveau_modeset; |
267 | ||
94580299 | 268 | #endif |