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drivers: net: generalize napi_complete_done()
[linux.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
CommitLineData
c0c050c5
MC		 1/* Broadcom NetXtreme-C/E network driver.
2 *
11f15ed3 3 * Copyright (c) 2014-2016 Broadcom Corporation
c0c050c5
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10#include <linux/module.h>
11
12#include <linux/stringify.h>
13#include <linux/kernel.h>
14#include <linux/timer.h>
15#include <linux/errno.h>
16#include <linux/ioport.h>
17#include <linux/slab.h>
18#include <linux/vmalloc.h>
19#include <linux/interrupt.h>
20#include <linux/pci.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/dma-mapping.h>
25#include <linux/bitops.h>
26#include <linux/io.h>
27#include <linux/irq.h>
28#include <linux/delay.h>
29#include <asm/byteorder.h>
30#include <asm/page.h>
31#include <linux/time.h>
32#include <linux/mii.h>
33#include <linux/if.h>
34#include <linux/if_vlan.h>
5ac67d8b 35#include <linux/rtc.h>
c0c050c5
MC		 36#include <net/ip.h>
37#include <net/tcp.h>
38#include <net/udp.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
ad51b8e9 41#include <net/udp_tunnel.h>
c0c050c5
MC		 42#include <linux/workqueue.h>
43#include <linux/prefetch.h>
44#include <linux/cache.h>
45#include <linux/log2.h>
46#include <linux/aer.h>
47#include <linux/bitmap.h>
48#include <linux/cpu_rmap.h>
49
50#include "bnxt_hsi.h"
51#include "bnxt.h"
a588e458 52#include "bnxt_ulp.h"
c0c050c5
MC		 53#include "bnxt_sriov.h"
54#include "bnxt_ethtool.h"
7df4ae9f 55#include "bnxt_dcb.h"
c0c050c5
MC		 56
57#define BNXT_TX_TIMEOUT (5 * HZ)
58
59static const char version[] =
60 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
61
62MODULE_LICENSE("GPL");
63MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
64MODULE_VERSION(DRV_MODULE_VERSION);
65
66#define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
67#define BNXT_RX_DMA_OFFSET NET_SKB_PAD
68#define BNXT_RX_COPY_THRESH 256
69
4419dbe6 70#define BNXT_TX_PUSH_THRESH 164
c0c050c5
MC		 71
72enum board_idx {
fbc9a523 73 BCM57301,
c0c050c5
MC		 74 BCM57302,
75 BCM57304,
1f681688 76 BCM57417_NPAR,
fa853dda 77 BCM58700,
b24eb6ae
MC		 78 BCM57311,
79 BCM57312,
fbc9a523 80 BCM57402,
c0c050c5
MC		 81 BCM57404,
82 BCM57406,
1f681688
MC		 83 BCM57402_NPAR,
84 BCM57407,
b24eb6ae
MC		 85 BCM57412,
86 BCM57414,
87 BCM57416,
88 BCM57417,
1f681688 89 BCM57412_NPAR,
5049e33b 90 BCM57314,
1f681688
MC		 91 BCM57417_SFP,
92 BCM57416_SFP,
93 BCM57404_NPAR,
94 BCM57406_NPAR,
95 BCM57407_SFP,
adbc8305 96 BCM57407_NPAR,
1f681688
MC		 97 BCM57414_NPAR,
98 BCM57416_NPAR,
adbc8305
MC		 99 NETXTREME_E_VF,
100 NETXTREME_C_VF,
c0c050c5
MC		 101};
102
103/* indexed by enum above */
104static const struct {
105 char *name;
106} board_info[] = {
adbc8305
MC		 107 { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
108 { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
109 { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
1f681688 110 { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
adbc8305
MC		 111 { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
112 { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
113 { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
114 { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
115 { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
116 { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
1f681688 117 { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
adbc8305
MC		 118 { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
119 { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
120 { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
121 { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
122 { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
1f681688 123 { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
adbc8305
MC		 124 { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
125 { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
126 { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
1f681688
MC		 127 { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
128 { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
adbc8305
MC		 129 { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
130 { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
1f681688
MC		 131 { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
132 { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
adbc8305
MC		 133 { "Broadcom NetXtreme-E Ethernet Virtual Function" },
134 { "Broadcom NetXtreme-C Ethernet Virtual Function" },
c0c050c5
MC		 135};
136
137static const struct pci_device_id bnxt_pci_tbl[] = {
adbc8305 138 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
fbc9a523 139 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
c0c050c5
MC		 140 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
141 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
1f681688 142 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
fa853dda 143 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
b24eb6ae
MC		 144 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
145 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
fbc9a523 146 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
c0c050c5
MC		 147 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
148 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
1f681688
MC		 149 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
150 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
b24eb6ae
MC		 151 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
152 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
153 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
154 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
1f681688 155 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
5049e33b 156 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
1f681688
MC		 157 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
158 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
159 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
160 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
161 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
adbc8305
MC		 162 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
163 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
1f681688 164 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
adbc8305 165 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
1f681688 166 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
adbc8305 167 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
c0c050c5 168#ifdef CONFIG_BNXT_SRIOV
adbc8305
MC		 169 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
170 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
171 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
172 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
173 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
174 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
c0c050c5
MC		 175#endif
176 { 0 }
177};
178
179MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
180
181static const u16 bnxt_vf_req_snif[] = {
182 HWRM_FUNC_CFG,
183 HWRM_PORT_PHY_QCFG,
184 HWRM_CFA_L2_FILTER_ALLOC,
185};
186
25be8623 187static const u16 bnxt_async_events_arr[] = {
87c374de
MC		 188 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
189 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
190 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
191 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
192 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
25be8623
MC		 193};
194
c0c050c5
MC		 195static bool bnxt_vf_pciid(enum board_idx idx)
196{
adbc8305 197 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF);
c0c050c5
MC		 198}
199
200#define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
201#define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
202#define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
203
204#define BNXT_CP_DB_REARM(db, raw_cons) \
205 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
206
207#define BNXT_CP_DB(db, raw_cons) \
208 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
209
210#define BNXT_CP_DB_IRQ_DIS(db) \
211 writel(DB_CP_IRQ_DIS_FLAGS, db)
212
213static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
214{
215 /* Tell compiler to fetch tx indices from memory. */
216 barrier();
217
218 return bp->tx_ring_size -
219 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
220}
221
222static const u16 bnxt_lhint_arr[] = {
223 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
224 TX_BD_FLAGS_LHINT_512_TO_1023,
225 TX_BD_FLAGS_LHINT_1024_TO_2047,
226 TX_BD_FLAGS_LHINT_1024_TO_2047,
227 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
228 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
229 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
230 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
231 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
232 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
233 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
234 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
235 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
236 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
237 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
238 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
239 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
240 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
241 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
242};
243
244static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
245{
246 struct bnxt *bp = netdev_priv(dev);
247 struct tx_bd *txbd;
248 struct tx_bd_ext *txbd1;
249 struct netdev_queue *txq;
250 int i;
251 dma_addr_t mapping;
252 unsigned int length, pad = 0;
253 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
254 u16 prod, last_frag;
255 struct pci_dev *pdev = bp->pdev;
c0c050c5
MC		 256 struct bnxt_tx_ring_info *txr;
257 struct bnxt_sw_tx_bd *tx_buf;
258
259 i = skb_get_queue_mapping(skb);
260 if (unlikely(i >= bp->tx_nr_rings)) {
261 dev_kfree_skb_any(skb);
262 return NETDEV_TX_OK;
263 }
264
b6ab4b01 265 txr = &bp->tx_ring[i];
c0c050c5
MC		 266 txq = netdev_get_tx_queue(dev, i);
267 prod = txr->tx_prod;
268
269 free_size = bnxt_tx_avail(bp, txr);
270 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
271 netif_tx_stop_queue(txq);
272 return NETDEV_TX_BUSY;
273 }
274
275 length = skb->len;
276 len = skb_headlen(skb);
277 last_frag = skb_shinfo(skb)->nr_frags;
278
279 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
280
281 txbd->tx_bd_opaque = prod;
282
283 tx_buf = &txr->tx_buf_ring[prod];
284 tx_buf->skb = skb;
285 tx_buf->nr_frags = last_frag;
286
287 vlan_tag_flags = 0;
288 cfa_action = 0;
289 if (skb_vlan_tag_present(skb)) {
290 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
291 skb_vlan_tag_get(skb);
292 /* Currently supports 8021Q, 8021AD vlan offloads
293 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
294 */
295 if (skb->vlan_proto == htons(ETH_P_8021Q))
296 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
297 }
298
299 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
4419dbe6
MC		 300 struct tx_push_buffer *tx_push_buf = txr->tx_push;
301 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
302 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
303 void *pdata = tx_push_buf->data;
304 u64 *end;
305 int j, push_len;
c0c050c5
MC		 306
307 /* Set COAL_NOW to be ready quickly for the next push */
308 tx_push->tx_bd_len_flags_type =
309 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
310 TX_BD_TYPE_LONG_TX_BD |
311 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
312 TX_BD_FLAGS_COAL_NOW |
313 TX_BD_FLAGS_PACKET_END |
314 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
315
316 if (skb->ip_summed == CHECKSUM_PARTIAL)
317 tx_push1->tx_bd_hsize_lflags =
318 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
319 else
320 tx_push1->tx_bd_hsize_lflags = 0;
321
322 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
323 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
324
fbb0fa8b
MC		 325 end = pdata + length;
326 end = PTR_ALIGN(end, 8) - 1;
4419dbe6
MC		 327 *end = 0;
328
c0c050c5
MC		 329 skb_copy_from_linear_data(skb, pdata, len);
330 pdata += len;
331 for (j = 0; j < last_frag; j++) {
332 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
333 void *fptr;
334
335 fptr = skb_frag_address_safe(frag);
336 if (!fptr)
337 goto normal_tx;
338
339 memcpy(pdata, fptr, skb_frag_size(frag));
340 pdata += skb_frag_size(frag);
341 }
342
4419dbe6
MC		 343 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
344 txbd->tx_bd_haddr = txr->data_mapping;
c0c050c5
MC		 345 prod = NEXT_TX(prod);
346 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
347 memcpy(txbd, tx_push1, sizeof(*txbd));
348 prod = NEXT_TX(prod);
4419dbe6 349 tx_push->doorbell =
c0c050c5
MC		 350 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
351 txr->tx_prod = prod;
352
b9a8460a 353 tx_buf->is_push = 1;
c0c050c5 354 netdev_tx_sent_queue(txq, skb->len);
b9a8460a 355 wmb(); /* Sync is_push and byte queue before pushing data */
c0c050c5 356
4419dbe6
MC		 357 push_len = (length + sizeof(*tx_push) + 7) / 8;
358 if (push_len > 16) {
359 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
9d13744b
MC		 360 __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
361 (push_len - 16) << 1);
4419dbe6
MC		 362 } else {
363 __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
364 push_len);
365 }
c0c050c5 366
c0c050c5
MC		 367 goto tx_done;
368 }
369
370normal_tx:
371 if (length < BNXT_MIN_PKT_SIZE) {
372 pad = BNXT_MIN_PKT_SIZE - length;
373 if (skb_pad(skb, pad)) {
374 /* SKB already freed. */
375 tx_buf->skb = NULL;
376 return NETDEV_TX_OK;
377 }
378 length = BNXT_MIN_PKT_SIZE;
379 }
380
381 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
382
383 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
384 dev_kfree_skb_any(skb);
385 tx_buf->skb = NULL;
386 return NETDEV_TX_OK;
387 }
388
389 dma_unmap_addr_set(tx_buf, mapping, mapping);
390 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
391 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
392
393 txbd->tx_bd_haddr = cpu_to_le64(mapping);
394
395 prod = NEXT_TX(prod);
396 txbd1 = (struct tx_bd_ext *)
397 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
398
399 txbd1->tx_bd_hsize_lflags = 0;
400 if (skb_is_gso(skb)) {
401 u32 hdr_len;
402
403 if (skb->encapsulation)
404 hdr_len = skb_inner_network_offset(skb) +
405 skb_inner_network_header_len(skb) +
406 inner_tcp_hdrlen(skb);
407 else
408 hdr_len = skb_transport_offset(skb) +
409 tcp_hdrlen(skb);
410
411 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
412 TX_BD_FLAGS_T_IPID |
413 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
414 length = skb_shinfo(skb)->gso_size;
415 txbd1->tx_bd_mss = cpu_to_le32(length);
416 length += hdr_len;
417 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
418 txbd1->tx_bd_hsize_lflags =
419 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
420 txbd1->tx_bd_mss = 0;
421 }
422
423 length >>= 9;
424 flags |= bnxt_lhint_arr[length];
425 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
426
427 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
428 txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
429 for (i = 0; i < last_frag; i++) {
430 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
431
432 prod = NEXT_TX(prod);
433 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
434
435 len = skb_frag_size(frag);
436 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
437 DMA_TO_DEVICE);
438
439 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
440 goto tx_dma_error;
441
442 tx_buf = &txr->tx_buf_ring[prod];
443 dma_unmap_addr_set(tx_buf, mapping, mapping);
444
445 txbd->tx_bd_haddr = cpu_to_le64(mapping);
446
447 flags = len << TX_BD_LEN_SHIFT;
448 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
449 }
450
451 flags &= ~TX_BD_LEN;
452 txbd->tx_bd_len_flags_type =
453 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
454 TX_BD_FLAGS_PACKET_END);
455
456 netdev_tx_sent_queue(txq, skb->len);
457
458 /* Sync BD data before updating doorbell */
459 wmb();
460
461 prod = NEXT_TX(prod);
462 txr->tx_prod = prod;
463
464 writel(DB_KEY_TX | prod, txr->tx_doorbell);
465 writel(DB_KEY_TX | prod, txr->tx_doorbell);
466
467tx_done:
468
469 mmiowb();
470
471 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
472 netif_tx_stop_queue(txq);
473
474 /* netif_tx_stop_queue() must be done before checking
475 * tx index in bnxt_tx_avail() below, because in
476 * bnxt_tx_int(), we update tx index before checking for
477 * netif_tx_queue_stopped().
478 */
479 smp_mb();
480 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
481 netif_tx_wake_queue(txq);
482 }
483 return NETDEV_TX_OK;
484
485tx_dma_error:
486 last_frag = i;
487
488 /* start back at beginning and unmap skb */
489 prod = txr->tx_prod;
490 tx_buf = &txr->tx_buf_ring[prod];
491 tx_buf->skb = NULL;
492 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
493 skb_headlen(skb), PCI_DMA_TODEVICE);
494 prod = NEXT_TX(prod);
495
496 /* unmap remaining mapped pages */
497 for (i = 0; i < last_frag; i++) {
498 prod = NEXT_TX(prod);
499 tx_buf = &txr->tx_buf_ring[prod];
500 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
501 skb_frag_size(&skb_shinfo(skb)->frags[i]),
502 PCI_DMA_TODEVICE);
503 }
504
505 dev_kfree_skb_any(skb);
506 return NETDEV_TX_OK;
507}
508
509static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
510{
b6ab4b01 511 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
b81a90d3 512 int index = txr - &bp->tx_ring[0];
c0c050c5
MC		 513 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
514 u16 cons = txr->tx_cons;
515 struct pci_dev *pdev = bp->pdev;
516 int i;
517 unsigned int tx_bytes = 0;
518
519 for (i = 0; i < nr_pkts; i++) {
520 struct bnxt_sw_tx_bd *tx_buf;
521 struct sk_buff *skb;
522 int j, last;
523
524 tx_buf = &txr->tx_buf_ring[cons];
525 cons = NEXT_TX(cons);
526 skb = tx_buf->skb;
527 tx_buf->skb = NULL;
528
529 if (tx_buf->is_push) {
530 tx_buf->is_push = 0;
531 goto next_tx_int;
532 }
533
534 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
535 skb_headlen(skb), PCI_DMA_TODEVICE);
536 last = tx_buf->nr_frags;
537
538 for (j = 0; j < last; j++) {
539 cons = NEXT_TX(cons);
540 tx_buf = &txr->tx_buf_ring[cons];
541 dma_unmap_page(
542 &pdev->dev,
543 dma_unmap_addr(tx_buf, mapping),
544 skb_frag_size(&skb_shinfo(skb)->frags[j]),
545 PCI_DMA_TODEVICE);
546 }
547
548next_tx_int:
549 cons = NEXT_TX(cons);
550
551 tx_bytes += skb->len;
552 dev_kfree_skb_any(skb);
553 }
554
555 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
556 txr->tx_cons = cons;
557
558 /* Need to make the tx_cons update visible to bnxt_start_xmit()
559 * before checking for netif_tx_queue_stopped(). Without the
560 * memory barrier, there is a small possibility that bnxt_start_xmit()
561 * will miss it and cause the queue to be stopped forever.
562 */
563 smp_mb();
564
565 if (unlikely(netif_tx_queue_stopped(txq)) &&
566 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
567 __netif_tx_lock(txq, smp_processor_id());
568 if (netif_tx_queue_stopped(txq) &&
569 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
570 txr->dev_state != BNXT_DEV_STATE_CLOSING)
571 netif_tx_wake_queue(txq);
572 __netif_tx_unlock(txq);
573 }
574}
575
576static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
577 gfp_t gfp)
578{
579 u8 *data;
580 struct pci_dev *pdev = bp->pdev;
581
582 data = kmalloc(bp->rx_buf_size, gfp);
583 if (!data)
584 return NULL;
585
586 *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
587 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
588
589 if (dma_mapping_error(&pdev->dev, *mapping)) {
590 kfree(data);
591 data = NULL;
592 }
593 return data;
594}
595
596static inline int bnxt_alloc_rx_data(struct bnxt *bp,
597 struct bnxt_rx_ring_info *rxr,
598 u16 prod, gfp_t gfp)
599{
600 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
601 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
602 u8 *data;
603 dma_addr_t mapping;
604
605 data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
606 if (!data)
607 return -ENOMEM;
608
609 rx_buf->data = data;
610 dma_unmap_addr_set(rx_buf, mapping, mapping);
611
612 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
613
614 return 0;
615}
616
617static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
618 u8 *data)
619{
620 u16 prod = rxr->rx_prod;
621 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
622 struct rx_bd *cons_bd, *prod_bd;
623
624 prod_rx_buf = &rxr->rx_buf_ring[prod];
625 cons_rx_buf = &rxr->rx_buf_ring[cons];
626
627 prod_rx_buf->data = data;
628
629 dma_unmap_addr_set(prod_rx_buf, mapping,
630 dma_unmap_addr(cons_rx_buf, mapping));
631
632 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
633 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
634
635 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
636}
637
638static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
639{
640 u16 next, max = rxr->rx_agg_bmap_size;
641
642 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
643 if (next >= max)
644 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
645 return next;
646}
647
648static inline int bnxt_alloc_rx_page(struct bnxt *bp,
649 struct bnxt_rx_ring_info *rxr,
650 u16 prod, gfp_t gfp)
651{
652 struct rx_bd *rxbd =
653 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
654 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
655 struct pci_dev *pdev = bp->pdev;
656 struct page *page;
657 dma_addr_t mapping;
658 u16 sw_prod = rxr->rx_sw_agg_prod;
89d0a06c 659 unsigned int offset = 0;
c0c050c5 660
89d0a06c
MC		 661 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
662 page = rxr->rx_page;
663 if (!page) {
664 page = alloc_page(gfp);
665 if (!page)
666 return -ENOMEM;
667 rxr->rx_page = page;
668 rxr->rx_page_offset = 0;
669 }
670 offset = rxr->rx_page_offset;
671 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
672 if (rxr->rx_page_offset == PAGE_SIZE)
673 rxr->rx_page = NULL;
674 else
675 get_page(page);
676 } else {
677 page = alloc_page(gfp);
678 if (!page)
679 return -ENOMEM;
680 }
c0c050c5 681
89d0a06c 682 mapping = dma_map_page(&pdev->dev, page, offset, BNXT_RX_PAGE_SIZE,
c0c050c5
MC		 683 PCI_DMA_FROMDEVICE);
684 if (dma_mapping_error(&pdev->dev, mapping)) {
685 __free_page(page);
686 return -EIO;
687 }
688
689 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
690 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
691
692 __set_bit(sw_prod, rxr->rx_agg_bmap);
693 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
694 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
695
696 rx_agg_buf->page = page;
89d0a06c 697 rx_agg_buf->offset = offset;
c0c050c5
MC		 698 rx_agg_buf->mapping = mapping;
699 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
700 rxbd->rx_bd_opaque = sw_prod;
701 return 0;
702}
703
704static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
705 u32 agg_bufs)
706{
707 struct bnxt *bp = bnapi->bp;
708 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 709 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 710 u16 prod = rxr->rx_agg_prod;
711 u16 sw_prod = rxr->rx_sw_agg_prod;
712 u32 i;
713
714 for (i = 0; i < agg_bufs; i++) {
715 u16 cons;
716 struct rx_agg_cmp *agg;
717 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
718 struct rx_bd *prod_bd;
719 struct page *page;
720
721 agg = (struct rx_agg_cmp *)
722 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
723 cons = agg->rx_agg_cmp_opaque;
724 __clear_bit(cons, rxr->rx_agg_bmap);
725
726 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
727 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
728
729 __set_bit(sw_prod, rxr->rx_agg_bmap);
730 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
731 cons_rx_buf = &rxr->rx_agg_ring[cons];
732
733 /* It is possible for sw_prod to be equal to cons, so
734 * set cons_rx_buf->page to NULL first.
735 */
736 page = cons_rx_buf->page;
737 cons_rx_buf->page = NULL;
738 prod_rx_buf->page = page;
89d0a06c 739 prod_rx_buf->offset = cons_rx_buf->offset;
c0c050c5
MC		 740
741 prod_rx_buf->mapping = cons_rx_buf->mapping;
742
743 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
744
745 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
746 prod_bd->rx_bd_opaque = sw_prod;
747
748 prod = NEXT_RX_AGG(prod);
749 sw_prod = NEXT_RX_AGG(sw_prod);
750 cp_cons = NEXT_CMP(cp_cons);
751 }
752 rxr->rx_agg_prod = prod;
753 rxr->rx_sw_agg_prod = sw_prod;
754}
755
756static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
757 struct bnxt_rx_ring_info *rxr, u16 cons,
758 u16 prod, u8 *data, dma_addr_t dma_addr,
759 unsigned int len)
760{
761 int err;
762 struct sk_buff *skb;
763
764 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
765 if (unlikely(err)) {
766 bnxt_reuse_rx_data(rxr, cons, data);
767 return NULL;
768 }
769
770 skb = build_skb(data, 0);
771 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
772 PCI_DMA_FROMDEVICE);
773 if (!skb) {
774 kfree(data);
775 return NULL;
776 }
777
778 skb_reserve(skb, BNXT_RX_OFFSET);
779 skb_put(skb, len);
780 return skb;
781}
782
783static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
784 struct sk_buff *skb, u16 cp_cons,
785 u32 agg_bufs)
786{
787 struct pci_dev *pdev = bp->pdev;
788 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 789 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 790 u16 prod = rxr->rx_agg_prod;
791 u32 i;
792
793 for (i = 0; i < agg_bufs; i++) {
794 u16 cons, frag_len;
795 struct rx_agg_cmp *agg;
796 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
797 struct page *page;
798 dma_addr_t mapping;
799
800 agg = (struct rx_agg_cmp *)
801 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
802 cons = agg->rx_agg_cmp_opaque;
803 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
804 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
805
806 cons_rx_buf = &rxr->rx_agg_ring[cons];
89d0a06c
MC		 807 skb_fill_page_desc(skb, i, cons_rx_buf->page,
808 cons_rx_buf->offset, frag_len);
c0c050c5
MC		 809 __clear_bit(cons, rxr->rx_agg_bmap);
810
811 /* It is possible for bnxt_alloc_rx_page() to allocate
812 * a sw_prod index that equals the cons index, so we
813 * need to clear the cons entry now.
814 */
815 mapping = dma_unmap_addr(cons_rx_buf, mapping);
816 page = cons_rx_buf->page;
817 cons_rx_buf->page = NULL;
818
819 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
820 struct skb_shared_info *shinfo;
821 unsigned int nr_frags;
822
823 shinfo = skb_shinfo(skb);
824 nr_frags = --shinfo->nr_frags;
825 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
826
827 dev_kfree_skb(skb);
828
829 cons_rx_buf->page = page;
830
831 /* Update prod since possibly some pages have been
832 * allocated already.
833 */
834 rxr->rx_agg_prod = prod;
835 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
836 return NULL;
837 }
838
2839f28b 839 dma_unmap_page(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
c0c050c5
MC		 840 PCI_DMA_FROMDEVICE);
841
842 skb->data_len += frag_len;
843 skb->len += frag_len;
844 skb->truesize += PAGE_SIZE;
845
846 prod = NEXT_RX_AGG(prod);
847 cp_cons = NEXT_CMP(cp_cons);
848 }
849 rxr->rx_agg_prod = prod;
850 return skb;
851}
852
853static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
854 u8 agg_bufs, u32 *raw_cons)
855{
856 u16 last;
857 struct rx_agg_cmp *agg;
858
859 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
860 last = RING_CMP(*raw_cons);
861 agg = (struct rx_agg_cmp *)
862 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
863 return RX_AGG_CMP_VALID(agg, *raw_cons);
864}
865
866static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
867 unsigned int len,
868 dma_addr_t mapping)
869{
870 struct bnxt *bp = bnapi->bp;
871 struct pci_dev *pdev = bp->pdev;
872 struct sk_buff *skb;
873
874 skb = napi_alloc_skb(&bnapi->napi, len);
875 if (!skb)
876 return NULL;
877
878 dma_sync_single_for_cpu(&pdev->dev, mapping,
879 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
880
881 memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
882
883 dma_sync_single_for_device(&pdev->dev, mapping,
884 bp->rx_copy_thresh,
885 PCI_DMA_FROMDEVICE);
886
887 skb_put(skb, len);
888 return skb;
889}
890
fa7e2812
MC		 891static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
892 u32 *raw_cons, void *cmp)
893{
894 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
895 struct rx_cmp *rxcmp = cmp;
896 u32 tmp_raw_cons = *raw_cons;
897 u8 cmp_type, agg_bufs = 0;
898
899 cmp_type = RX_CMP_TYPE(rxcmp);
900
901 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
902 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
903 RX_CMP_AGG_BUFS) >>
904 RX_CMP_AGG_BUFS_SHIFT;
905 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
906 struct rx_tpa_end_cmp *tpa_end = cmp;
907
908 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
909 RX_TPA_END_CMP_AGG_BUFS) >>
910 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
911 }
912
913 if (agg_bufs) {
914 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
915 return -EBUSY;
916 }
917 *raw_cons = tmp_raw_cons;
918 return 0;
919}
920
921static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
922{
923 if (!rxr->bnapi->in_reset) {
924 rxr->bnapi->in_reset = true;
925 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
926 schedule_work(&bp->sp_task);
927 }
928 rxr->rx_next_cons = 0xffff;
929}
930
c0c050c5
MC		 931static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
932 struct rx_tpa_start_cmp *tpa_start,
933 struct rx_tpa_start_cmp_ext *tpa_start1)
934{
935 u8 agg_id = TPA_START_AGG_ID(tpa_start);
936 u16 cons, prod;
937 struct bnxt_tpa_info *tpa_info;
938 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
939 struct rx_bd *prod_bd;
940 dma_addr_t mapping;
941
942 cons = tpa_start->rx_tpa_start_cmp_opaque;
943 prod = rxr->rx_prod;
944 cons_rx_buf = &rxr->rx_buf_ring[cons];
945 prod_rx_buf = &rxr->rx_buf_ring[prod];
946 tpa_info = &rxr->rx_tpa[agg_id];
947
fa7e2812
MC		 948 if (unlikely(cons != rxr->rx_next_cons)) {
949 bnxt_sched_reset(bp, rxr);
950 return;
951 }
952
c0c050c5
MC		 953 prod_rx_buf->data = tpa_info->data;
954
955 mapping = tpa_info->mapping;
956 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
957
958 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
959
960 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
961
962 tpa_info->data = cons_rx_buf->data;
963 cons_rx_buf->data = NULL;
964 tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
965
966 tpa_info->len =
967 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
968 RX_TPA_START_CMP_LEN_SHIFT;
969 if (likely(TPA_START_HASH_VALID(tpa_start))) {
970 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
971
972 tpa_info->hash_type = PKT_HASH_TYPE_L4;
973 tpa_info->gso_type = SKB_GSO_TCPV4;
974 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
975 if (hash_type == 3)
976 tpa_info->gso_type = SKB_GSO_TCPV6;
977 tpa_info->rss_hash =
978 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
979 } else {
980 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
981 tpa_info->gso_type = 0;
982 if (netif_msg_rx_err(bp))
983 netdev_warn(bp->dev, "TPA packet without valid hash\n");
984 }
985 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
986 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
94758f8d 987 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
c0c050c5
MC		 988
989 rxr->rx_prod = NEXT_RX(prod);
990 cons = NEXT_RX(cons);
376a5b86 991 rxr->rx_next_cons = NEXT_RX(cons);
c0c050c5
MC		 992 cons_rx_buf = &rxr->rx_buf_ring[cons];
993
994 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
995 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
996 cons_rx_buf->data = NULL;
997}
998
999static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1000 u16 cp_cons, u32 agg_bufs)
1001{
1002 if (agg_bufs)
1003 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1004}
1005
94758f8d
MC		 1006static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1007 int payload_off, int tcp_ts,
1008 struct sk_buff *skb)
1009{
1010#ifdef CONFIG_INET
1011 struct tcphdr *th;
1012 int len, nw_off;
1013 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1014 u32 hdr_info = tpa_info->hdr_info;
1015 bool loopback = false;
1016
1017 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1018 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1019 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1020
1021 /* If the packet is an internal loopback packet, the offsets will
1022 * have an extra 4 bytes.
1023 */
1024 if (inner_mac_off == 4) {
1025 loopback = true;
1026 } else if (inner_mac_off > 4) {
1027 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1028 ETH_HLEN - 2));
1029
1030 /* We only support inner iPv4/ipv6. If we don't see the
1031 * correct protocol ID, it must be a loopback packet where
1032 * the offsets are off by 4.
1033 */
09a7636a 1034 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
94758f8d
MC		 1035 loopback = true;
1036 }
1037 if (loopback) {
1038 /* internal loopback packet, subtract all offsets by 4 */
1039 inner_ip_off -= 4;
1040 inner_mac_off -= 4;
1041 outer_ip_off -= 4;
1042 }
1043
1044 nw_off = inner_ip_off - ETH_HLEN;
1045 skb_set_network_header(skb, nw_off);
1046 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1047 struct ipv6hdr *iph = ipv6_hdr(skb);
1048
1049 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1050 len = skb->len - skb_transport_offset(skb);
1051 th = tcp_hdr(skb);
1052 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1053 } else {
1054 struct iphdr *iph = ip_hdr(skb);
1055
1056 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1057 len = skb->len - skb_transport_offset(skb);
1058 th = tcp_hdr(skb);
1059 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1060 }
1061
1062 if (inner_mac_off) { /* tunnel */
1063 struct udphdr *uh = NULL;
1064 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1065 ETH_HLEN - 2));
1066
1067 if (proto == htons(ETH_P_IP)) {
1068 struct iphdr *iph = (struct iphdr *)skb->data;
1069
1070 if (iph->protocol == IPPROTO_UDP)
1071 uh = (struct udphdr *)(iph + 1);
1072 } else {
1073 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1074
1075 if (iph->nexthdr == IPPROTO_UDP)
1076 uh = (struct udphdr *)(iph + 1);
1077 }
1078 if (uh) {
1079 if (uh->check)
1080 skb_shinfo(skb)->gso_type |=
1081 SKB_GSO_UDP_TUNNEL_CSUM;
1082 else
1083 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1084 }
1085 }
1086#endif
1087 return skb;
1088}
1089
c0c050c5
MC		 1090#define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1091#define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1092
309369c9
MC		 1093static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1094 int payload_off, int tcp_ts,
c0c050c5
MC		 1095 struct sk_buff *skb)
1096{
d1611c3a 1097#ifdef CONFIG_INET
c0c050c5 1098 struct tcphdr *th;
719ca811 1099 int len, nw_off, tcp_opt_len = 0;
27e24189 1100
309369c9 1101 if (tcp_ts)
c0c050c5
MC		 1102 tcp_opt_len = 12;
1103
c0c050c5
MC		 1104 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1105 struct iphdr *iph;
1106
1107 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1108 ETH_HLEN;
1109 skb_set_network_header(skb, nw_off);
1110 iph = ip_hdr(skb);
1111 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1112 len = skb->len - skb_transport_offset(skb);
1113 th = tcp_hdr(skb);
1114 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1115 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1116 struct ipv6hdr *iph;
1117
1118 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1119 ETH_HLEN;
1120 skb_set_network_header(skb, nw_off);
1121 iph = ipv6_hdr(skb);
1122 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1123 len = skb->len - skb_transport_offset(skb);
1124 th = tcp_hdr(skb);
1125 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1126 } else {
1127 dev_kfree_skb_any(skb);
1128 return NULL;
1129 }
c0c050c5
MC		 1130
1131 if (nw_off) { /* tunnel */
1132 struct udphdr *uh = NULL;
1133
1134 if (skb->protocol == htons(ETH_P_IP)) {
1135 struct iphdr *iph = (struct iphdr *)skb->data;
1136
1137 if (iph->protocol == IPPROTO_UDP)
1138 uh = (struct udphdr *)(iph + 1);
1139 } else {
1140 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1141
1142 if (iph->nexthdr == IPPROTO_UDP)
1143 uh = (struct udphdr *)(iph + 1);
1144 }
1145 if (uh) {
1146 if (uh->check)
1147 skb_shinfo(skb)->gso_type |=
1148 SKB_GSO_UDP_TUNNEL_CSUM;
1149 else
1150 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1151 }
1152 }
1153#endif
1154 return skb;
1155}
1156
309369c9
MC		 1157static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1158 struct bnxt_tpa_info *tpa_info,
1159 struct rx_tpa_end_cmp *tpa_end,
1160 struct rx_tpa_end_cmp_ext *tpa_end1,
1161 struct sk_buff *skb)
1162{
1163#ifdef CONFIG_INET
1164 int payload_off;
1165 u16 segs;
1166
1167 segs = TPA_END_TPA_SEGS(tpa_end);
1168 if (segs == 1)
1169 return skb;
1170
1171 NAPI_GRO_CB(skb)->count = segs;
1172 skb_shinfo(skb)->gso_size =
1173 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1174 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1175 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1176 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1177 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1178 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
5910906c
MC		 1179 if (likely(skb))
1180 tcp_gro_complete(skb);
309369c9
MC		 1181#endif
1182 return skb;
1183}
1184
c0c050c5
MC		 1185static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1186 struct bnxt_napi *bnapi,
1187 u32 *raw_cons,
1188 struct rx_tpa_end_cmp *tpa_end,
1189 struct rx_tpa_end_cmp_ext *tpa_end1,
1190 bool *agg_event)
1191{
1192 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 1193 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1194 u8 agg_id = TPA_END_AGG_ID(tpa_end);
1195 u8 *data, agg_bufs;
1196 u16 cp_cons = RING_CMP(*raw_cons);
1197 unsigned int len;
1198 struct bnxt_tpa_info *tpa_info;
1199 dma_addr_t mapping;
1200 struct sk_buff *skb;
1201
fa7e2812
MC		 1202 if (unlikely(bnapi->in_reset)) {
1203 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1204
1205 if (rc < 0)
1206 return ERR_PTR(-EBUSY);
1207 return NULL;
1208 }
1209
c0c050c5
MC		 1210 tpa_info = &rxr->rx_tpa[agg_id];
1211 data = tpa_info->data;
1212 prefetch(data);
1213 len = tpa_info->len;
1214 mapping = tpa_info->mapping;
1215
1216 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1217 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1218
1219 if (agg_bufs) {
1220 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1221 return ERR_PTR(-EBUSY);
1222
1223 *agg_event = true;
1224 cp_cons = NEXT_CMP(cp_cons);
1225 }
1226
1227 if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
1228 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1229 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1230 agg_bufs, (int)MAX_SKB_FRAGS);
1231 return NULL;
1232 }
1233
1234 if (len <= bp->rx_copy_thresh) {
1235 skb = bnxt_copy_skb(bnapi, data, len, mapping);
1236 if (!skb) {
1237 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1238 return NULL;
1239 }
1240 } else {
1241 u8 *new_data;
1242 dma_addr_t new_mapping;
1243
1244 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1245 if (!new_data) {
1246 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1247 return NULL;
1248 }
1249
1250 tpa_info->data = new_data;
1251 tpa_info->mapping = new_mapping;
1252
1253 skb = build_skb(data, 0);
1254 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
1255 PCI_DMA_FROMDEVICE);
1256
1257 if (!skb) {
1258 kfree(data);
1259 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1260 return NULL;
1261 }
1262 skb_reserve(skb, BNXT_RX_OFFSET);
1263 skb_put(skb, len);
1264 }
1265
1266 if (agg_bufs) {
1267 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1268 if (!skb) {
1269 /* Page reuse already handled by bnxt_rx_pages(). */
1270 return NULL;
1271 }
1272 }
1273 skb->protocol = eth_type_trans(skb, bp->dev);
1274
1275 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1276 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1277
8852ddb4
MC		 1278 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1279 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
c0c050c5
MC		 1280 u16 vlan_proto = tpa_info->metadata >>
1281 RX_CMP_FLAGS2_METADATA_TPID_SFT;
8852ddb4 1282 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
c0c050c5 1283
8852ddb4 1284 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
c0c050c5
MC		 1285 }
1286
1287 skb_checksum_none_assert(skb);
1288 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1289 skb->ip_summed = CHECKSUM_UNNECESSARY;
1290 skb->csum_level =
1291 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1292 }
1293
1294 if (TPA_END_GRO(tpa_end))
309369c9 1295 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
c0c050c5
MC		 1296
1297 return skb;
1298}
1299
1300/* returns the following:
1301 * 1 - 1 packet successfully received
1302 * 0 - successful TPA_START, packet not completed yet
1303 * -EBUSY - completion ring does not have all the agg buffers yet
1304 * -ENOMEM - packet aborted due to out of memory
1305 * -EIO - packet aborted due to hw error indicated in BD
1306 */
1307static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1308 bool *agg_event)
1309{
1310 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
b6ab4b01 1311 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1312 struct net_device *dev = bp->dev;
1313 struct rx_cmp *rxcmp;
1314 struct rx_cmp_ext *rxcmp1;
1315 u32 tmp_raw_cons = *raw_cons;
1316 u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1317 struct bnxt_sw_rx_bd *rx_buf;
1318 unsigned int len;
1319 u8 *data, agg_bufs, cmp_type;
1320 dma_addr_t dma_addr;
1321 struct sk_buff *skb;
1322 int rc = 0;
1323
1324 rxcmp = (struct rx_cmp *)
1325 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1326
1327 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1328 cp_cons = RING_CMP(tmp_raw_cons);
1329 rxcmp1 = (struct rx_cmp_ext *)
1330 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1331
1332 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1333 return -EBUSY;
1334
1335 cmp_type = RX_CMP_TYPE(rxcmp);
1336
1337 prod = rxr->rx_prod;
1338
1339 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1340 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1341 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1342
1343 goto next_rx_no_prod;
1344
1345 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1346 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1347 (struct rx_tpa_end_cmp *)rxcmp,
1348 (struct rx_tpa_end_cmp_ext *)rxcmp1,
1349 agg_event);
1350
1351 if (unlikely(IS_ERR(skb)))
1352 return -EBUSY;
1353
1354 rc = -ENOMEM;
1355 if (likely(skb)) {
1356 skb_record_rx_queue(skb, bnapi->index);
b356a2e7 1357 napi_gro_receive(&bnapi->napi, skb);
c0c050c5
MC		 1358 rc = 1;
1359 }
1360 goto next_rx_no_prod;
1361 }
1362
1363 cons = rxcmp->rx_cmp_opaque;
1364 rx_buf = &rxr->rx_buf_ring[cons];
1365 data = rx_buf->data;
fa7e2812
MC		 1366 if (unlikely(cons != rxr->rx_next_cons)) {
1367 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1368
1369 bnxt_sched_reset(bp, rxr);
1370 return rc1;
1371 }
c0c050c5
MC		 1372 prefetch(data);
1373
1374 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1375 RX_CMP_AGG_BUFS_SHIFT;
1376
1377 if (agg_bufs) {
1378 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1379 return -EBUSY;
1380
1381 cp_cons = NEXT_CMP(cp_cons);
1382 *agg_event = true;
1383 }
1384
1385 rx_buf->data = NULL;
1386 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1387 bnxt_reuse_rx_data(rxr, cons, data);
1388 if (agg_bufs)
1389 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1390
1391 rc = -EIO;
1392 goto next_rx;
1393 }
1394
1395 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1396 dma_addr = dma_unmap_addr(rx_buf, mapping);
1397
1398 if (len <= bp->rx_copy_thresh) {
1399 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1400 bnxt_reuse_rx_data(rxr, cons, data);
1401 if (!skb) {
1402 rc = -ENOMEM;
1403 goto next_rx;
1404 }
1405 } else {
1406 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1407 if (!skb) {
1408 rc = -ENOMEM;
1409 goto next_rx;
1410 }
1411 }
1412
1413 if (agg_bufs) {
1414 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1415 if (!skb) {
1416 rc = -ENOMEM;
1417 goto next_rx;
1418 }
1419 }
1420
1421 if (RX_CMP_HASH_VALID(rxcmp)) {
1422 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1423 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1424
1425 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1426 if (hash_type != 1 && hash_type != 3)
1427 type = PKT_HASH_TYPE_L3;
1428 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1429 }
1430
1431 skb->protocol = eth_type_trans(skb, dev);
1432
8852ddb4
MC		 1433 if ((rxcmp1->rx_cmp_flags2 &
1434 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1435 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
c0c050c5 1436 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
8852ddb4 1437 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
c0c050c5
MC		 1438 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1439
8852ddb4 1440 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
c0c050c5
MC		 1441 }
1442
1443 skb_checksum_none_assert(skb);
1444 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1445 if (dev->features & NETIF_F_RXCSUM) {
1446 skb->ip_summed = CHECKSUM_UNNECESSARY;
1447 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1448 }
1449 } else {
665e350d
SB		 1450 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1451 if (dev->features & NETIF_F_RXCSUM)
1452 cpr->rx_l4_csum_errors++;
1453 }
c0c050c5
MC		 1454 }
1455
1456 skb_record_rx_queue(skb, bnapi->index);
b356a2e7 1457 napi_gro_receive(&bnapi->napi, skb);
c0c050c5
MC		 1458 rc = 1;
1459
1460next_rx:
1461 rxr->rx_prod = NEXT_RX(prod);
376a5b86 1462 rxr->rx_next_cons = NEXT_RX(cons);
c0c050c5
MC		 1463
1464next_rx_no_prod:
1465 *raw_cons = tmp_raw_cons;
1466
1467 return rc;
1468}
1469
4bb13abf 1470#define BNXT_GET_EVENT_PORT(data) \
87c374de
MC		 1471 ((data) & \
1472 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
4bb13abf 1473
c0c050c5
MC		 1474static int bnxt_async_event_process(struct bnxt *bp,
1475 struct hwrm_async_event_cmpl *cmpl)
1476{
1477 u16 event_id = le16_to_cpu(cmpl->event_id);
1478
1479 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1480 switch (event_id) {
87c374de 1481 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
8cbde117
MC		 1482 u32 data1 = le32_to_cpu(cmpl->event_data1);
1483 struct bnxt_link_info *link_info = &bp->link_info;
1484
1485 if (BNXT_VF(bp))
1486 goto async_event_process_exit;
1487 if (data1 & 0x20000) {
1488 u16 fw_speed = link_info->force_link_speed;
1489 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1490
1491 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1492 speed);
1493 }
286ef9d6 1494 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
8cbde117
MC		 1495 /* fall thru */
1496 }
87c374de 1497 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
c0c050c5 1498 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
19241368 1499 break;
87c374de 1500 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
19241368 1501 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
c0c050c5 1502 break;
87c374de 1503 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
4bb13abf
MC		 1504 u32 data1 = le32_to_cpu(cmpl->event_data1);
1505 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1506
1507 if (BNXT_VF(bp))
1508 break;
1509
1510 if (bp->pf.port_id != port_id)
1511 break;
1512
4bb13abf
MC		 1513 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1514 break;
1515 }
87c374de 1516 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
fc0f1929
MC		 1517 if (BNXT_PF(bp))
1518 goto async_event_process_exit;
1519 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1520 break;
c0c050c5 1521 default:
19241368 1522 goto async_event_process_exit;
c0c050c5 1523 }
19241368
JH		 1524 schedule_work(&bp->sp_task);
1525async_event_process_exit:
a588e458 1526 bnxt_ulp_async_events(bp, cmpl);
c0c050c5
MC		 1527 return 0;
1528}
1529
1530static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1531{
1532 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1533 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1534 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1535 (struct hwrm_fwd_req_cmpl *)txcmp;
1536
1537 switch (cmpl_type) {
1538 case CMPL_BASE_TYPE_HWRM_DONE:
1539 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1540 if (seq_id == bp->hwrm_intr_seq_id)
1541 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1542 else
1543 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1544 break;
1545
1546 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1547 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1548
1549 if ((vf_id < bp->pf.first_vf_id) ||
1550 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1551 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1552 vf_id);
1553 return -EINVAL;
1554 }
1555
1556 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1557 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1558 schedule_work(&bp->sp_task);
1559 break;
1560
1561 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1562 bnxt_async_event_process(bp,
1563 (struct hwrm_async_event_cmpl *)txcmp);
1564
1565 default:
1566 break;
1567 }
1568
1569 return 0;
1570}
1571
1572static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1573{
1574 struct bnxt_napi *bnapi = dev_instance;
1575 struct bnxt *bp = bnapi->bp;
1576 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1577 u32 cons = RING_CMP(cpr->cp_raw_cons);
1578
1579 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1580 napi_schedule(&bnapi->napi);
1581 return IRQ_HANDLED;
1582}
1583
1584static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1585{
1586 u32 raw_cons = cpr->cp_raw_cons;
1587 u16 cons = RING_CMP(raw_cons);
1588 struct tx_cmp *txcmp;
1589
1590 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1591
1592 return TX_CMP_VALID(txcmp, raw_cons);
1593}
1594
c0c050c5
MC		 1595static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1596{
1597 struct bnxt_napi *bnapi = dev_instance;
1598 struct bnxt *bp = bnapi->bp;
1599 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1600 u32 cons = RING_CMP(cpr->cp_raw_cons);
1601 u32 int_status;
1602
1603 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1604
1605 if (!bnxt_has_work(bp, cpr)) {
11809490 1606 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
c0c050c5
MC		 1607 /* return if erroneous interrupt */
1608 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1609 return IRQ_NONE;
1610 }
1611
1612 /* disable ring IRQ */
1613 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1614
1615 /* Return here if interrupt is shared and is disabled. */
1616 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1617 return IRQ_HANDLED;
1618
1619 napi_schedule(&bnapi->napi);
1620 return IRQ_HANDLED;
1621}
1622
1623static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1624{
1625 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1626 u32 raw_cons = cpr->cp_raw_cons;
1627 u32 cons;
1628 int tx_pkts = 0;
1629 int rx_pkts = 0;
1630 bool rx_event = false;
1631 bool agg_event = false;
1632 struct tx_cmp *txcmp;
1633
1634 while (1) {
1635 int rc;
1636
1637 cons = RING_CMP(raw_cons);
1638 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1639
1640 if (!TX_CMP_VALID(txcmp, raw_cons))
1641 break;
1642
67a95e20
MC		 1643 /* The valid test of the entry must be done first before
1644 * reading any further.
1645 */
b67daab0 1646 dma_rmb();
c0c050c5
MC		 1647 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1648 tx_pkts++;
1649 /* return full budget so NAPI will complete. */
1650 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1651 rx_pkts = budget;
1652 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1653 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1654 if (likely(rc >= 0))
1655 rx_pkts += rc;
1656 else if (rc == -EBUSY) /* partial completion */
1657 break;
1658 rx_event = true;
1659 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1660 CMPL_BASE_TYPE_HWRM_DONE) ||
1661 (TX_CMP_TYPE(txcmp) ==
1662 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1663 (TX_CMP_TYPE(txcmp) ==
1664 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1665 bnxt_hwrm_handler(bp, txcmp);
1666 }
1667 raw_cons = NEXT_RAW_CMP(raw_cons);
1668
1669 if (rx_pkts == budget)
1670 break;
1671 }
1672
1673 cpr->cp_raw_cons = raw_cons;
1674 /* ACK completion ring before freeing tx ring and producing new
1675 * buffers in rx/agg rings to prevent overflowing the completion
1676 * ring.
1677 */
1678 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1679
1680 if (tx_pkts)
1681 bnxt_tx_int(bp, bnapi, tx_pkts);
1682
1683 if (rx_event) {
b6ab4b01 1684 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
c0c050c5
MC		 1685
1686 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1687 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1688 if (agg_event) {
1689 writel(DB_KEY_RX | rxr->rx_agg_prod,
1690 rxr->rx_agg_doorbell);
1691 writel(DB_KEY_RX | rxr->rx_agg_prod,
1692 rxr->rx_agg_doorbell);
1693 }
1694 }
1695 return rx_pkts;
1696}
1697
10bbdaf5
PS		 1698static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1699{
1700 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1701 struct bnxt *bp = bnapi->bp;
1702 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1703 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1704 struct tx_cmp *txcmp;
1705 struct rx_cmp_ext *rxcmp1;
1706 u32 cp_cons, tmp_raw_cons;
1707 u32 raw_cons = cpr->cp_raw_cons;
1708 u32 rx_pkts = 0;
1709 bool agg_event = false;
1710
1711 while (1) {
1712 int rc;
1713
1714 cp_cons = RING_CMP(raw_cons);
1715 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1716
1717 if (!TX_CMP_VALID(txcmp, raw_cons))
1718 break;
1719
1720 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1721 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1722 cp_cons = RING_CMP(tmp_raw_cons);
1723 rxcmp1 = (struct rx_cmp_ext *)
1724 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1725
1726 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1727 break;
1728
1729 /* force an error to recycle the buffer */
1730 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1731 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1732
1733 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1734 if (likely(rc == -EIO))
1735 rx_pkts++;
1736 else if (rc == -EBUSY) /* partial completion */
1737 break;
1738 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1739 CMPL_BASE_TYPE_HWRM_DONE)) {
1740 bnxt_hwrm_handler(bp, txcmp);
1741 } else {
1742 netdev_err(bp->dev,
1743 "Invalid completion received on special ring\n");
1744 }
1745 raw_cons = NEXT_RAW_CMP(raw_cons);
1746
1747 if (rx_pkts == budget)
1748 break;
1749 }
1750
1751 cpr->cp_raw_cons = raw_cons;
1752 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1753 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1754 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1755
1756 if (agg_event) {
1757 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1758 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1759 }
1760
1761 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
6ad20165 1762 napi_complete_done(napi, rx_pkts);
10bbdaf5
PS		 1763 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1764 }
1765 return rx_pkts;
1766}
1767
c0c050c5
MC		 1768static int bnxt_poll(struct napi_struct *napi, int budget)
1769{
1770 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1771 struct bnxt *bp = bnapi->bp;
1772 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1773 int work_done = 0;
1774
c0c050c5
MC		 1775 while (1) {
1776 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1777
1778 if (work_done >= budget)
1779 break;
1780
1781 if (!bnxt_has_work(bp, cpr)) {
e7b95691
MC		 1782 if (napi_complete_done(napi, work_done))
1783 BNXT_CP_DB_REARM(cpr->cp_doorbell,
1784 cpr->cp_raw_cons);
c0c050c5
MC		 1785 break;
1786 }
1787 }
1788 mmiowb();
c0c050c5
MC		 1789 return work_done;
1790}
1791
c0c050c5
MC		 1792static void bnxt_free_tx_skbs(struct bnxt *bp)
1793{
1794 int i, max_idx;
1795 struct pci_dev *pdev = bp->pdev;
1796
b6ab4b01 1797 if (!bp->tx_ring)
c0c050c5
MC		 1798 return;
1799
1800 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1801 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 1802 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 1803 int j;
1804
c0c050c5
MC		 1805 for (j = 0; j < max_idx;) {
1806 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1807 struct sk_buff *skb = tx_buf->skb;
1808 int k, last;
1809
1810 if (!skb) {
1811 j++;
1812 continue;
1813 }
1814
1815 tx_buf->skb = NULL;
1816
1817 if (tx_buf->is_push) {
1818 dev_kfree_skb(skb);
1819 j += 2;
1820 continue;
1821 }
1822
1823 dma_unmap_single(&pdev->dev,
1824 dma_unmap_addr(tx_buf, mapping),
1825 skb_headlen(skb),
1826 PCI_DMA_TODEVICE);
1827
1828 last = tx_buf->nr_frags;
1829 j += 2;
d612a579
MC		 1830 for (k = 0; k < last; k++, j++) {
1831 int ring_idx = j & bp->tx_ring_mask;
c0c050c5
MC		 1832 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1833
d612a579 1834 tx_buf = &txr->tx_buf_ring[ring_idx];
c0c050c5
MC		 1835 dma_unmap_page(
1836 &pdev->dev,
1837 dma_unmap_addr(tx_buf, mapping),
1838 skb_frag_size(frag), PCI_DMA_TODEVICE);
1839 }
1840 dev_kfree_skb(skb);
1841 }
1842 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1843 }
1844}
1845
1846static void bnxt_free_rx_skbs(struct bnxt *bp)
1847{
1848 int i, max_idx, max_agg_idx;
1849 struct pci_dev *pdev = bp->pdev;
1850
b6ab4b01 1851 if (!bp->rx_ring)
c0c050c5
MC		 1852 return;
1853
1854 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1855 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1856 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 1857 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 1858 int j;
1859
c0c050c5
MC		 1860 if (rxr->rx_tpa) {
1861 for (j = 0; j < MAX_TPA; j++) {
1862 struct bnxt_tpa_info *tpa_info =
1863 &rxr->rx_tpa[j];
1864 u8 *data = tpa_info->data;
1865
1866 if (!data)
1867 continue;
1868
1869 dma_unmap_single(
1870 &pdev->dev,
1871 dma_unmap_addr(tpa_info, mapping),
1872 bp->rx_buf_use_size,
1873 PCI_DMA_FROMDEVICE);
1874
1875 tpa_info->data = NULL;
1876
1877 kfree(data);
1878 }
1879 }
1880
1881 for (j = 0; j < max_idx; j++) {
1882 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1883 u8 *data = rx_buf->data;
1884
1885 if (!data)
1886 continue;
1887
1888 dma_unmap_single(&pdev->dev,
1889 dma_unmap_addr(rx_buf, mapping),
1890 bp->rx_buf_use_size,
1891 PCI_DMA_FROMDEVICE);
1892
1893 rx_buf->data = NULL;
1894
1895 kfree(data);
1896 }
1897
1898 for (j = 0; j < max_agg_idx; j++) {
1899 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1900 &rxr->rx_agg_ring[j];
1901 struct page *page = rx_agg_buf->page;
1902
1903 if (!page)
1904 continue;
1905
1906 dma_unmap_page(&pdev->dev,
1907 dma_unmap_addr(rx_agg_buf, mapping),
2839f28b 1908 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE);
c0c050c5
MC		 1909
1910 rx_agg_buf->page = NULL;
1911 __clear_bit(j, rxr->rx_agg_bmap);
1912
1913 __free_page(page);
1914 }
89d0a06c
MC		 1915 if (rxr->rx_page) {
1916 __free_page(rxr->rx_page);
1917 rxr->rx_page = NULL;
1918 }
c0c050c5
MC		 1919 }
1920}
1921
1922static void bnxt_free_skbs(struct bnxt *bp)
1923{
1924 bnxt_free_tx_skbs(bp);
1925 bnxt_free_rx_skbs(bp);
1926}
1927
1928static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1929{
1930 struct pci_dev *pdev = bp->pdev;
1931 int i;
1932
1933 for (i = 0; i < ring->nr_pages; i++) {
1934 if (!ring->pg_arr[i])
1935 continue;
1936
1937 dma_free_coherent(&pdev->dev, ring->page_size,
1938 ring->pg_arr[i], ring->dma_arr[i]);
1939
1940 ring->pg_arr[i] = NULL;
1941 }
1942 if (ring->pg_tbl) {
1943 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1944 ring->pg_tbl, ring->pg_tbl_map);
1945 ring->pg_tbl = NULL;
1946 }
1947 if (ring->vmem_size && *ring->vmem) {
1948 vfree(*ring->vmem);
1949 *ring->vmem = NULL;
1950 }
1951}
1952
1953static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1954{
1955 int i;
1956 struct pci_dev *pdev = bp->pdev;
1957
1958 if (ring->nr_pages > 1) {
1959 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1960 ring->nr_pages * 8,
1961 &ring->pg_tbl_map,
1962 GFP_KERNEL);
1963 if (!ring->pg_tbl)
1964 return -ENOMEM;
1965 }
1966
1967 for (i = 0; i < ring->nr_pages; i++) {
1968 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
1969 ring->page_size,
1970 &ring->dma_arr[i],
1971 GFP_KERNEL);
1972 if (!ring->pg_arr[i])
1973 return -ENOMEM;
1974
1975 if (ring->nr_pages > 1)
1976 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
1977 }
1978
1979 if (ring->vmem_size) {
1980 *ring->vmem = vzalloc(ring->vmem_size);
1981 if (!(*ring->vmem))
1982 return -ENOMEM;
1983 }
1984 return 0;
1985}
1986
1987static void bnxt_free_rx_rings(struct bnxt *bp)
1988{
1989 int i;
1990
b6ab4b01 1991 if (!bp->rx_ring)
c0c050c5
MC		 1992 return;
1993
1994 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 1995 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 1996 struct bnxt_ring_struct *ring;
1997
c0c050c5
MC		 1998 kfree(rxr->rx_tpa);
1999 rxr->rx_tpa = NULL;
2000
2001 kfree(rxr->rx_agg_bmap);
2002 rxr->rx_agg_bmap = NULL;
2003
2004 ring = &rxr->rx_ring_struct;
2005 bnxt_free_ring(bp, ring);
2006
2007 ring = &rxr->rx_agg_ring_struct;
2008 bnxt_free_ring(bp, ring);
2009 }
2010}
2011
2012static int bnxt_alloc_rx_rings(struct bnxt *bp)
2013{
2014 int i, rc, agg_rings = 0, tpa_rings = 0;
2015
b6ab4b01
MC		 2016 if (!bp->rx_ring)
2017 return -ENOMEM;
2018
c0c050c5
MC		 2019 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2020 agg_rings = 1;
2021
2022 if (bp->flags & BNXT_FLAG_TPA)
2023 tpa_rings = 1;
2024
2025 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 2026 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 2027 struct bnxt_ring_struct *ring;
2028
c0c050c5
MC		 2029 ring = &rxr->rx_ring_struct;
2030
2031 rc = bnxt_alloc_ring(bp, ring);
2032 if (rc)
2033 return rc;
2034
2035 if (agg_rings) {
2036 u16 mem_size;
2037
2038 ring = &rxr->rx_agg_ring_struct;
2039 rc = bnxt_alloc_ring(bp, ring);
2040 if (rc)
2041 return rc;
2042
2043 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2044 mem_size = rxr->rx_agg_bmap_size / 8;
2045 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2046 if (!rxr->rx_agg_bmap)
2047 return -ENOMEM;
2048
2049 if (tpa_rings) {
2050 rxr->rx_tpa = kcalloc(MAX_TPA,
2051 sizeof(struct bnxt_tpa_info),
2052 GFP_KERNEL);
2053 if (!rxr->rx_tpa)
2054 return -ENOMEM;
2055 }
2056 }
2057 }
2058 return 0;
2059}
2060
2061static void bnxt_free_tx_rings(struct bnxt *bp)
2062{
2063 int i;
2064 struct pci_dev *pdev = bp->pdev;
2065
b6ab4b01 2066 if (!bp->tx_ring)
c0c050c5
MC		 2067 return;
2068
2069 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2070 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2071 struct bnxt_ring_struct *ring;
2072
c0c050c5
MC		 2073 if (txr->tx_push) {
2074 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2075 txr->tx_push, txr->tx_push_mapping);
2076 txr->tx_push = NULL;
2077 }
2078
2079 ring = &txr->tx_ring_struct;
2080
2081 bnxt_free_ring(bp, ring);
2082 }
2083}
2084
2085static int bnxt_alloc_tx_rings(struct bnxt *bp)
2086{
2087 int i, j, rc;
2088 struct pci_dev *pdev = bp->pdev;
2089
2090 bp->tx_push_size = 0;
2091 if (bp->tx_push_thresh) {
2092 int push_size;
2093
2094 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2095 bp->tx_push_thresh);
2096
4419dbe6 2097 if (push_size > 256) {
c0c050c5
MC		 2098 push_size = 0;
2099 bp->tx_push_thresh = 0;
2100 }
2101
2102 bp->tx_push_size = push_size;
2103 }
2104
2105 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2106 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2107 struct bnxt_ring_struct *ring;
2108
c0c050c5
MC		 2109 ring = &txr->tx_ring_struct;
2110
2111 rc = bnxt_alloc_ring(bp, ring);
2112 if (rc)
2113 return rc;
2114
2115 if (bp->tx_push_size) {
c0c050c5
MC		 2116 dma_addr_t mapping;
2117
2118 /* One pre-allocated DMA buffer to backup
2119 * TX push operation
2120 */
2121 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2122 bp->tx_push_size,
2123 &txr->tx_push_mapping,
2124 GFP_KERNEL);
2125
2126 if (!txr->tx_push)
2127 return -ENOMEM;
2128
c0c050c5
MC		 2129 mapping = txr->tx_push_mapping +
2130 sizeof(struct tx_push_bd);
4419dbe6 2131 txr->data_mapping = cpu_to_le64(mapping);
c0c050c5 2132
4419dbe6 2133 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
c0c050c5
MC		 2134 }
2135 ring->queue_id = bp->q_info[j].queue_id;
2136 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2137 j++;
2138 }
2139 return 0;
2140}
2141
2142static void bnxt_free_cp_rings(struct bnxt *bp)
2143{
2144 int i;
2145
2146 if (!bp->bnapi)
2147 return;
2148
2149 for (i = 0; i < bp->cp_nr_rings; i++) {
2150 struct bnxt_napi *bnapi = bp->bnapi[i];
2151 struct bnxt_cp_ring_info *cpr;
2152 struct bnxt_ring_struct *ring;
2153
2154 if (!bnapi)
2155 continue;
2156
2157 cpr = &bnapi->cp_ring;
2158 ring = &cpr->cp_ring_struct;
2159
2160 bnxt_free_ring(bp, ring);
2161 }
2162}
2163
2164static int bnxt_alloc_cp_rings(struct bnxt *bp)
2165{
2166 int i, rc;
2167
2168 for (i = 0; i < bp->cp_nr_rings; i++) {
2169 struct bnxt_napi *bnapi = bp->bnapi[i];
2170 struct bnxt_cp_ring_info *cpr;
2171 struct bnxt_ring_struct *ring;
2172
2173 if (!bnapi)
2174 continue;
2175
2176 cpr = &bnapi->cp_ring;
2177 ring = &cpr->cp_ring_struct;
2178
2179 rc = bnxt_alloc_ring(bp, ring);
2180 if (rc)
2181 return rc;
2182 }
2183 return 0;
2184}
2185
2186static void bnxt_init_ring_struct(struct bnxt *bp)
2187{
2188 int i;
2189
2190 for (i = 0; i < bp->cp_nr_rings; i++) {
2191 struct bnxt_napi *bnapi = bp->bnapi[i];
2192 struct bnxt_cp_ring_info *cpr;
2193 struct bnxt_rx_ring_info *rxr;
2194 struct bnxt_tx_ring_info *txr;
2195 struct bnxt_ring_struct *ring;
2196
2197 if (!bnapi)
2198 continue;
2199
2200 cpr = &bnapi->cp_ring;
2201 ring = &cpr->cp_ring_struct;
2202 ring->nr_pages = bp->cp_nr_pages;
2203 ring->page_size = HW_CMPD_RING_SIZE;
2204 ring->pg_arr = (void **)cpr->cp_desc_ring;
2205 ring->dma_arr = cpr->cp_desc_mapping;
2206 ring->vmem_size = 0;
2207
b6ab4b01 2208 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 2209 if (!rxr)
2210 goto skip_rx;
2211
c0c050c5
MC		 2212 ring = &rxr->rx_ring_struct;
2213 ring->nr_pages = bp->rx_nr_pages;
2214 ring->page_size = HW_RXBD_RING_SIZE;
2215 ring->pg_arr = (void **)rxr->rx_desc_ring;
2216 ring->dma_arr = rxr->rx_desc_mapping;
2217 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2218 ring->vmem = (void **)&rxr->rx_buf_ring;
2219
2220 ring = &rxr->rx_agg_ring_struct;
2221 ring->nr_pages = bp->rx_agg_nr_pages;
2222 ring->page_size = HW_RXBD_RING_SIZE;
2223 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2224 ring->dma_arr = rxr->rx_agg_desc_mapping;
2225 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2226 ring->vmem = (void **)&rxr->rx_agg_ring;
2227
3b2b7d9d 2228skip_rx:
b6ab4b01 2229 txr = bnapi->tx_ring;
3b2b7d9d
MC		 2230 if (!txr)
2231 continue;
2232
c0c050c5
MC		 2233 ring = &txr->tx_ring_struct;
2234 ring->nr_pages = bp->tx_nr_pages;
2235 ring->page_size = HW_RXBD_RING_SIZE;
2236 ring->pg_arr = (void **)txr->tx_desc_ring;
2237 ring->dma_arr = txr->tx_desc_mapping;
2238 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2239 ring->vmem = (void **)&txr->tx_buf_ring;
2240 }
2241}
2242
2243static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2244{
2245 int i;
2246 u32 prod;
2247 struct rx_bd **rx_buf_ring;
2248
2249 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2250 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2251 int j;
2252 struct rx_bd *rxbd;
2253
2254 rxbd = rx_buf_ring[i];
2255 if (!rxbd)
2256 continue;
2257
2258 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2259 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2260 rxbd->rx_bd_opaque = prod;
2261 }
2262 }
2263}
2264
2265static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2266{
2267 struct net_device *dev = bp->dev;
c0c050c5
MC		 2268 struct bnxt_rx_ring_info *rxr;
2269 struct bnxt_ring_struct *ring;
2270 u32 prod, type;
2271 int i;
2272
c0c050c5
MC		 2273 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2274 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2275
2276 if (NET_IP_ALIGN == 2)
2277 type |= RX_BD_FLAGS_SOP;
2278
b6ab4b01 2279 rxr = &bp->rx_ring[ring_nr];
c0c050c5
MC		 2280 ring = &rxr->rx_ring_struct;
2281 bnxt_init_rxbd_pages(ring, type);
2282
2283 prod = rxr->rx_prod;
2284 for (i = 0; i < bp->rx_ring_size; i++) {
2285 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2286 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2287 ring_nr, i, bp->rx_ring_size);
2288 break;
2289 }
2290 prod = NEXT_RX(prod);
2291 }
2292 rxr->rx_prod = prod;
2293 ring->fw_ring_id = INVALID_HW_RING_ID;
2294
edd0c2cc
MC		 2295 ring = &rxr->rx_agg_ring_struct;
2296 ring->fw_ring_id = INVALID_HW_RING_ID;
2297
c0c050c5
MC		 2298 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2299 return 0;
2300
2839f28b 2301 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
c0c050c5
MC		 2302 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2303
2304 bnxt_init_rxbd_pages(ring, type);
2305
2306 prod = rxr->rx_agg_prod;
2307 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2308 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2309 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2310 ring_nr, i, bp->rx_ring_size);
2311 break;
2312 }
2313 prod = NEXT_RX_AGG(prod);
2314 }
2315 rxr->rx_agg_prod = prod;
c0c050c5
MC		 2316
2317 if (bp->flags & BNXT_FLAG_TPA) {
2318 if (rxr->rx_tpa) {
2319 u8 *data;
2320 dma_addr_t mapping;
2321
2322 for (i = 0; i < MAX_TPA; i++) {
2323 data = __bnxt_alloc_rx_data(bp, &mapping,
2324 GFP_KERNEL);
2325 if (!data)
2326 return -ENOMEM;
2327
2328 rxr->rx_tpa[i].data = data;
2329 rxr->rx_tpa[i].mapping = mapping;
2330 }
2331 } else {
2332 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2333 return -ENOMEM;
2334 }
2335 }
2336
2337 return 0;
2338}
2339
2340static int bnxt_init_rx_rings(struct bnxt *bp)
2341{
2342 int i, rc = 0;
2343
2344 for (i = 0; i < bp->rx_nr_rings; i++) {
2345 rc = bnxt_init_one_rx_ring(bp, i);
2346 if (rc)
2347 break;
2348 }
2349
2350 return rc;
2351}
2352
2353static int bnxt_init_tx_rings(struct bnxt *bp)
2354{
2355 u16 i;
2356
2357 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2358 MAX_SKB_FRAGS + 1);
2359
2360 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 2361 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
c0c050c5
MC		 2362 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2363
2364 ring->fw_ring_id = INVALID_HW_RING_ID;
2365 }
2366
2367 return 0;
2368}
2369
2370static void bnxt_free_ring_grps(struct bnxt *bp)
2371{
2372 kfree(bp->grp_info);
2373 bp->grp_info = NULL;
2374}
2375
2376static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2377{
2378 int i;
2379
2380 if (irq_re_init) {
2381 bp->grp_info = kcalloc(bp->cp_nr_rings,
2382 sizeof(struct bnxt_ring_grp_info),
2383 GFP_KERNEL);
2384 if (!bp->grp_info)
2385 return -ENOMEM;
2386 }
2387 for (i = 0; i < bp->cp_nr_rings; i++) {
2388 if (irq_re_init)
2389 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2390 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2391 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2392 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2393 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2394 }
2395 return 0;
2396}
2397
2398static void bnxt_free_vnics(struct bnxt *bp)
2399{
2400 kfree(bp->vnic_info);
2401 bp->vnic_info = NULL;
2402 bp->nr_vnics = 0;
2403}
2404
2405static int bnxt_alloc_vnics(struct bnxt *bp)
2406{
2407 int num_vnics = 1;
2408
2409#ifdef CONFIG_RFS_ACCEL
2410 if (bp->flags & BNXT_FLAG_RFS)
2411 num_vnics += bp->rx_nr_rings;
2412#endif
2413
dc52c6c7
PS		 2414 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2415 num_vnics++;
2416
c0c050c5
MC		 2417 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2418 GFP_KERNEL);
2419 if (!bp->vnic_info)
2420 return -ENOMEM;
2421
2422 bp->nr_vnics = num_vnics;
2423 return 0;
2424}
2425
2426static void bnxt_init_vnics(struct bnxt *bp)
2427{
2428 int i;
2429
2430 for (i = 0; i < bp->nr_vnics; i++) {
2431 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2432
2433 vnic->fw_vnic_id = INVALID_HW_RING_ID;
94ce9caa
PS		 2434 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2435 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
c0c050c5
MC		 2436 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2437
2438 if (bp->vnic_info[i].rss_hash_key) {
2439 if (i == 0)
2440 prandom_bytes(vnic->rss_hash_key,
2441 HW_HASH_KEY_SIZE);
2442 else
2443 memcpy(vnic->rss_hash_key,
2444 bp->vnic_info[0].rss_hash_key,
2445 HW_HASH_KEY_SIZE);
2446 }
2447 }
2448}
2449
2450static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2451{
2452 int pages;
2453
2454 pages = ring_size / desc_per_pg;
2455
2456 if (!pages)
2457 return 1;
2458
2459 pages++;
2460
2461 while (pages & (pages - 1))
2462 pages++;
2463
2464 return pages;
2465}
2466
2467static void bnxt_set_tpa_flags(struct bnxt *bp)
2468{
2469 bp->flags &= ~BNXT_FLAG_TPA;
341138c3
MC		 2470 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2471 return;
c0c050c5
MC		 2472 if (bp->dev->features & NETIF_F_LRO)
2473 bp->flags |= BNXT_FLAG_LRO;
94758f8d 2474 if (bp->dev->features & NETIF_F_GRO)
c0c050c5
MC		 2475 bp->flags |= BNXT_FLAG_GRO;
2476}
2477
2478/* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2479 * be set on entry.
2480 */
2481void bnxt_set_ring_params(struct bnxt *bp)
2482{
2483 u32 ring_size, rx_size, rx_space;
2484 u32 agg_factor = 0, agg_ring_size = 0;
2485
2486 /* 8 for CRC and VLAN */
2487 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2488
2489 rx_space = rx_size + NET_SKB_PAD +
2490 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2491
2492 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2493 ring_size = bp->rx_ring_size;
2494 bp->rx_agg_ring_size = 0;
2495 bp->rx_agg_nr_pages = 0;
2496
2497 if (bp->flags & BNXT_FLAG_TPA)
2839f28b 2498 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
c0c050c5
MC		 2499
2500 bp->flags &= ~BNXT_FLAG_JUMBO;
bdbd1eb5 2501 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
c0c050c5
MC		 2502 u32 jumbo_factor;
2503
2504 bp->flags |= BNXT_FLAG_JUMBO;
2505 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2506 if (jumbo_factor > agg_factor)
2507 agg_factor = jumbo_factor;
2508 }
2509 agg_ring_size = ring_size * agg_factor;
2510
2511 if (agg_ring_size) {
2512 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2513 RX_DESC_CNT);
2514 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2515 u32 tmp = agg_ring_size;
2516
2517 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2518 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2519 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2520 tmp, agg_ring_size);
2521 }
2522 bp->rx_agg_ring_size = agg_ring_size;
2523 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2524 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2525 rx_space = rx_size + NET_SKB_PAD +
2526 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2527 }
2528
2529 bp->rx_buf_use_size = rx_size;
2530 bp->rx_buf_size = rx_space;
2531
2532 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2533 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2534
2535 ring_size = bp->tx_ring_size;
2536 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2537 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2538
2539 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2540 bp->cp_ring_size = ring_size;
2541
2542 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2543 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2544 bp->cp_nr_pages = MAX_CP_PAGES;
2545 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2546 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2547 ring_size, bp->cp_ring_size);
2548 }
2549 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2550 bp->cp_ring_mask = bp->cp_bit - 1;
2551}
2552
2553static void bnxt_free_vnic_attributes(struct bnxt *bp)
2554{
2555 int i;
2556 struct bnxt_vnic_info *vnic;
2557 struct pci_dev *pdev = bp->pdev;
2558
2559 if (!bp->vnic_info)
2560 return;
2561
2562 for (i = 0; i < bp->nr_vnics; i++) {
2563 vnic = &bp->vnic_info[i];
2564
2565 kfree(vnic->fw_grp_ids);
2566 vnic->fw_grp_ids = NULL;
2567
2568 kfree(vnic->uc_list);
2569 vnic->uc_list = NULL;
2570
2571 if (vnic->mc_list) {
2572 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2573 vnic->mc_list, vnic->mc_list_mapping);
2574 vnic->mc_list = NULL;
2575 }
2576
2577 if (vnic->rss_table) {
2578 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2579 vnic->rss_table,
2580 vnic->rss_table_dma_addr);
2581 vnic->rss_table = NULL;
2582 }
2583
2584 vnic->rss_hash_key = NULL;
2585 vnic->flags = 0;
2586 }
2587}
2588
2589static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2590{
2591 int i, rc = 0, size;
2592 struct bnxt_vnic_info *vnic;
2593 struct pci_dev *pdev = bp->pdev;
2594 int max_rings;
2595
2596 for (i = 0; i < bp->nr_vnics; i++) {
2597 vnic = &bp->vnic_info[i];
2598
2599 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2600 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2601
2602 if (mem_size > 0) {
2603 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2604 if (!vnic->uc_list) {
2605 rc = -ENOMEM;
2606 goto out;
2607 }
2608 }
2609 }
2610
2611 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2612 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2613 vnic->mc_list =
2614 dma_alloc_coherent(&pdev->dev,
2615 vnic->mc_list_size,
2616 &vnic->mc_list_mapping,
2617 GFP_KERNEL);
2618 if (!vnic->mc_list) {
2619 rc = -ENOMEM;
2620 goto out;
2621 }
2622 }
2623
2624 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2625 max_rings = bp->rx_nr_rings;
2626 else
2627 max_rings = 1;
2628
2629 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2630 if (!vnic->fw_grp_ids) {
2631 rc = -ENOMEM;
2632 goto out;
2633 }
2634
ae10ae74
MC		 2635 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
2636 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
2637 continue;
2638
c0c050c5
MC		 2639 /* Allocate rss table and hash key */
2640 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2641 &vnic->rss_table_dma_addr,
2642 GFP_KERNEL);
2643 if (!vnic->rss_table) {
2644 rc = -ENOMEM;
2645 goto out;
2646 }
2647
2648 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2649
2650 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2651 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2652 }
2653 return 0;
2654
2655out:
2656 return rc;
2657}
2658
2659static void bnxt_free_hwrm_resources(struct bnxt *bp)
2660{
2661 struct pci_dev *pdev = bp->pdev;
2662
2663 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2664 bp->hwrm_cmd_resp_dma_addr);
2665
2666 bp->hwrm_cmd_resp_addr = NULL;
2667 if (bp->hwrm_dbg_resp_addr) {
2668 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2669 bp->hwrm_dbg_resp_addr,
2670 bp->hwrm_dbg_resp_dma_addr);
2671
2672 bp->hwrm_dbg_resp_addr = NULL;
2673 }
2674}
2675
2676static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2677{
2678 struct pci_dev *pdev = bp->pdev;
2679
2680 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2681 &bp->hwrm_cmd_resp_dma_addr,
2682 GFP_KERNEL);
2683 if (!bp->hwrm_cmd_resp_addr)
2684 return -ENOMEM;
2685 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2686 HWRM_DBG_REG_BUF_SIZE,
2687 &bp->hwrm_dbg_resp_dma_addr,
2688 GFP_KERNEL);
2689 if (!bp->hwrm_dbg_resp_addr)
2690 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2691
2692 return 0;
2693}
2694
2695static void bnxt_free_stats(struct bnxt *bp)
2696{
2697 u32 size, i;
2698 struct pci_dev *pdev = bp->pdev;
2699
3bdf56c4
MC		 2700 if (bp->hw_rx_port_stats) {
2701 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
2702 bp->hw_rx_port_stats,
2703 bp->hw_rx_port_stats_map);
2704 bp->hw_rx_port_stats = NULL;
2705 bp->flags &= ~BNXT_FLAG_PORT_STATS;
2706 }
2707
c0c050c5
MC		 2708 if (!bp->bnapi)
2709 return;
2710
2711 size = sizeof(struct ctx_hw_stats);
2712
2713 for (i = 0; i < bp->cp_nr_rings; i++) {
2714 struct bnxt_napi *bnapi = bp->bnapi[i];
2715 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2716
2717 if (cpr->hw_stats) {
2718 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2719 cpr->hw_stats_map);
2720 cpr->hw_stats = NULL;
2721 }
2722 }
2723}
2724
2725static int bnxt_alloc_stats(struct bnxt *bp)
2726{
2727 u32 size, i;
2728 struct pci_dev *pdev = bp->pdev;
2729
2730 size = sizeof(struct ctx_hw_stats);
2731
2732 for (i = 0; i < bp->cp_nr_rings; i++) {
2733 struct bnxt_napi *bnapi = bp->bnapi[i];
2734 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2735
2736 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2737 &cpr->hw_stats_map,
2738 GFP_KERNEL);
2739 if (!cpr->hw_stats)
2740 return -ENOMEM;
2741
2742 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2743 }
3bdf56c4 2744
3e8060fa 2745 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3bdf56c4
MC		 2746 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
2747 sizeof(struct tx_port_stats) + 1024;
2748
2749 bp->hw_rx_port_stats =
2750 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
2751 &bp->hw_rx_port_stats_map,
2752 GFP_KERNEL);
2753 if (!bp->hw_rx_port_stats)
2754 return -ENOMEM;
2755
2756 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
2757 512;
2758 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
2759 sizeof(struct rx_port_stats) + 512;
2760 bp->flags |= BNXT_FLAG_PORT_STATS;
2761 }
c0c050c5
MC		 2762 return 0;
2763}
2764
2765static void bnxt_clear_ring_indices(struct bnxt *bp)
2766{
2767 int i;
2768
2769 if (!bp->bnapi)
2770 return;
2771
2772 for (i = 0; i < bp->cp_nr_rings; i++) {
2773 struct bnxt_napi *bnapi = bp->bnapi[i];
2774 struct bnxt_cp_ring_info *cpr;
2775 struct bnxt_rx_ring_info *rxr;
2776 struct bnxt_tx_ring_info *txr;
2777
2778 if (!bnapi)
2779 continue;
2780
2781 cpr = &bnapi->cp_ring;
2782 cpr->cp_raw_cons = 0;
2783
b6ab4b01 2784 txr = bnapi->tx_ring;
3b2b7d9d
MC		 2785 if (txr) {
2786 txr->tx_prod = 0;
2787 txr->tx_cons = 0;
2788 }
c0c050c5 2789
b6ab4b01 2790 rxr = bnapi->rx_ring;
3b2b7d9d
MC		 2791 if (rxr) {
2792 rxr->rx_prod = 0;
2793 rxr->rx_agg_prod = 0;
2794 rxr->rx_sw_agg_prod = 0;
376a5b86 2795 rxr->rx_next_cons = 0;
3b2b7d9d 2796 }
c0c050c5
MC		 2797 }
2798}
2799
2800static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2801{
2802#ifdef CONFIG_RFS_ACCEL
2803 int i;
2804
2805 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2806 * safe to delete the hash table.
2807 */
2808 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2809 struct hlist_head *head;
2810 struct hlist_node *tmp;
2811 struct bnxt_ntuple_filter *fltr;
2812
2813 head = &bp->ntp_fltr_hash_tbl[i];
2814 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2815 hlist_del(&fltr->hash);
2816 kfree(fltr);
2817 }
2818 }
2819 if (irq_reinit) {
2820 kfree(bp->ntp_fltr_bmap);
2821 bp->ntp_fltr_bmap = NULL;
2822 }
2823 bp->ntp_fltr_count = 0;
2824#endif
2825}
2826
2827static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2828{
2829#ifdef CONFIG_RFS_ACCEL
2830 int i, rc = 0;
2831
2832 if (!(bp->flags & BNXT_FLAG_RFS))
2833 return 0;
2834
2835 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2836 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2837
2838 bp->ntp_fltr_count = 0;
2839 bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2840 GFP_KERNEL);
2841
2842 if (!bp->ntp_fltr_bmap)
2843 rc = -ENOMEM;
2844
2845 return rc;
2846#else
2847 return 0;
2848#endif
2849}
2850
2851static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2852{
2853 bnxt_free_vnic_attributes(bp);
2854 bnxt_free_tx_rings(bp);
2855 bnxt_free_rx_rings(bp);
2856 bnxt_free_cp_rings(bp);
2857 bnxt_free_ntp_fltrs(bp, irq_re_init);
2858 if (irq_re_init) {
2859 bnxt_free_stats(bp);
2860 bnxt_free_ring_grps(bp);
2861 bnxt_free_vnics(bp);
b6ab4b01
MC		 2862 kfree(bp->tx_ring);
2863 bp->tx_ring = NULL;
2864 kfree(bp->rx_ring);
2865 bp->rx_ring = NULL;
c0c050c5
MC		 2866 kfree(bp->bnapi);
2867 bp->bnapi = NULL;
2868 } else {
2869 bnxt_clear_ring_indices(bp);
2870 }
2871}
2872
2873static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2874{
01657bcd 2875 int i, j, rc, size, arr_size;
c0c050c5
MC		 2876 void *bnapi;
2877
2878 if (irq_re_init) {
2879 /* Allocate bnapi mem pointer array and mem block for
2880 * all queues
2881 */
2882 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2883 bp->cp_nr_rings);
2884 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2885 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2886 if (!bnapi)
2887 return -ENOMEM;
2888
2889 bp->bnapi = bnapi;
2890 bnapi += arr_size;
2891 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2892 bp->bnapi[i] = bnapi;
2893 bp->bnapi[i]->index = i;
2894 bp->bnapi[i]->bp = bp;
2895 }
2896
b6ab4b01
MC		 2897 bp->rx_ring = kcalloc(bp->rx_nr_rings,
2898 sizeof(struct bnxt_rx_ring_info),
2899 GFP_KERNEL);
2900 if (!bp->rx_ring)
2901 return -ENOMEM;
2902
2903 for (i = 0; i < bp->rx_nr_rings; i++) {
2904 bp->rx_ring[i].bnapi = bp->bnapi[i];
2905 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
2906 }
2907
2908 bp->tx_ring = kcalloc(bp->tx_nr_rings,
2909 sizeof(struct bnxt_tx_ring_info),
2910 GFP_KERNEL);
2911 if (!bp->tx_ring)
2912 return -ENOMEM;
2913
01657bcd
MC		 2914 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
2915 j = 0;
2916 else
2917 j = bp->rx_nr_rings;
2918
2919 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
2920 bp->tx_ring[i].bnapi = bp->bnapi[j];
2921 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
b6ab4b01
MC		 2922 }
2923
c0c050c5
MC		 2924 rc = bnxt_alloc_stats(bp);
2925 if (rc)
2926 goto alloc_mem_err;
2927
2928 rc = bnxt_alloc_ntp_fltrs(bp);
2929 if (rc)
2930 goto alloc_mem_err;
2931
2932 rc = bnxt_alloc_vnics(bp);
2933 if (rc)
2934 goto alloc_mem_err;
2935 }
2936
2937 bnxt_init_ring_struct(bp);
2938
2939 rc = bnxt_alloc_rx_rings(bp);
2940 if (rc)
2941 goto alloc_mem_err;
2942
2943 rc = bnxt_alloc_tx_rings(bp);
2944 if (rc)
2945 goto alloc_mem_err;
2946
2947 rc = bnxt_alloc_cp_rings(bp);
2948 if (rc)
2949 goto alloc_mem_err;
2950
2951 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2952 BNXT_VNIC_UCAST_FLAG;
2953 rc = bnxt_alloc_vnic_attributes(bp);
2954 if (rc)
2955 goto alloc_mem_err;
2956 return 0;
2957
2958alloc_mem_err:
2959 bnxt_free_mem(bp, true);
2960 return rc;
2961}
2962
9d8bc097
MC		 2963static void bnxt_disable_int(struct bnxt *bp)
2964{
2965 int i;
2966
2967 if (!bp->bnapi)
2968 return;
2969
2970 for (i = 0; i < bp->cp_nr_rings; i++) {
2971 struct bnxt_napi *bnapi = bp->bnapi[i];
2972 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2973
2974 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
2975 }
2976}
2977
2978static void bnxt_disable_int_sync(struct bnxt *bp)
2979{
2980 int i;
2981
2982 atomic_inc(&bp->intr_sem);
2983
2984 bnxt_disable_int(bp);
2985 for (i = 0; i < bp->cp_nr_rings; i++)
2986 synchronize_irq(bp->irq_tbl[i].vector);
2987}
2988
2989static void bnxt_enable_int(struct bnxt *bp)
2990{
2991 int i;
2992
2993 atomic_set(&bp->intr_sem, 0);
2994 for (i = 0; i < bp->cp_nr_rings; i++) {
2995 struct bnxt_napi *bnapi = bp->bnapi[i];
2996 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2997
2998 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
2999 }
3000}
3001
c0c050c5
MC		 3002void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3003 u16 cmpl_ring, u16 target_id)
3004{
a8643e16 3005 struct input *req = request;
c0c050c5 3006
a8643e16
MC		 3007 req->req_type = cpu_to_le16(req_type);
3008 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3009 req->target_id = cpu_to_le16(target_id);
c0c050c5
MC		 3010 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3011}
3012
fbfbc485
MC		 3013static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3014 int timeout, bool silent)
c0c050c5 3015{
a11fa2be 3016 int i, intr_process, rc, tmo_count;
a8643e16 3017 struct input *req = msg;
c0c050c5
MC		 3018 u32 *data = msg;
3019 __le32 *resp_len, *valid;
3020 u16 cp_ring_id, len = 0;
3021 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3022
a8643e16 3023 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
c0c050c5 3024 memset(resp, 0, PAGE_SIZE);
a8643e16 3025 cp_ring_id = le16_to_cpu(req->cmpl_ring);
c0c050c5
MC		 3026 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3027
3028 /* Write request msg to hwrm channel */
3029 __iowrite32_copy(bp->bar0, data, msg_len / 4);
3030
e6ef2699 3031 for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4)
d79979a1
MC		 3032 writel(0, bp->bar0 + i);
3033
c0c050c5
MC		 3034 /* currently supports only one outstanding message */
3035 if (intr_process)
a8643e16 3036 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
c0c050c5
MC		 3037
3038 /* Ring channel doorbell */
3039 writel(1, bp->bar0 + 0x100);
3040
ff4fe81d
MC		 3041 if (!timeout)
3042 timeout = DFLT_HWRM_CMD_TIMEOUT;
3043
c0c050c5 3044 i = 0;
a11fa2be 3045 tmo_count = timeout * 40;
c0c050c5
MC		 3046 if (intr_process) {
3047 /* Wait until hwrm response cmpl interrupt is processed */
3048 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
a11fa2be
MC		 3049 i++ < tmo_count) {
3050 usleep_range(25, 40);
c0c050c5
MC		 3051 }
3052
3053 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3054 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
a8643e16 3055 le16_to_cpu(req->req_type));
c0c050c5
MC		 3056 return -1;
3057 }
3058 } else {
3059 /* Check if response len is updated */
3060 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
a11fa2be 3061 for (i = 0; i < tmo_count; i++) {
c0c050c5
MC		 3062 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3063 HWRM_RESP_LEN_SFT;
3064 if (len)
3065 break;
a11fa2be 3066 usleep_range(25, 40);
c0c050c5
MC		 3067 }
3068
a11fa2be 3069 if (i >= tmo_count) {
c0c050c5 3070 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
a8643e16 3071 timeout, le16_to_cpu(req->req_type),
8578d6c1 3072 le16_to_cpu(req->seq_id), len);
c0c050c5
MC		 3073 return -1;
3074 }
3075
3076 /* Last word of resp contains valid bit */
3077 valid = bp->hwrm_cmd_resp_addr + len - 4;
a11fa2be 3078 for (i = 0; i < 5; i++) {
c0c050c5
MC		 3079 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
3080 break;
a11fa2be 3081 udelay(1);
c0c050c5
MC		 3082 }
3083
a11fa2be 3084 if (i >= 5) {
c0c050c5 3085 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
a8643e16
MC		 3086 timeout, le16_to_cpu(req->req_type),
3087 le16_to_cpu(req->seq_id), len, *valid);
c0c050c5
MC		 3088 return -1;
3089 }
3090 }
3091
3092 rc = le16_to_cpu(resp->error_code);
fbfbc485 3093 if (rc && !silent)
c0c050c5
MC		 3094 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3095 le16_to_cpu(resp->req_type),
3096 le16_to_cpu(resp->seq_id), rc);
fbfbc485
MC		 3097 return rc;
3098}
3099
3100int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3101{
3102 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
c0c050c5
MC		 3103}
3104
3105int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3106{
3107 int rc;
3108
3109 mutex_lock(&bp->hwrm_cmd_lock);
3110 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3111 mutex_unlock(&bp->hwrm_cmd_lock);
3112 return rc;
3113}
3114
90e20921
MC		 3115int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3116 int timeout)
3117{
3118 int rc;
3119
3120 mutex_lock(&bp->hwrm_cmd_lock);
3121 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3122 mutex_unlock(&bp->hwrm_cmd_lock);
3123 return rc;
3124}
3125
a1653b13
MC		 3126int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3127 int bmap_size)
c0c050c5
MC		 3128{
3129 struct hwrm_func_drv_rgtr_input req = {0};
25be8623
MC		 3130 DECLARE_BITMAP(async_events_bmap, 256);
3131 u32 *events = (u32 *)async_events_bmap;
a1653b13 3132 int i;
c0c050c5
MC		 3133
3134 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3135
3136 req.enables =
a1653b13 3137 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
c0c050c5 3138
25be8623
MC		 3139 memset(async_events_bmap, 0, sizeof(async_events_bmap));
3140 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3141 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3142
a1653b13
MC		 3143 if (bmap && bmap_size) {
3144 for (i = 0; i < bmap_size; i++) {
3145 if (test_bit(i, bmap))
3146 __set_bit(i, async_events_bmap);
3147 }
3148 }
3149
25be8623
MC		 3150 for (i = 0; i < 8; i++)
3151 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3152
a1653b13
MC		 3153 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3154}
3155
3156static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3157{
3158 struct hwrm_func_drv_rgtr_input req = {0};
3159
3160 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3161
3162 req.enables =
3163 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3164 FUNC_DRV_RGTR_REQ_ENABLES_VER);
3165
11f15ed3 3166 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
c0c050c5
MC		 3167 req.ver_maj = DRV_VER_MAJ;
3168 req.ver_min = DRV_VER_MIN;
3169 req.ver_upd = DRV_VER_UPD;
3170
3171 if (BNXT_PF(bp)) {
de68f5de 3172 DECLARE_BITMAP(vf_req_snif_bmap, 256);
c0c050c5 3173 u32 *data = (u32 *)vf_req_snif_bmap;
a1653b13 3174 int i;
c0c050c5 3175
de68f5de 3176 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
c0c050c5
MC		 3177 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
3178 __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
3179
de68f5de
MC		 3180 for (i = 0; i < 8; i++)
3181 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3182
c0c050c5
MC		 3183 req.enables |=
3184 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3185 }
3186
3187 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3188}
3189
be58a0da
JH		 3190static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3191{
3192 struct hwrm_func_drv_unrgtr_input req = {0};
3193
3194 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3195 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3196}
3197
c0c050c5
MC		 3198static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3199{
3200 u32 rc = 0;
3201 struct hwrm_tunnel_dst_port_free_input req = {0};
3202
3203 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3204 req.tunnel_type = tunnel_type;
3205
3206 switch (tunnel_type) {
3207 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3208 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3209 break;
3210 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3211 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3212 break;
3213 default:
3214 break;
3215 }
3216
3217 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3218 if (rc)
3219 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3220 rc);
3221 return rc;
3222}
3223
3224static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3225 u8 tunnel_type)
3226{
3227 u32 rc = 0;
3228 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3229 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3230
3231 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3232
3233 req.tunnel_type = tunnel_type;
3234 req.tunnel_dst_port_val = port;
3235
3236 mutex_lock(&bp->hwrm_cmd_lock);
3237 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3238 if (rc) {
3239 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3240 rc);
3241 goto err_out;
3242 }
3243
57aac71b
CJ		 3244 switch (tunnel_type) {
3245 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
c0c050c5 3246 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
57aac71b
CJ		 3247 break;
3248 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
c0c050c5 3249 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
57aac71b
CJ		 3250 break;
3251 default:
3252 break;
3253 }
3254
c0c050c5
MC		 3255err_out:
3256 mutex_unlock(&bp->hwrm_cmd_lock);
3257 return rc;
3258}
3259
3260static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3261{
3262 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3263 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3264
3265 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
c193554e 3266 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
c0c050c5
MC		 3267
3268 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3269 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3270 req.mask = cpu_to_le32(vnic->rx_mask);
3271 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3272}
3273
3274#ifdef CONFIG_RFS_ACCEL
3275static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3276 struct bnxt_ntuple_filter *fltr)
3277{
3278 struct hwrm_cfa_ntuple_filter_free_input req = {0};
3279
3280 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3281 req.ntuple_filter_id = fltr->filter_id;
3282 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3283}
3284
3285#define BNXT_NTP_FLTR_FLAGS \
3286 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3287 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3288 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3289 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3290 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3291 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3292 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3293 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3294 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3295 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3296 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3297 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3298 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
c193554e 3299 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
c0c050c5
MC		 3300
3301static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3302 struct bnxt_ntuple_filter *fltr)
3303{
3304 int rc = 0;
3305 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3306 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3307 bp->hwrm_cmd_resp_addr;
3308 struct flow_keys *keys = &fltr->fkeys;
3309 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3310
3311 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
a54c4d74 3312 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
c0c050c5
MC		 3313
3314 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3315
3316 req.ethertype = htons(ETH_P_IP);
3317 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
c193554e 3318 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
c0c050c5
MC		 3319 req.ip_protocol = keys->basic.ip_proto;
3320
dda0e746
MC		 3321 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3322 int i;
3323
3324 req.ethertype = htons(ETH_P_IPV6);
3325 req.ip_addr_type =
3326 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3327 *(struct in6_addr *)&req.src_ipaddr[0] =
3328 keys->addrs.v6addrs.src;
3329 *(struct in6_addr *)&req.dst_ipaddr[0] =
3330 keys->addrs.v6addrs.dst;
3331 for (i = 0; i < 4; i++) {
3332 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3333 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3334 }
3335 } else {
3336 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3337 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3338 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3339 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3340 }
c0c050c5
MC		 3341
3342 req.src_port = keys->ports.src;
3343 req.src_port_mask = cpu_to_be16(0xffff);
3344 req.dst_port = keys->ports.dst;
3345 req.dst_port_mask = cpu_to_be16(0xffff);
3346
c193554e 3347 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
c0c050c5
MC		 3348 mutex_lock(&bp->hwrm_cmd_lock);
3349 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3350 if (!rc)
3351 fltr->filter_id = resp->ntuple_filter_id;
3352 mutex_unlock(&bp->hwrm_cmd_lock);
3353 return rc;
3354}
3355#endif
3356
3357static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3358 u8 *mac_addr)
3359{
3360 u32 rc = 0;
3361 struct hwrm_cfa_l2_filter_alloc_input req = {0};
3362 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3363
3364 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
dc52c6c7
PS		 3365 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3366 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3367 req.flags |=
3368 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
c193554e 3369 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
c0c050c5
MC		 3370 req.enables =
3371 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
c193554e 3372 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
c0c050c5
MC		 3373 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3374 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3375 req.l2_addr_mask[0] = 0xff;
3376 req.l2_addr_mask[1] = 0xff;
3377 req.l2_addr_mask[2] = 0xff;
3378 req.l2_addr_mask[3] = 0xff;
3379 req.l2_addr_mask[4] = 0xff;
3380 req.l2_addr_mask[5] = 0xff;
3381
3382 mutex_lock(&bp->hwrm_cmd_lock);
3383 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3384 if (!rc)
3385 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3386 resp->l2_filter_id;
3387 mutex_unlock(&bp->hwrm_cmd_lock);
3388 return rc;
3389}
3390
3391static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3392{
3393 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3394 int rc = 0;
3395
3396 /* Any associated ntuple filters will also be cleared by firmware. */
3397 mutex_lock(&bp->hwrm_cmd_lock);
3398 for (i = 0; i < num_of_vnics; i++) {
3399 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3400
3401 for (j = 0; j < vnic->uc_filter_count; j++) {
3402 struct hwrm_cfa_l2_filter_free_input req = {0};
3403
3404 bnxt_hwrm_cmd_hdr_init(bp, &req,
3405 HWRM_CFA_L2_FILTER_FREE, -1, -1);
3406
3407 req.l2_filter_id = vnic->fw_l2_filter_id[j];
3408
3409 rc = _hwrm_send_message(bp, &req, sizeof(req),
3410 HWRM_CMD_TIMEOUT);
3411 }
3412 vnic->uc_filter_count = 0;
3413 }
3414 mutex_unlock(&bp->hwrm_cmd_lock);
3415
3416 return rc;
3417}
3418
3419static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3420{
3421 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3422 struct hwrm_vnic_tpa_cfg_input req = {0};
3423
3424 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3425
3426 if (tpa_flags) {
3427 u16 mss = bp->dev->mtu - 40;
3428 u32 nsegs, n, segs = 0, flags;
3429
3430 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3431 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3432 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3433 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3434 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3435 if (tpa_flags & BNXT_FLAG_GRO)
3436 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3437
3438 req.flags = cpu_to_le32(flags);
3439
3440 req.enables =
3441 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
c193554e
MC		 3442 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3443 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
c0c050c5
MC		 3444
3445 /* Number of segs are log2 units, and first packet is not
3446 * included as part of this units.
3447 */
2839f28b
MC		 3448 if (mss <= BNXT_RX_PAGE_SIZE) {
3449 n = BNXT_RX_PAGE_SIZE / mss;
c0c050c5
MC		 3450 nsegs = (MAX_SKB_FRAGS - 1) * n;
3451 } else {
2839f28b
MC		 3452 n = mss / BNXT_RX_PAGE_SIZE;
3453 if (mss & (BNXT_RX_PAGE_SIZE - 1))
c0c050c5
MC		 3454 n++;
3455 nsegs = (MAX_SKB_FRAGS - n) / n;
3456 }
3457
3458 segs = ilog2(nsegs);
3459 req.max_agg_segs = cpu_to_le16(segs);
3460 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
c193554e
MC		 3461
3462 req.min_agg_len = cpu_to_le32(512);
c0c050c5
MC		 3463 }
3464 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3465
3466 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3467}
3468
3469static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3470{
3471 u32 i, j, max_rings;
3472 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3473 struct hwrm_vnic_rss_cfg_input req = {0};
3474
94ce9caa 3475 if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
c0c050c5
MC		 3476 return 0;
3477
3478 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3479 if (set_rss) {
87da7f79 3480 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
dc52c6c7
PS		 3481 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3482 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3483 max_rings = bp->rx_nr_rings - 1;
3484 else
3485 max_rings = bp->rx_nr_rings;
3486 } else {
c0c050c5 3487 max_rings = 1;
dc52c6c7 3488 }
c0c050c5
MC		 3489
3490 /* Fill the RSS indirection table with ring group ids */
3491 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3492 if (j == max_rings)
3493 j = 0;
3494 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3495 }
3496
3497 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3498 req.hash_key_tbl_addr =
3499 cpu_to_le64(vnic->rss_hash_key_dma_addr);
3500 }
94ce9caa 3501 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
c0c050c5
MC		 3502 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3503}
3504
3505static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3506{
3507 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3508 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3509
3510 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3511 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3512 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3513 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3514 req.enables =
3515 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3516 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3517 /* thresholds not implemented in firmware yet */
3518 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3519 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3520 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3521 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3522}
3523
94ce9caa
PS		 3524static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
3525 u16 ctx_idx)
c0c050c5
MC		 3526{
3527 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3528
3529 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3530 req.rss_cos_lb_ctx_id =
94ce9caa 3531 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
c0c050c5
MC		 3532
3533 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
94ce9caa 3534 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
c0c050c5
MC		 3535}
3536
3537static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3538{
94ce9caa 3539 int i, j;
c0c050c5
MC		 3540
3541 for (i = 0; i < bp->nr_vnics; i++) {
3542 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3543
94ce9caa
PS		 3544 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
3545 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
3546 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
3547 }
c0c050c5
MC		 3548 }
3549 bp->rsscos_nr_ctxs = 0;
3550}
3551
94ce9caa 3552static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
c0c050c5
MC		 3553{
3554 int rc;
3555 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3556 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3557 bp->hwrm_cmd_resp_addr;
3558
3559 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3560 -1);
3561
3562 mutex_lock(&bp->hwrm_cmd_lock);
3563 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3564 if (!rc)
94ce9caa 3565 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
c0c050c5
MC		 3566 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3567 mutex_unlock(&bp->hwrm_cmd_lock);
3568
3569 return rc;
3570}
3571
a588e458 3572int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
c0c050c5 3573{
b81a90d3 3574 unsigned int ring = 0, grp_idx;
c0c050c5
MC		 3575 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3576 struct hwrm_vnic_cfg_input req = {0};
cf6645f8 3577 u16 def_vlan = 0;
c0c050c5
MC		 3578
3579 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
dc52c6c7
PS		 3580
3581 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
c0c050c5 3582 /* Only RSS support for now TBD: COS & LB */
dc52c6c7
PS		 3583 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
3584 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3585 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3586 VNIC_CFG_REQ_ENABLES_MRU);
ae10ae74
MC		 3587 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
3588 req.rss_rule =
3589 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
3590 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3591 VNIC_CFG_REQ_ENABLES_MRU);
3592 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
dc52c6c7
PS		 3593 } else {
3594 req.rss_rule = cpu_to_le16(0xffff);
3595 }
94ce9caa 3596
dc52c6c7
PS		 3597 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
3598 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
94ce9caa
PS		 3599 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
3600 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
3601 } else {
3602 req.cos_rule = cpu_to_le16(0xffff);
3603 }
3604
c0c050c5 3605 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
b81a90d3 3606 ring = 0;
c0c050c5 3607 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
b81a90d3 3608 ring = vnic_id - 1;
76595193
PS		 3609 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
3610 ring = bp->rx_nr_rings - 1;
c0c050c5 3611
b81a90d3 3612 grp_idx = bp->rx_ring[ring].bnapi->index;
c0c050c5
MC		 3613 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3614 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3615
3616 req.lb_rule = cpu_to_le16(0xffff);
3617 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3618 VLAN_HLEN);
3619
cf6645f8
MC		 3620#ifdef CONFIG_BNXT_SRIOV
3621 if (BNXT_VF(bp))
3622 def_vlan = bp->vf.vlan;
3623#endif
3624 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
c0c050c5 3625 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
a588e458
MC		 3626 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
3627 req.flags |=
3628 cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE);
c0c050c5
MC		 3629
3630 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3631}
3632
3633static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3634{
3635 u32 rc = 0;
3636
3637 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3638 struct hwrm_vnic_free_input req = {0};
3639
3640 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3641 req.vnic_id =
3642 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3643
3644 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3645 if (rc)
3646 return rc;
3647 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3648 }
3649 return rc;
3650}
3651
3652static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3653{
3654 u16 i;
3655
3656 for (i = 0; i < bp->nr_vnics; i++)
3657 bnxt_hwrm_vnic_free_one(bp, i);
3658}
3659
b81a90d3
MC		 3660static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3661 unsigned int start_rx_ring_idx,
3662 unsigned int nr_rings)
c0c050c5 3663{
b81a90d3
MC		 3664 int rc = 0;
3665 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
c0c050c5
MC		 3666 struct hwrm_vnic_alloc_input req = {0};
3667 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3668
3669 /* map ring groups to this vnic */
b81a90d3
MC		 3670 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3671 grp_idx = bp->rx_ring[i].bnapi->index;
3672 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
c0c050c5 3673 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
b81a90d3 3674 j, nr_rings);
c0c050c5
MC		 3675 break;
3676 }
3677 bp->vnic_info[vnic_id].fw_grp_ids[j] =
b81a90d3 3678 bp->grp_info[grp_idx].fw_grp_id;
c0c050c5
MC		 3679 }
3680
94ce9caa
PS		 3681 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
3682 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
c0c050c5
MC		 3683 if (vnic_id == 0)
3684 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3685
3686 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3687
3688 mutex_lock(&bp->hwrm_cmd_lock);
3689 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3690 if (!rc)
3691 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3692 mutex_unlock(&bp->hwrm_cmd_lock);
3693 return rc;
3694}
3695
8fdefd63
MC		 3696static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
3697{
3698 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3699 struct hwrm_vnic_qcaps_input req = {0};
3700 int rc;
3701
3702 if (bp->hwrm_spec_code < 0x10600)
3703 return 0;
3704
3705 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
3706 mutex_lock(&bp->hwrm_cmd_lock);
3707 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3708 if (!rc) {
3709 if (resp->flags &
3710 cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
3711 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
3712 }
3713 mutex_unlock(&bp->hwrm_cmd_lock);
3714 return rc;
3715}
3716
c0c050c5
MC		 3717static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3718{
3719 u16 i;
3720 u32 rc = 0;
3721
3722 mutex_lock(&bp->hwrm_cmd_lock);
3723 for (i = 0; i < bp->rx_nr_rings; i++) {
3724 struct hwrm_ring_grp_alloc_input req = {0};
3725 struct hwrm_ring_grp_alloc_output *resp =
3726 bp->hwrm_cmd_resp_addr;
b81a90d3 3727 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
c0c050c5
MC		 3728
3729 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3730
b81a90d3
MC		 3731 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3732 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3733 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3734 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
c0c050c5
MC		 3735
3736 rc = _hwrm_send_message(bp, &req, sizeof(req),
3737 HWRM_CMD_TIMEOUT);
3738 if (rc)
3739 break;
3740
b81a90d3
MC		 3741 bp->grp_info[grp_idx].fw_grp_id =
3742 le32_to_cpu(resp->ring_group_id);
c0c050c5
MC		 3743 }
3744 mutex_unlock(&bp->hwrm_cmd_lock);
3745 return rc;
3746}
3747
3748static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3749{
3750 u16 i;
3751 u32 rc = 0;
3752 struct hwrm_ring_grp_free_input req = {0};
3753
3754 if (!bp->grp_info)
3755 return 0;
3756
3757 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3758
3759 mutex_lock(&bp->hwrm_cmd_lock);
3760 for (i = 0; i < bp->cp_nr_rings; i++) {
3761 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3762 continue;
3763 req.ring_group_id =
3764 cpu_to_le32(bp->grp_info[i].fw_grp_id);
3765
3766 rc = _hwrm_send_message(bp, &req, sizeof(req),
3767 HWRM_CMD_TIMEOUT);
3768 if (rc)
3769 break;
3770 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3771 }
3772 mutex_unlock(&bp->hwrm_cmd_lock);
3773 return rc;
3774}
3775
3776static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3777 struct bnxt_ring_struct *ring,
3778 u32 ring_type, u32 map_index,
3779 u32 stats_ctx_id)
3780{
3781 int rc = 0, err = 0;
3782 struct hwrm_ring_alloc_input req = {0};
3783 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3784 u16 ring_id;
3785
3786 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3787
3788 req.enables = 0;
3789 if (ring->nr_pages > 1) {
3790 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3791 /* Page size is in log2 units */
3792 req.page_size = BNXT_PAGE_SHIFT;
3793 req.page_tbl_depth = 1;
3794 } else {
3795 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
3796 }
3797 req.fbo = 0;
3798 /* Association of ring index with doorbell index and MSIX number */
3799 req.logical_id = cpu_to_le16(map_index);
3800
3801 switch (ring_type) {
3802 case HWRM_RING_ALLOC_TX:
3803 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3804 /* Association of transmit ring with completion ring */
3805 req.cmpl_ring_id =
3806 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3807 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3808 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3809 req.queue_id = cpu_to_le16(ring->queue_id);
3810 break;
3811 case HWRM_RING_ALLOC_RX:
3812 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3813 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3814 break;
3815 case HWRM_RING_ALLOC_AGG:
3816 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3817 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3818 break;
3819 case HWRM_RING_ALLOC_CMPL:
3820 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3821 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3822 if (bp->flags & BNXT_FLAG_USING_MSIX)
3823 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3824 break;
3825 default:
3826 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3827 ring_type);
3828 return -1;
3829 }
3830
3831 mutex_lock(&bp->hwrm_cmd_lock);
3832 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3833 err = le16_to_cpu(resp->error_code);
3834 ring_id = le16_to_cpu(resp->ring_id);
3835 mutex_unlock(&bp->hwrm_cmd_lock);
3836
3837 if (rc || err) {
3838 switch (ring_type) {
3839 case RING_FREE_REQ_RING_TYPE_CMPL:
3840 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3841 rc, err);
3842 return -1;
3843
3844 case RING_FREE_REQ_RING_TYPE_RX:
3845 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3846 rc, err);
3847 return -1;
3848
3849 case RING_FREE_REQ_RING_TYPE_TX:
3850 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3851 rc, err);
3852 return -1;
3853
3854 default:
3855 netdev_err(bp->dev, "Invalid ring\n");
3856 return -1;
3857 }
3858 }
3859 ring->fw_ring_id = ring_id;
3860 return rc;
3861}
3862
486b5c22
MC		 3863static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
3864{
3865 int rc;
3866
3867 if (BNXT_PF(bp)) {
3868 struct hwrm_func_cfg_input req = {0};
3869
3870 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
3871 req.fid = cpu_to_le16(0xffff);
3872 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
3873 req.async_event_cr = cpu_to_le16(idx);
3874 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3875 } else {
3876 struct hwrm_func_vf_cfg_input req = {0};
3877
3878 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
3879 req.enables =
3880 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
3881 req.async_event_cr = cpu_to_le16(idx);
3882 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3883 }
3884 return rc;
3885}
3886
c0c050c5
MC		 3887static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3888{
3889 int i, rc = 0;
3890
edd0c2cc
MC		 3891 for (i = 0; i < bp->cp_nr_rings; i++) {
3892 struct bnxt_napi *bnapi = bp->bnapi[i];
3893 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3894 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
c0c050c5 3895
33e52d88 3896 cpr->cp_doorbell = bp->bar1 + i * 0x80;
edd0c2cc
MC		 3897 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
3898 INVALID_STATS_CTX_ID);
3899 if (rc)
3900 goto err_out;
edd0c2cc
MC		 3901 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3902 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
486b5c22
MC		 3903
3904 if (!i) {
3905 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
3906 if (rc)
3907 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
3908 }
c0c050c5
MC		 3909 }
3910
edd0c2cc 3911 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 3912 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 3913 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 3914 u32 map_idx = txr->bnapi->index;
3915 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
c0c050c5 3916
b81a90d3
MC		 3917 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
3918 map_idx, fw_stats_ctx);
edd0c2cc
MC		 3919 if (rc)
3920 goto err_out;
b81a90d3 3921 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 3922 }
3923
edd0c2cc 3924 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3925 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 3926 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3 3927 u32 map_idx = rxr->bnapi->index;
c0c050c5 3928
b81a90d3
MC		 3929 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
3930 map_idx, INVALID_STATS_CTX_ID);
edd0c2cc
MC		 3931 if (rc)
3932 goto err_out;
b81a90d3 3933 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
edd0c2cc 3934 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
b81a90d3 3935 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 3936 }
3937
3938 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3939 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 3940 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
c0c050c5
MC		 3941 struct bnxt_ring_struct *ring =
3942 &rxr->rx_agg_ring_struct;
b81a90d3
MC		 3943 u32 grp_idx = rxr->bnapi->index;
3944 u32 map_idx = grp_idx + bp->rx_nr_rings;
c0c050c5
MC		 3945
3946 rc = hwrm_ring_alloc_send_msg(bp, ring,
3947 HWRM_RING_ALLOC_AGG,
b81a90d3 3948 map_idx,
c0c050c5
MC		 3949 INVALID_STATS_CTX_ID);
3950 if (rc)
3951 goto err_out;
3952
b81a90d3 3953 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
c0c050c5
MC		 3954 writel(DB_KEY_RX | rxr->rx_agg_prod,
3955 rxr->rx_agg_doorbell);
b81a90d3 3956 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
c0c050c5
MC		 3957 }
3958 }
3959err_out:
3960 return rc;
3961}
3962
3963static int hwrm_ring_free_send_msg(struct bnxt *bp,
3964 struct bnxt_ring_struct *ring,
3965 u32 ring_type, int cmpl_ring_id)
3966{
3967 int rc;
3968 struct hwrm_ring_free_input req = {0};
3969 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3970 u16 error_code;
3971
74608fc9 3972 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
c0c050c5
MC		 3973 req.ring_type = ring_type;
3974 req.ring_id = cpu_to_le16(ring->fw_ring_id);
3975
3976 mutex_lock(&bp->hwrm_cmd_lock);
3977 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3978 error_code = le16_to_cpu(resp->error_code);
3979 mutex_unlock(&bp->hwrm_cmd_lock);
3980
3981 if (rc || error_code) {
3982 switch (ring_type) {
3983 case RING_FREE_REQ_RING_TYPE_CMPL:
3984 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3985 rc);
3986 return rc;
3987 case RING_FREE_REQ_RING_TYPE_RX:
3988 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3989 rc);
3990 return rc;
3991 case RING_FREE_REQ_RING_TYPE_TX:
3992 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3993 rc);
3994 return rc;
3995 default:
3996 netdev_err(bp->dev, "Invalid ring\n");
3997 return -1;
3998 }
3999 }
4000 return 0;
4001}
4002
edd0c2cc 4003static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
c0c050c5 4004{
edd0c2cc 4005 int i;
c0c050c5
MC		 4006
4007 if (!bp->bnapi)
edd0c2cc 4008 return;
c0c050c5 4009
edd0c2cc 4010 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 4011 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
edd0c2cc 4012 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
b81a90d3
MC		 4013 u32 grp_idx = txr->bnapi->index;
4014 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 4015
4016 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4017 hwrm_ring_free_send_msg(bp, ring,
4018 RING_FREE_REQ_RING_TYPE_TX,
4019 close_path ? cmpl_ring_id :
4020 INVALID_HW_RING_ID);
4021 ring->fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 4022 }
4023 }
4024
edd0c2cc 4025 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4026 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 4027 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
b81a90d3
MC		 4028 u32 grp_idx = rxr->bnapi->index;
4029 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 4030
4031 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4032 hwrm_ring_free_send_msg(bp, ring,
4033 RING_FREE_REQ_RING_TYPE_RX,
4034 close_path ? cmpl_ring_id :
4035 INVALID_HW_RING_ID);
4036 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 4037 bp->grp_info[grp_idx].rx_fw_ring_id =
4038 INVALID_HW_RING_ID;
c0c050c5
MC		 4039 }
4040 }
4041
edd0c2cc 4042 for (i = 0; i < bp->rx_nr_rings; i++) {
b6ab4b01 4043 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
edd0c2cc 4044 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
b81a90d3
MC		 4045 u32 grp_idx = rxr->bnapi->index;
4046 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
edd0c2cc
MC		 4047
4048 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4049 hwrm_ring_free_send_msg(bp, ring,
4050 RING_FREE_REQ_RING_TYPE_RX,
4051 close_path ? cmpl_ring_id :
4052 INVALID_HW_RING_ID);
4053 ring->fw_ring_id = INVALID_HW_RING_ID;
b81a90d3
MC		 4054 bp->grp_info[grp_idx].agg_fw_ring_id =
4055 INVALID_HW_RING_ID;
c0c050c5
MC		 4056 }
4057 }
4058
9d8bc097
MC		 4059 /* The completion rings are about to be freed. After that the
4060 * IRQ doorbell will not work anymore. So we need to disable
4061 * IRQ here.
4062 */
4063 bnxt_disable_int_sync(bp);
4064
edd0c2cc
MC		 4065 for (i = 0; i < bp->cp_nr_rings; i++) {
4066 struct bnxt_napi *bnapi = bp->bnapi[i];
4067 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4068 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4069
4070 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4071 hwrm_ring_free_send_msg(bp, ring,
4072 RING_FREE_REQ_RING_TYPE_CMPL,
4073 INVALID_HW_RING_ID);
4074 ring->fw_ring_id = INVALID_HW_RING_ID;
4075 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
c0c050c5
MC		 4076 }
4077 }
c0c050c5
MC		 4078}
4079
391be5c2
MC		 4080/* Caller must hold bp->hwrm_cmd_lock */
4081int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4082{
4083 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4084 struct hwrm_func_qcfg_input req = {0};
4085 int rc;
4086
4087 if (bp->hwrm_spec_code < 0x10601)
4088 return 0;
4089
4090 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4091 req.fid = cpu_to_le16(fid);
4092 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4093 if (!rc)
4094 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4095
4096 return rc;
4097}
4098
4099int bnxt_hwrm_reserve_tx_rings(struct bnxt *bp, int *tx_rings)
4100{
4101 struct hwrm_func_cfg_input req = {0};
4102 int rc;
4103
4104 if (bp->hwrm_spec_code < 0x10601)
4105 return 0;
4106
4107 if (BNXT_VF(bp))
4108 return 0;
4109
4110 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4111 req.fid = cpu_to_le16(0xffff);
4112 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS);
4113 req.num_tx_rings = cpu_to_le16(*tx_rings);
4114 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4115 if (rc)
4116 return rc;
4117
4118 mutex_lock(&bp->hwrm_cmd_lock);
4119 rc = __bnxt_hwrm_get_tx_rings(bp, 0xffff, tx_rings);
4120 mutex_unlock(&bp->hwrm_cmd_lock);
4121 return rc;
4122}
4123
bb053f52
MC		 4124static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
4125 u32 buf_tmrs, u16 flags,
4126 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4127{
4128 req->flags = cpu_to_le16(flags);
4129 req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
4130 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
4131 req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
4132 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
4133 /* Minimum time between 2 interrupts set to buf_tmr x 2 */
4134 req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
4135 req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
4136 req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
4137}
4138
c0c050c5
MC		 4139int bnxt_hwrm_set_coal(struct bnxt *bp)
4140{
4141 int i, rc = 0;
dfc9c94a
MC		 4142 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
4143 req_tx = {0}, *req;
c0c050c5
MC		 4144 u16 max_buf, max_buf_irq;
4145 u16 buf_tmr, buf_tmr_irq;
4146 u32 flags;
4147
dfc9c94a
MC		 4148 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4149 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4150 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
4151 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
c0c050c5 4152
dfb5b894
MC		 4153 /* Each rx completion (2 records) should be DMAed immediately.
4154 * DMA 1/4 of the completion buffers at a time.
4155 */
4156 max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
c0c050c5
MC		 4157 /* max_buf must not be zero */
4158 max_buf = clamp_t(u16, max_buf, 1, 63);
dfb5b894
MC		 4159 max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
4160 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
4161 /* buf timer set to 1/4 of interrupt timer */
4162 buf_tmr = max_t(u16, buf_tmr / 4, 1);
4163 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
4164 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
c0c050c5
MC		 4165
4166 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4167
4168 /* RING_IDLE generates more IRQs for lower latency. Enable it only
4169 * if coal_ticks is less than 25 us.
4170 */
dfb5b894 4171 if (bp->rx_coal_ticks < 25)
c0c050c5
MC		 4172 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4173
bb053f52 4174 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
dfc9c94a
MC		 4175 buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
4176
4177 /* max_buf must not be zero */
4178 max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
4179 max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
4180 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
4181 /* buf timer set to 1/4 of interrupt timer */
4182 buf_tmr = max_t(u16, buf_tmr / 4, 1);
4183 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
4184 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4185
4186 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4187 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4188 buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
c0c050c5
MC		 4189
4190 mutex_lock(&bp->hwrm_cmd_lock);
4191 for (i = 0; i < bp->cp_nr_rings; i++) {
dfc9c94a 4192 struct bnxt_napi *bnapi = bp->bnapi[i];
c0c050c5 4193
dfc9c94a
MC		 4194 req = &req_rx;
4195 if (!bnapi->rx_ring)
4196 req = &req_tx;
4197 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
4198
4199 rc = _hwrm_send_message(bp, req, sizeof(*req),
c0c050c5
MC		 4200 HWRM_CMD_TIMEOUT);
4201 if (rc)
4202 break;
4203 }
4204 mutex_unlock(&bp->hwrm_cmd_lock);
4205 return rc;
4206}
4207
4208static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
4209{
4210 int rc = 0, i;
4211 struct hwrm_stat_ctx_free_input req = {0};
4212
4213 if (!bp->bnapi)
4214 return 0;
4215
3e8060fa
PS		 4216 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4217 return 0;
4218
c0c050c5
MC		 4219 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
4220
4221 mutex_lock(&bp->hwrm_cmd_lock);
4222 for (i = 0; i < bp->cp_nr_rings; i++) {
4223 struct bnxt_napi *bnapi = bp->bnapi[i];
4224 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4225
4226 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
4227 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
4228
4229 rc = _hwrm_send_message(bp, &req, sizeof(req),
4230 HWRM_CMD_TIMEOUT);
4231 if (rc)
4232 break;
4233
4234 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4235 }
4236 }
4237 mutex_unlock(&bp->hwrm_cmd_lock);
4238 return rc;
4239}
4240
4241static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
4242{
4243 int rc = 0, i;
4244 struct hwrm_stat_ctx_alloc_input req = {0};
4245 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4246
3e8060fa
PS		 4247 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4248 return 0;
4249
c0c050c5
MC		 4250 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
4251
51f30785 4252 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
c0c050c5
MC		 4253
4254 mutex_lock(&bp->hwrm_cmd_lock);
4255 for (i = 0; i < bp->cp_nr_rings; i++) {
4256 struct bnxt_napi *bnapi = bp->bnapi[i];
4257 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4258
4259 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
4260
4261 rc = _hwrm_send_message(bp, &req, sizeof(req),
4262 HWRM_CMD_TIMEOUT);
4263 if (rc)
4264 break;
4265
4266 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
4267
4268 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
4269 }
4270 mutex_unlock(&bp->hwrm_cmd_lock);
89aa8445 4271 return rc;
c0c050c5
MC		 4272}
4273
cf6645f8
MC		 4274static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
4275{
4276 struct hwrm_func_qcfg_input req = {0};
567b2abe 4277 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
cf6645f8
MC		 4278 int rc;
4279
4280 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4281 req.fid = cpu_to_le16(0xffff);
4282 mutex_lock(&bp->hwrm_cmd_lock);
4283 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4284 if (rc)
4285 goto func_qcfg_exit;
4286
4287#ifdef CONFIG_BNXT_SRIOV
4288 if (BNXT_VF(bp)) {
cf6645f8
MC		 4289 struct bnxt_vf_info *vf = &bp->vf;
4290
4291 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
4292 }
4293#endif
567b2abe
SB		 4294 switch (resp->port_partition_type) {
4295 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
4296 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
4297 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
4298 bp->port_partition_type = resp->port_partition_type;
4299 break;
4300 }
cf6645f8
MC		 4301
4302func_qcfg_exit:
4303 mutex_unlock(&bp->hwrm_cmd_lock);
4304 return rc;
4305}
4306
7b08f661 4307static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
c0c050c5
MC		 4308{
4309 int rc = 0;
4310 struct hwrm_func_qcaps_input req = {0};
4311 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4312
4313 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
4314 req.fid = cpu_to_le16(0xffff);
4315
4316 mutex_lock(&bp->hwrm_cmd_lock);
4317 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4318 if (rc)
4319 goto hwrm_func_qcaps_exit;
4320
e4060d30
MC		 4321 if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED))
4322 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
4323 if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED))
4324 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
4325
7cc5a20e
MC		 4326 bp->tx_push_thresh = 0;
4327 if (resp->flags &
4328 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
4329 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
4330
c0c050c5
MC		 4331 if (BNXT_PF(bp)) {
4332 struct bnxt_pf_info *pf = &bp->pf;
4333
4334 pf->fw_fid = le16_to_cpu(resp->fid);
4335 pf->port_id = le16_to_cpu(resp->port_id);
87027db1 4336 bp->dev->dev_port = pf->port_id;
11f15ed3 4337 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
bdd4347b 4338 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
c0c050c5
MC		 4339 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4340 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4341 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
c0c050c5 4342 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
b72d4a68
MC		 4343 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4344 if (!pf->max_hw_ring_grps)
4345 pf->max_hw_ring_grps = pf->max_tx_rings;
c0c050c5
MC		 4346 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4347 pf->max_vnics = le16_to_cpu(resp->max_vnics);
4348 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4349 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
4350 pf->max_vfs = le16_to_cpu(resp->max_vfs);
4351 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
4352 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
4353 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
4354 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
4355 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
4356 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
4357 } else {
379a80a1 4358#ifdef CONFIG_BNXT_SRIOV
c0c050c5
MC		 4359 struct bnxt_vf_info *vf = &bp->vf;
4360
4361 vf->fw_fid = le16_to_cpu(resp->fid);
c0c050c5
MC		 4362
4363 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4364 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4365 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4366 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
b72d4a68
MC		 4367 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4368 if (!vf->max_hw_ring_grps)
4369 vf->max_hw_ring_grps = vf->max_tx_rings;
c0c050c5
MC		 4370 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4371 vf->max_vnics = le16_to_cpu(resp->max_vnics);
4372 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
7cc5a20e
MC		 4373
4374 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
001154eb
MC		 4375 mutex_unlock(&bp->hwrm_cmd_lock);
4376
4377 if (is_valid_ether_addr(vf->mac_addr)) {
7cc5a20e
MC		 4378 /* overwrite netdev dev_adr with admin VF MAC */
4379 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
001154eb 4380 } else {
7cc5a20e 4381 random_ether_addr(bp->dev->dev_addr);
001154eb
MC		 4382 rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
4383 }
4384 return rc;
379a80a1 4385#endif
c0c050c5
MC		 4386 }
4387
c0c050c5
MC		 4388hwrm_func_qcaps_exit:
4389 mutex_unlock(&bp->hwrm_cmd_lock);
4390 return rc;
4391}
4392
4393static int bnxt_hwrm_func_reset(struct bnxt *bp)
4394{
4395 struct hwrm_func_reset_input req = {0};
4396
4397 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
4398 req.enables = 0;
4399
4400 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
4401}
4402
4403static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
4404{
4405 int rc = 0;
4406 struct hwrm_queue_qportcfg_input req = {0};
4407 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
4408 u8 i, *qptr;
4409
4410 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
4411
4412 mutex_lock(&bp->hwrm_cmd_lock);
4413 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4414 if (rc)
4415 goto qportcfg_exit;
4416
4417 if (!resp->max_configurable_queues) {
4418 rc = -EINVAL;
4419 goto qportcfg_exit;
4420 }
4421 bp->max_tc = resp->max_configurable_queues;
87c374de 4422 bp->max_lltc = resp->max_configurable_lossless_queues;
c0c050c5
MC		 4423 if (bp->max_tc > BNXT_MAX_QUEUE)
4424 bp->max_tc = BNXT_MAX_QUEUE;
4425
441cabbb
MC		 4426 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
4427 bp->max_tc = 1;
4428
87c374de
MC		 4429 if (bp->max_lltc > bp->max_tc)
4430 bp->max_lltc = bp->max_tc;
4431
c0c050c5
MC		 4432 qptr = &resp->queue_id0;
4433 for (i = 0; i < bp->max_tc; i++) {
4434 bp->q_info[i].queue_id = *qptr++;
4435 bp->q_info[i].queue_profile = *qptr++;
4436 }
4437
4438qportcfg_exit:
4439 mutex_unlock(&bp->hwrm_cmd_lock);
4440 return rc;
4441}
4442
4443static int bnxt_hwrm_ver_get(struct bnxt *bp)
4444{
4445 int rc;
4446 struct hwrm_ver_get_input req = {0};
4447 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
4448
e6ef2699 4449 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
c0c050c5
MC		 4450 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4451 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4452 req.hwrm_intf_min = HWRM_VERSION_MINOR;
4453 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4454 mutex_lock(&bp->hwrm_cmd_lock);
4455 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4456 if (rc)
4457 goto hwrm_ver_get_exit;
4458
4459 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4460
11f15ed3
MC		 4461 bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
4462 resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
c193554e
MC		 4463 if (resp->hwrm_intf_maj < 1) {
4464 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
c0c050c5 4465 resp->hwrm_intf_maj, resp->hwrm_intf_min,
c193554e
MC		 4466 resp->hwrm_intf_upd);
4467 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
c0c050c5 4468 }
3ebf6f0a 4469 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
c0c050c5
MC		 4470 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
4471 resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
4472
ff4fe81d
MC		 4473 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4474 if (!bp->hwrm_cmd_timeout)
4475 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4476
e6ef2699
MC		 4477 if (resp->hwrm_intf_maj >= 1)
4478 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4479
659c805c 4480 bp->chip_num = le16_to_cpu(resp->chip_num);
3e8060fa
PS		 4481 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
4482 !resp->chip_metal)
4483 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
659c805c 4484
c0c050c5
MC		 4485hwrm_ver_get_exit:
4486 mutex_unlock(&bp->hwrm_cmd_lock);
4487 return rc;
4488}
4489
5ac67d8b
RS		 4490int bnxt_hwrm_fw_set_time(struct bnxt *bp)
4491{
878786d9 4492#if IS_ENABLED(CONFIG_RTC_LIB)
5ac67d8b
RS		 4493 struct hwrm_fw_set_time_input req = {0};
4494 struct rtc_time tm;
4495 struct timeval tv;
4496
4497 if (bp->hwrm_spec_code < 0x10400)
4498 return -EOPNOTSUPP;
4499
4500 do_gettimeofday(&tv);
4501 rtc_time_to_tm(tv.tv_sec, &tm);
4502 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
4503 req.year = cpu_to_le16(1900 + tm.tm_year);
4504 req.month = 1 + tm.tm_mon;
4505 req.day = tm.tm_mday;
4506 req.hour = tm.tm_hour;
4507 req.minute = tm.tm_min;
4508 req.second = tm.tm_sec;
4509 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
878786d9
RS		 4510#else
4511 return -EOPNOTSUPP;
4512#endif
5ac67d8b
RS		 4513}
4514
3bdf56c4
MC		 4515static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4516{
4517 int rc;
4518 struct bnxt_pf_info *pf = &bp->pf;
4519 struct hwrm_port_qstats_input req = {0};
4520
4521 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
4522 return 0;
4523
4524 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
4525 req.port_id = cpu_to_le16(pf->port_id);
4526 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
4527 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
4528 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4529 return rc;
4530}
4531
c0c050c5
MC		 4532static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
4533{
4534 if (bp->vxlan_port_cnt) {
4535 bnxt_hwrm_tunnel_dst_port_free(
4536 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
4537 }
4538 bp->vxlan_port_cnt = 0;
4539 if (bp->nge_port_cnt) {
4540 bnxt_hwrm_tunnel_dst_port_free(
4541 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
4542 }
4543 bp->nge_port_cnt = 0;
4544}
4545
4546static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
4547{
4548 int rc, i;
4549 u32 tpa_flags = 0;
4550
4551 if (set_tpa)
4552 tpa_flags = bp->flags & BNXT_FLAG_TPA;
4553 for (i = 0; i < bp->nr_vnics; i++) {
4554 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
4555 if (rc) {
4556 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4557 rc, i);
4558 return rc;
4559 }
4560 }
4561 return 0;
4562}
4563
4564static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
4565{
4566 int i;
4567
4568 for (i = 0; i < bp->nr_vnics; i++)
4569 bnxt_hwrm_vnic_set_rss(bp, i, false);
4570}
4571
4572static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
4573 bool irq_re_init)
4574{
4575 if (bp->vnic_info) {
4576 bnxt_hwrm_clear_vnic_filter(bp);
4577 /* clear all RSS setting before free vnic ctx */
4578 bnxt_hwrm_clear_vnic_rss(bp);
4579 bnxt_hwrm_vnic_ctx_free(bp);
4580 /* before free the vnic, undo the vnic tpa settings */
4581 if (bp->flags & BNXT_FLAG_TPA)
4582 bnxt_set_tpa(bp, false);
4583 bnxt_hwrm_vnic_free(bp);
4584 }
4585 bnxt_hwrm_ring_free(bp, close_path);
4586 bnxt_hwrm_ring_grp_free(bp);
4587 if (irq_re_init) {
4588 bnxt_hwrm_stat_ctx_free(bp);
4589 bnxt_hwrm_free_tunnel_ports(bp);
4590 }
4591}
4592
4593static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
4594{
ae10ae74 4595 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
c0c050c5
MC		 4596 int rc;
4597
ae10ae74
MC		 4598 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
4599 goto skip_rss_ctx;
4600
c0c050c5 4601 /* allocate context for vnic */
94ce9caa 4602 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
c0c050c5
MC		 4603 if (rc) {
4604 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4605 vnic_id, rc);
4606 goto vnic_setup_err;
4607 }
4608 bp->rsscos_nr_ctxs++;
4609
94ce9caa
PS		 4610 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4611 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
4612 if (rc) {
4613 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
4614 vnic_id, rc);
4615 goto vnic_setup_err;
4616 }
4617 bp->rsscos_nr_ctxs++;
4618 }
4619
ae10ae74 4620skip_rss_ctx:
c0c050c5
MC		 4621 /* configure default vnic, ring grp */
4622 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
4623 if (rc) {
4624 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
4625 vnic_id, rc);
4626 goto vnic_setup_err;
4627 }
4628
4629 /* Enable RSS hashing on vnic */
4630 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
4631 if (rc) {
4632 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
4633 vnic_id, rc);
4634 goto vnic_setup_err;
4635 }
4636
4637 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4638 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
4639 if (rc) {
4640 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
4641 vnic_id, rc);
4642 }
4643 }
4644
4645vnic_setup_err:
4646 return rc;
4647}
4648
4649static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
4650{
4651#ifdef CONFIG_RFS_ACCEL
4652 int i, rc = 0;
4653
4654 for (i = 0; i < bp->rx_nr_rings; i++) {
ae10ae74 4655 struct bnxt_vnic_info *vnic;
c0c050c5
MC		 4656 u16 vnic_id = i + 1;
4657 u16 ring_id = i;
4658
4659 if (vnic_id >= bp->nr_vnics)
4660 break;
4661
ae10ae74
MC		 4662 vnic = &bp->vnic_info[vnic_id];
4663 vnic->flags |= BNXT_VNIC_RFS_FLAG;
4664 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
4665 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
b81a90d3 4666 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
c0c050c5
MC		 4667 if (rc) {
4668 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4669 vnic_id, rc);
4670 break;
4671 }
4672 rc = bnxt_setup_vnic(bp, vnic_id);
4673 if (rc)
4674 break;
4675 }
4676 return rc;
4677#else
4678 return 0;
4679#endif
4680}
4681
17c71ac3
MC		 4682/* Allow PF and VF with default VLAN to be in promiscuous mode */
4683static bool bnxt_promisc_ok(struct bnxt *bp)
4684{
4685#ifdef CONFIG_BNXT_SRIOV
4686 if (BNXT_VF(bp) && !bp->vf.vlan)
4687 return false;
4688#endif
4689 return true;
4690}
4691
dc52c6c7
PS		 4692static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
4693{
4694 unsigned int rc = 0;
4695
4696 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
4697 if (rc) {
4698 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4699 rc);
4700 return rc;
4701 }
4702
4703 rc = bnxt_hwrm_vnic_cfg(bp, 1);
4704 if (rc) {
4705 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4706 rc);
4707 return rc;
4708 }
4709 return rc;
4710}
4711
b664f008 4712static int bnxt_cfg_rx_mode(struct bnxt *);
7d2837dd 4713static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
b664f008 4714
c0c050c5
MC		 4715static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
4716{
7d2837dd 4717 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
c0c050c5 4718 int rc = 0;
76595193 4719 unsigned int rx_nr_rings = bp->rx_nr_rings;
c0c050c5
MC		 4720
4721 if (irq_re_init) {
4722 rc = bnxt_hwrm_stat_ctx_alloc(bp);
4723 if (rc) {
4724 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
4725 rc);
4726 goto err_out;
4727 }
4728 }
4729
4730 rc = bnxt_hwrm_ring_alloc(bp);
4731 if (rc) {
4732 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
4733 goto err_out;
4734 }
4735
4736 rc = bnxt_hwrm_ring_grp_alloc(bp);
4737 if (rc) {
4738 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
4739 goto err_out;
4740 }
4741
76595193
PS		 4742 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4743 rx_nr_rings--;
4744
c0c050c5 4745 /* default vnic 0 */
76595193 4746 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
c0c050c5
MC		 4747 if (rc) {
4748 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
4749 goto err_out;
4750 }
4751
4752 rc = bnxt_setup_vnic(bp, 0);
4753 if (rc)
4754 goto err_out;
4755
4756 if (bp->flags & BNXT_FLAG_RFS) {
4757 rc = bnxt_alloc_rfs_vnics(bp);
4758 if (rc)
4759 goto err_out;
4760 }
4761
4762 if (bp->flags & BNXT_FLAG_TPA) {
4763 rc = bnxt_set_tpa(bp, true);
4764 if (rc)
4765 goto err_out;
4766 }
4767
4768 if (BNXT_VF(bp))
4769 bnxt_update_vf_mac(bp);
4770
4771 /* Filter for default vnic 0 */
4772 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
4773 if (rc) {
4774 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
4775 goto err_out;
4776 }
7d2837dd 4777 vnic->uc_filter_count = 1;
c0c050c5 4778
7d2837dd 4779 vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
c0c050c5 4780
17c71ac3 4781 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7d2837dd
MC		 4782 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4783
4784 if (bp->dev->flags & IFF_ALLMULTI) {
4785 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4786 vnic->mc_list_count = 0;
4787 } else {
4788 u32 mask = 0;
4789
4790 bnxt_mc_list_updated(bp, &mask);
4791 vnic->rx_mask |= mask;
4792 }
c0c050c5 4793
b664f008
MC		 4794 rc = bnxt_cfg_rx_mode(bp);
4795 if (rc)
c0c050c5 4796 goto err_out;
c0c050c5
MC		 4797
4798 rc = bnxt_hwrm_set_coal(bp);
4799 if (rc)
4800 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
dc52c6c7
PS		 4801 rc);
4802
4803 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4804 rc = bnxt_setup_nitroa0_vnic(bp);
4805 if (rc)
4806 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
4807 rc);
4808 }
c0c050c5 4809
cf6645f8
MC		 4810 if (BNXT_VF(bp)) {
4811 bnxt_hwrm_func_qcfg(bp);
4812 netdev_update_features(bp->dev);
4813 }
4814
c0c050c5
MC		 4815 return 0;
4816
4817err_out:
4818 bnxt_hwrm_resource_free(bp, 0, true);
4819
4820 return rc;
4821}
4822
4823static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
4824{
4825 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
4826 return 0;
4827}
4828
4829static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
4830{
4831 bnxt_init_rx_rings(bp);
4832 bnxt_init_tx_rings(bp);
4833 bnxt_init_ring_grps(bp, irq_re_init);
4834 bnxt_init_vnics(bp);
4835
4836 return bnxt_init_chip(bp, irq_re_init);
4837}
4838
c0c050c5
MC		 4839static int bnxt_set_real_num_queues(struct bnxt *bp)
4840{
4841 int rc;
4842 struct net_device *dev = bp->dev;
4843
4844 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4845 if (rc)
4846 return rc;
4847
4848 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4849 if (rc)
4850 return rc;
4851
4852#ifdef CONFIG_RFS_ACCEL
45019a18 4853 if (bp->flags & BNXT_FLAG_RFS)
c0c050c5 4854 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
c0c050c5
MC		 4855#endif
4856
4857 return rc;
4858}
4859
6e6c5a57
MC		 4860static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4861 bool shared)
4862{
4863 int _rx = *rx, _tx = *tx;
4864
4865 if (shared) {
4866 *rx = min_t(int, _rx, max);
4867 *tx = min_t(int, _tx, max);
4868 } else {
4869 if (max < 2)
4870 return -ENOMEM;
4871
4872 while (_rx + _tx > max) {
4873 if (_rx > _tx && _rx > 1)
4874 _rx--;
4875 else if (_tx > 1)
4876 _tx--;
4877 }
4878 *rx = _rx;
4879 *tx = _tx;
4880 }
4881 return 0;
4882}
4883
7809592d
MC		 4884static void bnxt_setup_msix(struct bnxt *bp)
4885{
4886 const int len = sizeof(bp->irq_tbl[0].name);
4887 struct net_device *dev = bp->dev;
4888 int tcs, i;
4889
4890 tcs = netdev_get_num_tc(dev);
4891 if (tcs > 1) {
4892 bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4893 if (bp->tx_nr_rings_per_tc == 0) {
4894 netdev_reset_tc(dev);
4895 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4896 } else {
4897 int i, off, count;
4898
4899 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4900 for (i = 0; i < tcs; i++) {
4901 count = bp->tx_nr_rings_per_tc;
4902 off = i * count;
4903 netdev_set_tc_queue(dev, i, count, off);
4904 }
4905 }
4906 }
4907
4908 for (i = 0; i < bp->cp_nr_rings; i++) {
4909 char *attr;
4910
4911 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4912 attr = "TxRx";
4913 else if (i < bp->rx_nr_rings)
4914 attr = "rx";
4915 else
4916 attr = "tx";
4917
4918 snprintf(bp->irq_tbl[i].name, len, "%s-%s-%d", dev->name, attr,
4919 i);
4920 bp->irq_tbl[i].handler = bnxt_msix;
4921 }
4922}
4923
4924static void bnxt_setup_inta(struct bnxt *bp)
4925{
4926 const int len = sizeof(bp->irq_tbl[0].name);
4927
4928 if (netdev_get_num_tc(bp->dev))
4929 netdev_reset_tc(bp->dev);
4930
4931 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
4932 0);
4933 bp->irq_tbl[0].handler = bnxt_inta;
4934}
4935
4936static int bnxt_setup_int_mode(struct bnxt *bp)
4937{
4938 int rc;
4939
4940 if (bp->flags & BNXT_FLAG_USING_MSIX)
4941 bnxt_setup_msix(bp);
4942 else
4943 bnxt_setup_inta(bp);
4944
4945 rc = bnxt_set_real_num_queues(bp);
4946 return rc;
4947}
4948
b7429954 4949#ifdef CONFIG_RFS_ACCEL
8079e8f1
MC		 4950static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
4951{
4952#if defined(CONFIG_BNXT_SRIOV)
4953 if (BNXT_VF(bp))
4954 return bp->vf.max_rsscos_ctxs;
4955#endif
4956 return bp->pf.max_rsscos_ctxs;
4957}
4958
4959static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
4960{
4961#if defined(CONFIG_BNXT_SRIOV)
4962 if (BNXT_VF(bp))
4963 return bp->vf.max_vnics;
4964#endif
4965 return bp->pf.max_vnics;
4966}
b7429954 4967#endif
8079e8f1 4968
e4060d30
MC		 4969unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
4970{
4971#if defined(CONFIG_BNXT_SRIOV)
4972 if (BNXT_VF(bp))
4973 return bp->vf.max_stat_ctxs;
4974#endif
4975 return bp->pf.max_stat_ctxs;
4976}
4977
a588e458
MC		 4978void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
4979{
4980#if defined(CONFIG_BNXT_SRIOV)
4981 if (BNXT_VF(bp))
4982 bp->vf.max_stat_ctxs = max;
4983 else
4984#endif
4985 bp->pf.max_stat_ctxs = max;
4986}
4987
e4060d30
MC		 4988unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
4989{
4990#if defined(CONFIG_BNXT_SRIOV)
4991 if (BNXT_VF(bp))
4992 return bp->vf.max_cp_rings;
4993#endif
4994 return bp->pf.max_cp_rings;
4995}
4996
a588e458
MC		 4997void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max)
4998{
4999#if defined(CONFIG_BNXT_SRIOV)
5000 if (BNXT_VF(bp))
5001 bp->vf.max_cp_rings = max;
5002 else
5003#endif
5004 bp->pf.max_cp_rings = max;
5005}
5006
7809592d
MC		 5007static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5008{
5009#if defined(CONFIG_BNXT_SRIOV)
5010 if (BNXT_VF(bp))
5011 return bp->vf.max_irqs;
5012#endif
5013 return bp->pf.max_irqs;
5014}
5015
33c2657e
MC		 5016void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
5017{
5018#if defined(CONFIG_BNXT_SRIOV)
5019 if (BNXT_VF(bp))
5020 bp->vf.max_irqs = max_irqs;
5021 else
5022#endif
5023 bp->pf.max_irqs = max_irqs;
5024}
5025
7809592d 5026static int bnxt_init_msix(struct bnxt *bp)
c0c050c5 5027{
01657bcd 5028 int i, total_vecs, rc = 0, min = 1;
7809592d 5029 struct msix_entry *msix_ent;
c0c050c5 5030
7809592d 5031 total_vecs = bnxt_get_max_func_irqs(bp);
c0c050c5
MC		 5032 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
5033 if (!msix_ent)
5034 return -ENOMEM;
5035
5036 for (i = 0; i < total_vecs; i++) {
5037 msix_ent[i].entry = i;
5038 msix_ent[i].vector = 0;
5039 }
5040
01657bcd
MC		 5041 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
5042 min = 2;
5043
5044 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
c0c050c5
MC		 5045 if (total_vecs < 0) {
5046 rc = -ENODEV;
5047 goto msix_setup_exit;
5048 }
5049
5050 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
5051 if (bp->irq_tbl) {
7809592d
MC		 5052 for (i = 0; i < total_vecs; i++)
5053 bp->irq_tbl[i].vector = msix_ent[i].vector;
c0c050c5 5054
7809592d 5055 bp->total_irqs = total_vecs;
c0c050c5 5056 /* Trim rings based upon num of vectors allocated */
6e6c5a57 5057 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
01657bcd 5058 total_vecs, min == 1);
6e6c5a57
MC		 5059 if (rc)
5060 goto msix_setup_exit;
5061
c0c050c5 5062 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
7809592d
MC		 5063 bp->cp_nr_rings = (min == 1) ?
5064 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5065 bp->tx_nr_rings + bp->rx_nr_rings;
c0c050c5 5066
c0c050c5
MC		 5067 } else {
5068 rc = -ENOMEM;
5069 goto msix_setup_exit;
5070 }
5071 bp->flags |= BNXT_FLAG_USING_MSIX;
5072 kfree(msix_ent);
5073 return 0;
5074
5075msix_setup_exit:
7809592d
MC		 5076 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
5077 kfree(bp->irq_tbl);
5078 bp->irq_tbl = NULL;
c0c050c5
MC		 5079 pci_disable_msix(bp->pdev);
5080 kfree(msix_ent);
5081 return rc;
5082}
5083
7809592d 5084static int bnxt_init_inta(struct bnxt *bp)
c0c050c5 5085{
c0c050c5 5086 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
7809592d
MC		 5087 if (!bp->irq_tbl)
5088 return -ENOMEM;
5089
5090 bp->total_irqs = 1;
c0c050c5
MC		 5091 bp->rx_nr_rings = 1;
5092 bp->tx_nr_rings = 1;
5093 bp->cp_nr_rings = 1;
5094 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
01657bcd 5095 bp->flags |= BNXT_FLAG_SHARED_RINGS;
c0c050c5 5096 bp->irq_tbl[0].vector = bp->pdev->irq;
7809592d 5097 return 0;
c0c050c5
MC		 5098}
5099
7809592d 5100static int bnxt_init_int_mode(struct bnxt *bp)
c0c050c5
MC		 5101{
5102 int rc = 0;
5103
5104 if (bp->flags & BNXT_FLAG_MSIX_CAP)
7809592d 5105 rc = bnxt_init_msix(bp);
c0c050c5 5106
1fa72e29 5107 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
c0c050c5 5108 /* fallback to INTA */
7809592d 5109 rc = bnxt_init_inta(bp);
c0c050c5
MC		 5110 }
5111 return rc;
5112}
5113
7809592d
MC		 5114static void bnxt_clear_int_mode(struct bnxt *bp)
5115{
5116 if (bp->flags & BNXT_FLAG_USING_MSIX)
5117 pci_disable_msix(bp->pdev);
5118
5119 kfree(bp->irq_tbl);
5120 bp->irq_tbl = NULL;
5121 bp->flags &= ~BNXT_FLAG_USING_MSIX;
5122}
5123
c0c050c5
MC		 5124static void bnxt_free_irq(struct bnxt *bp)
5125{
5126 struct bnxt_irq *irq;
5127 int i;
5128
5129#ifdef CONFIG_RFS_ACCEL
5130 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
5131 bp->dev->rx_cpu_rmap = NULL;
5132#endif
5133 if (!bp->irq_tbl)
5134 return;
5135
5136 for (i = 0; i < bp->cp_nr_rings; i++) {
5137 irq = &bp->irq_tbl[i];
5138 if (irq->requested)
5139 free_irq(irq->vector, bp->bnapi[i]);
5140 irq->requested = 0;
5141 }
c0c050c5
MC		 5142}
5143
5144static int bnxt_request_irq(struct bnxt *bp)
5145{
b81a90d3 5146 int i, j, rc = 0;
c0c050c5
MC		 5147 unsigned long flags = 0;
5148#ifdef CONFIG_RFS_ACCEL
5149 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
5150#endif
5151
5152 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
5153 flags = IRQF_SHARED;
5154
b81a90d3 5155 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
c0c050c5
MC		 5156 struct bnxt_irq *irq = &bp->irq_tbl[i];
5157#ifdef CONFIG_RFS_ACCEL
b81a90d3 5158 if (rmap && bp->bnapi[i]->rx_ring) {
c0c050c5
MC		 5159 rc = irq_cpu_rmap_add(rmap, irq->vector);
5160 if (rc)
5161 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
b81a90d3
MC		 5162 j);
5163 j++;
c0c050c5
MC		 5164 }
5165#endif
5166 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5167 bp->bnapi[i]);
5168 if (rc)
5169 break;
5170
5171 irq->requested = 1;
5172 }
5173 return rc;
5174}
5175
5176static void bnxt_del_napi(struct bnxt *bp)
5177{
5178 int i;
5179
5180 if (!bp->bnapi)
5181 return;
5182
5183 for (i = 0; i < bp->cp_nr_rings; i++) {
5184 struct bnxt_napi *bnapi = bp->bnapi[i];
5185
5186 napi_hash_del(&bnapi->napi);
5187 netif_napi_del(&bnapi->napi);
5188 }
e5f6f564
ED		 5189 /* We called napi_hash_del() before netif_napi_del(), we need
5190 * to respect an RCU grace period before freeing napi structures.
5191 */
5192 synchronize_net();
c0c050c5
MC		 5193}
5194
5195static void bnxt_init_napi(struct bnxt *bp)
5196{
5197 int i;
10bbdaf5 5198 unsigned int cp_nr_rings = bp->cp_nr_rings;
c0c050c5
MC		 5199 struct bnxt_napi *bnapi;
5200
5201 if (bp->flags & BNXT_FLAG_USING_MSIX) {
10bbdaf5
PS		 5202 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5203 cp_nr_rings--;
5204 for (i = 0; i < cp_nr_rings; i++) {
c0c050c5
MC		 5205 bnapi = bp->bnapi[i];
5206 netif_napi_add(bp->dev, &bnapi->napi,
5207 bnxt_poll, 64);
c0c050c5 5208 }
10bbdaf5
PS		 5209 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5210 bnapi = bp->bnapi[cp_nr_rings];
5211 netif_napi_add(bp->dev, &bnapi->napi,
5212 bnxt_poll_nitroa0, 64);
10bbdaf5 5213 }
c0c050c5
MC		 5214 } else {
5215 bnapi = bp->bnapi[0];
5216 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
c0c050c5
MC		 5217 }
5218}
5219
5220static void bnxt_disable_napi(struct bnxt *bp)
5221{
5222 int i;
5223
5224 if (!bp->bnapi)
5225 return;
5226
b356a2e7 5227 for (i = 0; i < bp->cp_nr_rings; i++)
c0c050c5 5228 napi_disable(&bp->bnapi[i]->napi);
c0c050c5
MC		 5229}
5230
5231static void bnxt_enable_napi(struct bnxt *bp)
5232{
5233 int i;
5234
5235 for (i = 0; i < bp->cp_nr_rings; i++) {
fa7e2812 5236 bp->bnapi[i]->in_reset = false;
c0c050c5
MC		 5237 napi_enable(&bp->bnapi[i]->napi);
5238 }
5239}
5240
7df4ae9f 5241void bnxt_tx_disable(struct bnxt *bp)
c0c050c5
MC		 5242{
5243 int i;
c0c050c5
MC		 5244 struct bnxt_tx_ring_info *txr;
5245 struct netdev_queue *txq;
5246
b6ab4b01 5247 if (bp->tx_ring) {
c0c050c5 5248 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 5249 txr = &bp->tx_ring[i];
c0c050c5 5250 txq = netdev_get_tx_queue(bp->dev, i);
c0c050c5 5251 txr->dev_state = BNXT_DEV_STATE_CLOSING;
c0c050c5
MC		 5252 }
5253 }
5254 /* Stop all TX queues */
5255 netif_tx_disable(bp->dev);
5256 netif_carrier_off(bp->dev);
5257}
5258
7df4ae9f 5259void bnxt_tx_enable(struct bnxt *bp)
c0c050c5
MC		 5260{
5261 int i;
c0c050c5
MC		 5262 struct bnxt_tx_ring_info *txr;
5263 struct netdev_queue *txq;
5264
5265 for (i = 0; i < bp->tx_nr_rings; i++) {
b6ab4b01 5266 txr = &bp->tx_ring[i];
c0c050c5
MC		 5267 txq = netdev_get_tx_queue(bp->dev, i);
5268 txr->dev_state = 0;
5269 }
5270 netif_tx_wake_all_queues(bp->dev);
5271 if (bp->link_info.link_up)
5272 netif_carrier_on(bp->dev);
5273}
5274
5275static void bnxt_report_link(struct bnxt *bp)
5276{
5277 if (bp->link_info.link_up) {
5278 const char *duplex;
5279 const char *flow_ctrl;
5280 u16 speed;
5281
5282 netif_carrier_on(bp->dev);
5283 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
5284 duplex = "full";
5285 else
5286 duplex = "half";
5287 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
5288 flow_ctrl = "ON - receive & transmit";
5289 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
5290 flow_ctrl = "ON - transmit";
5291 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
5292 flow_ctrl = "ON - receive";
5293 else
5294 flow_ctrl = "none";
5295 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
5296 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
5297 speed, duplex, flow_ctrl);
170ce013
MC		 5298 if (bp->flags & BNXT_FLAG_EEE_CAP)
5299 netdev_info(bp->dev, "EEE is %s\n",
5300 bp->eee.eee_active ? "active" :
5301 "not active");
c0c050c5
MC		 5302 } else {
5303 netif_carrier_off(bp->dev);
5304 netdev_err(bp->dev, "NIC Link is Down\n");
5305 }
5306}
5307
170ce013
MC		 5308static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
5309{
5310 int rc = 0;
5311 struct hwrm_port_phy_qcaps_input req = {0};
5312 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
93ed8117 5313 struct bnxt_link_info *link_info = &bp->link_info;
170ce013
MC		 5314
5315 if (bp->hwrm_spec_code < 0x10201)
5316 return 0;
5317
5318 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
5319
5320 mutex_lock(&bp->hwrm_cmd_lock);
5321 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5322 if (rc)
5323 goto hwrm_phy_qcaps_exit;
5324
5325 if (resp->eee_supported & PORT_PHY_QCAPS_RESP_EEE_SUPPORTED) {
5326 struct ethtool_eee *eee = &bp->eee;
5327 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
5328
5329 bp->flags |= BNXT_FLAG_EEE_CAP;
5330 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5331 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
5332 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
5333 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
5334 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
5335 }
93ed8117
MC		 5336 link_info->support_auto_speeds =
5337 le16_to_cpu(resp->supported_speeds_auto_mode);
170ce013
MC		 5338
5339hwrm_phy_qcaps_exit:
5340 mutex_unlock(&bp->hwrm_cmd_lock);
5341 return rc;
5342}
5343
c0c050c5
MC		 5344static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
5345{
5346 int rc = 0;
5347 struct bnxt_link_info *link_info = &bp->link_info;
5348 struct hwrm_port_phy_qcfg_input req = {0};
5349 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5350 u8 link_up = link_info->link_up;
286ef9d6 5351 u16 diff;
c0c050c5
MC		 5352
5353 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
5354
5355 mutex_lock(&bp->hwrm_cmd_lock);
5356 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5357 if (rc) {
5358 mutex_unlock(&bp->hwrm_cmd_lock);
5359 return rc;
5360 }
5361
5362 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
5363 link_info->phy_link_status = resp->link;
5364 link_info->duplex = resp->duplex;
5365 link_info->pause = resp->pause;
5366 link_info->auto_mode = resp->auto_mode;
5367 link_info->auto_pause_setting = resp->auto_pause;
3277360e 5368 link_info->lp_pause = resp->link_partner_adv_pause;
c0c050c5 5369 link_info->force_pause_setting = resp->force_pause;
c193554e 5370 link_info->duplex_setting = resp->duplex;
c0c050c5
MC		 5371 if (link_info->phy_link_status == BNXT_LINK_LINK)
5372 link_info->link_speed = le16_to_cpu(resp->link_speed);
5373 else
5374 link_info->link_speed = 0;
5375 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
c0c050c5
MC		 5376 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
5377 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
3277360e
MC		 5378 link_info->lp_auto_link_speeds =
5379 le16_to_cpu(resp->link_partner_adv_speeds);
c0c050c5
MC		 5380 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
5381 link_info->phy_ver[0] = resp->phy_maj;
5382 link_info->phy_ver[1] = resp->phy_min;
5383 link_info->phy_ver[2] = resp->phy_bld;
5384 link_info->media_type = resp->media_type;
03efbec0 5385 link_info->phy_type = resp->phy_type;
11f15ed3 5386 link_info->transceiver = resp->xcvr_pkg_type;
170ce013
MC		 5387 link_info->phy_addr = resp->eee_config_phy_addr &
5388 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
42ee18fe 5389 link_info->module_status = resp->module_status;
170ce013
MC		 5390
5391 if (bp->flags & BNXT_FLAG_EEE_CAP) {
5392 struct ethtool_eee *eee = &bp->eee;
5393 u16 fw_speeds;
5394
5395 eee->eee_active = 0;
5396 if (resp->eee_config_phy_addr &
5397 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
5398 eee->eee_active = 1;
5399 fw_speeds = le16_to_cpu(
5400 resp->link_partner_adv_eee_link_speed_mask);
5401 eee->lp_advertised =
5402 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5403 }
5404
5405 /* Pull initial EEE config */
5406 if (!chng_link_state) {
5407 if (resp->eee_config_phy_addr &
5408 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
5409 eee->eee_enabled = 1;
c0c050c5 5410
170ce013
MC		 5411 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
5412 eee->advertised =
5413 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5414
5415 if (resp->eee_config_phy_addr &
5416 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
5417 __le32 tmr;
5418
5419 eee->tx_lpi_enabled = 1;
5420 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
5421 eee->tx_lpi_timer = le32_to_cpu(tmr) &
5422 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
5423 }
5424 }
5425 }
c0c050c5
MC		 5426 /* TODO: need to add more logic to report VF link */
5427 if (chng_link_state) {
5428 if (link_info->phy_link_status == BNXT_LINK_LINK)
5429 link_info->link_up = 1;
5430 else
5431 link_info->link_up = 0;
5432 if (link_up != link_info->link_up)
5433 bnxt_report_link(bp);
5434 } else {
5435 /* alwasy link down if not require to update link state */
5436 link_info->link_up = 0;
5437 }
5438 mutex_unlock(&bp->hwrm_cmd_lock);
286ef9d6
MC		 5439
5440 diff = link_info->support_auto_speeds ^ link_info->advertising;
5441 if ((link_info->support_auto_speeds | diff) !=
5442 link_info->support_auto_speeds) {
5443 /* An advertised speed is no longer supported, so we need to
0eaa24b9
MC		 5444 * update the advertisement settings. Caller holds RTNL
5445 * so we can modify link settings.
286ef9d6 5446 */
286ef9d6 5447 link_info->advertising = link_info->support_auto_speeds;
0eaa24b9 5448 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
286ef9d6 5449 bnxt_hwrm_set_link_setting(bp, true, false);
286ef9d6 5450 }
c0c050c5
MC		 5451 return 0;
5452}
5453
10289bec
MC		 5454static void bnxt_get_port_module_status(struct bnxt *bp)
5455{
5456 struct bnxt_link_info *link_info = &bp->link_info;
5457 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
5458 u8 module_status;
5459
5460 if (bnxt_update_link(bp, true))
5461 return;
5462
5463 module_status = link_info->module_status;
5464 switch (module_status) {
5465 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
5466 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
5467 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
5468 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
5469 bp->pf.port_id);
5470 if (bp->hwrm_spec_code >= 0x10201) {
5471 netdev_warn(bp->dev, "Module part number %s\n",
5472 resp->phy_vendor_partnumber);
5473 }
5474 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
5475 netdev_warn(bp->dev, "TX is disabled\n");
5476 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
5477 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
5478 }
5479}
5480
c0c050c5
MC		 5481static void
5482bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
5483{
5484 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
c9ee9516
MC		 5485 if (bp->hwrm_spec_code >= 0x10201)
5486 req->auto_pause =
5487 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
c0c050c5
MC		 5488 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5489 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
5490 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
49b5c7a1 5491 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
c0c050c5
MC		 5492 req->enables |=
5493 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5494 } else {
5495 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5496 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
5497 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5498 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
5499 req->enables |=
5500 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
c9ee9516
MC		 5501 if (bp->hwrm_spec_code >= 0x10201) {
5502 req->auto_pause = req->force_pause;
5503 req->enables |= cpu_to_le32(
5504 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5505 }
c0c050c5
MC		 5506 }
5507}
5508
5509static void bnxt_hwrm_set_link_common(struct bnxt *bp,
5510 struct hwrm_port_phy_cfg_input *req)
5511{
5512 u8 autoneg = bp->link_info.autoneg;
5513 u16 fw_link_speed = bp->link_info.req_link_speed;
68515a18 5514 u16 advertising = bp->link_info.advertising;
c0c050c5
MC		 5515
5516 if (autoneg & BNXT_AUTONEG_SPEED) {
5517 req->auto_mode |=
11f15ed3 5518 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
c0c050c5
MC		 5519
5520 req->enables |= cpu_to_le32(
5521 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
5522 req->auto_link_speed_mask = cpu_to_le16(advertising);
5523
5524 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
5525 req->flags |=
5526 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
5527 } else {
5528 req->force_link_speed = cpu_to_le16(fw_link_speed);
5529 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
5530 }
5531
c0c050c5
MC		 5532 /* tell chimp that the setting takes effect immediately */
5533 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
5534}
5535
5536int bnxt_hwrm_set_pause(struct bnxt *bp)
5537{
5538 struct hwrm_port_phy_cfg_input req = {0};
5539 int rc;
5540
5541 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5542 bnxt_hwrm_set_pause_common(bp, &req);
5543
5544 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
5545 bp->link_info.force_link_chng)
5546 bnxt_hwrm_set_link_common(bp, &req);
5547
5548 mutex_lock(&bp->hwrm_cmd_lock);
5549 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5550 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
5551 /* since changing of pause setting doesn't trigger any link
5552 * change event, the driver needs to update the current pause
5553 * result upon successfully return of the phy_cfg command
5554 */
5555 bp->link_info.pause =
5556 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
5557 bp->link_info.auto_pause_setting = 0;
5558 if (!bp->link_info.force_link_chng)
5559 bnxt_report_link(bp);
5560 }
5561 bp->link_info.force_link_chng = false;
5562 mutex_unlock(&bp->hwrm_cmd_lock);
5563 return rc;
5564}
5565
939f7f0c
MC		 5566static void bnxt_hwrm_set_eee(struct bnxt *bp,
5567 struct hwrm_port_phy_cfg_input *req)
5568{
5569 struct ethtool_eee *eee = &bp->eee;
5570
5571 if (eee->eee_enabled) {
5572 u16 eee_speeds;
5573 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
5574
5575 if (eee->tx_lpi_enabled)
5576 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
5577 else
5578 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
5579
5580 req->flags |= cpu_to_le32(flags);
5581 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
5582 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
5583 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
5584 } else {
5585 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
5586 }
5587}
5588
5589int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
c0c050c5
MC		 5590{
5591 struct hwrm_port_phy_cfg_input req = {0};
5592
5593 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5594 if (set_pause)
5595 bnxt_hwrm_set_pause_common(bp, &req);
5596
5597 bnxt_hwrm_set_link_common(bp, &req);
939f7f0c
MC		 5598
5599 if (set_eee)
5600 bnxt_hwrm_set_eee(bp, &req);
c0c050c5
MC		 5601 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5602}
5603
33f7d55f
MC		 5604static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
5605{
5606 struct hwrm_port_phy_cfg_input req = {0};
5607
567b2abe 5608 if (!BNXT_SINGLE_PF(bp))
33f7d55f
MC		 5609 return 0;
5610
5611 if (pci_num_vf(bp->pdev))
5612 return 0;
5613
5614 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
16d663a6 5615 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
33f7d55f
MC		 5616 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5617}
5618
5ad2cbee
MC		 5619static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
5620{
5621 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5622 struct hwrm_port_led_qcaps_input req = {0};
5623 struct bnxt_pf_info *pf = &bp->pf;
5624 int rc;
5625
5626 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
5627 return 0;
5628
5629 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
5630 req.port_id = cpu_to_le16(pf->port_id);
5631 mutex_lock(&bp->hwrm_cmd_lock);
5632 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5633 if (rc) {
5634 mutex_unlock(&bp->hwrm_cmd_lock);
5635 return rc;
5636 }
5637 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
5638 int i;
5639
5640 bp->num_leds = resp->num_leds;
5641 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
5642 bp->num_leds);
5643 for (i = 0; i < bp->num_leds; i++) {
5644 struct bnxt_led_info *led = &bp->leds[i];
5645 __le16 caps = led->led_state_caps;
5646
5647 if (!led->led_group_id ||
5648 !BNXT_LED_ALT_BLINK_CAP(caps)) {
5649 bp->num_leds = 0;
5650 break;
5651 }
5652 }
5653 }
5654 mutex_unlock(&bp->hwrm_cmd_lock);
5655 return 0;
5656}
5657
939f7f0c
MC		 5658static bool bnxt_eee_config_ok(struct bnxt *bp)
5659{
5660 struct ethtool_eee *eee = &bp->eee;
5661 struct bnxt_link_info *link_info = &bp->link_info;
5662
5663 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
5664 return true;
5665
5666 if (eee->eee_enabled) {
5667 u32 advertising =
5668 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
5669
5670 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5671 eee->eee_enabled = 0;
5672 return false;
5673 }
5674 if (eee->advertised & ~advertising) {
5675 eee->advertised = advertising & eee->supported;
5676 return false;
5677 }
5678 }
5679 return true;
5680}
5681
c0c050c5
MC		 5682static int bnxt_update_phy_setting(struct bnxt *bp)
5683{
5684 int rc;
5685 bool update_link = false;
5686 bool update_pause = false;
939f7f0c 5687 bool update_eee = false;
c0c050c5
MC		 5688 struct bnxt_link_info *link_info = &bp->link_info;
5689
5690 rc = bnxt_update_link(bp, true);
5691 if (rc) {
5692 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
5693 rc);
5694 return rc;
5695 }
5696 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
c9ee9516
MC		 5697 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
5698 link_info->req_flow_ctrl)
c0c050c5
MC		 5699 update_pause = true;
5700 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5701 link_info->force_pause_setting != link_info->req_flow_ctrl)
5702 update_pause = true;
c0c050c5
MC		 5703 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5704 if (BNXT_AUTO_MODE(link_info->auto_mode))
5705 update_link = true;
5706 if (link_info->req_link_speed != link_info->force_link_speed)
5707 update_link = true;
de73018f
MC		 5708 if (link_info->req_duplex != link_info->duplex_setting)
5709 update_link = true;
c0c050c5
MC		 5710 } else {
5711 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
5712 update_link = true;
5713 if (link_info->advertising != link_info->auto_link_speeds)
5714 update_link = true;
c0c050c5
MC		 5715 }
5716
16d663a6
MC		 5717 /* The last close may have shutdown the link, so need to call
5718 * PHY_CFG to bring it back up.
5719 */
5720 if (!netif_carrier_ok(bp->dev))
5721 update_link = true;
5722
939f7f0c
MC		 5723 if (!bnxt_eee_config_ok(bp))
5724 update_eee = true;
5725
c0c050c5 5726 if (update_link)
939f7f0c 5727 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
c0c050c5
MC		 5728 else if (update_pause)
5729 rc = bnxt_hwrm_set_pause(bp);
5730 if (rc) {
5731 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
5732 rc);
5733 return rc;
5734 }
5735
5736 return rc;
5737}
5738
11809490
JH		 5739/* Common routine to pre-map certain register block to different GRC window.
5740 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
5741 * in PF and 3 windows in VF that can be customized to map in different
5742 * register blocks.
5743 */
5744static void bnxt_preset_reg_win(struct bnxt *bp)
5745{
5746 if (BNXT_PF(bp)) {
5747 /* CAG registers map to GRC window #4 */
5748 writel(BNXT_CAG_REG_BASE,
5749 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
5750 }
5751}
5752
c0c050c5
MC		 5753static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5754{
5755 int rc = 0;
5756
11809490 5757 bnxt_preset_reg_win(bp);
c0c050c5
MC		 5758 netif_carrier_off(bp->dev);
5759 if (irq_re_init) {
5760 rc = bnxt_setup_int_mode(bp);
5761 if (rc) {
5762 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
5763 rc);
5764 return rc;
5765 }
5766 }
5767 if ((bp->flags & BNXT_FLAG_RFS) &&
5768 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
5769 /* disable RFS if falling back to INTA */
5770 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
5771 bp->flags &= ~BNXT_FLAG_RFS;
5772 }
5773
5774 rc = bnxt_alloc_mem(bp, irq_re_init);
5775 if (rc) {
5776 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
5777 goto open_err_free_mem;
5778 }
5779
5780 if (irq_re_init) {
5781 bnxt_init_napi(bp);
5782 rc = bnxt_request_irq(bp);
5783 if (rc) {
5784 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
5785 goto open_err;
5786 }
5787 }
5788
5789 bnxt_enable_napi(bp);
5790
5791 rc = bnxt_init_nic(bp, irq_re_init);
5792 if (rc) {
5793 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
5794 goto open_err;
5795 }
5796
5797 if (link_re_init) {
5798 rc = bnxt_update_phy_setting(bp);
5799 if (rc)
ba41d46f 5800 netdev_warn(bp->dev, "failed to update phy settings\n");
c0c050c5
MC		 5801 }
5802
7cdd5fc3 5803 if (irq_re_init)
ad51b8e9 5804 udp_tunnel_get_rx_info(bp->dev);
c0c050c5 5805
caefe526 5806 set_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 5807 bnxt_enable_int(bp);
5808 /* Enable TX queues */
5809 bnxt_tx_enable(bp);
5810 mod_timer(&bp->timer, jiffies + bp->current_interval);
10289bec
MC		 5811 /* Poll link status and check for SFP+ module status */
5812 bnxt_get_port_module_status(bp);
c0c050c5
MC		 5813
5814 return 0;
5815
5816open_err:
5817 bnxt_disable_napi(bp);
5818 bnxt_del_napi(bp);
5819
5820open_err_free_mem:
5821 bnxt_free_skbs(bp);
5822 bnxt_free_irq(bp);
5823 bnxt_free_mem(bp, true);
5824 return rc;
5825}
5826
5827/* rtnl_lock held */
5828int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5829{
5830 int rc = 0;
5831
5832 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
5833 if (rc) {
5834 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
5835 dev_close(bp->dev);
5836 }
5837 return rc;
5838}
5839
5840static int bnxt_open(struct net_device *dev)
5841{
5842 struct bnxt *bp = netdev_priv(dev);
c0c050c5 5843
c0c050c5
MC		 5844 return __bnxt_open_nic(bp, true, true);
5845}
5846
c0c050c5
MC		 5847int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5848{
5849 int rc = 0;
5850
5851#ifdef CONFIG_BNXT_SRIOV
5852 if (bp->sriov_cfg) {
5853 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
5854 !bp->sriov_cfg,
5855 BNXT_SRIOV_CFG_WAIT_TMO);
5856 if (rc)
5857 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
5858 }
5859#endif
5860 /* Change device state to avoid TX queue wake up's */
5861 bnxt_tx_disable(bp);
5862
caefe526 5863 clear_bit(BNXT_STATE_OPEN, &bp->state);
4cebdcec
MC		 5864 smp_mb__after_atomic();
5865 while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
5866 msleep(20);
c0c050c5 5867
9d8bc097 5868 /* Flush rings and and disable interrupts */
c0c050c5
MC		 5869 bnxt_shutdown_nic(bp, irq_re_init);
5870
5871 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
5872
5873 bnxt_disable_napi(bp);
c0c050c5
MC		 5874 del_timer_sync(&bp->timer);
5875 bnxt_free_skbs(bp);
5876
5877 if (irq_re_init) {
5878 bnxt_free_irq(bp);
5879 bnxt_del_napi(bp);
5880 }
5881 bnxt_free_mem(bp, irq_re_init);
5882 return rc;
5883}
5884
5885static int bnxt_close(struct net_device *dev)
5886{
5887 struct bnxt *bp = netdev_priv(dev);
5888
5889 bnxt_close_nic(bp, true, true);
33f7d55f 5890 bnxt_hwrm_shutdown_link(bp);
c0c050c5
MC		 5891 return 0;
5892}
5893
5894/* rtnl_lock held */
5895static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5896{
5897 switch (cmd) {
5898 case SIOCGMIIPHY:
5899 /* fallthru */
5900 case SIOCGMIIREG: {
5901 if (!netif_running(dev))
5902 return -EAGAIN;
5903
5904 return 0;
5905 }
5906
5907 case SIOCSMIIREG:
5908 if (!netif_running(dev))
5909 return -EAGAIN;
5910
5911 return 0;
5912
5913 default:
5914 /* do nothing */
5915 break;
5916 }
5917 return -EOPNOTSUPP;
5918}
5919
bc1f4470 5920static void
c0c050c5
MC		 5921bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5922{
5923 u32 i;
5924 struct bnxt *bp = netdev_priv(dev);
5925
c0c050c5 5926 if (!bp->bnapi)
bc1f4470 5927 return;
c0c050c5
MC		 5928
5929 /* TODO check if we need to synchronize with bnxt_close path */
5930 for (i = 0; i < bp->cp_nr_rings; i++) {
5931 struct bnxt_napi *bnapi = bp->bnapi[i];
5932 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5933 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
5934
5935 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
5936 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
5937 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
5938
5939 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
5940 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
5941 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
5942
5943 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
5944 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
5945 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
5946
5947 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
5948 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
5949 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
5950
5951 stats->rx_missed_errors +=
5952 le64_to_cpu(hw_stats->rx_discard_pkts);
5953
5954 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
5955
c0c050c5
MC		 5956 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
5957 }
5958
9947f83f
MC		 5959 if (bp->flags & BNXT_FLAG_PORT_STATS) {
5960 struct rx_port_stats *rx = bp->hw_rx_port_stats;
5961 struct tx_port_stats *tx = bp->hw_tx_port_stats;
5962
5963 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
5964 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
5965 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
5966 le64_to_cpu(rx->rx_ovrsz_frames) +
5967 le64_to_cpu(rx->rx_runt_frames);
5968 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
5969 le64_to_cpu(rx->rx_jbr_frames);
5970 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
5971 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
5972 stats->tx_errors = le64_to_cpu(tx->tx_err);
5973 }
c0c050c5
MC		 5974}
5975
5976static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
5977{
5978 struct net_device *dev = bp->dev;
5979 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5980 struct netdev_hw_addr *ha;
5981 u8 *haddr;
5982 int mc_count = 0;
5983 bool update = false;
5984 int off = 0;
5985
5986 netdev_for_each_mc_addr(ha, dev) {
5987 if (mc_count >= BNXT_MAX_MC_ADDRS) {
5988 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5989 vnic->mc_list_count = 0;
5990 return false;
5991 }
5992 haddr = ha->addr;
5993 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
5994 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
5995 update = true;
5996 }
5997 off += ETH_ALEN;
5998 mc_count++;
5999 }
6000 if (mc_count)
6001 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
6002
6003 if (mc_count != vnic->mc_list_count) {
6004 vnic->mc_list_count = mc_count;
6005 update = true;
6006 }
6007 return update;
6008}
6009
6010static bool bnxt_uc_list_updated(struct bnxt *bp)
6011{
6012 struct net_device *dev = bp->dev;
6013 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6014 struct netdev_hw_addr *ha;
6015 int off = 0;
6016
6017 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
6018 return true;
6019
6020 netdev_for_each_uc_addr(ha, dev) {
6021 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
6022 return true;
6023
6024 off += ETH_ALEN;
6025 }
6026 return false;
6027}
6028
6029static void bnxt_set_rx_mode(struct net_device *dev)
6030{
6031 struct bnxt *bp = netdev_priv(dev);
6032 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6033 u32 mask = vnic->rx_mask;
6034 bool mc_update = false;
6035 bool uc_update;
6036
6037 if (!netif_running(dev))
6038 return;
6039
6040 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
6041 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
6042 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
6043
17c71ac3 6044 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
c0c050c5
MC		 6045 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6046
6047 uc_update = bnxt_uc_list_updated(bp);
6048
6049 if (dev->flags & IFF_ALLMULTI) {
6050 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6051 vnic->mc_list_count = 0;
6052 } else {
6053 mc_update = bnxt_mc_list_updated(bp, &mask);
6054 }
6055
6056 if (mask != vnic->rx_mask || uc_update || mc_update) {
6057 vnic->rx_mask = mask;
6058
6059 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
6060 schedule_work(&bp->sp_task);
6061 }
6062}
6063
b664f008 6064static int bnxt_cfg_rx_mode(struct bnxt *bp)
c0c050c5
MC		 6065{
6066 struct net_device *dev = bp->dev;
6067 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6068 struct netdev_hw_addr *ha;
6069 int i, off = 0, rc;
6070 bool uc_update;
6071
6072 netif_addr_lock_bh(dev);
6073 uc_update = bnxt_uc_list_updated(bp);
6074 netif_addr_unlock_bh(dev);
6075
6076 if (!uc_update)
6077 goto skip_uc;
6078
6079 mutex_lock(&bp->hwrm_cmd_lock);
6080 for (i = 1; i < vnic->uc_filter_count; i++) {
6081 struct hwrm_cfa_l2_filter_free_input req = {0};
6082
6083 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
6084 -1);
6085
6086 req.l2_filter_id = vnic->fw_l2_filter_id[i];
6087
6088 rc = _hwrm_send_message(bp, &req, sizeof(req),
6089 HWRM_CMD_TIMEOUT);
6090 }
6091 mutex_unlock(&bp->hwrm_cmd_lock);
6092
6093 vnic->uc_filter_count = 1;
6094
6095 netif_addr_lock_bh(dev);
6096 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
6097 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6098 } else {
6099 netdev_for_each_uc_addr(ha, dev) {
6100 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
6101 off += ETH_ALEN;
6102 vnic->uc_filter_count++;
6103 }
6104 }
6105 netif_addr_unlock_bh(dev);
6106
6107 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
6108 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
6109 if (rc) {
6110 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
6111 rc);
6112 vnic->uc_filter_count = i;
b664f008 6113 return rc;
c0c050c5
MC		 6114 }
6115 }
6116
6117skip_uc:
6118 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
6119 if (rc)
6120 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
6121 rc);
b664f008
MC		 6122
6123 return rc;
c0c050c5
MC		 6124}
6125
8079e8f1
MC		 6126/* If the chip and firmware supports RFS */
6127static bool bnxt_rfs_supported(struct bnxt *bp)
6128{
6129 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
6130 return true;
ae10ae74
MC		 6131 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6132 return true;
8079e8f1
MC		 6133 return false;
6134}
6135
6136/* If runtime conditions support RFS */
2bcfa6f6
MC		 6137static bool bnxt_rfs_capable(struct bnxt *bp)
6138{
6139#ifdef CONFIG_RFS_ACCEL
8079e8f1 6140 int vnics, max_vnics, max_rss_ctxs;
2bcfa6f6
MC		 6141
6142 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
6143 return false;
6144
6145 vnics = 1 + bp->rx_nr_rings;
8079e8f1
MC		 6146 max_vnics = bnxt_get_max_func_vnics(bp);
6147 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
ae10ae74
MC		 6148
6149 /* RSS contexts not a limiting factor */
6150 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6151 max_rss_ctxs = max_vnics;
8079e8f1 6152 if (vnics > max_vnics || vnics > max_rss_ctxs) {
a2304909
VV		 6153 netdev_warn(bp->dev,
6154 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
8079e8f1 6155 min(max_rss_ctxs - 1, max_vnics - 1));
2bcfa6f6 6156 return false;
a2304909 6157 }
2bcfa6f6
MC		 6158
6159 return true;
6160#else
6161 return false;
6162#endif
6163}
6164
c0c050c5
MC		 6165static netdev_features_t bnxt_fix_features(struct net_device *dev,
6166 netdev_features_t features)
6167{
2bcfa6f6
MC		 6168 struct bnxt *bp = netdev_priv(dev);
6169
a2304909 6170 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
2bcfa6f6 6171 features &= ~NETIF_F_NTUPLE;
5a9f6b23
MC		 6172
6173 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
6174 * turned on or off together.
6175 */
6176 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
6177 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
6178 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
6179 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6180 NETIF_F_HW_VLAN_STAG_RX);
6181 else
6182 features |= NETIF_F_HW_VLAN_CTAG_RX |
6183 NETIF_F_HW_VLAN_STAG_RX;
6184 }
cf6645f8
MC		 6185#ifdef CONFIG_BNXT_SRIOV
6186 if (BNXT_VF(bp)) {
6187 if (bp->vf.vlan) {
6188 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6189 NETIF_F_HW_VLAN_STAG_RX);
6190 }
6191 }
6192#endif
c0c050c5
MC		 6193 return features;
6194}
6195
6196static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
6197{
6198 struct bnxt *bp = netdev_priv(dev);
6199 u32 flags = bp->flags;
6200 u32 changes;
6201 int rc = 0;
6202 bool re_init = false;
6203 bool update_tpa = false;
6204
6205 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
3e8060fa 6206 if ((features & NETIF_F_GRO) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
c0c050c5
MC		 6207 flags |= BNXT_FLAG_GRO;
6208 if (features & NETIF_F_LRO)
6209 flags |= BNXT_FLAG_LRO;
6210
bdbd1eb5
MC		 6211 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
6212 flags &= ~BNXT_FLAG_TPA;
6213
c0c050c5
MC		 6214 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6215 flags |= BNXT_FLAG_STRIP_VLAN;
6216
6217 if (features & NETIF_F_NTUPLE)
6218 flags |= BNXT_FLAG_RFS;
6219
6220 changes = flags ^ bp->flags;
6221 if (changes & BNXT_FLAG_TPA) {
6222 update_tpa = true;
6223 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
6224 (flags & BNXT_FLAG_TPA) == 0)
6225 re_init = true;
6226 }
6227
6228 if (changes & ~BNXT_FLAG_TPA)
6229 re_init = true;
6230
6231 if (flags != bp->flags) {
6232 u32 old_flags = bp->flags;
6233
6234 bp->flags = flags;
6235
2bcfa6f6 6236 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
c0c050c5
MC		 6237 if (update_tpa)
6238 bnxt_set_ring_params(bp);
6239 return rc;
6240 }
6241
6242 if (re_init) {
6243 bnxt_close_nic(bp, false, false);
6244 if (update_tpa)
6245 bnxt_set_ring_params(bp);
6246
6247 return bnxt_open_nic(bp, false, false);
6248 }
6249 if (update_tpa) {
6250 rc = bnxt_set_tpa(bp,
6251 (flags & BNXT_FLAG_TPA) ?
6252 true : false);
6253 if (rc)
6254 bp->flags = old_flags;
6255 }
6256 }
6257 return rc;
6258}
6259
9f554590
MC		 6260static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
6261{
b6ab4b01 6262 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9f554590
MC		 6263 int i = bnapi->index;
6264
3b2b7d9d
MC		 6265 if (!txr)
6266 return;
6267
9f554590
MC		 6268 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
6269 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
6270 txr->tx_cons);
6271}
6272
6273static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
6274{
b6ab4b01 6275 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9f554590
MC		 6276 int i = bnapi->index;
6277
3b2b7d9d
MC		 6278 if (!rxr)
6279 return;
6280
9f554590
MC		 6281 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
6282 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
6283 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
6284 rxr->rx_sw_agg_prod);
6285}
6286
6287static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
6288{
6289 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6290 int i = bnapi->index;
6291
6292 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
6293 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
6294}
6295
c0c050c5
MC		 6296static void bnxt_dbg_dump_states(struct bnxt *bp)
6297{
6298 int i;
6299 struct bnxt_napi *bnapi;
c0c050c5
MC		 6300
6301 for (i = 0; i < bp->cp_nr_rings; i++) {
6302 bnapi = bp->bnapi[i];
c0c050c5 6303 if (netif_msg_drv(bp)) {
9f554590
MC		 6304 bnxt_dump_tx_sw_state(bnapi);
6305 bnxt_dump_rx_sw_state(bnapi);
6306 bnxt_dump_cp_sw_state(bnapi);
c0c050c5
MC		 6307 }
6308 }
6309}
6310
6988bd92 6311static void bnxt_reset_task(struct bnxt *bp, bool silent)
c0c050c5 6312{
6988bd92
MC		 6313 if (!silent)
6314 bnxt_dbg_dump_states(bp);
028de140
MC		 6315 if (netif_running(bp->dev)) {
6316 bnxt_close_nic(bp, false, false);
6317 bnxt_open_nic(bp, false, false);
6318 }
c0c050c5
MC		 6319}
6320
6321static void bnxt_tx_timeout(struct net_device *dev)
6322{
6323 struct bnxt *bp = netdev_priv(dev);
6324
6325 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
6326 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
6327 schedule_work(&bp->sp_task);
6328}
6329
6330#ifdef CONFIG_NET_POLL_CONTROLLER
6331static void bnxt_poll_controller(struct net_device *dev)
6332{
6333 struct bnxt *bp = netdev_priv(dev);
6334 int i;
6335
6336 for (i = 0; i < bp->cp_nr_rings; i++) {
6337 struct bnxt_irq *irq = &bp->irq_tbl[i];
6338
6339 disable_irq(irq->vector);
6340 irq->handler(irq->vector, bp->bnapi[i]);
6341 enable_irq(irq->vector);
6342 }
6343}
6344#endif
6345
6346static void bnxt_timer(unsigned long data)
6347{
6348 struct bnxt *bp = (struct bnxt *)data;
6349 struct net_device *dev = bp->dev;
6350
6351 if (!netif_running(dev))
6352 return;
6353
6354 if (atomic_read(&bp->intr_sem) != 0)
6355 goto bnxt_restart_timer;
6356
3bdf56c4
MC		 6357 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) {
6358 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
6359 schedule_work(&bp->sp_task);
6360 }
c0c050c5
MC		 6361bnxt_restart_timer:
6362 mod_timer(&bp->timer, jiffies + bp->current_interval);
6363}
6364
a551ee94 6365static void bnxt_rtnl_lock_sp(struct bnxt *bp)
6988bd92 6366{
a551ee94
MC		 6367 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
6368 * set. If the device is being closed, bnxt_close() may be holding
6988bd92
MC		 6369 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
6370 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
6371 */
6372 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6373 rtnl_lock();
a551ee94
MC		 6374}
6375
6376static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
6377{
6988bd92
MC		 6378 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6379 rtnl_unlock();
6380}
6381
a551ee94
MC		 6382/* Only called from bnxt_sp_task() */
6383static void bnxt_reset(struct bnxt *bp, bool silent)
6384{
6385 bnxt_rtnl_lock_sp(bp);
6386 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6387 bnxt_reset_task(bp, silent);
6388 bnxt_rtnl_unlock_sp(bp);
6389}
6390
c0c050c5
MC		 6391static void bnxt_cfg_ntp_filters(struct bnxt *);
6392
6393static void bnxt_sp_task(struct work_struct *work)
6394{
6395 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
c0c050c5 6396
4cebdcec
MC		 6397 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6398 smp_mb__after_atomic();
6399 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6400 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5 6401 return;
4cebdcec 6402 }
c0c050c5
MC		 6403
6404 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
6405 bnxt_cfg_rx_mode(bp);
6406
6407 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
6408 bnxt_cfg_ntp_filters(bp);
c0c050c5
MC		 6409 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
6410 bnxt_hwrm_exec_fwd_req(bp);
6411 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6412 bnxt_hwrm_tunnel_dst_port_alloc(
6413 bp, bp->vxlan_port,
6414 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6415 }
6416 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6417 bnxt_hwrm_tunnel_dst_port_free(
6418 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6419 }
7cdd5fc3
AD		 6420 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6421 bnxt_hwrm_tunnel_dst_port_alloc(
6422 bp, bp->nge_port,
6423 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6424 }
6425 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6426 bnxt_hwrm_tunnel_dst_port_free(
6427 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6428 }
3bdf56c4
MC		 6429 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
6430 bnxt_hwrm_port_qstats(bp);
6431
a551ee94
MC		 6432 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
6433 * must be the last functions to be called before exiting.
6434 */
0eaa24b9
MC		 6435 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
6436 int rc = 0;
6437
6438 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
6439 &bp->sp_event))
6440 bnxt_hwrm_phy_qcaps(bp);
6441
6442 bnxt_rtnl_lock_sp(bp);
6443 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6444 rc = bnxt_update_link(bp, true);
6445 bnxt_rtnl_unlock_sp(bp);
6446 if (rc)
6447 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
6448 rc);
6449 }
90c694bb
MC		 6450 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
6451 bnxt_rtnl_lock_sp(bp);
6452 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6453 bnxt_get_port_module_status(bp);
6454 bnxt_rtnl_unlock_sp(bp);
6455 }
6988bd92
MC		 6456 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
6457 bnxt_reset(bp, false);
4cebdcec 6458
fc0f1929
MC		 6459 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
6460 bnxt_reset(bp, true);
6461
4cebdcec
MC		 6462 smp_mb__before_atomic();
6463 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
c0c050c5
MC		 6464}
6465
6466static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
6467{
6468 int rc;
6469 struct bnxt *bp = netdev_priv(dev);
6470
6471 SET_NETDEV_DEV(dev, &pdev->dev);
6472
6473 /* enable device (incl. PCI PM wakeup), and bus-mastering */
6474 rc = pci_enable_device(pdev);
6475 if (rc) {
6476 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
6477 goto init_err;
6478 }
6479
6480 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
6481 dev_err(&pdev->dev,
6482 "Cannot find PCI device base address, aborting\n");
6483 rc = -ENODEV;
6484 goto init_err_disable;
6485 }
6486
6487 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
6488 if (rc) {
6489 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
6490 goto init_err_disable;
6491 }
6492
6493 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
6494 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
6495 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
6496 goto init_err_disable;
6497 }
6498
6499 pci_set_master(pdev);
6500
6501 bp->dev = dev;
6502 bp->pdev = pdev;
6503
6504 bp->bar0 = pci_ioremap_bar(pdev, 0);
6505 if (!bp->bar0) {
6506 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
6507 rc = -ENOMEM;
6508 goto init_err_release;
6509 }
6510
6511 bp->bar1 = pci_ioremap_bar(pdev, 2);
6512 if (!bp->bar1) {
6513 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
6514 rc = -ENOMEM;
6515 goto init_err_release;
6516 }
6517
6518 bp->bar2 = pci_ioremap_bar(pdev, 4);
6519 if (!bp->bar2) {
6520 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
6521 rc = -ENOMEM;
6522 goto init_err_release;
6523 }
6524
6316ea6d
SB		 6525 pci_enable_pcie_error_reporting(pdev);
6526
c0c050c5
MC		 6527 INIT_WORK(&bp->sp_task, bnxt_sp_task);
6528
6529 spin_lock_init(&bp->ntp_fltr_lock);
6530
6531 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
6532 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
6533
dfb5b894 6534 /* tick values in micro seconds */
dfc9c94a
MC		 6535 bp->rx_coal_ticks = 12;
6536 bp->rx_coal_bufs = 30;
dfb5b894
MC		 6537 bp->rx_coal_ticks_irq = 1;
6538 bp->rx_coal_bufs_irq = 2;
c0c050c5 6539
dfc9c94a
MC		 6540 bp->tx_coal_ticks = 25;
6541 bp->tx_coal_bufs = 30;
6542 bp->tx_coal_ticks_irq = 2;
6543 bp->tx_coal_bufs_irq = 2;
6544
51f30785
MC		 6545 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
6546
c0c050c5
MC		 6547 init_timer(&bp->timer);
6548 bp->timer.data = (unsigned long)bp;
6549 bp->timer.function = bnxt_timer;
6550 bp->current_interval = BNXT_TIMER_INTERVAL;
6551
caefe526 6552 clear_bit(BNXT_STATE_OPEN, &bp->state);
c0c050c5
MC		 6553
6554 return 0;
6555
6556init_err_release:
6557 if (bp->bar2) {
6558 pci_iounmap(pdev, bp->bar2);
6559 bp->bar2 = NULL;
6560 }
6561
6562 if (bp->bar1) {
6563 pci_iounmap(pdev, bp->bar1);
6564 bp->bar1 = NULL;
6565 }
6566
6567 if (bp->bar0) {
6568 pci_iounmap(pdev, bp->bar0);
6569 bp->bar0 = NULL;
6570 }
6571
6572 pci_release_regions(pdev);
6573
6574init_err_disable:
6575 pci_disable_device(pdev);
6576
6577init_err:
6578 return rc;
6579}
6580
6581/* rtnl_lock held */
6582static int bnxt_change_mac_addr(struct net_device *dev, void *p)
6583{
6584 struct sockaddr *addr = p;
1fc2cfd0
JH		 6585 struct bnxt *bp = netdev_priv(dev);
6586 int rc = 0;
c0c050c5
MC		 6587
6588 if (!is_valid_ether_addr(addr->sa_data))
6589 return -EADDRNOTAVAIL;
6590
84c33dd3
MC		 6591 rc = bnxt_approve_mac(bp, addr->sa_data);
6592 if (rc)
6593 return rc;
bdd4347b 6594
1fc2cfd0
JH		 6595 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
6596 return 0;
6597
c0c050c5 6598 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1fc2cfd0
JH		 6599 if (netif_running(dev)) {
6600 bnxt_close_nic(bp, false, false);
6601 rc = bnxt_open_nic(bp, false, false);
6602 }
c0c050c5 6603
1fc2cfd0 6604 return rc;
c0c050c5
MC		 6605}
6606
6607/* rtnl_lock held */
6608static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
6609{
6610 struct bnxt *bp = netdev_priv(dev);
6611
c0c050c5
MC		 6612 if (netif_running(dev))
6613 bnxt_close_nic(bp, false, false);
6614
6615 dev->mtu = new_mtu;
6616 bnxt_set_ring_params(bp);
6617
6618 if (netif_running(dev))
6619 return bnxt_open_nic(bp, false, false);
6620
6621 return 0;
6622}
6623
c5e3deb8 6624int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
c0c050c5
MC		 6625{
6626 struct bnxt *bp = netdev_priv(dev);
3ffb6a39 6627 bool sh = false;
16e5cc64 6628
c0c050c5
MC		 6629 if (tc > bp->max_tc) {
6630 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
6631 tc, bp->max_tc);
6632 return -EINVAL;
6633 }
6634
6635 if (netdev_get_num_tc(dev) == tc)
6636 return 0;
6637
3ffb6a39
MC		 6638 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6639 sh = true;
6640
c0c050c5 6641 if (tc) {
391be5c2 6642 int max_rx_rings, max_tx_rings, req_tx_rings, rsv_tx_rings, rc;
c0c050c5 6643
391be5c2 6644 req_tx_rings = bp->tx_nr_rings_per_tc * tc;
01657bcd 6645 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
391be5c2
MC		 6646 if (rc || req_tx_rings > max_tx_rings)
6647 return -ENOMEM;
6648
6649 rsv_tx_rings = req_tx_rings;
6650 if (bnxt_hwrm_reserve_tx_rings(bp, &rsv_tx_rings) ||
6651 rsv_tx_rings < req_tx_rings)
c0c050c5
MC		 6652 return -ENOMEM;
6653 }
6654
6655 /* Needs to close the device and do hw resource re-allocations */
6656 if (netif_running(bp->dev))
6657 bnxt_close_nic(bp, true, false);
6658
6659 if (tc) {
6660 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
6661 netdev_set_num_tc(dev, tc);
6662 } else {
6663 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6664 netdev_reset_tc(dev);
6665 }
3ffb6a39
MC		 6666 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
6667 bp->tx_nr_rings + bp->rx_nr_rings;
c0c050c5
MC		 6668 bp->num_stat_ctxs = bp->cp_nr_rings;
6669
6670 if (netif_running(bp->dev))
6671 return bnxt_open_nic(bp, true, false);
6672
6673 return 0;
6674}
6675
c5e3deb8
MC		 6676static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
6677 struct tc_to_netdev *ntc)
6678{
6679 if (ntc->type != TC_SETUP_MQPRIO)
6680 return -EINVAL;
6681
6682 return bnxt_setup_mq_tc(dev, ntc->tc);
6683}
6684
c0c050c5
MC		 6685#ifdef CONFIG_RFS_ACCEL
6686static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
6687 struct bnxt_ntuple_filter *f2)
6688{
6689 struct flow_keys *keys1 = &f1->fkeys;
6690 struct flow_keys *keys2 = &f2->fkeys;
6691
6692 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
6693 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
6694 keys1->ports.ports == keys2->ports.ports &&
6695 keys1->basic.ip_proto == keys2->basic.ip_proto &&
6696 keys1->basic.n_proto == keys2->basic.n_proto &&
a54c4d74
MC		 6697 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
6698 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
c0c050c5
MC		 6699 return true;
6700
6701 return false;
6702}
6703
6704static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
6705 u16 rxq_index, u32 flow_id)
6706{
6707 struct bnxt *bp = netdev_priv(dev);
6708 struct bnxt_ntuple_filter *fltr, *new_fltr;
6709 struct flow_keys *fkeys;
6710 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
a54c4d74 6711 int rc = 0, idx, bit_id, l2_idx = 0;
c0c050c5
MC		 6712 struct hlist_head *head;
6713
6714 if (skb->encapsulation)
6715 return -EPROTONOSUPPORT;
6716
a54c4d74
MC		 6717 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
6718 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6719 int off = 0, j;
6720
6721 netif_addr_lock_bh(dev);
6722 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
6723 if (ether_addr_equal(eth->h_dest,
6724 vnic->uc_list + off)) {
6725 l2_idx = j + 1;
6726 break;
6727 }
6728 }
6729 netif_addr_unlock_bh(dev);
6730 if (!l2_idx)
6731 return -EINVAL;
6732 }
c0c050c5
MC		 6733 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
6734 if (!new_fltr)
6735 return -ENOMEM;
6736
6737 fkeys = &new_fltr->fkeys;
6738 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
6739 rc = -EPROTONOSUPPORT;
6740 goto err_free;
6741 }
6742
dda0e746
MC		 6743 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
6744 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
c0c050c5
MC		 6745 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
6746 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
6747 rc = -EPROTONOSUPPORT;
6748 goto err_free;
6749 }
dda0e746
MC		 6750 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
6751 bp->hwrm_spec_code < 0x10601) {
6752 rc = -EPROTONOSUPPORT;
6753 goto err_free;
6754 }
c0c050c5 6755
a54c4d74 6756 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
c0c050c5
MC		 6757 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
6758
6759 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
6760 head = &bp->ntp_fltr_hash_tbl[idx];
6761 rcu_read_lock();
6762 hlist_for_each_entry_rcu(fltr, head, hash) {
6763 if (bnxt_fltr_match(fltr, new_fltr)) {
6764 rcu_read_unlock();
6765 rc = 0;
6766 goto err_free;
6767 }
6768 }
6769 rcu_read_unlock();
6770
6771 spin_lock_bh(&bp->ntp_fltr_lock);
84e86b98
MC		 6772 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
6773 BNXT_NTP_FLTR_MAX_FLTR, 0);
6774 if (bit_id < 0) {
c0c050c5
MC		 6775 spin_unlock_bh(&bp->ntp_fltr_lock);
6776 rc = -ENOMEM;
6777 goto err_free;
6778 }
6779
84e86b98 6780 new_fltr->sw_id = (u16)bit_id;
c0c050c5 6781 new_fltr->flow_id = flow_id;
a54c4d74 6782 new_fltr->l2_fltr_idx = l2_idx;
c0c050c5
MC		 6783 new_fltr->rxq = rxq_index;
6784 hlist_add_head_rcu(&new_fltr->hash, head);
6785 bp->ntp_fltr_count++;
6786 spin_unlock_bh(&bp->ntp_fltr_lock);
6787
6788 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
6789 schedule_work(&bp->sp_task);
6790
6791 return new_fltr->sw_id;
6792
6793err_free:
6794 kfree(new_fltr);
6795 return rc;
6796}
6797
6798static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6799{
6800 int i;
6801
6802 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
6803 struct hlist_head *head;
6804 struct hlist_node *tmp;
6805 struct bnxt_ntuple_filter *fltr;
6806 int rc;
6807
6808 head = &bp->ntp_fltr_hash_tbl[i];
6809 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
6810 bool del = false;
6811
6812 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
6813 if (rps_may_expire_flow(bp->dev, fltr->rxq,
6814 fltr->flow_id,
6815 fltr->sw_id)) {
6816 bnxt_hwrm_cfa_ntuple_filter_free(bp,
6817 fltr);
6818 del = true;
6819 }
6820 } else {
6821 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
6822 fltr);
6823 if (rc)
6824 del = true;
6825 else
6826 set_bit(BNXT_FLTR_VALID, &fltr->state);
6827 }
6828
6829 if (del) {
6830 spin_lock_bh(&bp->ntp_fltr_lock);
6831 hlist_del_rcu(&fltr->hash);
6832 bp->ntp_fltr_count--;
6833 spin_unlock_bh(&bp->ntp_fltr_lock);
6834 synchronize_rcu();
6835 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
6836 kfree(fltr);
6837 }
6838 }
6839 }
19241368
JH		 6840 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
6841 netdev_info(bp->dev, "Receive PF driver unload event!");
c0c050c5
MC		 6842}
6843
6844#else
6845
6846static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6847{
6848}
6849
6850#endif /* CONFIG_RFS_ACCEL */
6851
ad51b8e9
AD		 6852static void bnxt_udp_tunnel_add(struct net_device *dev,
6853 struct udp_tunnel_info *ti)
c0c050c5
MC		 6854{
6855 struct bnxt *bp = netdev_priv(dev);
6856
ad51b8e9 6857 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
c0c050c5
MC		 6858 return;
6859
ad51b8e9 6860 if (!netif_running(dev))
c0c050c5
MC		 6861 return;
6862
ad51b8e9
AD		 6863 switch (ti->type) {
6864 case UDP_TUNNEL_TYPE_VXLAN:
6865 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
6866 return;
c0c050c5 6867
ad51b8e9
AD		 6868 bp->vxlan_port_cnt++;
6869 if (bp->vxlan_port_cnt == 1) {
6870 bp->vxlan_port = ti->port;
6871 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
6872 schedule_work(&bp->sp_task);
6873 }
6874 break;
7cdd5fc3
AD		 6875 case UDP_TUNNEL_TYPE_GENEVE:
6876 if (bp->nge_port_cnt && bp->nge_port != ti->port)
6877 return;
6878
6879 bp->nge_port_cnt++;
6880 if (bp->nge_port_cnt == 1) {
6881 bp->nge_port = ti->port;
6882 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
6883 }
6884 break;
ad51b8e9
AD		 6885 default:
6886 return;
c0c050c5 6887 }
ad51b8e9
AD		 6888
6889 schedule_work(&bp->sp_task);
c0c050c5
MC		 6890}
6891
ad51b8e9
AD		 6892static void bnxt_udp_tunnel_del(struct net_device *dev,
6893 struct udp_tunnel_info *ti)
c0c050c5
MC		 6894{
6895 struct bnxt *bp = netdev_priv(dev);
6896
ad51b8e9 6897 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
c0c050c5
MC		 6898 return;
6899
ad51b8e9 6900 if (!netif_running(dev))
c0c050c5
MC		 6901 return;
6902
ad51b8e9
AD		 6903 switch (ti->type) {
6904 case UDP_TUNNEL_TYPE_VXLAN:
6905 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
6906 return;
c0c050c5
MC		 6907 bp->vxlan_port_cnt--;
6908
ad51b8e9
AD		 6909 if (bp->vxlan_port_cnt != 0)
6910 return;
6911
6912 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
6913 break;
7cdd5fc3
AD		 6914 case UDP_TUNNEL_TYPE_GENEVE:
6915 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
6916 return;
6917 bp->nge_port_cnt--;
6918
6919 if (bp->nge_port_cnt != 0)
6920 return;
6921
6922 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
6923 break;
ad51b8e9
AD		 6924 default:
6925 return;
c0c050c5 6926 }
ad51b8e9
AD		 6927
6928 schedule_work(&bp->sp_task);
c0c050c5
MC		 6929}
6930
6931static const struct net_device_ops bnxt_netdev_ops = {
6932 .ndo_open = bnxt_open,
6933 .ndo_start_xmit = bnxt_start_xmit,
6934 .ndo_stop = bnxt_close,
6935 .ndo_get_stats64 = bnxt_get_stats64,
6936 .ndo_set_rx_mode = bnxt_set_rx_mode,
6937 .ndo_do_ioctl = bnxt_ioctl,
6938 .ndo_validate_addr = eth_validate_addr,
6939 .ndo_set_mac_address = bnxt_change_mac_addr,
6940 .ndo_change_mtu = bnxt_change_mtu,
6941 .ndo_fix_features = bnxt_fix_features,
6942 .ndo_set_features = bnxt_set_features,
6943 .ndo_tx_timeout = bnxt_tx_timeout,
6944#ifdef CONFIG_BNXT_SRIOV
6945 .ndo_get_vf_config = bnxt_get_vf_config,
6946 .ndo_set_vf_mac = bnxt_set_vf_mac,
6947 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
6948 .ndo_set_vf_rate = bnxt_set_vf_bw,
6949 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
6950 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
6951#endif
6952#ifdef CONFIG_NET_POLL_CONTROLLER
6953 .ndo_poll_controller = bnxt_poll_controller,
6954#endif
6955 .ndo_setup_tc = bnxt_setup_tc,
6956#ifdef CONFIG_RFS_ACCEL
6957 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
6958#endif
ad51b8e9
AD		 6959 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
6960 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
c0c050c5
MC		 6961};
6962
6963static void bnxt_remove_one(struct pci_dev *pdev)
6964{
6965 struct net_device *dev = pci_get_drvdata(pdev);
6966 struct bnxt *bp = netdev_priv(dev);
6967
6968 if (BNXT_PF(bp))
6969 bnxt_sriov_disable(bp);
6970
6316ea6d 6971 pci_disable_pcie_error_reporting(pdev);
c0c050c5
MC		 6972 unregister_netdev(dev);
6973 cancel_work_sync(&bp->sp_task);
6974 bp->sp_event = 0;
6975
7809592d 6976 bnxt_clear_int_mode(bp);
be58a0da 6977 bnxt_hwrm_func_drv_unrgtr(bp);
c0c050c5 6978 bnxt_free_hwrm_resources(bp);
7df4ae9f 6979 bnxt_dcb_free(bp);
c0c050c5
MC		 6980 pci_iounmap(pdev, bp->bar2);
6981 pci_iounmap(pdev, bp->bar1);
6982 pci_iounmap(pdev, bp->bar0);
a588e458
MC		 6983 kfree(bp->edev);
6984 bp->edev = NULL;
c0c050c5
MC		 6985 free_netdev(dev);
6986
6987 pci_release_regions(pdev);
6988 pci_disable_device(pdev);
6989}
6990
6991static int bnxt_probe_phy(struct bnxt *bp)
6992{
6993 int rc = 0;
6994 struct bnxt_link_info *link_info = &bp->link_info;
c0c050c5 6995
170ce013
MC		 6996 rc = bnxt_hwrm_phy_qcaps(bp);
6997 if (rc) {
6998 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
6999 rc);
7000 return rc;
7001 }
7002
c0c050c5
MC		 7003 rc = bnxt_update_link(bp, false);
7004 if (rc) {
7005 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
7006 rc);
7007 return rc;
7008 }
7009
93ed8117
MC		 7010 /* Older firmware does not have supported_auto_speeds, so assume
7011 * that all supported speeds can be autonegotiated.
7012 */
7013 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
7014 link_info->support_auto_speeds = link_info->support_speeds;
7015
c0c050c5 7016 /*initialize the ethool setting copy with NVM settings */
0d8abf02 7017 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
c9ee9516
MC		 7018 link_info->autoneg = BNXT_AUTONEG_SPEED;
7019 if (bp->hwrm_spec_code >= 0x10201) {
7020 if (link_info->auto_pause_setting &
7021 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
7022 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7023 } else {
7024 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7025 }
0d8abf02 7026 link_info->advertising = link_info->auto_link_speeds;
0d8abf02
MC		 7027 } else {
7028 link_info->req_link_speed = link_info->force_link_speed;
7029 link_info->req_duplex = link_info->duplex_setting;
c0c050c5 7030 }
c9ee9516
MC		 7031 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
7032 link_info->req_flow_ctrl =
7033 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
7034 else
7035 link_info->req_flow_ctrl = link_info->force_pause_setting;
c0c050c5
MC		 7036 return rc;
7037}
7038
7039static int bnxt_get_max_irq(struct pci_dev *pdev)
7040{
7041 u16 ctrl;
7042
7043 if (!pdev->msix_cap)
7044 return 1;
7045
7046 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
7047 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
7048}
7049
6e6c5a57
MC		 7050static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7051 int *max_cp)
c0c050c5 7052{
6e6c5a57 7053 int max_ring_grps = 0;
c0c050c5 7054
379a80a1 7055#ifdef CONFIG_BNXT_SRIOV
415b6f19 7056 if (!BNXT_PF(bp)) {
c0c050c5
MC		 7057 *max_tx = bp->vf.max_tx_rings;
7058 *max_rx = bp->vf.max_rx_rings;
6e6c5a57
MC		 7059 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
7060 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
b72d4a68 7061 max_ring_grps = bp->vf.max_hw_ring_grps;
415b6f19 7062 } else
379a80a1 7063#endif
415b6f19
AB		 7064 {
7065 *max_tx = bp->pf.max_tx_rings;
7066 *max_rx = bp->pf.max_rx_rings;
7067 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
7068 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
7069 max_ring_grps = bp->pf.max_hw_ring_grps;
c0c050c5 7070 }
76595193
PS		 7071 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
7072 *max_cp -= 1;
7073 *max_rx -= 2;
7074 }
c0c050c5
MC		 7075 if (bp->flags & BNXT_FLAG_AGG_RINGS)
7076 *max_rx >>= 1;
b72d4a68 7077 *max_rx = min_t(int, *max_rx, max_ring_grps);
6e6c5a57
MC		 7078}
7079
7080int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
7081{
7082 int rx, tx, cp;
7083
7084 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
7085 if (!rx || !tx || !cp)
7086 return -ENOMEM;
7087
7088 *max_rx = rx;
7089 *max_tx = tx;
7090 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
7091}
7092
e4060d30
MC		 7093static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7094 bool shared)
7095{
7096 int rc;
7097
7098 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
bdbd1eb5
MC		 7099 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
7100 /* Not enough rings, try disabling agg rings. */
7101 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
7102 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7103 if (rc)
7104 return rc;
7105 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
7106 bp->dev->hw_features &= ~NETIF_F_LRO;
7107 bp->dev->features &= ~NETIF_F_LRO;
7108 bnxt_set_ring_params(bp);
7109 }
e4060d30
MC		 7110
7111 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
7112 int max_cp, max_stat, max_irq;
7113
7114 /* Reserve minimum resources for RoCE */
7115 max_cp = bnxt_get_max_func_cp_rings(bp);
7116 max_stat = bnxt_get_max_func_stat_ctxs(bp);
7117 max_irq = bnxt_get_max_func_irqs(bp);
7118 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
7119 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
7120 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
7121 return 0;
7122
7123 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
7124 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
7125 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
7126 max_cp = min_t(int, max_cp, max_irq);
7127 max_cp = min_t(int, max_cp, max_stat);
7128 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
7129 if (rc)
7130 rc = 0;
7131 }
7132 return rc;
7133}
7134
6e6c5a57
MC		 7135static int bnxt_set_dflt_rings(struct bnxt *bp)
7136{
7137 int dflt_rings, max_rx_rings, max_tx_rings, rc;
7138 bool sh = true;
7139
7140 if (sh)
7141 bp->flags |= BNXT_FLAG_SHARED_RINGS;
7142 dflt_rings = netif_get_num_default_rss_queues();
e4060d30 7143 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6e6c5a57
MC		 7144 if (rc)
7145 return rc;
7146 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
7147 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
391be5c2
MC		 7148
7149 rc = bnxt_hwrm_reserve_tx_rings(bp, &bp->tx_nr_rings_per_tc);
7150 if (rc)
7151 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
7152
6e6c5a57
MC		 7153 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7154 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7155 bp->tx_nr_rings + bp->rx_nr_rings;
7156 bp->num_stat_ctxs = bp->cp_nr_rings;
76595193
PS		 7157 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7158 bp->rx_nr_rings++;
7159 bp->cp_nr_rings++;
7160 }
6e6c5a57 7161 return rc;
c0c050c5
MC		 7162}
7163
7b08f661
MC		 7164void bnxt_restore_pf_fw_resources(struct bnxt *bp)
7165{
7166 ASSERT_RTNL();
7167 bnxt_hwrm_func_qcaps(bp);
a588e458 7168 bnxt_subtract_ulp_resources(bp, BNXT_ROCE_ULP);
7b08f661
MC		 7169}
7170
90c4f788
AK		 7171static void bnxt_parse_log_pcie_link(struct bnxt *bp)
7172{
7173 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
7174 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
7175
7176 if (pcie_get_minimum_link(bp->pdev, &speed, &width) ||
7177 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
7178 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
7179 else
7180 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
7181 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
7182 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
7183 speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
7184 "Unknown", width);
7185}
7186
c0c050c5
MC		 7187static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7188{
7189 static int version_printed;
7190 struct net_device *dev;
7191 struct bnxt *bp;
6e6c5a57 7192 int rc, max_irqs;
c0c050c5 7193
fa853dda
PS		 7194 if (pdev->device == 0x16cd && pci_is_bridge(pdev))
7195 return -ENODEV;
7196
c0c050c5
MC		 7197 if (version_printed++ == 0)
7198 pr_info("%s", version);
7199
7200 max_irqs = bnxt_get_max_irq(pdev);
7201 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
7202 if (!dev)
7203 return -ENOMEM;
7204
7205 bp = netdev_priv(dev);
7206
7207 if (bnxt_vf_pciid(ent->driver_data))
7208 bp->flags |= BNXT_FLAG_VF;
7209
2bcfa6f6 7210 if (pdev->msix_cap)
c0c050c5 7211 bp->flags |= BNXT_FLAG_MSIX_CAP;
c0c050c5
MC		 7212
7213 rc = bnxt_init_board(pdev, dev);
7214 if (rc < 0)
7215 goto init_err_free;
7216
7217 dev->netdev_ops = &bnxt_netdev_ops;
7218 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
7219 dev->ethtool_ops = &bnxt_ethtool_ops;
7220
7221 pci_set_drvdata(pdev, dev);
7222
3e8060fa
PS		 7223 rc = bnxt_alloc_hwrm_resources(bp);
7224 if (rc)
7225 goto init_err;
7226
7227 mutex_init(&bp->hwrm_cmd_lock);
7228 rc = bnxt_hwrm_ver_get(bp);
7229 if (rc)
7230 goto init_err;
7231
5ac67d8b
RS		 7232 bnxt_hwrm_fw_set_time(bp);
7233
c0c050c5
MC		 7234 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
7235 NETIF_F_TSO | NETIF_F_TSO6 |
7236 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
7e13318d 7237 NETIF_F_GSO_IPXIP4 |
152971ee
AD		 7238 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7239 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
3e8060fa
PS		 7240 NETIF_F_RXCSUM | NETIF_F_GRO;
7241
7242 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
7243 dev->hw_features |= NETIF_F_LRO;
c0c050c5 7244
c0c050c5
MC		 7245 dev->hw_enc_features =
7246 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
7247 NETIF_F_TSO | NETIF_F_TSO6 |
7248 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
152971ee 7249 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7e13318d 7250 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
152971ee
AD		 7251 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
7252 NETIF_F_GSO_GRE_CSUM;
c0c050c5
MC		 7253 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
7254 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
7255 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
7256 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
7257 dev->priv_flags |= IFF_UNICAST_FLT;
7258
e1c6dcca
JW		 7259 /* MTU range: 60 - 9500 */
7260 dev->min_mtu = ETH_ZLEN;
7261 dev->max_mtu = 9500;
7262
7df4ae9f
MC		 7263 bnxt_dcb_init(bp);
7264
c0c050c5
MC		 7265#ifdef CONFIG_BNXT_SRIOV
7266 init_waitqueue_head(&bp->sriov_cfg_wait);
7267#endif
309369c9 7268 bp->gro_func = bnxt_gro_func_5730x;
94758f8d
MC		 7269 if (BNXT_CHIP_NUM_57X1X(bp->chip_num))
7270 bp->gro_func = bnxt_gro_func_5731x;
309369c9 7271
c0c050c5
MC		 7272 rc = bnxt_hwrm_func_drv_rgtr(bp);
7273 if (rc)
7274 goto init_err;
7275
a1653b13
MC		 7276 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
7277 if (rc)
7278 goto init_err;
7279
a588e458
MC		 7280 bp->ulp_probe = bnxt_ulp_probe;
7281
c0c050c5
MC		 7282 /* Get the MAX capabilities for this function */
7283 rc = bnxt_hwrm_func_qcaps(bp);
7284 if (rc) {
7285 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
7286 rc);
7287 rc = -1;
7288 goto init_err;
7289 }
7290
7291 rc = bnxt_hwrm_queue_qportcfg(bp);
7292 if (rc) {
7293 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
7294 rc);
7295 rc = -1;
7296 goto init_err;
7297 }
7298
567b2abe 7299 bnxt_hwrm_func_qcfg(bp);
5ad2cbee 7300 bnxt_hwrm_port_led_qcaps(bp);
567b2abe 7301
c0c050c5
MC		 7302 bnxt_set_tpa_flags(bp);
7303 bnxt_set_ring_params(bp);
33c2657e 7304 bnxt_set_max_func_irqs(bp, max_irqs);
bdbd1eb5
MC		 7305 rc = bnxt_set_dflt_rings(bp);
7306 if (rc) {
7307 netdev_err(bp->dev, "Not enough rings available.\n");
7308 rc = -ENOMEM;
7309 goto init_err;
7310 }
c0c050c5 7311
87da7f79
MC		 7312 /* Default RSS hash cfg. */
7313 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
7314 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
7315 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
7316 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
7317 if (!BNXT_CHIP_NUM_57X0X(bp->chip_num) &&
7318 !BNXT_CHIP_TYPE_NITRO_A0(bp) &&
7319 bp->hwrm_spec_code >= 0x10501) {
7320 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
7321 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
7322 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
7323 }
7324
8fdefd63 7325 bnxt_hwrm_vnic_qcaps(bp);
8079e8f1 7326 if (bnxt_rfs_supported(bp)) {
2bcfa6f6
MC		 7327 dev->hw_features |= NETIF_F_NTUPLE;
7328 if (bnxt_rfs_capable(bp)) {
7329 bp->flags |= BNXT_FLAG_RFS;
7330 dev->features |= NETIF_F_NTUPLE;
7331 }
7332 }
7333
c0c050c5
MC		 7334 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
7335 bp->flags |= BNXT_FLAG_STRIP_VLAN;
7336
7337 rc = bnxt_probe_phy(bp);
7338 if (rc)
7339 goto init_err;
7340
aa8ed021
MC		 7341 rc = bnxt_hwrm_func_reset(bp);
7342 if (rc)
7343 goto init_err;
7344
7809592d 7345 rc = bnxt_init_int_mode(bp);
c0c050c5
MC		 7346 if (rc)
7347 goto init_err;
7348
7809592d
MC		 7349 rc = register_netdev(dev);
7350 if (rc)
7351 goto init_err_clr_int;
7352
c0c050c5
MC		 7353 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
7354 board_info[ent->driver_data].name,
7355 (long)pci_resource_start(pdev, 0), dev->dev_addr);
7356
90c4f788
AK		 7357 bnxt_parse_log_pcie_link(bp);
7358
c0c050c5
MC		 7359 return 0;
7360
7809592d
MC		 7361init_err_clr_int:
7362 bnxt_clear_int_mode(bp);
7363
c0c050c5
MC		 7364init_err:
7365 pci_iounmap(pdev, bp->bar0);
7366 pci_release_regions(pdev);
7367 pci_disable_device(pdev);
7368
7369init_err_free:
7370 free_netdev(dev);
7371 return rc;
7372}
7373
6316ea6d
SB		 7374/**
7375 * bnxt_io_error_detected - called when PCI error is detected
7376 * @pdev: Pointer to PCI device
7377 * @state: The current pci connection state
7378 *
7379 * This function is called after a PCI bus error affecting
7380 * this device has been detected.
7381 */
7382static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
7383 pci_channel_state_t state)
7384{
7385 struct net_device *netdev = pci_get_drvdata(pdev);
a588e458 7386 struct bnxt *bp = netdev_priv(netdev);
6316ea6d
SB		 7387
7388 netdev_info(netdev, "PCI I/O error detected\n");
7389
7390 rtnl_lock();
7391 netif_device_detach(netdev);
7392
a588e458
MC		 7393 bnxt_ulp_stop(bp);
7394
6316ea6d
SB		 7395 if (state == pci_channel_io_perm_failure) {
7396 rtnl_unlock();
7397 return PCI_ERS_RESULT_DISCONNECT;
7398 }
7399
7400 if (netif_running(netdev))
7401 bnxt_close(netdev);
7402
7403 pci_disable_device(pdev);
7404 rtnl_unlock();
7405
7406 /* Request a slot slot reset. */
7407 return PCI_ERS_RESULT_NEED_RESET;
7408}
7409
7410/**
7411 * bnxt_io_slot_reset - called after the pci bus has been reset.
7412 * @pdev: Pointer to PCI device
7413 *
7414 * Restart the card from scratch, as if from a cold-boot.
7415 * At this point, the card has exprienced a hard reset,
7416 * followed by fixups by BIOS, and has its config space
7417 * set up identically to what it was at cold boot.
7418 */
7419static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
7420{
7421 struct net_device *netdev = pci_get_drvdata(pdev);
7422 struct bnxt *bp = netdev_priv(netdev);
7423 int err = 0;
7424 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
7425
7426 netdev_info(bp->dev, "PCI Slot Reset\n");
7427
7428 rtnl_lock();
7429
7430 if (pci_enable_device(pdev)) {
7431 dev_err(&pdev->dev,
7432 "Cannot re-enable PCI device after reset.\n");
7433 } else {
7434 pci_set_master(pdev);
7435
aa8ed021
MC		 7436 err = bnxt_hwrm_func_reset(bp);
7437 if (!err && netif_running(netdev))
6316ea6d
SB		 7438 err = bnxt_open(netdev);
7439
a588e458 7440 if (!err) {
6316ea6d 7441 result = PCI_ERS_RESULT_RECOVERED;
a588e458
MC		 7442 bnxt_ulp_start(bp);
7443 }
6316ea6d
SB		 7444 }
7445
7446 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
7447 dev_close(netdev);
7448
7449 rtnl_unlock();
7450
7451 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7452 if (err) {
7453 dev_err(&pdev->dev,
7454 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7455 err); /* non-fatal, continue */
7456 }
7457
7458 return PCI_ERS_RESULT_RECOVERED;
7459}
7460
7461/**
7462 * bnxt_io_resume - called when traffic can start flowing again.
7463 * @pdev: Pointer to PCI device
7464 *
7465 * This callback is called when the error recovery driver tells
7466 * us that its OK to resume normal operation.
7467 */
7468static void bnxt_io_resume(struct pci_dev *pdev)
7469{
7470 struct net_device *netdev = pci_get_drvdata(pdev);
7471
7472 rtnl_lock();
7473
7474 netif_device_attach(netdev);
7475
7476 rtnl_unlock();
7477}
7478
7479static const struct pci_error_handlers bnxt_err_handler = {
7480 .error_detected = bnxt_io_error_detected,
7481 .slot_reset = bnxt_io_slot_reset,
7482 .resume = bnxt_io_resume
7483};
7484
c0c050c5
MC		 7485static struct pci_driver bnxt_pci_driver = {
7486 .name = DRV_MODULE_NAME,
7487 .id_table = bnxt_pci_tbl,
7488 .probe = bnxt_init_one,
7489 .remove = bnxt_remove_one,
6316ea6d 7490 .err_handler = &bnxt_err_handler,
c0c050c5
MC		 7491#if defined(CONFIG_BNXT_SRIOV)
7492 .sriov_configure = bnxt_sriov_configure,
7493#endif
7494};
7495
7496module_pci_driver(bnxt_pci_driver);
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