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f492ec9f | 1 | /* |
896f66b7 HG |
2 | * TI DaVinci Audio Serial Port support |
3 | * | |
4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation version 2. | |
9 | * | |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
11 | * kind, whether express or implied; without even the implied warranty | |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
f492ec9f | 14 | */ |
f492ec9f | 15 | |
896f66b7 HG |
16 | #ifndef __DAVINCI_ASP_H |
17 | #define __DAVINCI_ASP_H | |
f492ec9f | 18 | |
b8ec56d8 MP |
19 | #include <linux/genalloc.h> |
20 | ||
25acf553 | 21 | struct snd_platform_data { |
25acf553 C |
22 | u32 tx_dma_offset; |
23 | u32 rx_dma_offset; | |
896f66b7 HG |
24 | int asp_chan_q; /* event queue number for ASP channel */ |
25 | int ram_chan_q; /* event queue number for RAM channel */ | |
0d6c9774 TK |
26 | /* |
27 | * Allowing this is more efficient and eliminates left and right swaps | |
28 | * caused by underruns, but will swap the left and right channels | |
29 | * when compared to previous behavior. | |
30 | */ | |
31 | unsigned enable_channel_combine:1; | |
1e224f32 TK |
32 | unsigned sram_size_playback; |
33 | unsigned sram_size_capture; | |
b8ec56d8 | 34 | struct gen_pool *sram_pool; |
25acf553 | 35 | |
ec637553 RR |
36 | /* |
37 | * If McBSP peripheral gets the clock from an external pin, | |
38 | * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR | |
39 | * and MCBSP_CLKS. | |
40 | * Depending on different hardware connections it is possible | |
41 | * to use this setting to change the behaviour of McBSP | |
896f66b7 | 42 | * driver. |
ec637553 RR |
43 | */ |
44 | int clk_input_pin; | |
45 | ||
d9823ed9 RR |
46 | /* |
47 | * This flag works when both clock and FS are outputs for the cpu | |
48 | * and makes clock more accurate (FS is not symmetrical and the | |
49 | * clock is very fast. | |
50 | * The clock becoming faster is named | |
51 | * i2s continuous serial clock (I2S_SCK) and it is an externally | |
52 | * visible bit clock. | |
53 | * | |
54 | * first line : WordSelect | |
55 | * second line : ContinuousSerialClock | |
56 | * third line: SerialData | |
57 | * | |
58 | * SYMMETRICAL APPROACH: | |
59 | * _______________________ LEFT | |
60 | * _| RIGHT |______________________| | |
61 | * _ _ _ _ _ _ _ _ | |
62 | * _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_ | |
63 | * _ _ _ _ _ _ _ _ | |
64 | * _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_ | |
65 | * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ | |
66 | * | |
67 | * ACCURATE CLOCK APPROACH: | |
68 | * ______________ LEFT | |
69 | * _| RIGHT |_______________________________| | |
70 | * _ _ _ _ _ _ _ _ _ | |
71 | * _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| | | |
72 | * _ _ _ _ dummy cycles | |
73 | * _/ \_ ... _/ \_/ \_ ... _/ \__________________ | |
74 | * \_/ \_/ \_/ \_/ | |
75 | * | |
76 | */ | |
77 | bool i2s_accurate_sck; | |
78 | ||
25acf553 C |
79 | /* McASP specific fields */ |
80 | int tdm_slots; | |
81 | u8 op_mode; | |
82 | u8 num_serializer; | |
83 | u8 *serial_dir; | |
e33ef5e3 C |
84 | u8 version; |
85 | u8 txnumevt; | |
86 | u8 rxnumevt; | |
87 | }; | |
88 | ||
89 | enum { | |
90 | MCASP_VERSION_1 = 0, /* DM646x */ | |
91 | MCASP_VERSION_2, /* DA8xx/OMAPL1x */ | |
e5ec69da | 92 | MCASP_VERSION_3, /* TI81xx/AM33xx */ |
25acf553 C |
93 | }; |
94 | ||
896f66b7 HG |
95 | enum mcbsp_clk_input_pin { |
96 | MCBSP_CLKR = 0, /* as in DM365 */ | |
ec637553 RR |
97 | MCBSP_CLKS, |
98 | }; | |
99 | ||
25acf553 C |
100 | #define INACTIVE_MODE 0 |
101 | #define TX_MODE 1 | |
102 | #define RX_MODE 2 | |
103 | ||
104 | #define DAVINCI_MCASP_IIS_MODE 0 | |
105 | #define DAVINCI_MCASP_DIT_MODE 1 | |
106 | ||
896f66b7 | 107 | #endif |