[linux.git] / drivers / clk / clk-mux.c

/*
 * Copyright (C) 2011 Sascha Hauer, Pengutronix <[email protected]>
 * Copyright (C) 2011 Richard Zhao, Linaro <[email protected]>
 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Simple multiplexer clock implementation
 */

#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>

/*
 * DOC: basic adjustable multiplexer clock that cannot gate
 *
 * Traits of this clock:
 * prepare - clk_prepare only ensures that parents are prepared
 * enable - clk_enable only ensures that parents are enabled
 * rate - rate is only affected by parent switching.  No clk_set_rate support
 * parent - parent is adjustable through clk_set_parent
 */

int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
			 unsigned int val)
{
	int num_parents = clk_hw_get_num_parents(hw);

	if (table) {
		int i;

		for (i = 0; i < num_parents; i++)
			if (table[i] == val)
				return i;
		return -EINVAL;
	}

	if (val && (flags & CLK_MUX_INDEX_BIT))
		val = ffs(val) - 1;

	if (val && (flags & CLK_MUX_INDEX_ONE))
		val--;

	if (val >= num_parents)
		return -EINVAL;

	return val;
}
EXPORT_SYMBOL_GPL(clk_mux_val_to_index);

unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index)
{
	unsigned int val = index;

	if (table) {
		val = table[index];
	} else {
		if (flags & CLK_MUX_INDEX_BIT)
			val = 1 << index;

		if (flags & CLK_MUX_INDEX_ONE)
			val++;
	}

	return val;
}
EXPORT_SYMBOL_GPL(clk_mux_index_to_val);

static u8 clk_mux_get_parent(struct clk_hw *hw)
{
	struct clk_mux *mux = to_clk_mux(hw);
	u32 val;

	val = clk_readl(mux->reg) >> mux->shift;
	val &= mux->mask;

	return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
}

static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
{
	struct clk_mux *mux = to_clk_mux(hw);
	u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
	unsigned long flags = 0;
	u32 reg;

	if (mux->lock)
		spin_lock_irqsave(mux->lock, flags);
	else
		__acquire(mux->lock);

	if (mux->flags & CLK_MUX_HIWORD_MASK) {
		reg = mux->mask << (mux->shift + 16);
	} else {
		reg = clk_readl(mux->reg);
		reg &= ~(mux->mask << mux->shift);
	}
	val = val << mux->shift;
	reg |= val;
	clk_writel(reg, mux->reg);

	if (mux->lock)
		spin_unlock_irqrestore(mux->lock, flags);
	else
		__release(mux->lock);

	return 0;
}

static int clk_mux_determine_rate(struct clk_hw *hw,
				  struct clk_rate_request *req)
{
	struct clk_mux *mux = to_clk_mux(hw);

	return clk_mux_determine_rate_flags(hw, req, mux->flags);
}

const struct clk_ops clk_mux_ops = {
	.get_parent = clk_mux_get_parent,
	.set_parent = clk_mux_set_parent,
	.determine_rate = clk_mux_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_mux_ops);

const struct clk_ops clk_mux_ro_ops = {
	.get_parent = clk_mux_get_parent,
};
EXPORT_SYMBOL_GPL(clk_mux_ro_ops);

struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
		const char * const *parent_names, u8 num_parents,
		unsigned long flags,
		void __iomem *reg, u8 shift, u32 mask,
		u8 clk_mux_flags, u32 *table, spinlock_t *lock)
{
	struct clk_mux *mux;
	struct clk_hw *hw;
	struct clk_init_data init;
	u8 width = 0;
	int ret;

	if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
		width = fls(mask) - ffs(mask) + 1;
		if (width + shift > 16) {
			pr_err("mux value exceeds LOWORD field\n");
			return ERR_PTR(-EINVAL);
		}
	}

	/* allocate the mux */
	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
	if (!mux)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	if (clk_mux_flags & CLK_MUX_READ_ONLY)
		init.ops = &clk_mux_ro_ops;
	else
		init.ops = &clk_mux_ops;
	init.flags = flags | CLK_IS_BASIC;
	init.parent_names = parent_names;
	init.num_parents = num_parents;

	/* struct clk_mux assignments */
	mux->reg = reg;
	mux->shift = shift;
	mux->mask = mask;
	mux->flags = clk_mux_flags;
	mux->lock = lock;
	mux->table = table;
	mux->hw.init = &init;

	hw = &mux->hw;
	ret = clk_hw_register(dev, hw);
	if (ret) {
		kfree(mux);
		hw = ERR_PTR(ret);
	}

	return hw;
}
EXPORT_SYMBOL_GPL(clk_hw_register_mux_table);

struct clk *clk_register_mux_table(struct device *dev, const char *name,
		const char * const *parent_names, u8 num_parents,
		unsigned long flags,
		void __iomem *reg, u8 shift, u32 mask,
		u8 clk_mux_flags, u32 *table, spinlock_t *lock)
{
	struct clk_hw *hw;

	hw = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
				       flags, reg, shift, mask, clk_mux_flags,
				       table, lock);
	if (IS_ERR(hw))
		return ERR_CAST(hw);
	return hw->clk;
}
EXPORT_SYMBOL_GPL(clk_register_mux_table);

struct clk *clk_register_mux(struct device *dev, const char *name,
		const char * const *parent_names, u8 num_parents,
		unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_mux_flags, spinlock_t *lock)
{
	u32 mask = BIT(width) - 1;

	return clk_register_mux_table(dev, name, parent_names, num_parents,
				      flags, reg, shift, mask, clk_mux_flags,
				      NULL, lock);
}
EXPORT_SYMBOL_GPL(clk_register_mux);

struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,
		const char * const *parent_names, u8 num_parents,
		unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_mux_flags, spinlock_t *lock)
{
	u32 mask = BIT(width) - 1;

	return clk_hw_register_mux_table(dev, name, parent_names, num_parents,
				      flags, reg, shift, mask, clk_mux_flags,
				      NULL, lock);
}
EXPORT_SYMBOL_GPL(clk_hw_register_mux);

void clk_unregister_mux(struct clk *clk)
{
	struct clk_mux *mux;
	struct clk_hw *hw;

	hw = __clk_get_hw(clk);
	if (!hw)
		return;

	mux = to_clk_mux(hw);

	clk_unregister(clk);
	kfree(mux);
}
EXPORT_SYMBOL_GPL(clk_unregister_mux);

void clk_hw_unregister_mux(struct clk_hw *hw)
{
	struct clk_mux *mux;

	mux = to_clk_mux(hw);

	clk_hw_unregister(hw);
	kfree(mux);
}
EXPORT_SYMBOL_GPL(clk_hw_unregister_mux);
Commit	Line	Data
9d9f78ed MT	1	/*
	2	* Copyright (C) 2011 Sascha Hauer, Pengutronix <[email protected]>
	3	* Copyright (C) 2011 Richard Zhao, Linaro <[email protected]>
	4	* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <[email protected]>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Simple multiplexer clock implementation
	11	*/
	12
9d9f78ed MT	13	#include <linux/clk-provider.h>
	14	#include <linux/module.h>
	15	#include <linux/slab.h>
	16	#include <linux/io.h>
	17	#include <linux/err.h>
	18
	19	/*
	20	* DOC: basic adjustable multiplexer clock that cannot gate
	21	*
	22	* Traits of this clock:
	23	* prepare - clk_prepare only ensures that parents are prepared
	24	* enable - clk_enable only ensures that parents are enabled
	25	* rate - rate is only affected by parent switching. No clk_set_rate support
	26	* parent - parent is adjustable through clk_set_parent
	27	*/
	28
77deb66d JB	29	int clk_mux_val_to_index(struct clk_hw hw, u32 table, unsigned int flags,
77deb66d JB	30	unsigned int val)
9d9f78ed	31	{
497295af	32	int num_parents = clk_hw_get_num_parents(hw);
9d9f78ed	33
77deb66d	34	if (table) {
ce4f3313 PDS	35	int i;
	36
	37	for (i = 0; i < num_parents; i++)
77deb66d	38	if (table[i] == val)
ce4f3313 PDS	39	return i;
	40	return -EINVAL;
	41	}
9d9f78ed	42
77deb66d	43	if (val && (flags & CLK_MUX_INDEX_BIT))
9d9f78ed MT	44	val = ffs(val) - 1;
9d9f78ed MT	45
77deb66d	46	if (val && (flags & CLK_MUX_INDEX_ONE))
9d9f78ed MT	47	val--;
9d9f78ed MT	48
ce4f3313	49	if (val >= num_parents)
9d9f78ed MT	50	return -EINVAL;
	51
	52	return val;
	53	}
77deb66d	54	EXPORT_SYMBOL_GPL(clk_mux_val_to_index);
9d9f78ed	55
77deb66d	56	unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index)
9d9f78ed	57	{
77deb66d	58	unsigned int val = index;
9d9f78ed	59
77deb66d JB	60	if (table) {
77deb66d JB	61	val = table[index];
3837bd27	62	} else {
77deb66d JB	63	if (flags & CLK_MUX_INDEX_BIT)
77deb66d JB	64	val = 1 << index;
ce4f3313	65
77deb66d JB	66	if (flags & CLK_MUX_INDEX_ONE)
77deb66d JB	67	val++;
ce4f3313	68	}
9d9f78ed	69
77deb66d JB	70	return val;
	71	}
	72	EXPORT_SYMBOL_GPL(clk_mux_index_to_val);
	73
	74	static u8 clk_mux_get_parent(struct clk_hw *hw)
	75	{
	76	struct clk_mux *mux = to_clk_mux(hw);
	77	u32 val;
	78
	79	val = clk_readl(mux->reg) >> mux->shift;
	80	val &= mux->mask;
	81
	82	return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
	83	}
	84
	85	static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
	86	{
	87	struct clk_mux *mux = to_clk_mux(hw);
	88	u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
	89	unsigned long flags = 0;
	90	u32 reg;
	91
9d9f78ed MT	92	if (mux->lock)
9d9f78ed MT	93	spin_lock_irqsave(mux->lock, flags);
661e2180 SB	94	else
661e2180 SB	95	__acquire(mux->lock);
9d9f78ed	96
ba492e90	97	if (mux->flags & CLK_MUX_HIWORD_MASK) {
77deb66d	98	reg = mux->mask << (mux->shift + 16);
ba492e90	99	} else {
77deb66d JB	100	reg = clk_readl(mux->reg);
77deb66d JB	101	reg &= ~(mux->mask << mux->shift);
ba492e90	102	}
77deb66d JB	103	val = val << mux->shift;
	104	reg \|= val;
	105	clk_writel(reg, mux->reg);
9d9f78ed MT	106
	107	if (mux->lock)
	108	spin_unlock_irqrestore(mux->lock, flags);
661e2180 SB	109	else
661e2180 SB	110	__release(mux->lock);
9d9f78ed MT	111
	112	return 0;
	113	}
9d9f78ed	114
4ad69b80 JB	115	static int clk_mux_determine_rate(struct clk_hw *hw,
	116	struct clk_rate_request *req)
	117	{
	118	struct clk_mux *mux = to_clk_mux(hw);
	119
	120	return clk_mux_determine_rate_flags(hw, req, mux->flags);
	121	}
	122
822c250e	123	const struct clk_ops clk_mux_ops = {
9d9f78ed MT	124	.get_parent = clk_mux_get_parent,
9d9f78ed MT	125	.set_parent = clk_mux_set_parent,
4ad69b80	126	.determine_rate = clk_mux_determine_rate,
9d9f78ed MT	127	};
	128	EXPORT_SYMBOL_GPL(clk_mux_ops);
	129
c57acd14 TF	130	const struct clk_ops clk_mux_ro_ops = {
	131	.get_parent = clk_mux_get_parent,
	132	};
	133	EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
	134
264b3171	135	struct clk_hw clk_hw_register_mux_table(struct device dev, const char *name,
2893c379 SH	136	const char * const *parent_names, u8 num_parents,
2893c379 SH	137	unsigned long flags,
ce4f3313 PDS	138	void __iomem *reg, u8 shift, u32 mask,
ce4f3313 PDS	139	u8 clk_mux_flags, u32 table, spinlock_t lock)
9d9f78ed MT	140	{
9d9f78ed MT	141	struct clk_mux *mux;
264b3171	142	struct clk_hw *hw;
0197b3ea	143	struct clk_init_data init;
ba492e90	144	u8 width = 0;
264b3171	145	int ret;
ba492e90 HZ	146
	147	if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
	148	width = fls(mask) - ffs(mask) + 1;
	149	if (width + shift > 16) {
	150	pr_err("mux value exceeds LOWORD field\n");
	151	return ERR_PTR(-EINVAL);
	152	}
	153	}
9d9f78ed	154
27d54591	155	/* allocate the mux */
1e28733e	156	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
0b910402	157	if (!mux)
9d9f78ed	158	return ERR_PTR(-ENOMEM);
9d9f78ed	159
0197b3ea	160	init.name = name;
c57acd14 TF	161	if (clk_mux_flags & CLK_MUX_READ_ONLY)
	162	init.ops = &clk_mux_ro_ops;
	163	else
	164	init.ops = &clk_mux_ops;
f7d8caad	165	init.flags = flags \| CLK_IS_BASIC;
0197b3ea SK	166	init.parent_names = parent_names;
	167	init.num_parents = num_parents;
	168
9d9f78ed MT	169	/* struct clk_mux assignments */
	170	mux->reg = reg;
	171	mux->shift = shift;
ce4f3313	172	mux->mask = mask;
9d9f78ed MT	173	mux->flags = clk_mux_flags;
9d9f78ed MT	174	mux->lock = lock;
ce4f3313	175	mux->table = table;
31df9db9	176	mux->hw.init = &init;
9d9f78ed	177
264b3171 SB	178	hw = &mux->hw;
	179	ret = clk_hw_register(dev, hw);
	180	if (ret) {
27d54591	181	kfree(mux);
264b3171 SB	182	hw = ERR_PTR(ret);
264b3171 SB	183	}
27d54591	184
264b3171 SB	185	return hw;
	186	}
	187	EXPORT_SYMBOL_GPL(clk_hw_register_mux_table);
	188
	189	struct clk clk_register_mux_table(struct device dev, const char *name,
	190	const char * const *parent_names, u8 num_parents,
	191	unsigned long flags,
	192	void __iomem *reg, u8 shift, u32 mask,
	193	u8 clk_mux_flags, u32 table, spinlock_t lock)
	194	{
	195	struct clk_hw *hw;
	196
	197	hw = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
	198	flags, reg, shift, mask, clk_mux_flags,
	199	table, lock);
	200	if (IS_ERR(hw))
	201	return ERR_CAST(hw);
	202	return hw->clk;
9d9f78ed	203	}
5cfe10bb	204	EXPORT_SYMBOL_GPL(clk_register_mux_table);
ce4f3313 PDS	205
ce4f3313 PDS	206	struct clk clk_register_mux(struct device dev, const char *name,
2893c379 SH	207	const char * const *parent_names, u8 num_parents,
2893c379 SH	208	unsigned long flags,
ce4f3313 PDS	209	void __iomem *reg, u8 shift, u8 width,
	210	u8 clk_mux_flags, spinlock_t *lock)
	211	{
	212	u32 mask = BIT(width) - 1;
	213
	214	return clk_register_mux_table(dev, name, parent_names, num_parents,
	215	flags, reg, shift, mask, clk_mux_flags,
	216	NULL, lock);
	217	}
5cfe10bb	218	EXPORT_SYMBOL_GPL(clk_register_mux);
4e3c021f	219
264b3171 SB	220	struct clk_hw clk_hw_register_mux(struct device dev, const char *name,
	221	const char * const *parent_names, u8 num_parents,
	222	unsigned long flags,
	223	void __iomem *reg, u8 shift, u8 width,
	224	u8 clk_mux_flags, spinlock_t *lock)
	225	{
	226	u32 mask = BIT(width) - 1;
	227
	228	return clk_hw_register_mux_table(dev, name, parent_names, num_parents,
	229	flags, reg, shift, mask, clk_mux_flags,
	230	NULL, lock);
	231	}
	232	EXPORT_SYMBOL_GPL(clk_hw_register_mux);
	233
4e3c021f KK	234	void clk_unregister_mux(struct clk *clk)
	235	{
	236	struct clk_mux *mux;
	237	struct clk_hw *hw;
	238
	239	hw = __clk_get_hw(clk);
	240	if (!hw)
	241	return;
	242
	243	mux = to_clk_mux(hw);
	244
	245	clk_unregister(clk);
	246	kfree(mux);
	247	}
	248	EXPORT_SYMBOL_GPL(clk_unregister_mux);
264b3171 SB	249
	250	void clk_hw_unregister_mux(struct clk_hw *hw)
	251	{
	252	struct clk_mux *mux;
	253
	254	mux = to_clk_mux(hw);
	255
	256	clk_hw_unregister(hw);
	257	kfree(mux);
	258	}
	259	EXPORT_SYMBOL_GPL(clk_hw_unregister_mux);