[linux.git] / arch / mips / mti-malta / malta-pci.c

/*
 * Copyright (C) 1999, 2000, 2004, 2005	 MIPS Technologies, Inc.
 *	All rights reserved.
 *	Authors: Carsten Langgaard <[email protected]>
 *		 Maciej W. Rozycki <[email protected]>
 *
 * Copyright (C) 2004 by Ralf Baechle ([email protected])
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * MIPS boards specific PCI support.
 */
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>

#include <asm/gt64120.h>
#include <asm/gcmpregs.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/bonito64.h>
#include <asm/mips-boards/msc01_pci.h>

static struct resource bonito64_mem_resource = {
	.name	= "Bonito PCI MEM",
	.flags	= IORESOURCE_MEM,
};

static struct resource bonito64_io_resource = {
	.name	= "Bonito PCI I/O",
	.start	= 0x00000000UL,
	.end	= 0x000fffffUL,
	.flags	= IORESOURCE_IO,
};

static struct resource gt64120_mem_resource = {
	.name	= "GT-64120 PCI MEM",
	.flags	= IORESOURCE_MEM,
};

static struct resource gt64120_io_resource = {
	.name	= "GT-64120 PCI I/O",
	.flags	= IORESOURCE_IO,
};

static struct resource msc_mem_resource = {
	.name	= "MSC PCI MEM",
	.flags	= IORESOURCE_MEM,
};

static struct resource msc_io_resource = {
	.name	= "MSC PCI I/O",
	.flags	= IORESOURCE_IO,
};

extern struct pci_ops bonito64_pci_ops;
extern struct pci_ops gt64xxx_pci0_ops;
extern struct pci_ops msc_pci_ops;

static struct pci_controller bonito64_controller = {
	.pci_ops	= &bonito64_pci_ops,
	.io_resource	= &bonito64_io_resource,
	.mem_resource	= &bonito64_mem_resource,
	.io_offset	= 0x00000000UL,
};

static struct pci_controller gt64120_controller = {
	.pci_ops	= &gt64xxx_pci0_ops,
	.io_resource	= &gt64120_io_resource,
	.mem_resource	= &gt64120_mem_resource,
};

static struct pci_controller msc_controller = {
	.pci_ops	= &msc_pci_ops,
	.io_resource	= &msc_io_resource,
	.mem_resource	= &msc_mem_resource,
};

void __init mips_pcibios_init(void)
{
	struct pci_controller *controller;
	resource_size_t start, end, map, start1, end1, map1, map2, map3, mask;

	switch (mips_revision_sconid) {
	case MIPS_REVISION_SCON_GT64120:
		/*
		 * Due to a bug in the Galileo system controller, we need
		 * to setup the PCI BAR for the Galileo internal registers.
		 * This should be done in the bios/bootprom and will be
		 * fixed in a later revision of YAMON (the MIPS boards
		 * boot prom).
		 */
		GT_WRITE(GT_PCI0_CFGADDR_OFS,
			 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */
			 (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */
			 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/
			 ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/
			 GT_PCI0_CFGADDR_CONFIGEN_BIT);

		/* Perform the write */
		GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));

		/* Set up resource ranges from the controller's registers.  */
		start = GT_READ(GT_PCI0M0LD_OFS);
		end = GT_READ(GT_PCI0M0HD_OFS);
		map = GT_READ(GT_PCI0M0REMAP_OFS);
		end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
		start1 = GT_READ(GT_PCI0M1LD_OFS);
		end1 = GT_READ(GT_PCI0M1HD_OFS);
		map1 = GT_READ(GT_PCI0M1REMAP_OFS);
		end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK);
		/* Cannot support multiple windows, use the wider.  */
		if (end1 - start1 > end - start) {
			start = start1;
			end = end1;
			map = map1;
		}
		mask = ~(start ^ end);
		/* We don't support remapping with a discontiguous mask.  */
		BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
		       mask != ~((mask & -mask) - 1));
		gt64120_mem_resource.start = start;
		gt64120_mem_resource.end = end;
		gt64120_controller.mem_offset = (start & mask) - (map & mask);
		/* Addresses are 36-bit, so do shifts in the destinations.  */
		gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF;
		gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF;
		gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
		gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF;

		start = GT_READ(GT_PCI0IOLD_OFS);
		end = GT_READ(GT_PCI0IOHD_OFS);
		map = GT_READ(GT_PCI0IOREMAP_OFS);
		end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
		mask = ~(start ^ end);
		/* We don't support remapping with a discontiguous mask.  */
		BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
		       mask != ~((mask & -mask) - 1));
		gt64120_io_resource.start = map & mask;
		gt64120_io_resource.end = (map & mask) | ~mask;
		gt64120_controller.io_offset = 0;
		/* Addresses are 36-bit, so do shifts in the destinations.  */
		gt64120_io_resource.start <<= GT_PCI_DCRM_SHF;
		gt64120_io_resource.end <<= GT_PCI_DCRM_SHF;
		gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;

		controller = &gt64120_controller;
		break;

	case MIPS_REVISION_SCON_BONITO:
		/* Set up resource ranges from the controller's registers.  */
		map = BONITO_PCIMAP;
		map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >>
		       BONITO_PCIMAP_PCIMAP_LO0_SHIFT;
		map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >>
		       BONITO_PCIMAP_PCIMAP_LO1_SHIFT;
		map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >>
		       BONITO_PCIMAP_PCIMAP_LO2_SHIFT;
		/* Combine as many adjacent windows as possible.  */
		map = map1;
		start = BONITO_PCILO0_BASE;
		end = 1;
		if (map3 == map2 + 1) {
			map = map2;
			start = BONITO_PCILO1_BASE;
			end++;
		}
		if (map2 == map1 + 1) {
			map = map1;
			start = BONITO_PCILO0_BASE;
			end++;
		}
		bonito64_mem_resource.start = start;
		bonito64_mem_resource.end = start +
					    BONITO_PCIMAP_WINBASE(end) - 1;
		bonito64_controller.mem_offset = start -
						 BONITO_PCIMAP_WINBASE(map);

		controller = &bonito64_controller;
		break;

	case MIPS_REVISION_SCON_SOCIT:
	case MIPS_REVISION_SCON_ROCIT:
	case MIPS_REVISION_SCON_SOCITSC:
	case MIPS_REVISION_SCON_SOCITSCP:
		/* Set up resource ranges from the controller's registers.  */
		MSC_READ(MSC01_PCI_SC2PMBASL, start);
		MSC_READ(MSC01_PCI_SC2PMMSKL, mask);
		MSC_READ(MSC01_PCI_SC2PMMAPL, map);
		msc_mem_resource.start = start & mask;
		msc_mem_resource.end = (start & mask) | ~mask;
		msc_controller.mem_offset = (start & mask) - (map & mask);
#ifdef CONFIG_MIPS_CMP
		if (gcmp_niocu())
			gcmp_setregion(0, start, mask,
				GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
#endif
		MSC_READ(MSC01_PCI_SC2PIOBASL, start);
		MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
		MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
		msc_io_resource.start = map & mask;
		msc_io_resource.end = (map & mask) | ~mask;
		msc_controller.io_offset = 0;
		ioport_resource.end = ~mask;
#ifdef CONFIG_MIPS_CMP
		if (gcmp_niocu())
			gcmp_setregion(1, start, mask,
				GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
#endif
		/* If ranges overlap I/O takes precedence.  */
		start = start & mask;
		end = start | ~mask;
		if ((start >= msc_mem_resource.start &&
		     start <= msc_mem_resource.end) ||
		    (end >= msc_mem_resource.start &&
		     end <= msc_mem_resource.end)) {
			/* Use the larger space.  */
			start = max(start, msc_mem_resource.start);
			end = min(end, msc_mem_resource.end);
			if (start - msc_mem_resource.start >=
			    msc_mem_resource.end - end)
				msc_mem_resource.end = start - 1;
			else
				msc_mem_resource.start = end + 1;
		}

		controller = &msc_controller;
		break;
	default:
		return;
	}

	/* Change start address to avoid conflicts with ACPI and SMB devices */
	if (controller->io_resource->start < 0x00002000UL)
		controller->io_resource->start = 0x00002000UL;

	iomem_resource.end &= 0xfffffffffULL;			/* 64 GB */
	ioport_resource.end = controller->io_resource->end;

	controller->io_map_base = mips_io_port_base;

	register_pci_controller(controller);
}
Commit	Line	Data
1da177e4	1	/*
70342287	2	* Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
aa0980b8 MR	3	* All rights reserved.
	4	* Authors: Carsten Langgaard <[email protected]>
	5	* Maciej W. Rozycki <[email protected]>
1da177e4 LT	6	*
	7	* Copyright (C) 2004 by Ralf Baechle ([email protected])
	8	*
	9	* This program is free software; you can distribute it and/or modify it
	10	* under the terms of the GNU General Public License (Version 2) as
	11	* published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope it will be useful, but WITHOUT
	14	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	15	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	16	* for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License along
	19	* with this program; if not, write to the Free Software Foundation, Inc.,
	20	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	21	*
	22	* MIPS boards specific PCI support.
	23	*/
1da177e4 LT	24	#include <linux/types.h>
	25	#include <linux/pci.h>
	26	#include <linux/kernel.h>
	27	#include <linux/init.h>
	28
1da177e4	29	#include <asm/gt64120.h>
7098f748	30	#include <asm/gcmpregs.h>
aa0980b8	31	#include <asm/mips-boards/generic.h>
1da177e4 LT	32	#include <asm/mips-boards/bonito64.h>
1da177e4 LT	33	#include <asm/mips-boards/msc01_pci.h>
1da177e4 LT	34
	35	static struct resource bonito64_mem_resource = {
	36	.name = "Bonito PCI MEM",
1da177e4 LT	37	.flags = IORESOURCE_MEM,
	38	};
	39
	40	static struct resource bonito64_io_resource = {
aa0980b8 MR	41	.name = "Bonito PCI I/O",
aa0980b8 MR	42	.start = 0x00000000UL,
1da177e4 LT	43	.end = 0x000fffffUL,
	44	.flags = IORESOURCE_IO,
	45	};
	46
	47	static struct resource gt64120_mem_resource = {
aa0980b8	48	.name = "GT-64120 PCI MEM",
1da177e4 LT	49	.flags = IORESOURCE_MEM,
	50	};
	51
	52	static struct resource gt64120_io_resource = {
aa0980b8	53	.name = "GT-64120 PCI I/O",
1da177e4 LT	54	.flags = IORESOURCE_IO,
	55	};
	56
	57	static struct resource msc_mem_resource = {
	58	.name = "MSC PCI MEM",
1da177e4 LT	59	.flags = IORESOURCE_MEM,
	60	};
	61
	62	static struct resource msc_io_resource = {
aa0980b8	63	.name = "MSC PCI I/O",
1da177e4 LT	64	.flags = IORESOURCE_IO,
	65	};
	66
	67	extern struct pci_ops bonito64_pci_ops;
252161ec	68	extern struct pci_ops gt64xxx_pci0_ops;
1da177e4 LT	69	extern struct pci_ops msc_pci_ops;
	70
	71	static struct pci_controller bonito64_controller = {
	72	.pci_ops = &bonito64_pci_ops,
	73	.io_resource = &bonito64_io_resource,
	74	.mem_resource = &bonito64_mem_resource,
1da177e4 LT	75	.io_offset = 0x00000000UL,
	76	};
	77
	78	static struct pci_controller gt64120_controller = {
252161ec	79	.pci_ops = &gt64xxx_pci0_ops,
1da177e4 LT	80	.io_resource = &gt64120_io_resource,
1da177e4 LT	81	.mem_resource = &gt64120_mem_resource,
1da177e4 LT	82	};
1da177e4 LT	83
aa0980b8	84	static struct pci_controller msc_controller = {
1da177e4 LT	85	.pci_ops = &msc_pci_ops,
	86	.io_resource = &msc_io_resource,
	87	.mem_resource = &msc_mem_resource,
1da177e4 LT	88	};
1da177e4 LT	89
c83cfc9c	90	void __init mips_pcibios_init(void)
1da177e4 LT	91	{
1da177e4 LT	92	struct pci_controller *controller;
67cac1eb	93	resource_size_t start, end, map, start1, end1, map1, map2, map3, mask;
1da177e4	94
b72c0526 CD	95	switch (mips_revision_sconid) {
b72c0526 CD	96	case MIPS_REVISION_SCON_GT64120:
1da177e4 LT	97	/*
	98	* Due to a bug in the Galileo system controller, we need
	99	* to setup the PCI BAR for the Galileo internal registers.
	100	* This should be done in the bios/bootprom and will be
	101	* fixed in a later revision of YAMON (the MIPS boards
	102	* boot prom).
	103	*/
	104	GT_WRITE(GT_PCI0_CFGADDR_OFS,
	105	(0 << GT_PCI0_CFGADDR_BUSNUM_SHF) \| /* Local bus */
	106	(0 << GT_PCI0_CFGADDR_DEVNUM_SHF) \| /* GT64120 dev */
	107	(0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) \| /* Function 0*/
	108	((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) \| /* BAR 4*/
aa0980b8	109	GT_PCI0_CFGADDR_CONFIGEN_BIT);
1da177e4 LT	110
	111	/* Perform the write */
	112	GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));
	113
aa0980b8 MR	114	/* Set up resource ranges from the controller's registers. */
	115	start = GT_READ(GT_PCI0M0LD_OFS);
	116	end = GT_READ(GT_PCI0M0HD_OFS);
	117	map = GT_READ(GT_PCI0M0REMAP_OFS);
	118	end = (end & GT_PCI_HD_MSK) \| (start & ~GT_PCI_HD_MSK);
	119	start1 = GT_READ(GT_PCI0M1LD_OFS);
	120	end1 = GT_READ(GT_PCI0M1HD_OFS);
	121	map1 = GT_READ(GT_PCI0M1REMAP_OFS);
	122	end1 = (end1 & GT_PCI_HD_MSK) \| (start1 & ~GT_PCI_HD_MSK);
	123	/* Cannot support multiple windows, use the wider. */
	124	if (end1 - start1 > end - start) {
	125	start = start1;
	126	end = end1;
	127	map = map1;
	128	}
	129	mask = ~(start ^ end);
70342287	130	/* We don't support remapping with a discontiguous mask. */
aa0980b8 MR	131	BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
	132	mask != ~((mask & -mask) - 1));
	133	gt64120_mem_resource.start = start;
	134	gt64120_mem_resource.end = end;
	135	gt64120_controller.mem_offset = (start & mask) - (map & mask);
	136	/* Addresses are 36-bit, so do shifts in the destinations. */
	137	gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF;
	138	gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF;
	139	gt64120_mem_resource.end \|= (1 << GT_PCI_DCRM_SHF) - 1;
	140	gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF;
	141
	142	start = GT_READ(GT_PCI0IOLD_OFS);
	143	end = GT_READ(GT_PCI0IOHD_OFS);
	144	map = GT_READ(GT_PCI0IOREMAP_OFS);
	145	end = (end & GT_PCI_HD_MSK) \| (start & ~GT_PCI_HD_MSK);
	146	mask = ~(start ^ end);
70342287	147	/* We don't support remapping with a discontiguous mask. */
aa0980b8 MR	148	BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
	149	mask != ~((mask & -mask) - 1));
	150	gt64120_io_resource.start = map & mask;
	151	gt64120_io_resource.end = (map & mask) \| ~mask;
	152	gt64120_controller.io_offset = 0;
	153	/* Addresses are 36-bit, so do shifts in the destinations. */
	154	gt64120_io_resource.start <<= GT_PCI_DCRM_SHF;
	155	gt64120_io_resource.end <<= GT_PCI_DCRM_SHF;
	156	gt64120_io_resource.end \|= (1 << GT_PCI_DCRM_SHF) - 1;
	157
1da177e4 LT	158	controller = &gt64120_controller;
	159	break;
	160
b72c0526	161	case MIPS_REVISION_SCON_BONITO:
aa0980b8 MR	162	/* Set up resource ranges from the controller's registers. */
	163	map = BONITO_PCIMAP;
	164	map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >>
	165	BONITO_PCIMAP_PCIMAP_LO0_SHIFT;
	166	map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >>
	167	BONITO_PCIMAP_PCIMAP_LO1_SHIFT;
	168	map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >>
	169	BONITO_PCIMAP_PCIMAP_LO2_SHIFT;
	170	/* Combine as many adjacent windows as possible. */
	171	map = map1;
	172	start = BONITO_PCILO0_BASE;
	173	end = 1;
	174	if (map3 == map2 + 1) {
	175	map = map2;
	176	start = BONITO_PCILO1_BASE;
	177	end++;
	178	}
	179	if (map2 == map1 + 1) {
	180	map = map1;
	181	start = BONITO_PCILO0_BASE;
	182	end++;
	183	}
	184	bonito64_mem_resource.start = start;
	185	bonito64_mem_resource.end = start +
	186	BONITO_PCIMAP_WINBASE(end) - 1;
	187	bonito64_controller.mem_offset = start -
	188	BONITO_PCIMAP_WINBASE(map);
	189
1da177e4 LT	190	controller = &bonito64_controller;
	191	break;
	192
b72c0526 CD	193	case MIPS_REVISION_SCON_SOCIT:
	194	case MIPS_REVISION_SCON_ROCIT:
	195	case MIPS_REVISION_SCON_SOCITSC:
	196	case MIPS_REVISION_SCON_SOCITSCP:
aa0980b8 MR	197	/* Set up resource ranges from the controller's registers. */
	198	MSC_READ(MSC01_PCI_SC2PMBASL, start);
	199	MSC_READ(MSC01_PCI_SC2PMMSKL, mask);
	200	MSC_READ(MSC01_PCI_SC2PMMAPL, map);
	201	msc_mem_resource.start = start & mask;
	202	msc_mem_resource.end = (start & mask) \| ~mask;
	203	msc_controller.mem_offset = (start & mask) - (map & mask);
7098f748 CD	204	#ifdef CONFIG_MIPS_CMP
	205	if (gcmp_niocu())
	206	gcmp_setregion(0, start, mask,
	207	GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
	208	#endif
aa0980b8 MR	209	MSC_READ(MSC01_PCI_SC2PIOBASL, start);
	210	MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
	211	MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
	212	msc_io_resource.start = map & mask;
	213	msc_io_resource.end = (map & mask) \| ~mask;
	214	msc_controller.io_offset = 0;
	215	ioport_resource.end = ~mask;
7098f748 CD	216	#ifdef CONFIG_MIPS_CMP
	217	if (gcmp_niocu())
	218	gcmp_setregion(1, start, mask,
	219	GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
	220	#endif
aa0980b8 MR	221	/* If ranges overlap I/O takes precedence. */
	222	start = start & mask;
	223	end = start \| ~mask;
	224	if ((start >= msc_mem_resource.start &&
	225	start <= msc_mem_resource.end) \|\|
	226	(end >= msc_mem_resource.start &&
	227	end <= msc_mem_resource.end)) {
	228	/* Use the larger space. */
	229	start = max(start, msc_mem_resource.start);
	230	end = min(end, msc_mem_resource.end);
	231	if (start - msc_mem_resource.start >=
	232	msc_mem_resource.end - end)
	233	msc_mem_resource.end = start - 1;
	234	else
	235	msc_mem_resource.start = end + 1;
	236	}
	237
1da177e4 LT	238	controller = &msc_controller;
	239	break;
	240	default:
c83cfc9c	241	return;
1da177e4 LT	242	}
1da177e4 LT	243
c5de50da SH	244	/* Change start address to avoid conflicts with ACPI and SMB devices */
	245	if (controller->io_resource->start < 0x00002000UL)
	246	controller->io_resource->start = 0x00002000UL;
aa0980b8 MR	247
aa0980b8 MR	248	iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
1da177e4 LT	249	ioport_resource.end = controller->io_resource->end;
1da177e4 LT	250
8faf2e6c BH	251	controller->io_map_base = mips_io_port_base;
8faf2e6c BH	252
49a89efb	253	register_pci_controller(controller);
1da177e4	254	}