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Merge remote-tracking branch 'asoc/fix/adsp' into asoc-adsp
[linux.git] / sound / soc / codecs / wm_adsp.c
CommitLineData
2159ad93
MB		 1/*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/firmware.h>
18#include <linux/pm.h>
19#include <linux/pm_runtime.h>
20#include <linux/regmap.h>
973838a0 21#include <linux/regulator/consumer.h>
2159ad93
MB		 22#include <linux/slab.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/jack.h>
28#include <sound/initval.h>
29#include <sound/tlv.h>
30
31#include <linux/mfd/arizona/registers.h>
32
33#include "wm_adsp.h"
34
35#define adsp_crit(_dsp, fmt, ...) \
36 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
37#define adsp_err(_dsp, fmt, ...) \
38 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
39#define adsp_warn(_dsp, fmt, ...) \
40 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
41#define adsp_info(_dsp, fmt, ...) \
42 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
43#define adsp_dbg(_dsp, fmt, ...) \
44 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
45
46#define ADSP1_CONTROL_1 0x00
47#define ADSP1_CONTROL_2 0x02
48#define ADSP1_CONTROL_3 0x03
49#define ADSP1_CONTROL_4 0x04
50#define ADSP1_CONTROL_5 0x06
51#define ADSP1_CONTROL_6 0x07
52#define ADSP1_CONTROL_7 0x08
53#define ADSP1_CONTROL_8 0x09
54#define ADSP1_CONTROL_9 0x0A
55#define ADSP1_CONTROL_10 0x0B
56#define ADSP1_CONTROL_11 0x0C
57#define ADSP1_CONTROL_12 0x0D
58#define ADSP1_CONTROL_13 0x0F
59#define ADSP1_CONTROL_14 0x10
60#define ADSP1_CONTROL_15 0x11
61#define ADSP1_CONTROL_16 0x12
62#define ADSP1_CONTROL_17 0x13
63#define ADSP1_CONTROL_18 0x14
64#define ADSP1_CONTROL_19 0x16
65#define ADSP1_CONTROL_20 0x17
66#define ADSP1_CONTROL_21 0x18
67#define ADSP1_CONTROL_22 0x1A
68#define ADSP1_CONTROL_23 0x1B
69#define ADSP1_CONTROL_24 0x1C
70#define ADSP1_CONTROL_25 0x1E
71#define ADSP1_CONTROL_26 0x20
72#define ADSP1_CONTROL_27 0x21
73#define ADSP1_CONTROL_28 0x22
74#define ADSP1_CONTROL_29 0x23
75#define ADSP1_CONTROL_30 0x24
76#define ADSP1_CONTROL_31 0x26
77
78/*
79 * ADSP1 Control 19
80 */
81#define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
82#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
83#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
84
85
86/*
87 * ADSP1 Control 30
88 */
89#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
90#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
91#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
92#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
93#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
94#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
95#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
96#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
97#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
98#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
99#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
100#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
101#define ADSP1_START 0x0001 /* DSP1_START */
102#define ADSP1_START_MASK 0x0001 /* DSP1_START */
103#define ADSP1_START_SHIFT 0 /* DSP1_START */
104#define ADSP1_START_WIDTH 1 /* DSP1_START */
105
94e205bf
CR		 106/*
107 * ADSP1 Control 31
108 */
109#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
110#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
111#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
112
973838a0
MB		 113#define ADSP2_CONTROL 0
114#define ADSP2_CLOCKING 1
115#define ADSP2_STATUS1 4
2159ad93
MB		 116
117/*
118 * ADSP2 Control
119 */
120
121#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
122#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
123#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
124#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
125#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
126#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
127#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
128#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
129#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
130#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
131#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
132#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
133#define ADSP2_START 0x0001 /* DSP1_START */
134#define ADSP2_START_MASK 0x0001 /* DSP1_START */
135#define ADSP2_START_SHIFT 0 /* DSP1_START */
136#define ADSP2_START_WIDTH 1 /* DSP1_START */
137
973838a0
MB		 138/*
139 * ADSP2 clocking
140 */
141#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
142#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
143#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
144
2159ad93
MB		 145/*
146 * ADSP2 Status 1
147 */
148#define ADSP2_RAM_RDY 0x0001
149#define ADSP2_RAM_RDY_MASK 0x0001
150#define ADSP2_RAM_RDY_SHIFT 0
151#define ADSP2_RAM_RDY_WIDTH 1
152
1023dbd9
MB		 153#define WM_ADSP_NUM_FW 3
154
155static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
156 "MBC/VSS", "Tx", "Rx ANC"
157};
158
159static struct {
160 const char *file;
161} wm_adsp_fw[WM_ADSP_NUM_FW] = {
162 { .file = "mbc-vss" },
163 { .file = "tx" },
164 { .file = "rx-anc" },
165};
166
167static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
168 struct snd_ctl_elem_value *ucontrol)
169{
170 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
171 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
172 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
173
174 ucontrol->value.integer.value[0] = adsp[e->shift_l].fw;
175
176 return 0;
177}
178
179static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
180 struct snd_ctl_elem_value *ucontrol)
181{
182 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
183 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
184 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
185
186 if (ucontrol->value.integer.value[0] == adsp[e->shift_l].fw)
187 return 0;
188
189 if (ucontrol->value.integer.value[0] >= WM_ADSP_NUM_FW)
190 return -EINVAL;
191
192 if (adsp[e->shift_l].running)
193 return -EBUSY;
194
195 adsp->fw = ucontrol->value.integer.value[0];
196
197 return 0;
198}
199
200static const struct soc_enum wm_adsp_fw_enum[] = {
201 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
202 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
203 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
204 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
205};
206
207const struct snd_kcontrol_new wm_adsp_fw_controls[] = {
208 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
209 wm_adsp_fw_get, wm_adsp_fw_put),
210 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
211 wm_adsp_fw_get, wm_adsp_fw_put),
212 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
213 wm_adsp_fw_get, wm_adsp_fw_put),
214 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
215 wm_adsp_fw_get, wm_adsp_fw_put),
216};
217EXPORT_SYMBOL_GPL(wm_adsp_fw_controls);
2159ad93
MB		 218
219static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
220 int type)
221{
222 int i;
223
224 for (i = 0; i < dsp->num_mems; i++)
225 if (dsp->mem[i].type == type)
226 return &dsp->mem[i];
227
228 return NULL;
229}
230
45b9ee72
MB		 231static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *region,
232 unsigned int offset)
233{
234 switch (region->type) {
235 case WMFW_ADSP1_PM:
236 return region->base + (offset * 3);
237 case WMFW_ADSP1_DM:
238 return region->base + (offset * 2);
239 case WMFW_ADSP2_XM:
240 return region->base + (offset * 2);
241 case WMFW_ADSP2_YM:
242 return region->base + (offset * 2);
243 case WMFW_ADSP1_ZM:
244 return region->base + (offset * 2);
245 default:
246 WARN_ON(NULL != "Unknown memory region type");
247 return offset;
248 }
249}
250
2159ad93
MB		 251static int wm_adsp_load(struct wm_adsp *dsp)
252{
253 const struct firmware *firmware;
254 struct regmap *regmap = dsp->regmap;
255 unsigned int pos = 0;
256 const struct wmfw_header *header;
257 const struct wmfw_adsp1_sizes *adsp1_sizes;
258 const struct wmfw_adsp2_sizes *adsp2_sizes;
259 const struct wmfw_footer *footer;
260 const struct wmfw_region *region;
261 const struct wm_adsp_region *mem;
262 const char *region_name;
263 char *file, *text;
a76fefab 264 void *buf;
2159ad93
MB		 265 unsigned int reg;
266 int regions = 0;
267 int ret, offset, type, sizes;
268
269 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
270 if (file == NULL)
271 return -ENOMEM;
272
1023dbd9
MB		 273 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
274 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 275 file[PAGE_SIZE - 1] = '\0';
276
277 ret = request_firmware(&firmware, file, dsp->dev);
278 if (ret != 0) {
279 adsp_err(dsp, "Failed to request '%s'\n", file);
280 goto out;
281 }
282 ret = -EINVAL;
283
284 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
285 if (pos >= firmware->size) {
286 adsp_err(dsp, "%s: file too short, %zu bytes\n",
287 file, firmware->size);
288 goto out_fw;
289 }
290
291 header = (void*)&firmware->data[0];
292
293 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
294 adsp_err(dsp, "%s: invalid magic\n", file);
295 goto out_fw;
296 }
297
298 if (header->ver != 0) {
299 adsp_err(dsp, "%s: unknown file format %d\n",
300 file, header->ver);
301 goto out_fw;
302 }
303
304 if (header->core != dsp->type) {
305 adsp_err(dsp, "%s: invalid core %d != %d\n",
306 file, header->core, dsp->type);
307 goto out_fw;
308 }
309
310 switch (dsp->type) {
311 case WMFW_ADSP1:
312 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
313 adsp1_sizes = (void *)&(header[1]);
314 footer = (void *)&(adsp1_sizes[1]);
315 sizes = sizeof(*adsp1_sizes);
316
317 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
318 file, le32_to_cpu(adsp1_sizes->dm),
319 le32_to_cpu(adsp1_sizes->pm),
320 le32_to_cpu(adsp1_sizes->zm));
321 break;
322
323 case WMFW_ADSP2:
324 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
325 adsp2_sizes = (void *)&(header[1]);
326 footer = (void *)&(adsp2_sizes[1]);
327 sizes = sizeof(*adsp2_sizes);
328
329 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
330 file, le32_to_cpu(adsp2_sizes->xm),
331 le32_to_cpu(adsp2_sizes->ym),
332 le32_to_cpu(adsp2_sizes->pm),
333 le32_to_cpu(adsp2_sizes->zm));
334 break;
335
336 default:
337 BUG_ON(NULL == "Unknown DSP type");
338 goto out_fw;
339 }
340
341 if (le32_to_cpu(header->len) != sizeof(*header) +
342 sizes + sizeof(*footer)) {
343 adsp_err(dsp, "%s: unexpected header length %d\n",
344 file, le32_to_cpu(header->len));
345 goto out_fw;
346 }
347
348 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
349 le64_to_cpu(footer->timestamp));
350
351 while (pos < firmware->size &&
352 pos - firmware->size > sizeof(*region)) {
353 region = (void *)&(firmware->data[pos]);
354 region_name = "Unknown";
355 reg = 0;
356 text = NULL;
357 offset = le32_to_cpu(region->offset) & 0xffffff;
358 type = be32_to_cpu(region->type) & 0xff;
359 mem = wm_adsp_find_region(dsp, type);
360
361 switch (type) {
362 case WMFW_NAME_TEXT:
363 region_name = "Firmware name";
364 text = kzalloc(le32_to_cpu(region->len) + 1,
365 GFP_KERNEL);
366 break;
367 case WMFW_INFO_TEXT:
368 region_name = "Information";
369 text = kzalloc(le32_to_cpu(region->len) + 1,
370 GFP_KERNEL);
371 break;
372 case WMFW_ABSOLUTE:
373 region_name = "Absolute";
374 reg = offset;
375 break;
376 case WMFW_ADSP1_PM:
377 BUG_ON(!mem);
378 region_name = "PM";
45b9ee72 379 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 380 break;
381 case WMFW_ADSP1_DM:
382 BUG_ON(!mem);
383 region_name = "DM";
45b9ee72 384 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 385 break;
386 case WMFW_ADSP2_XM:
387 BUG_ON(!mem);
388 region_name = "XM";
45b9ee72 389 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 390 break;
391 case WMFW_ADSP2_YM:
392 BUG_ON(!mem);
393 region_name = "YM";
45b9ee72 394 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 395 break;
396 case WMFW_ADSP1_ZM:
397 BUG_ON(!mem);
398 region_name = "ZM";
45b9ee72 399 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 400 break;
401 default:
402 adsp_warn(dsp,
403 "%s.%d: Unknown region type %x at %d(%x)\n",
404 file, regions, type, pos, pos);
405 break;
406 }
407
408 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
409 regions, le32_to_cpu(region->len), offset,
410 region_name);
411
412 if (text) {
413 memcpy(text, region->data, le32_to_cpu(region->len));
414 adsp_info(dsp, "%s: %s\n", file, text);
415 kfree(text);
416 }
417
418 if (reg) {
a76fefab 419 buf = kmemdup(region->data, le32_to_cpu(region->len),
7881fd0f 420 GFP_KERNEL | GFP_DMA);
a76fefab
MB		 421 if (!buf) {
422 adsp_err(dsp, "Out of memory\n");
423 return -ENOMEM;
424 }
425
426 ret = regmap_raw_write(regmap, reg, buf,
2159ad93 427 le32_to_cpu(region->len));
a76fefab
MB		 428
429 kfree(buf);
430
2159ad93
MB		 431 if (ret != 0) {
432 adsp_err(dsp,
433 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
434 file, regions,
435 le32_to_cpu(region->len), offset,
436 region_name, ret);
437 goto out_fw;
438 }
439 }
440
441 pos += le32_to_cpu(region->len) + sizeof(*region);
442 regions++;
443 }
444
445 if (pos > firmware->size)
446 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
447 file, regions, pos - firmware->size);
448
449out_fw:
450 release_firmware(firmware);
451out:
452 kfree(file);
453
454 return ret;
455}
456
db40517c
MB		 457static int wm_adsp_setup_algs(struct wm_adsp *dsp)
458{
459 struct regmap *regmap = dsp->regmap;
460 struct wmfw_adsp1_id_hdr adsp1_id;
461 struct wmfw_adsp2_id_hdr adsp2_id;
462 struct wmfw_adsp1_alg_hdr *adsp1_alg;
463 struct wmfw_adsp2_alg_hdr *adsp2_alg;
d62f4bc6 464 void *alg, *buf;
471f4885 465 struct wm_adsp_alg_region *region;
db40517c
MB		 466 const struct wm_adsp_region *mem;
467 unsigned int pos, term;
d62f4bc6 468 size_t algs, buf_size;
db40517c
MB		 469 __be32 val;
470 int i, ret;
471
472 switch (dsp->type) {
473 case WMFW_ADSP1:
474 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
475 break;
476 case WMFW_ADSP2:
477 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
478 break;
479 default:
480 mem = NULL;
481 break;
482 }
483
484 if (mem == NULL) {
485 BUG_ON(mem != NULL);
486 return -EINVAL;
487 }
488
489 switch (dsp->type) {
490 case WMFW_ADSP1:
491 ret = regmap_raw_read(regmap, mem->base, &adsp1_id,
492 sizeof(adsp1_id));
493 if (ret != 0) {
494 adsp_err(dsp, "Failed to read algorithm info: %d\n",
495 ret);
496 return ret;
497 }
498
d62f4bc6
MB		 499 buf = &adsp1_id;
500 buf_size = sizeof(adsp1_id);
501
db40517c
MB		 502 algs = be32_to_cpu(adsp1_id.algs);
503 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
504 be32_to_cpu(adsp1_id.fw.id),
505 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
506 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
507 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
508 algs);
509
510 pos = sizeof(adsp1_id) / 2;
511 term = pos + ((sizeof(*adsp1_alg) * algs) / 2);
512 break;
513
514 case WMFW_ADSP2:
515 ret = regmap_raw_read(regmap, mem->base, &adsp2_id,
516 sizeof(adsp2_id));
517 if (ret != 0) {
518 adsp_err(dsp, "Failed to read algorithm info: %d\n",
519 ret);
520 return ret;
521 }
522
d62f4bc6
MB		 523 buf = &adsp2_id;
524 buf_size = sizeof(adsp2_id);
525
db40517c
MB		 526 algs = be32_to_cpu(adsp2_id.algs);
527 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
528 be32_to_cpu(adsp2_id.fw.id),
529 (be32_to_cpu(adsp2_id.fw.ver) & 0xff0000) >> 16,
530 (be32_to_cpu(adsp2_id.fw.ver) & 0xff00) >> 8,
531 be32_to_cpu(adsp2_id.fw.ver) & 0xff,
532 algs);
533
534 pos = sizeof(adsp2_id) / 2;
535 term = pos + ((sizeof(*adsp2_alg) * algs) / 2);
536 break;
537
538 default:
539 BUG_ON(NULL == "Unknown DSP type");
540 return -EINVAL;
541 }
542
543 if (algs == 0) {
544 adsp_err(dsp, "No algorithms\n");
545 return -EINVAL;
546 }
547
d62f4bc6
MB		 548 if (algs > 1024) {
549 adsp_err(dsp, "Algorithm count %zx excessive\n", algs);
550 print_hex_dump_bytes(dev_name(dsp->dev), DUMP_PREFIX_OFFSET,
551 buf, buf_size);
552 return -EINVAL;
553 }
554
db40517c
MB		 555 /* Read the terminator first to validate the length */
556 ret = regmap_raw_read(regmap, mem->base + term, &val, sizeof(val));
557 if (ret != 0) {
558 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
559 ret);
560 return ret;
561 }
562
563 if (be32_to_cpu(val) != 0xbedead)
564 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
565 term, be32_to_cpu(val));
566
f2a93e2a 567 alg = kzalloc((term - pos) * 2, GFP_KERNEL | GFP_DMA);
db40517c
MB		 568 if (!alg)
569 return -ENOMEM;
570
571 ret = regmap_raw_read(regmap, mem->base + pos, alg, (term - pos) * 2);
572 if (ret != 0) {
573 adsp_err(dsp, "Failed to read algorithm list: %d\n",
574 ret);
575 goto out;
576 }
577
578 adsp1_alg = alg;
579 adsp2_alg = alg;
580
581 for (i = 0; i < algs; i++) {
582 switch (dsp->type) {
583 case WMFW_ADSP1:
471f4885 584 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
db40517c
MB		 585 i, be32_to_cpu(adsp1_alg[i].alg.id),
586 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
587 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
471f4885
MB		 588 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
589 be32_to_cpu(adsp1_alg[i].dm),
590 be32_to_cpu(adsp1_alg[i].zm));
591
592 if (adsp1_alg[i].dm) {
593 region = kzalloc(sizeof(*region), GFP_KERNEL);
594 if (!region)
595 return -ENOMEM;
596 region->type = WMFW_ADSP1_DM;
597 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
598 region->base = be32_to_cpu(adsp1_alg[i].dm);
599 list_add_tail(&region->list,
600 &dsp->alg_regions);
601 }
602
603 if (adsp1_alg[i].zm) {
604 region = kzalloc(sizeof(*region), GFP_KERNEL);
605 if (!region)
606 return -ENOMEM;
607 region->type = WMFW_ADSP1_ZM;
608 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
609 region->base = be32_to_cpu(adsp1_alg[i].zm);
610 list_add_tail(&region->list,
611 &dsp->alg_regions);
612 }
db40517c
MB		 613 break;
614
615 case WMFW_ADSP2:
471f4885
MB		 616 adsp_info(dsp,
617 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
db40517c
MB		 618 i, be32_to_cpu(adsp2_alg[i].alg.id),
619 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
620 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
471f4885
MB		 621 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
622 be32_to_cpu(adsp2_alg[i].xm),
623 be32_to_cpu(adsp2_alg[i].ym),
624 be32_to_cpu(adsp2_alg[i].zm));
625
626 if (adsp2_alg[i].xm) {
627 region = kzalloc(sizeof(*region), GFP_KERNEL);
628 if (!region)
629 return -ENOMEM;
630 region->type = WMFW_ADSP2_XM;
631 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
632 region->base = be32_to_cpu(adsp2_alg[i].xm);
633 list_add_tail(&region->list,
634 &dsp->alg_regions);
635 }
636
637 if (adsp2_alg[i].ym) {
638 region = kzalloc(sizeof(*region), GFP_KERNEL);
639 if (!region)
640 return -ENOMEM;
641 region->type = WMFW_ADSP2_YM;
642 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
643 region->base = be32_to_cpu(adsp2_alg[i].ym);
644 list_add_tail(&region->list,
645 &dsp->alg_regions);
646 }
647
648 if (adsp2_alg[i].zm) {
649 region = kzalloc(sizeof(*region), GFP_KERNEL);
650 if (!region)
651 return -ENOMEM;
652 region->type = WMFW_ADSP2_ZM;
653 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
654 region->base = be32_to_cpu(adsp2_alg[i].zm);
655 list_add_tail(&region->list,
656 &dsp->alg_regions);
657 }
db40517c
MB		 658 break;
659 }
660 }
661
662out:
663 kfree(alg);
664 return ret;
665}
666
2159ad93
MB		 667static int wm_adsp_load_coeff(struct wm_adsp *dsp)
668{
669 struct regmap *regmap = dsp->regmap;
670 struct wmfw_coeff_hdr *hdr;
671 struct wmfw_coeff_item *blk;
672 const struct firmware *firmware;
471f4885
MB		 673 const struct wm_adsp_region *mem;
674 struct wm_adsp_alg_region *alg_region;
2159ad93
MB		 675 const char *region_name;
676 int ret, pos, blocks, type, offset, reg;
677 char *file;
a76fefab 678 void *buf;
2159ad93
MB		 679
680 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
681 if (file == NULL)
682 return -ENOMEM;
683
1023dbd9
MB		 684 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
685 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 686 file[PAGE_SIZE - 1] = '\0';
687
688 ret = request_firmware(&firmware, file, dsp->dev);
689 if (ret != 0) {
690 adsp_warn(dsp, "Failed to request '%s'\n", file);
691 ret = 0;
692 goto out;
693 }
694 ret = -EINVAL;
695
696 if (sizeof(*hdr) >= firmware->size) {
697 adsp_err(dsp, "%s: file too short, %zu bytes\n",
698 file, firmware->size);
699 goto out_fw;
700 }
701
702 hdr = (void*)&firmware->data[0];
703 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
704 adsp_err(dsp, "%s: invalid magic\n", file);
705 return -EINVAL;
706 }
707
c712326d
MB		 708 switch (be32_to_cpu(hdr->rev) & 0xff) {
709 case 1:
710 break;
711 default:
712 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
713 file, be32_to_cpu(hdr->rev) & 0xff);
714 ret = -EINVAL;
715 goto out_fw;
716 }
717
2159ad93
MB		 718 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
719 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
720 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
721 le32_to_cpu(hdr->ver) & 0xff);
722
723 pos = le32_to_cpu(hdr->len);
724
725 blocks = 0;
726 while (pos < firmware->size &&
727 pos - firmware->size > sizeof(*blk)) {
728 blk = (void*)(&firmware->data[pos]);
729
c712326d
MB		 730 type = le16_to_cpu(blk->type);
731 offset = le16_to_cpu(blk->offset);
2159ad93
MB		 732
733 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
734 file, blocks, le32_to_cpu(blk->id),
735 (le32_to_cpu(blk->ver) >> 16) & 0xff,
736 (le32_to_cpu(blk->ver) >> 8) & 0xff,
737 le32_to_cpu(blk->ver) & 0xff);
738 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
739 file, blocks, le32_to_cpu(blk->len), offset, type);
740
741 reg = 0;
742 region_name = "Unknown";
743 switch (type) {
c712326d
MB		 744 case (WMFW_NAME_TEXT << 8):
745 case (WMFW_INFO_TEXT << 8):
2159ad93 746 break;
c712326d 747 case (WMFW_ABSOLUTE << 8):
2159ad93
MB		 748 region_name = "register";
749 reg = offset;
750 break;
471f4885
MB		 751
752 case WMFW_ADSP1_DM:
753 case WMFW_ADSP1_ZM:
754 case WMFW_ADSP2_XM:
755 case WMFW_ADSP2_YM:
756 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
757 file, blocks, le32_to_cpu(blk->len),
758 type, le32_to_cpu(blk->id));
759
760 mem = wm_adsp_find_region(dsp, type);
761 if (!mem) {
762 adsp_err(dsp, "No base for region %x\n", type);
763 break;
764 }
765
766 reg = 0;
767 list_for_each_entry(alg_region,
768 &dsp->alg_regions, list) {
769 if (le32_to_cpu(blk->id) == alg_region->alg &&
770 type == alg_region->type) {
771 reg = alg_region->base + offset;
772 reg = wm_adsp_region_to_reg(mem,
773 reg);
774 }
775 }
776
777 if (reg == 0)
778 adsp_err(dsp, "No %x for algorithm %x\n",
779 type, le32_to_cpu(blk->id));
780 break;
781
2159ad93 782 default:
25c62f7e
MB		 783 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
784 file, blocks, type, pos);
2159ad93
MB		 785 break;
786 }
787
788 if (reg) {
a76fefab 789 buf = kmemdup(blk->data, le32_to_cpu(blk->len),
7881fd0f 790 GFP_KERNEL | GFP_DMA);
a76fefab
MB		 791 if (!buf) {
792 adsp_err(dsp, "Out of memory\n");
793 return -ENOMEM;
794 }
795
2159ad93
MB		 796 ret = regmap_raw_write(regmap, reg, blk->data,
797 le32_to_cpu(blk->len));
798 if (ret != 0) {
799 adsp_err(dsp,
800 "%s.%d: Failed to write to %x in %s\n",
801 file, blocks, reg, region_name);
802 }
a76fefab
MB		 803
804 kfree(buf);
2159ad93
MB		 805 }
806
807 pos += le32_to_cpu(blk->len) + sizeof(*blk);
808 blocks++;
809 }
810
811 if (pos > firmware->size)
812 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
813 file, blocks, pos - firmware->size);
814
815out_fw:
816 release_firmware(firmware);
817out:
818 kfree(file);
819 return 0;
820}
821
5e7a7a22
MB		 822int wm_adsp1_init(struct wm_adsp *adsp)
823{
824 INIT_LIST_HEAD(&adsp->alg_regions);
825
826 return 0;
827}
828EXPORT_SYMBOL_GPL(wm_adsp1_init);
829
2159ad93
MB		 830int wm_adsp1_event(struct snd_soc_dapm_widget *w,
831 struct snd_kcontrol *kcontrol,
832 int event)
833{
834 struct snd_soc_codec *codec = w->codec;
835 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
836 struct wm_adsp *dsp = &dsps[w->shift];
837 int ret;
94e205bf 838 int val;
2159ad93
MB		 839
840 switch (event) {
841 case SND_SOC_DAPM_POST_PMU:
842 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
843 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
844
94e205bf
CR		 845 /*
846 * For simplicity set the DSP clock rate to be the
847 * SYSCLK rate rather than making it configurable.
848 */
849 if(dsp->sysclk_reg) {
850 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
851 if (ret != 0) {
852 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
853 ret);
854 return ret;
855 }
856
857 val = (val & dsp->sysclk_mask)
858 >> dsp->sysclk_shift;
859
860 ret = regmap_update_bits(dsp->regmap,
861 dsp->base + ADSP1_CONTROL_31,
862 ADSP1_CLK_SEL_MASK, val);
863 if (ret != 0) {
864 adsp_err(dsp, "Failed to set clock rate: %d\n",
865 ret);
866 return ret;
867 }
868 }
869
2159ad93
MB		 870 ret = wm_adsp_load(dsp);
871 if (ret != 0)
872 goto err;
873
db40517c
MB		 874 ret = wm_adsp_setup_algs(dsp);
875 if (ret != 0)
876 goto err;
877
2159ad93
MB		 878 ret = wm_adsp_load_coeff(dsp);
879 if (ret != 0)
880 goto err;
881
882 /* Start the core running */
883 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
884 ADSP1_CORE_ENA | ADSP1_START,
885 ADSP1_CORE_ENA | ADSP1_START);
886 break;
887
888 case SND_SOC_DAPM_PRE_PMD:
889 /* Halt the core */
890 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
891 ADSP1_CORE_ENA | ADSP1_START, 0);
892
893 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
894 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
895
896 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
897 ADSP1_SYS_ENA, 0);
898 break;
899
900 default:
901 break;
902 }
903
904 return 0;
905
906err:
907 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
908 ADSP1_SYS_ENA, 0);
909 return ret;
910}
911EXPORT_SYMBOL_GPL(wm_adsp1_event);
912
913static int wm_adsp2_ena(struct wm_adsp *dsp)
914{
915 unsigned int val;
916 int ret, count;
917
918 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
919 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
920 if (ret != 0)
921 return ret;
922
923 /* Wait for the RAM to start, should be near instantaneous */
924 count = 0;
925 do {
926 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1,
927 &val);
928 if (ret != 0)
929 return ret;
930 } while (!(val & ADSP2_RAM_RDY) && ++count < 10);
931
932 if (!(val & ADSP2_RAM_RDY)) {
933 adsp_err(dsp, "Failed to start DSP RAM\n");
934 return -EBUSY;
935 }
936
937 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
938 adsp_info(dsp, "RAM ready after %d polls\n", count);
939
940 return 0;
941}
942
943int wm_adsp2_event(struct snd_soc_dapm_widget *w,
944 struct snd_kcontrol *kcontrol, int event)
945{
946 struct snd_soc_codec *codec = w->codec;
947 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
948 struct wm_adsp *dsp = &dsps[w->shift];
471f4885 949 struct wm_adsp_alg_region *alg_region;
973838a0 950 unsigned int val;
2159ad93
MB		 951 int ret;
952
953 switch (event) {
954 case SND_SOC_DAPM_POST_PMU:
dd49e2c8
MB		 955 /*
956 * For simplicity set the DSP clock rate to be the
957 * SYSCLK rate rather than making it configurable.
958 */
959 ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
960 if (ret != 0) {
961 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
962 ret);
963 return ret;
964 }
965 val = (val & ARIZONA_SYSCLK_FREQ_MASK)
966 >> ARIZONA_SYSCLK_FREQ_SHIFT;
967
968 ret = regmap_update_bits(dsp->regmap,
969 dsp->base + ADSP2_CLOCKING,
970 ADSP2_CLK_SEL_MASK, val);
971 if (ret != 0) {
972 adsp_err(dsp, "Failed to set clock rate: %d\n",
973 ret);
974 return ret;
975 }
976
973838a0
MB		 977 if (dsp->dvfs) {
978 ret = regmap_read(dsp->regmap,
979 dsp->base + ADSP2_CLOCKING, &val);
980 if (ret != 0) {
981 dev_err(dsp->dev,
982 "Failed to read clocking: %d\n", ret);
983 return ret;
984 }
985
25c6fdb0 986 if ((val & ADSP2_CLK_SEL_MASK) >= 3) {
973838a0
MB		 987 ret = regulator_enable(dsp->dvfs);
988 if (ret != 0) {
989 dev_err(dsp->dev,
990 "Failed to enable supply: %d\n",
991 ret);
992 return ret;
993 }
994
995 ret = regulator_set_voltage(dsp->dvfs,
996 1800000,
997 1800000);
998 if (ret != 0) {
999 dev_err(dsp->dev,
1000 "Failed to raise supply: %d\n",
1001 ret);
1002 return ret;
1003 }
1004 }
1005 }
1006
2159ad93
MB		 1007 ret = wm_adsp2_ena(dsp);
1008 if (ret != 0)
1009 return ret;
1010
1011 ret = wm_adsp_load(dsp);
1012 if (ret != 0)
1013 goto err;
1014
db40517c
MB		 1015 ret = wm_adsp_setup_algs(dsp);
1016 if (ret != 0)
1017 goto err;
1018
2159ad93
MB		 1019 ret = wm_adsp_load_coeff(dsp);
1020 if (ret != 0)
1021 goto err;
1022
1023 ret = regmap_update_bits(dsp->regmap,
1024 dsp->base + ADSP2_CONTROL,
a7f9be7e
MB		 1025 ADSP2_CORE_ENA | ADSP2_START,
1026 ADSP2_CORE_ENA | ADSP2_START);
2159ad93
MB		 1027 if (ret != 0)
1028 goto err;
1023dbd9
MB		 1029
1030 dsp->running = true;
2159ad93
MB		 1031 break;
1032
1033 case SND_SOC_DAPM_PRE_PMD:
1023dbd9
MB		 1034 dsp->running = false;
1035
2159ad93 1036 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e
MB		 1037 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
1038 ADSP2_START, 0);
973838a0
MB		 1039
1040 if (dsp->dvfs) {
1041 ret = regulator_set_voltage(dsp->dvfs, 1200000,
1042 1800000);
1043 if (ret != 0)
1044 dev_warn(dsp->dev,
1045 "Failed to lower supply: %d\n",
1046 ret);
1047
1048 ret = regulator_disable(dsp->dvfs);
1049 if (ret != 0)
1050 dev_err(dsp->dev,
1051 "Failed to enable supply: %d\n",
1052 ret);
1053 }
471f4885
MB		 1054
1055 while (!list_empty(&dsp->alg_regions)) {
1056 alg_region = list_first_entry(&dsp->alg_regions,
1057 struct wm_adsp_alg_region,
1058 list);
1059 list_del(&alg_region->list);
1060 kfree(alg_region);
1061 }
2159ad93
MB		 1062 break;
1063
1064 default:
1065 break;
1066 }
1067
1068 return 0;
1069err:
1070 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e 1071 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2159ad93
MB		 1072 return ret;
1073}
1074EXPORT_SYMBOL_GPL(wm_adsp2_event);
973838a0
MB		 1075
1076int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs)
1077{
1078 int ret;
1079
10a2b662
MB		 1080 /*
1081 * Disable the DSP memory by default when in reset for a small
1082 * power saving.
1083 */
1084 ret = regmap_update_bits(adsp->regmap, adsp->base + ADSP2_CONTROL,
1085 ADSP2_MEM_ENA, 0);
1086 if (ret != 0) {
1087 adsp_err(adsp, "Failed to clear memory retention: %d\n", ret);
1088 return ret;
1089 }
1090
471f4885
MB		 1091 INIT_LIST_HEAD(&adsp->alg_regions);
1092
973838a0
MB		 1093 if (dvfs) {
1094 adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD");
1095 if (IS_ERR(adsp->dvfs)) {
1096 ret = PTR_ERR(adsp->dvfs);
1097 dev_err(adsp->dev, "Failed to get DCVDD: %d\n", ret);
1098 return ret;
1099 }
1100
1101 ret = regulator_enable(adsp->dvfs);
1102 if (ret != 0) {
1103 dev_err(adsp->dev, "Failed to enable DCVDD: %d\n",
1104 ret);
1105 return ret;
1106 }
1107
1108 ret = regulator_set_voltage(adsp->dvfs, 1200000, 1800000);
1109 if (ret != 0) {
1110 dev_err(adsp->dev, "Failed to initialise DVFS: %d\n",
1111 ret);
1112 return ret;
1113 }
1114
1115 ret = regulator_disable(adsp->dvfs);
1116 if (ret != 0) {
1117 dev_err(adsp->dev, "Failed to disable DCVDD: %d\n",
1118 ret);
1119 return ret;
1120 }
1121 }
1122
1123 return 0;
1124}
1125EXPORT_SYMBOL_GPL(wm_adsp2_init);
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