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drm/amdgpu/soc15: add support for vega12
[linux.git] / drivers / gpu / drm / amd / amdgpu / soc15.c
CommitLineData
220ab9bd
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
248a1d6f 26#include <drm/drmP.h>
220ab9bd 27#include "amdgpu.h"
d05da0e2 28#include "amdgpu_atombios.h"
220ab9bd
KW		 29#include "amdgpu_ih.h"
30#include "amdgpu_uvd.h"
31#include "amdgpu_vce.h"
32#include "amdgpu_ucode.h"
33#include "amdgpu_psp.h"
34#include "atom.h"
35#include "amd_pcie.h"
36
5d735f83 37#include "uvd/uvd_7_0_offset.h"
cde5c34f
FX		 38#include "gc/gc_9_0_offset.h"
39#include "gc/gc_9_0_sh_mask.h"
812f77b7
FX		 40#include "sdma0/sdma0_4_0_offset.h"
41#include "sdma1/sdma1_4_0_offset.h"
75199b8c
FX		 42#include "hdp/hdp_4_0_offset.h"
43#include "hdp/hdp_4_0_sh_mask.h"
a6651c98
FX		 44#include "mp/mp_9_0_offset.h"
45#include "mp/mp_9_0_sh_mask.h"
424d9bb4
FX		 46#include "smuio/smuio_9_0_offset.h"
47#include "smuio/smuio_9_0_sh_mask.h"
220ab9bd
KW		 48
49#include "soc15.h"
50#include "soc15_common.h"
51#include "gfx_v9_0.h"
52#include "gmc_v9_0.h"
53#include "gfxhub_v1_0.h"
54#include "mmhub_v1_0.h"
55#include "vega10_ih.h"
56#include "sdma_v4_0.h"
57#include "uvd_v7_0.h"
58#include "vce_v4_0.h"
f2d7e707 59#include "vcn_v1_0.h"
796b6568 60#include "dce_virtual.h"
f1a34465 61#include "mxgpu_ai.h"
220ab9bd 62
220ab9bd
KW		 63#define mmFabricConfigAccessControl 0x0410
64#define mmFabricConfigAccessControl_BASE_IDX 0
65#define mmFabricConfigAccessControl_DEFAULT 0x00000000
66//FabricConfigAccessControl
67#define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT 0x0
68#define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT 0x1
69#define FabricConfigAccessControl__CfgRegInstID__SHIFT 0x10
70#define FabricConfigAccessControl__CfgRegInstAccEn_MASK 0x00000001L
71#define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK 0x00000002L
72#define FabricConfigAccessControl__CfgRegInstID_MASK 0x00FF0000L
73
74
75#define mmDF_PIE_AON0_DfGlobalClkGater 0x00fc
76#define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX 0
77//DF_PIE_AON0_DfGlobalClkGater
78#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT 0x0
79#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK 0x0000000FL
80
81enum {
82 DF_MGCG_DISABLE = 0,
83 DF_MGCG_ENABLE_00_CYCLE_DELAY =1,
84 DF_MGCG_ENABLE_01_CYCLE_DELAY =2,
85 DF_MGCG_ENABLE_15_CYCLE_DELAY =13,
86 DF_MGCG_ENABLE_31_CYCLE_DELAY =14,
87 DF_MGCG_ENABLE_63_CYCLE_DELAY =15
88};
89
90#define mmMP0_MISC_CGTT_CTRL0 0x01b9
91#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
92#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
93#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
94
95/*
96 * Indirect registers accessor
97 */
98static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
99{
100 unsigned long flags, address, data;
101 u32 r;
946a4d5b
SL		 102 address = adev->nbio_funcs->get_pcie_index_offset(adev);
103 data = adev->nbio_funcs->get_pcie_data_offset(adev);
220ab9bd
KW		 104
105 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
106 WREG32(address, reg);
107 (void)RREG32(address);
108 r = RREG32(data);
109 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
110 return r;
111}
112
113static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
114{
115 unsigned long flags, address, data;
220ab9bd 116
946a4d5b
SL		 117 address = adev->nbio_funcs->get_pcie_index_offset(adev);
118 data = adev->nbio_funcs->get_pcie_data_offset(adev);
220ab9bd
KW		 119
120 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
121 WREG32(address, reg);
122 (void)RREG32(address);
123 WREG32(data, v);
124 (void)RREG32(data);
125 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
126}
127
128static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
129{
130 unsigned long flags, address, data;
131 u32 r;
132
133 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
134 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
135
136 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
137 WREG32(address, ((reg) & 0x1ff));
138 r = RREG32(data);
139 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
140 return r;
141}
142
143static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
144{
145 unsigned long flags, address, data;
146
147 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
148 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
149
150 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
151 WREG32(address, ((reg) & 0x1ff));
152 WREG32(data, (v));
153 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
154}
155
156static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
157{
158 unsigned long flags, address, data;
159 u32 r;
160
161 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
162 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
163
164 spin_lock_irqsave(&adev->didt_idx_lock, flags);
165 WREG32(address, (reg));
166 r = RREG32(data);
167 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
168 return r;
169}
170
171static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
172{
173 unsigned long flags, address, data;
174
175 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
176 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
177
178 spin_lock_irqsave(&adev->didt_idx_lock, flags);
179 WREG32(address, (reg));
180 WREG32(data, (v));
181 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
182}
183
560460f2
EQ		 184static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
185{
186 unsigned long flags;
187 u32 r;
188
189 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
190 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
191 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
192 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
193 return r;
194}
195
196static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
197{
198 unsigned long flags;
199
200 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
201 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
202 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
203 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
204}
205
2f11fb02
EQ		 206static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
207{
208 unsigned long flags;
209 u32 r;
210
211 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
212 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
213 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
214 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
215 return r;
216}
217
218static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
219{
220 unsigned long flags;
221
222 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
223 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
224 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
225 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
226}
227
220ab9bd
KW		 228static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
229{
bf383fb6 230 return adev->nbio_funcs->get_memsize(adev);
220ab9bd
KW		 231}
232
220ab9bd
KW		 233static u32 soc15_get_xclk(struct amdgpu_device *adev)
234{
76d6172b 235 return adev->clock.spll.reference_freq;
220ab9bd
KW		 236}
237
238
239void soc15_grbm_select(struct amdgpu_device *adev,
240 u32 me, u32 pipe, u32 queue, u32 vmid)
241{
242 u32 grbm_gfx_cntl = 0;
243 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
244 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
245 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
246 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
247
248 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
249}
250
251static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
252{
253 /* todo */
254}
255
256static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
257{
258 /* todo */
259 return false;
260}
261
262static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
263 u8 *bios, u32 length_bytes)
264{
265 u32 *dw_ptr;
266 u32 i, length_dw;
267
268 if (bios == NULL)
269 return false;
270 if (length_bytes == 0)
271 return false;
272 /* APU vbios image is part of sbios image */
273 if (adev->flags & AMD_IS_APU)
274 return false;
275
276 dw_ptr = (u32 *)bios;
277 length_dw = ALIGN(length_bytes, 4) / 4;
278
279 /* set rom index to 0 */
280 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
281 /* read out the rom data */
282 for (i = 0; i < length_dw; i++)
283 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
284
285 return true;
286}
287
946a4d5b
SL		 288struct soc15_allowed_register_entry {
289 uint32_t hwip;
290 uint32_t inst;
291 uint32_t seg;
292 uint32_t reg_offset;
293 bool grbm_indexed;
294};
295
296
297static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
298 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
299 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
300 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
301 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
302 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
303 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
304 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
305 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
306 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
307 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
308 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
309 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
310 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
311 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
312 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
313 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
314 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
315 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
220ab9bd
KW		 316};
317
318static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
319 u32 sh_num, u32 reg_offset)
320{
321 uint32_t val;
322
323 mutex_lock(&adev->grbm_idx_mutex);
324 if (se_num != 0xffffffff || sh_num != 0xffffffff)
325 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
326
327 val = RREG32(reg_offset);
328
329 if (se_num != 0xffffffff || sh_num != 0xffffffff)
330 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
331 mutex_unlock(&adev->grbm_idx_mutex);
332 return val;
333}
334
c013cea2
AD		 335static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
336 bool indexed, u32 se_num,
337 u32 sh_num, u32 reg_offset)
338{
339 if (indexed) {
340 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
341 } else {
cd29253f 342 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
c013cea2 343 return adev->gfx.config.gb_addr_config;
cd29253f 344 return RREG32(reg_offset);
c013cea2
AD		 345 }
346}
347
220ab9bd
KW		 348static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
349 u32 sh_num, u32 reg_offset, u32 *value)
350{
3032f350 351 uint32_t i;
946a4d5b 352 struct soc15_allowed_register_entry *en;
220ab9bd
KW		 353
354 *value = 0;
220ab9bd 355 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
946a4d5b
SL		 356 en = &soc15_allowed_read_registers[i];
357 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
358 + en->reg_offset))
220ab9bd
KW		 359 continue;
360
97fcc76b
CK		 361 *value = soc15_get_register_value(adev,
362 soc15_allowed_read_registers[i].grbm_indexed,
363 se_num, sh_num, reg_offset);
220ab9bd
KW		 364 return 0;
365 }
366 return -EINVAL;
367}
368
946a4d5b
SL		 369
370/**
371 * soc15_program_register_sequence - program an array of registers.
372 *
373 * @adev: amdgpu_device pointer
374 * @regs: pointer to the register array
375 * @array_size: size of the register array
376 *
377 * Programs an array or registers with and and or masks.
378 * This is a helper for setting golden registers.
379 */
380
381void soc15_program_register_sequence(struct amdgpu_device *adev,
382 const struct soc15_reg_golden *regs,
383 const u32 array_size)
384{
385 const struct soc15_reg_golden *entry;
386 u32 tmp, reg;
387 int i;
388
389 for (i = 0; i < array_size; ++i) {
390 entry = &regs[i];
391 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
392
393 if (entry->and_mask == 0xffffffff) {
394 tmp = entry->or_mask;
395 } else {
396 tmp = RREG32(reg);
397 tmp &= ~(entry->and_mask);
398 tmp |= entry->or_mask;
399 }
400 WREG32(reg, tmp);
401 }
402
403}
404
405
98512bb8 406static int soc15_asic_reset(struct amdgpu_device *adev)
220ab9bd
KW		 407{
408 u32 i;
409
98512bb8
KW		 410 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
411
412 dev_info(adev->dev, "GPU reset\n");
220ab9bd
KW		 413
414 /* disable BM */
415 pci_clear_master(adev->pdev);
220ab9bd 416
98512bb8
KW		 417 pci_save_state(adev->pdev);
418
f75a9a5d 419 psp_gpu_reset(adev);
98512bb8
KW		 420
421 pci_restore_state(adev->pdev);
220ab9bd
KW		 422
423 /* wait for asic to come out of reset */
424 for (i = 0; i < adev->usec_timeout; i++) {
bf383fb6
AD		 425 u32 memsize = adev->nbio_funcs->get_memsize(adev);
426
aecbe64f 427 if (memsize != 0xffffffff)
220ab9bd
KW		 428 break;
429 udelay(1);
430 }
431
d05da0e2 432 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
220ab9bd
KW		 433
434 return 0;
435}
436
437/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
438 u32 cntl_reg, u32 status_reg)
439{
440 return 0;
441}*/
442
443static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
444{
445 /*int r;
446
447 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
448 if (r)
449 return r;
450
451 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
452 */
453 return 0;
454}
455
456static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
457{
458 /* todo */
459
460 return 0;
461}
462
463static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
464{
465 if (pci_is_root_bus(adev->pdev->bus))
466 return;
467
468 if (amdgpu_pcie_gen2 == 0)
469 return;
470
471 if (adev->flags & AMD_IS_APU)
472 return;
473
474 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
475 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
476 return;
477
478 /* todo */
479}
480
481static void soc15_program_aspm(struct amdgpu_device *adev)
482{
483
484 if (amdgpu_aspm == 0)
485 return;
486
487 /* todo */
488}
489
490static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
bf383fb6 491 bool enable)
220ab9bd 492{
bf383fb6
AD		 493 adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
494 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
220ab9bd
KW		 495}
496
497static const struct amdgpu_ip_block_version vega10_common_ip_block =
498{
499 .type = AMD_IP_BLOCK_TYPE_COMMON,
500 .major = 2,
501 .minor = 0,
502 .rev = 0,
503 .funcs = &soc15_common_ip_funcs,
504};
505
506int soc15_set_ip_blocks(struct amdgpu_device *adev)
507{
4522824c
SL		 508 /* Set IP register base before any HW register access */
509 switch (adev->asic_type) {
510 case CHIP_VEGA10:
511 case CHIP_RAVEN:
512 vega10_reg_base_init(adev);
513 break;
514 default:
515 return -EINVAL;
516 }
517
bf383fb6
AD		 518 if (adev->flags & AMD_IS_APU)
519 adev->nbio_funcs = &nbio_v7_0_funcs;
520 else
521 adev->nbio_funcs = &nbio_v6_1_funcs;
522
523 adev->nbio_funcs->detect_hw_virt(adev);
1b922423 524
f1a34465
XY		 525 if (amdgpu_sriov_vf(adev))
526 adev->virt.ops = &xgpu_ai_virt_ops;
527
220ab9bd
KW		 528 switch (adev->asic_type) {
529 case CHIP_VEGA10:
692069a1 530 case CHIP_VEGA12:
2990a1fc
AD		 531 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
532 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
533 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
3cdfe700 534 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
c6f3e7cb 535 if (!amdgpu_sriov_vf(adev))
b905090d 536 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
f8445307 537 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 538 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
ab587d4a
AD		 539#if defined(CONFIG_DRM_AMD_DC)
540 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 541 amdgpu_device_ip_block_add(adev, &dm_ip_block);
ab587d4a
AD		 542#else
543# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
544#endif
2990a1fc
AD		 545 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
546 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
547 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
548 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
220ab9bd 549 break;
1023b797 550 case CHIP_RAVEN:
2990a1fc
AD		 551 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
552 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
553 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
554 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
b905090d 555 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
d67fed16 556 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 557 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
0bf954c1
AD		 558#if defined(CONFIG_DRM_AMD_DC)
559 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 560 amdgpu_device_ip_block_add(adev, &dm_ip_block);
0bf954c1
AD		 561#else
562# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
563#endif
2990a1fc
AD		 564 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
565 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
566 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
1023b797 567 break;
220ab9bd
KW		 568 default:
569 return -EINVAL;
570 }
571
572 return 0;
573}
574
575static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
576{
bf383fb6 577 return adev->nbio_funcs->get_rev_id(adev);
220ab9bd
KW		 578}
579
69882565 580static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
73c73240 581{
69882565 582 adev->nbio_funcs->hdp_flush(adev, ring);
73c73240
AD		 583}
584
69882565
CK		 585static void soc15_invalidate_hdp(struct amdgpu_device *adev,
586 struct amdgpu_ring *ring)
73c73240 587{
69882565
CK		 588 if (!ring || !ring->funcs->emit_wreg)
589 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
590 else
591 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
592 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
73c73240
AD		 593}
594
220ab9bd
KW		 595static const struct amdgpu_asic_funcs soc15_asic_funcs =
596{
597 .read_disabled_bios = &soc15_read_disabled_bios,
598 .read_bios_from_rom = &soc15_read_bios_from_rom,
599 .read_register = &soc15_read_register,
600 .reset = &soc15_asic_reset,
601 .set_vga_state = &soc15_vga_set_state,
602 .get_xclk = &soc15_get_xclk,
603 .set_uvd_clocks = &soc15_set_uvd_clocks,
604 .set_vce_clocks = &soc15_set_vce_clocks,
605 .get_config_memsize = &soc15_get_config_memsize,
73c73240
AD		 606 .flush_hdp = &soc15_flush_hdp,
607 .invalidate_hdp = &soc15_invalidate_hdp,
220ab9bd
KW		 608};
609
610static int soc15_common_early_init(void *handle)
611{
220ab9bd
KW		 612 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
613
614 adev->smc_rreg = NULL;
615 adev->smc_wreg = NULL;
616 adev->pcie_rreg = &soc15_pcie_rreg;
617 adev->pcie_wreg = &soc15_pcie_wreg;
618 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
619 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
620 adev->didt_rreg = &soc15_didt_rreg;
621 adev->didt_wreg = &soc15_didt_wreg;
560460f2
EQ		 622 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
623 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
2f11fb02
EQ		 624 adev->se_cac_rreg = &soc15_se_cac_rreg;
625 adev->se_cac_wreg = &soc15_se_cac_wreg;
220ab9bd
KW		 626
627 adev->asic_funcs = &soc15_asic_funcs;
628
220ab9bd
KW		 629 adev->rev_id = soc15_get_rev_id(adev);
630 adev->external_rev_id = 0xFF;
631 switch (adev->asic_type) {
632 case CHIP_VEGA10:
633 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
634 AMD_CG_SUPPORT_GFX_MGLS |
635 AMD_CG_SUPPORT_GFX_RLC_LS |
636 AMD_CG_SUPPORT_GFX_CP_LS |
637 AMD_CG_SUPPORT_GFX_3D_CGCG |
638 AMD_CG_SUPPORT_GFX_3D_CGLS |
639 AMD_CG_SUPPORT_GFX_CGCG |
640 AMD_CG_SUPPORT_GFX_CGLS |
641 AMD_CG_SUPPORT_BIF_MGCG |
642 AMD_CG_SUPPORT_BIF_LS |
643 AMD_CG_SUPPORT_HDP_LS |
644 AMD_CG_SUPPORT_DRM_MGCG |
645 AMD_CG_SUPPORT_DRM_LS |
646 AMD_CG_SUPPORT_ROM_MGCG |
647 AMD_CG_SUPPORT_DF_MGCG |
648 AMD_CG_SUPPORT_SDMA_MGCG |
649 AMD_CG_SUPPORT_SDMA_LS |
650 AMD_CG_SUPPORT_MC_MGCG |
651 AMD_CG_SUPPORT_MC_LS;
652 adev->pg_flags = 0;
653 adev->external_rev_id = 0x1;
654 break;
692069a1
AD		 655 case CHIP_VEGA12:
656 adev->cg_flags = 0;
657 adev->pg_flags = 0;
658 adev->external_rev_id = 0x1; /* ??? */
659 break;
957c6fe1 660 case CHIP_RAVEN:
5c5928a2
HR		 661 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
662 AMD_CG_SUPPORT_GFX_MGLS |
663 AMD_CG_SUPPORT_GFX_RLC_LS |
664 AMD_CG_SUPPORT_GFX_CP_LS |
665 AMD_CG_SUPPORT_GFX_3D_CGCG |
666 AMD_CG_SUPPORT_GFX_3D_CGLS |
667 AMD_CG_SUPPORT_GFX_CGCG |
668 AMD_CG_SUPPORT_GFX_CGLS |
669 AMD_CG_SUPPORT_BIF_MGCG |
670 AMD_CG_SUPPORT_BIF_LS |
671 AMD_CG_SUPPORT_HDP_MGCG |
672 AMD_CG_SUPPORT_HDP_LS |
673 AMD_CG_SUPPORT_DRM_MGCG |
674 AMD_CG_SUPPORT_DRM_LS |
c2cdb0ec
HR		 675 AMD_CG_SUPPORT_ROM_MGCG |
676 AMD_CG_SUPPORT_MC_MGCG |
fe1a3b2e
HR		 677 AMD_CG_SUPPORT_MC_LS |
678 AMD_CG_SUPPORT_SDMA_MGCG |
679 AMD_CG_SUPPORT_SDMA_LS;
400b6afb
HR		 680 adev->pg_flags = AMD_PG_SUPPORT_SDMA;
681
957c6fe1
HZ		 682 adev->external_rev_id = 0x1;
683 break;
220ab9bd
KW		 684 default:
685 /* FIXME: not supported yet */
686 return -EINVAL;
687 }
688
ab276632
XY		 689 if (amdgpu_sriov_vf(adev)) {
690 amdgpu_virt_init_setting(adev);
691 xgpu_ai_mailbox_set_irq_funcs(adev);
692 }
693
220ab9bd
KW		 694 return 0;
695}
696
81758c55
ML		 697static int soc15_common_late_init(void *handle)
698{
699 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
700
701 if (amdgpu_sriov_vf(adev))
702 xgpu_ai_mailbox_get_irq(adev);
703
704 return 0;
705}
706
220ab9bd
KW		 707static int soc15_common_sw_init(void *handle)
708{
81758c55
ML		 709 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
710
711 if (amdgpu_sriov_vf(adev))
712 xgpu_ai_mailbox_add_irq_id(adev);
713
220ab9bd
KW		 714 return 0;
715}
716
717static int soc15_common_sw_fini(void *handle)
718{
719 return 0;
720}
721
722static int soc15_common_hw_init(void *handle)
723{
724 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
725
220ab9bd
KW		 726 /* enable pcie gen2/3 link */
727 soc15_pcie_gen3_enable(adev);
728 /* enable aspm */
729 soc15_program_aspm(adev);
833fa075 730 /* setup nbio registers */
bf383fb6 731 adev->nbio_funcs->init_registers(adev);
220ab9bd
KW		 732 /* enable the doorbell aperture */
733 soc15_enable_doorbell_aperture(adev, true);
734
735 return 0;
736}
737
738static int soc15_common_hw_fini(void *handle)
739{
740 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
741
742 /* disable the doorbell aperture */
743 soc15_enable_doorbell_aperture(adev, false);
81758c55
ML		 744 if (amdgpu_sriov_vf(adev))
745 xgpu_ai_mailbox_put_irq(adev);
220ab9bd
KW		 746
747 return 0;
748}
749
750static int soc15_common_suspend(void *handle)
751{
752 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
753
754 return soc15_common_hw_fini(adev);
755}
756
757static int soc15_common_resume(void *handle)
758{
759 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
760
761 return soc15_common_hw_init(adev);
762}
763
764static bool soc15_common_is_idle(void *handle)
765{
766 return true;
767}
768
769static int soc15_common_wait_for_idle(void *handle)
770{
771 return 0;
772}
773
774static int soc15_common_soft_reset(void *handle)
775{
776 return 0;
777}
778
779static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
780{
781 uint32_t def, data;
782
783 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
784
785 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
786 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
787 else
788 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
789
790 if (def != data)
791 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
792}
793
794static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
795{
796 uint32_t def, data;
797
798 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
799
800 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
801 data &= ~(0x01000000 |
802 0x02000000 |
803 0x04000000 |
804 0x08000000 |
805 0x10000000 |
806 0x20000000 |
807 0x40000000 |
808 0x80000000);
809 else
810 data |= (0x01000000 |
811 0x02000000 |
812 0x04000000 |
813 0x08000000 |
814 0x10000000 |
815 0x20000000 |
816 0x40000000 |
817 0x80000000);
818
819 if (def != data)
820 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
821}
822
823static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
824{
825 uint32_t def, data;
826
827 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
828
829 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
830 data |= 1;
831 else
832 data &= ~1;
833
834 if (def != data)
835 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
836}
837
838static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
839 bool enable)
840{
841 uint32_t def, data;
842
843 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
844
845 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
846 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
847 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
848 else
849 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
850 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
851
852 if (def != data)
853 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
854}
855
856static void soc15_update_df_medium_grain_clock_gating(struct amdgpu_device *adev,
857 bool enable)
858{
859 uint32_t data;
860
861 /* Put DF on broadcast mode */
862 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl));
863 data &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
864 WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), data);
865
866 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
867 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
868 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
869 data |= DF_MGCG_ENABLE_15_CYCLE_DELAY;
870 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
871 } else {
872 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
873 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
874 data |= DF_MGCG_DISABLE;
875 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
876 }
877
878 WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl),
879 mmFabricConfigAccessControl_DEFAULT);
880}
881
882static int soc15_common_set_clockgating_state(void *handle,
883 enum amd_clockgating_state state)
884{
885 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
886
6e9dc861
ML		 887 if (amdgpu_sriov_vf(adev))
888 return 0;
889
220ab9bd
KW		 890 switch (adev->asic_type) {
891 case CHIP_VEGA10:
692069a1 892 case CHIP_VEGA12:
bf383fb6 893 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
220ab9bd 894 state == AMD_CG_STATE_GATE ? true : false);
bf383fb6 895 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
220ab9bd
KW		 896 state == AMD_CG_STATE_GATE ? true : false);
897 soc15_update_hdp_light_sleep(adev,
898 state == AMD_CG_STATE_GATE ? true : false);
899 soc15_update_drm_clock_gating(adev,
900 state == AMD_CG_STATE_GATE ? true : false);
901 soc15_update_drm_light_sleep(adev,
902 state == AMD_CG_STATE_GATE ? true : false);
903 soc15_update_rom_medium_grain_clock_gating(adev,
904 state == AMD_CG_STATE_GATE ? true : false);
905 soc15_update_df_medium_grain_clock_gating(adev,
906 state == AMD_CG_STATE_GATE ? true : false);
907 break;
9e5a9eb4 908 case CHIP_RAVEN:
bf383fb6 909 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
9e5a9eb4 910 state == AMD_CG_STATE_GATE ? true : false);
bf383fb6 911 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
9e5a9eb4
HR		 912 state == AMD_CG_STATE_GATE ? true : false);
913 soc15_update_hdp_light_sleep(adev,
914 state == AMD_CG_STATE_GATE ? true : false);
915 soc15_update_drm_clock_gating(adev,
916 state == AMD_CG_STATE_GATE ? true : false);
917 soc15_update_drm_light_sleep(adev,
918 state == AMD_CG_STATE_GATE ? true : false);
919 soc15_update_rom_medium_grain_clock_gating(adev,
920 state == AMD_CG_STATE_GATE ? true : false);
921 break;
220ab9bd
KW		 922 default:
923 break;
924 }
925 return 0;
926}
927
f9abe35c
HR		 928static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
929{
930 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
931 int data;
932
933 if (amdgpu_sriov_vf(adev))
934 *flags = 0;
935
bf383fb6 936 adev->nbio_funcs->get_clockgating_state(adev, flags);
f9abe35c
HR		 937
938 /* AMD_CG_SUPPORT_HDP_LS */
939 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
940 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
941 *flags |= AMD_CG_SUPPORT_HDP_LS;
942
943 /* AMD_CG_SUPPORT_DRM_MGCG */
944 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
945 if (!(data & 0x01000000))
946 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
947
948 /* AMD_CG_SUPPORT_DRM_LS */
949 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
950 if (data & 0x1)
951 *flags |= AMD_CG_SUPPORT_DRM_LS;
952
953 /* AMD_CG_SUPPORT_ROM_MGCG */
954 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
955 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
956 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
957
958 /* AMD_CG_SUPPORT_DF_MGCG */
959 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
960 if (data & DF_MGCG_ENABLE_15_CYCLE_DELAY)
961 *flags |= AMD_CG_SUPPORT_DF_MGCG;
962}
963
220ab9bd
KW		 964static int soc15_common_set_powergating_state(void *handle,
965 enum amd_powergating_state state)
966{
967 /* todo */
968 return 0;
969}
970
971const struct amd_ip_funcs soc15_common_ip_funcs = {
972 .name = "soc15_common",
973 .early_init = soc15_common_early_init,
81758c55 974 .late_init = soc15_common_late_init,
220ab9bd
KW		 975 .sw_init = soc15_common_sw_init,
976 .sw_fini = soc15_common_sw_fini,
977 .hw_init = soc15_common_hw_init,
978 .hw_fini = soc15_common_hw_fini,
979 .suspend = soc15_common_suspend,
980 .resume = soc15_common_resume,
981 .is_idle = soc15_common_is_idle,
982 .wait_for_idle = soc15_common_wait_for_idle,
983 .soft_reset = soc15_common_soft_reset,
984 .set_clockgating_state = soc15_common_set_clockgating_state,
985 .set_powergating_state = soc15_common_set_powergating_state,
f9abe35c 986 .get_clockgating_state= soc15_common_get_clockgating_state,
220ab9bd 987};
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