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Commit | Line | Data |
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2c2e6ecf DD |
1 | /* |
2 | * cpuidle-powernv - idle state cpuidle driver. | |
3 | * Adapted from drivers/cpuidle/cpuidle-pseries | |
4 | * | |
5 | */ | |
6 | ||
7 | #include <linux/kernel.h> | |
8 | #include <linux/module.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/moduleparam.h> | |
11 | #include <linux/cpuidle.h> | |
12 | #include <linux/cpu.h> | |
13 | #include <linux/notifier.h> | |
0d948730 | 14 | #include <linux/clockchips.h> |
0888839c | 15 | #include <linux/of.h> |
92c83ff5 | 16 | #include <linux/slab.h> |
2c2e6ecf DD |
17 | |
18 | #include <asm/machdep.h> | |
19 | #include <asm/firmware.h> | |
8eb8ac89 | 20 | #include <asm/opal.h> |
591ac0cb | 21 | #include <asm/runlatch.h> |
09206b60 | 22 | #include <asm/cpuidle.h> |
2c2e6ecf | 23 | |
9e9fc6f0 GS |
24 | /* |
25 | * Expose only those Hardware idle states via the cpuidle framework | |
26 | * that have latency value below POWERNV_THRESHOLD_LATENCY_NS. | |
27 | */ | |
3005c597 SP |
28 | #define POWERNV_THRESHOLD_LATENCY_NS 200000 |
29 | ||
ed61390b | 30 | static struct cpuidle_driver powernv_idle_driver = { |
2c2e6ecf DD |
31 | .name = "powernv_idle", |
32 | .owner = THIS_MODULE, | |
33 | }; | |
34 | ||
35 | static int max_idle_state; | |
36 | static struct cpuidle_state *cpuidle_state_table; | |
3005c597 | 37 | |
09206b60 GS |
38 | struct stop_psscr_table { |
39 | u64 val; | |
40 | u64 mask; | |
41 | }; | |
42 | ||
43 | static struct stop_psscr_table stop_psscr_table[CPUIDLE_STATE_MAX]; | |
3005c597 | 44 | |
78eaa10f SB |
45 | static u64 snooze_timeout; |
46 | static bool snooze_timeout_en; | |
2c2e6ecf DD |
47 | |
48 | static int snooze_loop(struct cpuidle_device *dev, | |
49 | struct cpuidle_driver *drv, | |
50 | int index) | |
51 | { | |
78eaa10f SB |
52 | u64 snooze_exit_time; |
53 | ||
2c2e6ecf DD |
54 | local_irq_enable(); |
55 | set_thread_flag(TIF_POLLING_NRFLAG); | |
56 | ||
78eaa10f | 57 | snooze_exit_time = get_tb() + snooze_timeout; |
591ac0cb | 58 | ppc64_runlatch_off(); |
26eb48a9 | 59 | HMT_very_low(); |
2c2e6ecf | 60 | while (!need_resched()) { |
0baa91cb | 61 | if (likely(snooze_timeout_en) && get_tb() > snooze_exit_time) |
78eaa10f | 62 | break; |
2c2e6ecf DD |
63 | } |
64 | ||
65 | HMT_medium(); | |
591ac0cb | 66 | ppc64_runlatch_on(); |
2c2e6ecf DD |
67 | clear_thread_flag(TIF_POLLING_NRFLAG); |
68 | smp_mb(); | |
69 | return index; | |
70 | } | |
71 | ||
72 | static int nap_loop(struct cpuidle_device *dev, | |
73 | struct cpuidle_driver *drv, | |
74 | int index) | |
75 | { | |
2201f994 NP |
76 | power7_idle_type(PNV_THREAD_NAP); |
77 | ||
2c2e6ecf DD |
78 | return index; |
79 | } | |
80 | ||
cc5a2f7b | 81 | /* Register for fastsleep only in oneshot mode of broadcast */ |
82 | #ifdef CONFIG_TICK_ONESHOT | |
0d948730 PM |
83 | static int fastsleep_loop(struct cpuidle_device *dev, |
84 | struct cpuidle_driver *drv, | |
85 | int index) | |
86 | { | |
87 | unsigned long old_lpcr = mfspr(SPRN_LPCR); | |
88 | unsigned long new_lpcr; | |
89 | ||
90 | if (unlikely(system_state < SYSTEM_RUNNING)) | |
91 | return index; | |
92 | ||
93 | new_lpcr = old_lpcr; | |
9b6a68d9 MN |
94 | /* Do not exit powersave upon decrementer as we've setup the timer |
95 | * offload. | |
0d948730 | 96 | */ |
9b6a68d9 | 97 | new_lpcr &= ~LPCR_PECE1; |
0d948730 PM |
98 | |
99 | mtspr(SPRN_LPCR, new_lpcr); | |
2201f994 NP |
100 | |
101 | power7_idle_type(PNV_THREAD_SLEEP); | |
0d948730 PM |
102 | |
103 | mtspr(SPRN_LPCR, old_lpcr); | |
104 | ||
105 | return index; | |
106 | } | |
cc5a2f7b | 107 | #endif |
3005c597 SP |
108 | |
109 | static int stop_loop(struct cpuidle_device *dev, | |
110 | struct cpuidle_driver *drv, | |
111 | int index) | |
112 | { | |
2201f994 | 113 | power9_idle_type(stop_psscr_table[index].val, |
09206b60 | 114 | stop_psscr_table[index].mask); |
3005c597 SP |
115 | return index; |
116 | } | |
117 | ||
2c2e6ecf DD |
118 | /* |
119 | * States for dedicated partition case. | |
120 | */ | |
169f3fae | 121 | static struct cpuidle_state powernv_states[CPUIDLE_STATE_MAX] = { |
2c2e6ecf DD |
122 | { /* Snooze */ |
123 | .name = "snooze", | |
124 | .desc = "snooze", | |
2c2e6ecf DD |
125 | .exit_latency = 0, |
126 | .target_residency = 0, | |
957efced | 127 | .enter = snooze_loop }, |
2c2e6ecf DD |
128 | }; |
129 | ||
10fcca9d | 130 | static int powernv_cpuidle_cpu_online(unsigned int cpu) |
2c2e6ecf | 131 | { |
10fcca9d | 132 | struct cpuidle_device *dev = per_cpu(cpuidle_devices, cpu); |
2c2e6ecf DD |
133 | |
134 | if (dev && cpuidle_get_driver()) { | |
10fcca9d SAS |
135 | cpuidle_pause_and_lock(); |
136 | cpuidle_enable_device(dev); | |
137 | cpuidle_resume_and_unlock(); | |
138 | } | |
139 | return 0; | |
140 | } | |
2c2e6ecf | 141 | |
10fcca9d SAS |
142 | static int powernv_cpuidle_cpu_dead(unsigned int cpu) |
143 | { | |
144 | struct cpuidle_device *dev = per_cpu(cpuidle_devices, cpu); | |
2c2e6ecf | 145 | |
10fcca9d SAS |
146 | if (dev && cpuidle_get_driver()) { |
147 | cpuidle_pause_and_lock(); | |
148 | cpuidle_disable_device(dev); | |
149 | cpuidle_resume_and_unlock(); | |
2c2e6ecf | 150 | } |
10fcca9d | 151 | return 0; |
2c2e6ecf DD |
152 | } |
153 | ||
2c2e6ecf DD |
154 | /* |
155 | * powernv_cpuidle_driver_init() | |
156 | */ | |
157 | static int powernv_cpuidle_driver_init(void) | |
158 | { | |
159 | int idle_state; | |
160 | struct cpuidle_driver *drv = &powernv_idle_driver; | |
161 | ||
162 | drv->state_count = 0; | |
163 | ||
164 | for (idle_state = 0; idle_state < max_idle_state; ++idle_state) { | |
165 | /* Is the state not enabled? */ | |
166 | if (cpuidle_state_table[idle_state].enter == NULL) | |
167 | continue; | |
168 | ||
169 | drv->states[drv->state_count] = /* structure copy */ | |
170 | cpuidle_state_table[idle_state]; | |
171 | ||
172 | drv->state_count += 1; | |
173 | } | |
174 | ||
293d264f VS |
175 | /* |
176 | * On the PowerNV platform cpu_present may be less than cpu_possible in | |
177 | * cases when firmware detects the CPU, but it is not available to the | |
178 | * OS. If CONFIG_HOTPLUG_CPU=n, then such CPUs are not hotplugable at | |
179 | * run time and hence cpu_devices are not created for those CPUs by the | |
180 | * generic topology_init(). | |
181 | * | |
182 | * drv->cpumask defaults to cpu_possible_mask in | |
183 | * __cpuidle_driver_init(). This breaks cpuidle on PowerNV where | |
184 | * cpu_devices are not created for CPUs in cpu_possible_mask that | |
185 | * cannot be hot-added later at run time. | |
186 | * | |
187 | * Trying cpuidle_register_device() on a CPU without a cpu_device is | |
188 | * incorrect, so pass a correct CPU mask to the generic cpuidle driver. | |
189 | */ | |
190 | ||
191 | drv->cpumask = (struct cpumask *)cpu_present_mask; | |
192 | ||
2c2e6ecf DD |
193 | return 0; |
194 | } | |
195 | ||
9e9fc6f0 GS |
196 | static inline void add_powernv_state(int index, const char *name, |
197 | unsigned int flags, | |
198 | int (*idle_fn)(struct cpuidle_device *, | |
199 | struct cpuidle_driver *, | |
200 | int), | |
201 | unsigned int target_residency, | |
202 | unsigned int exit_latency, | |
09206b60 | 203 | u64 psscr_val, u64 psscr_mask) |
9e9fc6f0 GS |
204 | { |
205 | strlcpy(powernv_states[index].name, name, CPUIDLE_NAME_LEN); | |
206 | strlcpy(powernv_states[index].desc, name, CPUIDLE_NAME_LEN); | |
207 | powernv_states[index].flags = flags; | |
208 | powernv_states[index].target_residency = target_residency; | |
209 | powernv_states[index].exit_latency = exit_latency; | |
210 | powernv_states[index].enter = idle_fn; | |
09206b60 GS |
211 | stop_psscr_table[index].val = psscr_val; |
212 | stop_psscr_table[index].mask = psscr_mask; | |
9e9fc6f0 GS |
213 | } |
214 | ||
ecad4502 GS |
215 | /* |
216 | * Returns 0 if prop1_len == prop2_len. Else returns -1 | |
217 | */ | |
218 | static inline int validate_dt_prop_sizes(const char *prop1, int prop1_len, | |
219 | const char *prop2, int prop2_len) | |
220 | { | |
221 | if (prop1_len == prop2_len) | |
222 | return 0; | |
223 | ||
224 | pr_warn("cpuidle-powernv: array sizes don't match for %s and %s\n", | |
225 | prop1, prop2); | |
226 | return -1; | |
227 | } | |
228 | ||
0888839c PM |
229 | static int powernv_add_idle_states(void) |
230 | { | |
231 | struct device_node *power_mgt; | |
0888839c | 232 | int nr_idle_states = 1; /* Snooze */ |
ecad4502 | 233 | int dt_idle_states, count; |
957efced SP |
234 | u32 latency_ns[CPUIDLE_STATE_MAX]; |
235 | u32 residency_ns[CPUIDLE_STATE_MAX]; | |
236 | u32 flags[CPUIDLE_STATE_MAX]; | |
3005c597 | 237 | u64 psscr_val[CPUIDLE_STATE_MAX]; |
09206b60 | 238 | u64 psscr_mask[CPUIDLE_STATE_MAX]; |
3005c597 | 239 | const char *names[CPUIDLE_STATE_MAX]; |
09206b60 | 240 | u32 has_stop_states = 0; |
92c83ff5 | 241 | int i, rc; |
0888839c PM |
242 | |
243 | /* Currently we have snooze statically defined */ | |
244 | ||
245 | power_mgt = of_find_node_by_path("/ibm,opal/power-mgt"); | |
246 | if (!power_mgt) { | |
247 | pr_warn("opal: PowerMgmt Node not found\n"); | |
92c83ff5 | 248 | goto out; |
0888839c PM |
249 | } |
250 | ||
70734a78 PM |
251 | /* Read values of any property to determine the num of idle states */ |
252 | dt_idle_states = of_property_count_u32_elems(power_mgt, "ibm,cpu-idle-state-flags"); | |
253 | if (dt_idle_states < 0) { | |
254 | pr_warn("cpuidle-powernv: no idle states found in the DT\n"); | |
92c83ff5 | 255 | goto out; |
0888839c PM |
256 | } |
257 | ||
ecad4502 GS |
258 | count = of_property_count_u32_elems(power_mgt, |
259 | "ibm,cpu-idle-state-latencies-ns"); | |
260 | ||
261 | if (validate_dt_prop_sizes("ibm,cpu-idle-state-flags", dt_idle_states, | |
262 | "ibm,cpu-idle-state-latencies-ns", | |
263 | count) != 0) | |
264 | goto out; | |
265 | ||
266 | count = of_property_count_strings(power_mgt, | |
267 | "ibm,cpu-idle-state-names"); | |
268 | if (validate_dt_prop_sizes("ibm,cpu-idle-state-flags", dt_idle_states, | |
269 | "ibm,cpu-idle-state-names", | |
270 | count) != 0) | |
271 | goto out; | |
272 | ||
957efced SP |
273 | /* |
274 | * Since snooze is used as first idle state, max idle states allowed is | |
275 | * CPUIDLE_STATE_MAX -1 | |
276 | */ | |
277 | if (dt_idle_states > CPUIDLE_STATE_MAX - 1) { | |
278 | pr_warn("cpuidle-powernv: discovered idle states more than allowed"); | |
279 | dt_idle_states = CPUIDLE_STATE_MAX - 1; | |
280 | } | |
281 | ||
70734a78 PM |
282 | if (of_property_read_u32_array(power_mgt, |
283 | "ibm,cpu-idle-state-flags", flags, dt_idle_states)) { | |
284 | pr_warn("cpuidle-powernv : missing ibm,cpu-idle-state-flags in DT\n"); | |
957efced | 285 | goto out; |
70734a78 | 286 | } |
92c83ff5 | 287 | |
957efced SP |
288 | if (of_property_read_u32_array(power_mgt, |
289 | "ibm,cpu-idle-state-latencies-ns", latency_ns, | |
290 | dt_idle_states)) { | |
92c83ff5 | 291 | pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-latencies-ns in DT\n"); |
957efced | 292 | goto out; |
74aa51b5 | 293 | } |
3005c597 SP |
294 | if (of_property_read_string_array(power_mgt, |
295 | "ibm,cpu-idle-state-names", names, dt_idle_states) < 0) { | |
296 | pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-names in DT\n"); | |
297 | goto out; | |
298 | } | |
299 | ||
300 | /* | |
301 | * If the idle states use stop instruction, probe for psscr values | |
09206b60 | 302 | * and psscr mask which are necessary to specify required stop level. |
3005c597 | 303 | */ |
09206b60 GS |
304 | has_stop_states = (flags[0] & |
305 | (OPAL_PM_STOP_INST_FAST | OPAL_PM_STOP_INST_DEEP)); | |
306 | if (has_stop_states) { | |
ecad4502 GS |
307 | count = of_property_count_u64_elems(power_mgt, |
308 | "ibm,cpu-idle-state-psscr"); | |
309 | if (validate_dt_prop_sizes("ibm,cpu-idle-state-flags", | |
310 | dt_idle_states, | |
311 | "ibm,cpu-idle-state-psscr", | |
312 | count) != 0) | |
313 | goto out; | |
314 | ||
315 | count = of_property_count_u64_elems(power_mgt, | |
316 | "ibm,cpu-idle-state-psscr-mask"); | |
317 | if (validate_dt_prop_sizes("ibm,cpu-idle-state-flags", | |
318 | dt_idle_states, | |
319 | "ibm,cpu-idle-state-psscr-mask", | |
320 | count) != 0) | |
321 | goto out; | |
322 | ||
3005c597 SP |
323 | if (of_property_read_u64_array(power_mgt, |
324 | "ibm,cpu-idle-state-psscr", psscr_val, dt_idle_states)) { | |
09206b60 | 325 | pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr in DT\n"); |
3005c597 SP |
326 | goto out; |
327 | } | |
74aa51b5 | 328 | |
09206b60 GS |
329 | if (of_property_read_u64_array(power_mgt, |
330 | "ibm,cpu-idle-state-psscr-mask", | |
331 | psscr_mask, dt_idle_states)) { | |
332 | pr_warn("cpuidle-powernv:Missing ibm,cpu-idle-state-psscr-mask in DT\n"); | |
333 | goto out; | |
334 | } | |
335 | } | |
336 | ||
ecad4502 GS |
337 | count = of_property_count_u32_elems(power_mgt, |
338 | "ibm,cpu-idle-state-residency-ns"); | |
339 | ||
340 | if (count < 0) { | |
341 | rc = count; | |
342 | } else if (validate_dt_prop_sizes("ibm,cpu-idle-state-flags", | |
343 | dt_idle_states, | |
344 | "ibm,cpu-idle-state-residency-ns", | |
345 | count) != 0) { | |
346 | goto out; | |
347 | } else { | |
348 | rc = of_property_read_u32_array(power_mgt, | |
349 | "ibm,cpu-idle-state-residency-ns", | |
350 | residency_ns, dt_idle_states); | |
351 | } | |
0888839c PM |
352 | |
353 | for (i = 0; i < dt_idle_states; i++) { | |
9e9fc6f0 | 354 | unsigned int exit_latency, target_residency; |
f9122ee4 | 355 | bool stops_timebase = false; |
3005c597 SP |
356 | /* |
357 | * If an idle state has exit latency beyond | |
358 | * POWERNV_THRESHOLD_LATENCY_NS then don't use it | |
359 | * in cpu-idle. | |
360 | */ | |
361 | if (latency_ns[i] > POWERNV_THRESHOLD_LATENCY_NS) | |
362 | continue; | |
9e9fc6f0 GS |
363 | /* |
364 | * Firmware passes residency and latency values in ns. | |
365 | * cpuidle expects it in us. | |
366 | */ | |
367 | exit_latency = latency_ns[i] / 1000; | |
368 | if (!rc) | |
369 | target_residency = residency_ns[i] / 1000; | |
370 | else | |
371 | target_residency = 0; | |
0888839c | 372 | |
09206b60 GS |
373 | if (has_stop_states) { |
374 | int err = validate_psscr_val_mask(&psscr_val[i], | |
375 | &psscr_mask[i], | |
376 | flags[i]); | |
377 | if (err) { | |
378 | report_invalid_psscr_val(psscr_val[i], err); | |
379 | continue; | |
380 | } | |
381 | } | |
382 | ||
f9122ee4 GS |
383 | if (flags[i] & OPAL_PM_TIMEBASE_STOP) |
384 | stops_timebase = true; | |
385 | ||
92c83ff5 | 386 | /* |
9e9fc6f0 GS |
387 | * For nap and fastsleep, use default target_residency |
388 | * values if f/w does not expose it. | |
74aa51b5 | 389 | */ |
70734a78 | 390 | if (flags[i] & OPAL_PM_NAP_ENABLED) { |
9e9fc6f0 GS |
391 | if (!rc) |
392 | target_residency = 100; | |
0888839c | 393 | /* Add NAP state */ |
9e9fc6f0 GS |
394 | add_powernv_state(nr_idle_states, "Nap", |
395 | CPUIDLE_FLAG_NONE, nap_loop, | |
09206b60 | 396 | target_residency, exit_latency, 0, 0); |
f9122ee4 | 397 | } else if (has_stop_states && !stops_timebase) { |
9e9fc6f0 GS |
398 | add_powernv_state(nr_idle_states, names[i], |
399 | CPUIDLE_FLAG_NONE, stop_loop, | |
400 | target_residency, exit_latency, | |
09206b60 | 401 | psscr_val[i], psscr_mask[i]); |
cc5a2f7b | 402 | } |
403 | ||
404 | /* | |
405 | * All cpuidle states with CPUIDLE_FLAG_TIMER_STOP set must come | |
406 | * within this config dependency check. | |
407 | */ | |
408 | #ifdef CONFIG_TICK_ONESHOT | |
f9122ee4 GS |
409 | else if (flags[i] & OPAL_PM_SLEEP_ENABLED || |
410 | flags[i] & OPAL_PM_SLEEP_ENABLED_ER1) { | |
9e9fc6f0 GS |
411 | if (!rc) |
412 | target_residency = 300000; | |
0888839c | 413 | /* Add FASTSLEEP state */ |
9e9fc6f0 GS |
414 | add_powernv_state(nr_idle_states, "FastSleep", |
415 | CPUIDLE_FLAG_TIMER_STOP, | |
416 | fastsleep_loop, | |
09206b60 | 417 | target_residency, exit_latency, 0, 0); |
f9122ee4 | 418 | } else if (has_stop_states && stops_timebase) { |
9e9fc6f0 GS |
419 | add_powernv_state(nr_idle_states, names[i], |
420 | CPUIDLE_FLAG_TIMER_STOP, stop_loop, | |
421 | target_residency, exit_latency, | |
09206b60 | 422 | psscr_val[i], psscr_mask[i]); |
0888839c | 423 | } |
cc5a2f7b | 424 | #endif |
f9122ee4 GS |
425 | else |
426 | continue; | |
92c83ff5 | 427 | nr_idle_states++; |
0888839c | 428 | } |
92c83ff5 | 429 | out: |
0888839c PM |
430 | return nr_idle_states; |
431 | } | |
432 | ||
2c2e6ecf DD |
433 | /* |
434 | * powernv_idle_probe() | |
435 | * Choose state table for shared versus dedicated partition | |
436 | */ | |
437 | static int powernv_idle_probe(void) | |
438 | { | |
2c2e6ecf DD |
439 | if (cpuidle_disable != IDLE_NO_OVERRIDE) |
440 | return -ENODEV; | |
441 | ||
e4d54f71 | 442 | if (firmware_has_feature(FW_FEATURE_OPAL)) { |
2c2e6ecf | 443 | cpuidle_state_table = powernv_states; |
0888839c PM |
444 | /* Device tree can indicate more idle states */ |
445 | max_idle_state = powernv_add_idle_states(); | |
78eaa10f SB |
446 | if (max_idle_state > 1) { |
447 | snooze_timeout_en = true; | |
448 | snooze_timeout = powernv_states[1].target_residency * | |
449 | tb_ticks_per_usec; | |
450 | } | |
2c2e6ecf DD |
451 | } else |
452 | return -ENODEV; | |
453 | ||
454 | return 0; | |
455 | } | |
456 | ||
457 | static int __init powernv_processor_idle_init(void) | |
458 | { | |
459 | int retval; | |
460 | ||
461 | retval = powernv_idle_probe(); | |
462 | if (retval) | |
463 | return retval; | |
464 | ||
465 | powernv_cpuidle_driver_init(); | |
466 | retval = cpuidle_register(&powernv_idle_driver, NULL); | |
467 | if (retval) { | |
468 | printk(KERN_DEBUG "Registration of powernv driver failed.\n"); | |
469 | return retval; | |
470 | } | |
471 | ||
10fcca9d SAS |
472 | retval = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, |
473 | "cpuidle/powernv:online", | |
474 | powernv_cpuidle_cpu_online, NULL); | |
475 | WARN_ON(retval < 0); | |
476 | retval = cpuhp_setup_state_nocalls(CPUHP_CPUIDLE_DEAD, | |
477 | "cpuidle/powernv:dead", NULL, | |
478 | powernv_cpuidle_cpu_dead); | |
479 | WARN_ON(retval < 0); | |
2c2e6ecf DD |
480 | printk(KERN_DEBUG "powernv_idle_driver registered\n"); |
481 | return 0; | |
482 | } | |
483 | ||
484 | device_initcall(powernv_processor_idle_init); |