projects / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * linux/include/asm/traps.h | |
| 3 | * | |
| 4 | * Copyright (C) 1993 Hamish Macdonald | |
| 5 | * | |
| 6 | * This file is subject to the terms and conditions of the GNU General Public | |
| 7 | * License. See the file COPYING in the main directory of this archive | |
| 8 | * for more details. | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef _M68K_TRAPS_H | |
| 12 | #define _M68K_TRAPS_H | |
| 13 | ||
| 14 | #ifndef __ASSEMBLY__ | |
| 15 | ||
| 92445eaa RZ |
16 | #include <linux/linkage.h> |
| 17 | #include <asm/ptrace.h> | |
| 18 | ||
| 1da177e4 LT |
19 | typedef void (*e_vector)(void); |
| 20 | ||
| 92445eaa | 21 | asmlinkage void auto_inthandler(void); |
| 68387c44 | 22 | asmlinkage void user_inthandler(void); |
| 92445eaa RZ |
23 | asmlinkage void bad_inthandler(void); |
| 24 | ||
| 1da177e4 LT |
25 | extern e_vector vectors[]; |
| 26 | ||
| 27 | #endif | |
| 28 | ||
| 29 | #define VEC_RESETSP (0) | |
| 30 | #define VEC_RESETPC (1) | |
| 31 | #define VEC_BUSERR (2) | |
| 32 | #define VEC_ADDRERR (3) | |
| 33 | #define VEC_ILLEGAL (4) | |
| 34 | #define VEC_ZERODIV (5) | |
| 35 | #define VEC_CHK (6) | |
| 36 | #define VEC_TRAP (7) | |
| 37 | #define VEC_PRIV (8) | |
| 38 | #define VEC_TRACE (9) | |
| 39 | #define VEC_LINE10 (10) | |
| 40 | #define VEC_LINE11 (11) | |
| 41 | #define VEC_RESV12 (12) | |
| 42 | #define VEC_COPROC (13) | |
| 43 | #define VEC_FORMAT (14) | |
| 44 | #define VEC_UNINT (15) | |
| 45 | #define VEC_RESV16 (16) | |
| 46 | #define VEC_RESV17 (17) | |
| 47 | #define VEC_RESV18 (18) | |
| 48 | #define VEC_RESV19 (19) | |
| 49 | #define VEC_RESV20 (20) | |
| 50 | #define VEC_RESV21 (21) | |
| 51 | #define VEC_RESV22 (22) | |
| 52 | #define VEC_RESV23 (23) | |
| 53 | #define VEC_SPUR (24) | |
| 54 | #define VEC_INT1 (25) | |
| 55 | #define VEC_INT2 (26) | |
| 56 | #define VEC_INT3 (27) | |
| 57 | #define VEC_INT4 (28) | |
| 58 | #define VEC_INT5 (29) | |
| 59 | #define VEC_INT6 (30) | |
| 60 | #define VEC_INT7 (31) | |
| 61 | #define VEC_SYS (32) | |
| 62 | #define VEC_TRAP1 (33) | |
| 63 | #define VEC_TRAP2 (34) | |
| 64 | #define VEC_TRAP3 (35) | |
| 65 | #define VEC_TRAP4 (36) | |
| 66 | #define VEC_TRAP5 (37) | |
| 67 | #define VEC_TRAP6 (38) | |
| 68 | #define VEC_TRAP7 (39) | |
| 69 | #define VEC_TRAP8 (40) | |
| 70 | #define VEC_TRAP9 (41) | |
| 71 | #define VEC_TRAP10 (42) | |
| 72 | #define VEC_TRAP11 (43) | |
| 73 | #define VEC_TRAP12 (44) | |
| 74 | #define VEC_TRAP13 (45) | |
| 75 | #define VEC_TRAP14 (46) | |
| 76 | #define VEC_TRAP15 (47) | |
| 77 | #define VEC_FPBRUC (48) | |
| 78 | #define VEC_FPIR (49) | |
| 79 | #define VEC_FPDIVZ (50) | |
| 80 | #define VEC_FPUNDER (51) | |
| 81 | #define VEC_FPOE (52) | |
| 82 | #define VEC_FPOVER (53) | |
| 83 | #define VEC_FPNAN (54) | |
| 84 | #define VEC_FPUNSUP (55) | |
| 85 | #define VEC_MMUCFG (56) | |
| 86 | #define VEC_MMUILL (57) | |
| 87 | #define VEC_MMUACC (58) | |
| 88 | #define VEC_RESV59 (59) | |
| 89 | #define VEC_UNIMPEA (60) | |
| 90 | #define VEC_UNIMPII (61) | |
| 91 | #define VEC_RESV62 (62) | |
| 92 | #define VEC_RESV63 (63) | |
| 93 | #define VEC_USER (64) | |
| 94 | ||
| 95 | #define VECOFF(vec) ((vec)<<2) | |
| 96 | ||
| 97 | #ifndef __ASSEMBLY__ | |
| 98 | ||
| 99 | /* Status register bits */ | |
| 100 | #define PS_T (0x8000) | |
| 101 | #define PS_S (0x2000) | |
| 102 | #define PS_M (0x1000) | |
| 103 | #define PS_C (0x0001) | |
| 104 | ||
| 105 | /* bits for 68020/68030 special status word */ | |
| 106 | ||
| 107 | #define FC (0x8000) | |
| 108 | #define FB (0x4000) | |
| 109 | #define RC (0x2000) | |
| 110 | #define RB (0x1000) | |
| 111 | #define DF (0x0100) | |
| 112 | #define RM (0x0080) | |
| 113 | #define RW (0x0040) | |
| 114 | #define SZ (0x0030) | |
| 115 | #define DFC (0x0007) | |
| 116 | ||
| 117 | /* bits for 68030 MMU status register (mmusr,psr) */ | |
| 118 | ||
| 119 | #define MMU_B (0x8000) /* bus error */ | |
| 120 | #define MMU_L (0x4000) /* limit violation */ | |
| 121 | #define MMU_S (0x2000) /* supervisor violation */ | |
| 122 | #define MMU_WP (0x0800) /* write-protected */ | |
| 123 | #define MMU_I (0x0400) /* invalid descriptor */ | |
| 124 | #define MMU_M (0x0200) /* ATC entry modified */ | |
| 125 | #define MMU_T (0x0040) /* transparent translation */ | |
| 126 | #define MMU_NUM (0x0007) /* number of levels traversed */ | |
| 127 | ||
| 128 | ||
| 129 | /* bits for 68040 special status word */ | |
| 130 | #define CP_040 (0x8000) | |
| 131 | #define CU_040 (0x4000) | |
| 132 | #define CT_040 (0x2000) | |
| 133 | #define CM_040 (0x1000) | |
| 134 | #define MA_040 (0x0800) | |
| 135 | #define ATC_040 (0x0400) | |
| 136 | #define LK_040 (0x0200) | |
| 137 | #define RW_040 (0x0100) | |
| 138 | #define SIZ_040 (0x0060) | |
| 139 | #define TT_040 (0x0018) | |
| 140 | #define TM_040 (0x0007) | |
| 141 | ||
| 142 | /* bits for 68040 write back status word */ | |
| 143 | #define WBV_040 (0x80) | |
| 144 | #define WBSIZ_040 (0x60) | |
| 145 | #define WBBYT_040 (0x20) | |
| 146 | #define WBWRD_040 (0x40) | |
| 147 | #define WBLNG_040 (0x00) | |
| 148 | #define WBTT_040 (0x18) | |
| 149 | #define WBTM_040 (0x07) | |
| 150 | ||
| 151 | /* bus access size codes */ | |
| 152 | #define BA_SIZE_BYTE (0x20) | |
| 153 | #define BA_SIZE_WORD (0x40) | |
| 154 | #define BA_SIZE_LONG (0x00) | |
| 155 | #define BA_SIZE_LINE (0x60) | |
| 156 | ||
| 157 | /* bus access transfer type codes */ | |
| 158 | #define BA_TT_MOVE16 (0x08) | |
| 159 | ||
| 160 | /* bits for 68040 MMU status register (mmusr) */ | |
| 161 | #define MMU_B_040 (0x0800) | |
| 162 | #define MMU_G_040 (0x0400) | |
| 163 | #define MMU_S_040 (0x0080) | |
| 164 | #define MMU_CM_040 (0x0060) | |
| 165 | #define MMU_M_040 (0x0010) | |
| 166 | #define MMU_WP_040 (0x0004) | |
| 167 | #define MMU_T_040 (0x0002) | |
| 168 | #define MMU_R_040 (0x0001) | |
| 169 | ||
| 170 | /* bits in the 68060 fault status long word (FSLW) */ | |
| 171 | #define MMU060_MA (0x08000000) /* misaligned */ | |
| 172 | #define MMU060_LK (0x02000000) /* locked transfer */ | |
| 173 | #define MMU060_RW (0x01800000) /* read/write */ | |
| 174 | # define MMU060_RW_W (0x00800000) /* write */ | |
| 175 | # define MMU060_RW_R (0x01000000) /* read */ | |
| 176 | # define MMU060_RW_RMW (0x01800000) /* read/modify/write */ | |
| 177 | # define MMU060_W (0x00800000) /* general write, includes rmw */ | |
| 178 | #define MMU060_SIZ (0x00600000) /* transfer size */ | |
| 179 | #define MMU060_TT (0x00180000) /* transfer type (TT) bits */ | |
| 180 | #define MMU060_TM (0x00070000) /* transfer modifier (TM) bits */ | |
| 181 | #define MMU060_IO (0x00008000) /* instruction or operand */ | |
| 182 | #define MMU060_PBE (0x00004000) /* push buffer bus error */ | |
| 183 | #define MMU060_SBE (0x00002000) /* store buffer bus error */ | |
| 184 | #define MMU060_PTA (0x00001000) /* pointer A fault */ | |
| 185 | #define MMU060_PTB (0x00000800) /* pointer B fault */ | |
| 186 | #define MMU060_IL (0x00000400) /* double indirect descr fault */ | |
| 187 | #define MMU060_PF (0x00000200) /* page fault (invalid descr) */ | |
| 188 | #define MMU060_SP (0x00000100) /* supervisor protection */ | |
| 189 | #define MMU060_WP (0x00000080) /* write protection */ | |
| 190 | #define MMU060_TWE (0x00000040) /* bus error on table search */ | |
| 191 | #define MMU060_RE (0x00000020) /* bus error on read */ | |
| 192 | #define MMU060_WE (0x00000010) /* bus error on write */ | |
| 193 | #define MMU060_TTR (0x00000008) /* error caused by TTR translation */ | |
| 194 | #define MMU060_BPE (0x00000004) /* branch prediction error */ | |
| 195 | #define MMU060_SEE (0x00000001) /* software emulated error */ | |
| 196 | ||
| 197 | /* cases of missing or invalid descriptors */ | |
| 198 | #define MMU060_DESC_ERR (MMU060_PTA | MMU060_PTB | \ | |
| 199 | MMU060_IL | MMU060_PF) | |
| 200 | /* bits that indicate real errors */ | |
| 201 | #define MMU060_ERR_BITS (MMU060_PBE | MMU060_SBE | MMU060_DESC_ERR | MMU060_SP | \ | |
| 202 | MMU060_WP | MMU060_TWE | MMU060_RE | MMU060_WE) | |
| 203 | ||
| 204 | /* structure for stack frames */ | |
| 205 | ||
| 206 | struct frame { | |
| 207 | struct pt_regs ptregs; | |
| 208 | union { | |
| 209 | struct { | |
| 210 | unsigned long iaddr; /* instruction address */ | |
| 211 | } fmt2; | |
| 212 | struct { | |
| 213 | unsigned long effaddr; /* effective address */ | |
| 214 | } fmt3; | |
| 215 | struct { | |
| 216 | unsigned long effaddr; /* effective address */ | |
| 217 | unsigned long pc; /* pc of faulted instr */ | |
| 218 | } fmt4; | |
| 219 | struct { | |
| 220 | unsigned long effaddr; /* effective address */ | |
| 221 | unsigned short ssw; /* special status word */ | |
| 222 | unsigned short wb3s; /* write back 3 status */ | |
| 223 | unsigned short wb2s; /* write back 2 status */ | |
| 224 | unsigned short wb1s; /* write back 1 status */ | |
| 225 | unsigned long faddr; /* fault address */ | |
| 226 | unsigned long wb3a; /* write back 3 address */ | |
| 227 | unsigned long wb3d; /* write back 3 data */ | |
| 228 | unsigned long wb2a; /* write back 2 address */ | |
| 229 | unsigned long wb2d; /* write back 2 data */ | |
| 230 | unsigned long wb1a; /* write back 1 address */ | |
| 231 | unsigned long wb1dpd0; /* write back 1 data/push data 0*/ | |
| 232 | unsigned long pd1; /* push data 1*/ | |
| 233 | unsigned long pd2; /* push data 2*/ | |
| 234 | unsigned long pd3; /* push data 3*/ | |
| 235 | } fmt7; | |
| 236 | struct { | |
| 237 | unsigned long iaddr; /* instruction address */ | |
| 238 | unsigned short int1[4]; /* internal registers */ | |
| 239 | } fmt9; | |
| 240 | struct { | |
| 241 | unsigned short int1; | |
| 242 | unsigned short ssw; /* special status word */ | |
| 243 | unsigned short isc; /* instruction stage c */ | |
| 244 | unsigned short isb; /* instruction stage b */ | |
| 245 | unsigned long daddr; /* data cycle fault address */ | |
| 246 | unsigned short int2[2]; | |
| 247 | unsigned long dobuf; /* data cycle output buffer */ | |
| 248 | unsigned short int3[2]; | |
| 249 | } fmta; | |
| 250 | struct { | |
| 251 | unsigned short int1; | |
| 252 | unsigned short ssw; /* special status word */ | |
| 253 | unsigned short isc; /* instruction stage c */ | |
| 254 | unsigned short isb; /* instruction stage b */ | |
| 255 | unsigned long daddr; /* data cycle fault address */ | |
| 256 | unsigned short int2[2]; | |
| 257 | unsigned long dobuf; /* data cycle output buffer */ | |
| 258 | unsigned short int3[4]; | |
| 259 | unsigned long baddr; /* stage B address */ | |
| 260 | unsigned short int4[2]; | |
| 261 | unsigned long dibuf; /* data cycle input buffer */ | |
| 262 | unsigned short int5[3]; | |
| 263 | unsigned ver : 4; /* stack frame version # */ | |
| 264 | unsigned int6:12; | |
| 265 | unsigned short int7[18]; | |
| 266 | } fmtb; | |
| 267 | } un; | |
| 268 | }; | |
| 269 | ||
| 270 | #endif /* __ASSEMBLY__ */ | |
| 271 | ||
| 272 | #endif /* _M68K_TRAPS_H */ |