]> Git Repo - linux.git/blame - arch/x86/kvm/svm.c
projects / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: SVM: reset mmu context in init_vmcb
[linux.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
221d059d 7 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 8 *
9 * Authors:
10 * Yaniv Kamay <[email protected]>
11 * Avi Kivity <[email protected]>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
edf88417
AK		 17#include <linux/kvm_host.h>
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
fe4c7b19 22#include "x86.h"
e495606d 23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/vmalloc.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
6aa8b732 31
67ec6607 32#include <asm/tlbflush.h>
e495606d 33#include <asm/desc.h>
6aa8b732 34
63d1142f 35#include <asm/virtext.h>
229456fc 36#include "trace.h"
63d1142f 37
4ecac3fd
AK		 38#define __ex(x) __kvm_handle_fault_on_reboot(x)
39
6aa8b732
AK		 40MODULE_AUTHOR("Qumranet");
41MODULE_LICENSE("GPL");
42
43#define IOPM_ALLOC_ORDER 2
44#define MSRPM_ALLOC_ORDER 1
45
6aa8b732
AK		 46#define SEG_TYPE_LDT 2
47#define SEG_TYPE_BUSY_TSS16 3
48
6bc31bdc
AP		 49#define SVM_FEATURE_NPT (1 << 0)
50#define SVM_FEATURE_LBRV (1 << 1)
51#define SVM_FEATURE_SVML (1 << 2)
52#define SVM_FEATURE_NRIP (1 << 3)
53#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 54
410e4d57
JR		 55#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
56#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
57#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
58
24e09cbf
JR		 59#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
60
67ec6607
JR		 61static bool erratum_383_found __read_mostly;
62
6c8166a7
AK		 63static const u32 host_save_user_msrs[] = {
64#ifdef CONFIG_X86_64
65 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
66 MSR_FS_BASE,
67#endif
68 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
69};
70
71#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
72
73struct kvm_vcpu;
74
e6aa9abd
JR		 75struct nested_state {
76 struct vmcb *hsave;
77 u64 hsave_msr;
4a810181 78 u64 vm_cr_msr;
e6aa9abd
JR		 79 u64 vmcb;
80
81 /* These are the merged vectors */
82 u32 *msrpm;
83
84 /* gpa pointers to the real vectors */
85 u64 vmcb_msrpm;
ce2ac085 86 u64 vmcb_iopm;
aad42c64 87
cd3ff653
JR		 88 /* A VMEXIT is required but not yet emulated */
89 bool exit_required;
90
aad42c64
JR		 91 /* cache for intercepts of the guest */
92 u16 intercept_cr_read;
93 u16 intercept_cr_write;
94 u16 intercept_dr_read;
95 u16 intercept_dr_write;
96 u32 intercept_exceptions;
97 u64 intercept;
98
e6aa9abd
JR		 99};
100
323c3d80
JR		 101#define MSRPM_OFFSETS 16
102static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
103
6c8166a7
AK		 104struct vcpu_svm {
105 struct kvm_vcpu vcpu;
106 struct vmcb *vmcb;
107 unsigned long vmcb_pa;
108 struct svm_cpu_data *svm_data;
109 uint64_t asid_generation;
110 uint64_t sysenter_esp;
111 uint64_t sysenter_eip;
112
113 u64 next_rip;
114
115 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
116 u64 host_gs_base;
6c8166a7
AK		 117
118 u32 *msrpm;
6c8166a7 119
e6aa9abd 120 struct nested_state nested;
6be7d306
JK		 121
122 bool nmi_singlestep;
66b7138f
JK		 123
124 unsigned int3_injected;
125 unsigned long int3_rip;
6c8166a7
AK		 126};
127
455716fa
JR		 128#define MSR_INVALID 0xffffffffU
129
ac72a9b7
JR		 130static struct svm_direct_access_msrs {
131 u32 index; /* Index of the MSR */
132 bool always; /* True if intercept is always on */
133} direct_access_msrs[] = {
8c06585d 134 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 135 { .index = MSR_IA32_SYSENTER_CS, .always = true },
136#ifdef CONFIG_X86_64
137 { .index = MSR_GS_BASE, .always = true },
138 { .index = MSR_FS_BASE, .always = true },
139 { .index = MSR_KERNEL_GS_BASE, .always = true },
140 { .index = MSR_LSTAR, .always = true },
141 { .index = MSR_CSTAR, .always = true },
142 { .index = MSR_SYSCALL_MASK, .always = true },
143#endif
144 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
145 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
146 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
147 { .index = MSR_IA32_LASTINTTOIP, .always = false },
148 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 149};
150
709ddebf
JR		 151/* enable NPT for AMD64 and X86 with PAE */
152#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
153static bool npt_enabled = true;
154#else
e0231715 155static bool npt_enabled;
709ddebf 156#endif
6c7dac72
JR		 157static int npt = 1;
158
159module_param(npt, int, S_IRUGO);
e3da3acd 160
4b6e4dca 161static int nested = 1;
236de055
AG		 162module_param(nested, int, S_IRUGO);
163
44874f84 164static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 165static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 166
410e4d57 167static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 168static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 169static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 170static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
171 bool has_error_code, u32 error_code);
172
a2fa3e9f
GH		 173static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
174{
fb3f0f51 175 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 176}
177
3d6368ef
AG		 178static inline bool is_nested(struct vcpu_svm *svm)
179{
e6aa9abd 180 return svm->nested.vmcb;
3d6368ef
AG		 181}
182
2af9194d
JR		 183static inline void enable_gif(struct vcpu_svm *svm)
184{
185 svm->vcpu.arch.hflags |= HF_GIF_MASK;
186}
187
188static inline void disable_gif(struct vcpu_svm *svm)
189{
190 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
191}
192
193static inline bool gif_set(struct vcpu_svm *svm)
194{
195 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
196}
197
4866d5e3 198static unsigned long iopm_base;
6aa8b732
AK		 199
200struct kvm_ldttss_desc {
201 u16 limit0;
202 u16 base0;
e0231715
JR		 203 unsigned base1:8, type:5, dpl:2, p:1;
204 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 205 u32 base3;
206 u32 zero1;
207} __attribute__((packed));
208
209struct svm_cpu_data {
210 int cpu;
211
5008fdf5
AK		 212 u64 asid_generation;
213 u32 max_asid;
214 u32 next_asid;
6aa8b732
AK		 215 struct kvm_ldttss_desc *tss_desc;
216
217 struct page *save_area;
218};
219
220static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 221static uint32_t svm_features;
6aa8b732
AK		 222
223struct svm_init_data {
224 int cpu;
225 int r;
226};
227
228static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
229
9d8f549d 230#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 231#define MSRS_RANGE_SIZE 2048
232#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
233
455716fa
JR		 234static u32 svm_msrpm_offset(u32 msr)
235{
236 u32 offset;
237 int i;
238
239 for (i = 0; i < NUM_MSR_MAPS; i++) {
240 if (msr < msrpm_ranges[i] ||
241 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
242 continue;
243
244 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
245 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
246
247 /* Now we have the u8 offset - but need the u32 offset */
248 return offset / 4;
249 }
250
251 /* MSR not in any range */
252 return MSR_INVALID;
253}
254
6aa8b732
AK		 255#define MAX_INST_SIZE 15
256
80b7706e
JR		 257static inline u32 svm_has(u32 feat)
258{
259 return svm_features & feat;
260}
261
6aa8b732
AK		 262static inline void clgi(void)
263{
4ecac3fd 264 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 265}
266
267static inline void stgi(void)
268{
4ecac3fd 269 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 270}
271
272static inline void invlpga(unsigned long addr, u32 asid)
273{
e0231715 274 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 275}
276
6aa8b732
AK		 277static inline void force_new_asid(struct kvm_vcpu *vcpu)
278{
a2fa3e9f 279 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 280}
281
282static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
283{
284 force_new_asid(vcpu);
285}
286
287static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
288{
6dc696d4 289 vcpu->arch.efer = efer;
709ddebf 290 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 291 efer &= ~EFER_LME;
6aa8b732 292
9962d032 293 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
6aa8b732
AK		 294}
295
6aa8b732
AK		 296static int is_external_interrupt(u32 info)
297{
298 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
299 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
300}
301
2809f5d2
GC		 302static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
303{
304 struct vcpu_svm *svm = to_svm(vcpu);
305 u32 ret = 0;
306
307 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 308 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 309 return ret & mask;
310}
311
312static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
313{
314 struct vcpu_svm *svm = to_svm(vcpu);
315
316 if (mask == 0)
317 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
318 else
319 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
320
321}
322
6aa8b732
AK		 323static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
324{
a2fa3e9f
GH		 325 struct vcpu_svm *svm = to_svm(vcpu);
326
6bc31bdc
AP		 327 if (svm->vmcb->control.next_rip != 0)
328 svm->next_rip = svm->vmcb->control.next_rip;
329
a2fa3e9f 330 if (!svm->next_rip) {
851ba692 331 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 332 EMULATE_DONE)
333 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 334 return;
335 }
5fdbf976
MT		 336 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
337 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
338 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 339
5fdbf976 340 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 341 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 342}
343
116a4752 344static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 345 bool has_error_code, u32 error_code,
346 bool reinject)
116a4752
JK		 347{
348 struct vcpu_svm *svm = to_svm(vcpu);
349
e0231715
JR		 350 /*
351 * If we are within a nested VM we'd better #VMEXIT and let the guest
352 * handle the exception
353 */
ce7ddec4
JR		 354 if (!reinject &&
355 nested_svm_check_exception(svm, nr, has_error_code, error_code))
116a4752
JK		 356 return;
357
66b7138f
JK		 358 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
359 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
360
361 /*
362 * For guest debugging where we have to reinject #BP if some
363 * INT3 is guest-owned:
364 * Emulate nRIP by moving RIP forward. Will fail if injection
365 * raises a fault that is not intercepted. Still better than
366 * failing in all cases.
367 */
368 skip_emulated_instruction(&svm->vcpu);
369 rip = kvm_rip_read(&svm->vcpu);
370 svm->int3_rip = rip + svm->vmcb->save.cs.base;
371 svm->int3_injected = rip - old_rip;
372 }
373
116a4752
JK		 374 svm->vmcb->control.event_inj = nr
375 | SVM_EVTINJ_VALID
376 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
377 | SVM_EVTINJ_TYPE_EXEPT;
378 svm->vmcb->control.event_inj_err = error_code;
379}
380
67ec6607
JR		 381static void svm_init_erratum_383(void)
382{
383 u32 low, high;
384 int err;
385 u64 val;
386
1be85a6d 387 if (!cpu_has_amd_erratum(amd_erratum_383))
67ec6607
JR		 388 return;
389
390 /* Use _safe variants to not break nested virtualization */
391 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
392 if (err)
393 return;
394
395 val |= (1ULL << 47);
396
397 low = lower_32_bits(val);
398 high = upper_32_bits(val);
399
400 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
401
402 erratum_383_found = true;
403}
404
6aa8b732
AK		 405static int has_svm(void)
406{
63d1142f 407 const char *msg;
6aa8b732 408
63d1142f 409 if (!cpu_has_svm(&msg)) {
ff81ff10 410 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 411 return 0;
412 }
413
6aa8b732
AK		 414 return 1;
415}
416
417static void svm_hardware_disable(void *garbage)
418{
2c8dceeb 419 cpu_svm_disable();
6aa8b732
AK		 420}
421
10474ae8 422static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 423{
424
0fe1e009 425 struct svm_cpu_data *sd;
6aa8b732 426 uint64_t efer;
89a27f4d 427 struct desc_ptr gdt_descr;
6aa8b732
AK		 428 struct desc_struct *gdt;
429 int me = raw_smp_processor_id();
430
10474ae8
AG		 431 rdmsrl(MSR_EFER, efer);
432 if (efer & EFER_SVME)
433 return -EBUSY;
434
6aa8b732 435 if (!has_svm()) {
e6732a5a
ZA		 436 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
437 me);
10474ae8 438 return -EINVAL;
6aa8b732 439 }
0fe1e009 440 sd = per_cpu(svm_data, me);
6aa8b732 441
0fe1e009 442 if (!sd) {
e6732a5a 443 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 444 me);
10474ae8 445 return -EINVAL;
6aa8b732
AK		 446 }
447
0fe1e009
TH		 448 sd->asid_generation = 1;
449 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
450 sd->next_asid = sd->max_asid + 1;
6aa8b732 451
d6ab1ed4 452 native_store_gdt(&gdt_descr);
89a27f4d 453 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 454 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 455
9962d032 456 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 457
d0316554 458 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 459
67ec6607
JR		 460 svm_init_erratum_383();
461
10474ae8 462 return 0;
6aa8b732
AK		 463}
464
0da1db75
JR		 465static void svm_cpu_uninit(int cpu)
466{
0fe1e009 467 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 468
0fe1e009 469 if (!sd)
0da1db75
JR		 470 return;
471
472 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 473 __free_page(sd->save_area);
474 kfree(sd);
0da1db75
JR		 475}
476
6aa8b732
AK		 477static int svm_cpu_init(int cpu)
478{
0fe1e009 479 struct svm_cpu_data *sd;
6aa8b732
AK		 480 int r;
481
0fe1e009
TH		 482 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
483 if (!sd)
6aa8b732 484 return -ENOMEM;
0fe1e009
TH		 485 sd->cpu = cpu;
486 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 487 r = -ENOMEM;
0fe1e009 488 if (!sd->save_area)
6aa8b732
AK		 489 goto err_1;
490
0fe1e009 491 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 492
493 return 0;
494
495err_1:
0fe1e009 496 kfree(sd);
6aa8b732
AK		 497 return r;
498
499}
500
ac72a9b7
JR		 501static bool valid_msr_intercept(u32 index)
502{
503 int i;
504
505 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
506 if (direct_access_msrs[i].index == index)
507 return true;
508
509 return false;
510}
511
bfc733a7
RR		 512static void set_msr_interception(u32 *msrpm, unsigned msr,
513 int read, int write)
6aa8b732 514{
455716fa
JR		 515 u8 bit_read, bit_write;
516 unsigned long tmp;
517 u32 offset;
6aa8b732 518
ac72a9b7
JR		 519 /*
520 * If this warning triggers extend the direct_access_msrs list at the
521 * beginning of the file
522 */
523 WARN_ON(!valid_msr_intercept(msr));
524
455716fa
JR		 525 offset = svm_msrpm_offset(msr);
526 bit_read = 2 * (msr & 0x0f);
527 bit_write = 2 * (msr & 0x0f) + 1;
528 tmp = msrpm[offset];
529
530 BUG_ON(offset == MSR_INVALID);
531
532 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
533 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
534
535 msrpm[offset] = tmp;
6aa8b732
AK		 536}
537
f65c229c 538static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 539{
540 int i;
541
f65c229c
JR		 542 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
543
ac72a9b7
JR		 544 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
545 if (!direct_access_msrs[i].always)
546 continue;
547
548 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
549 }
f65c229c
JR		 550}
551
323c3d80
JR		 552static void add_msr_offset(u32 offset)
553{
554 int i;
555
556 for (i = 0; i < MSRPM_OFFSETS; ++i) {
557
558 /* Offset already in list? */
559 if (msrpm_offsets[i] == offset)
bfc733a7 560 return;
323c3d80
JR		 561
562 /* Slot used by another offset? */
563 if (msrpm_offsets[i] != MSR_INVALID)
564 continue;
565
566 /* Add offset to list */
567 msrpm_offsets[i] = offset;
568
569 return;
6aa8b732 570 }
323c3d80
JR		 571
572 /*
573 * If this BUG triggers the msrpm_offsets table has an overflow. Just
574 * increase MSRPM_OFFSETS in this case.
575 */
bfc733a7 576 BUG();
6aa8b732
AK		 577}
578
323c3d80 579static void init_msrpm_offsets(void)
f65c229c 580{
323c3d80 581 int i;
f65c229c 582
323c3d80
JR		 583 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
584
585 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
586 u32 offset;
587
588 offset = svm_msrpm_offset(direct_access_msrs[i].index);
589 BUG_ON(offset == MSR_INVALID);
590
591 add_msr_offset(offset);
592 }
f65c229c
JR		 593}
594
24e09cbf
JR		 595static void svm_enable_lbrv(struct vcpu_svm *svm)
596{
597 u32 *msrpm = svm->msrpm;
598
599 svm->vmcb->control.lbr_ctl = 1;
600 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
601 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
602 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
603 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
604}
605
606static void svm_disable_lbrv(struct vcpu_svm *svm)
607{
608 u32 *msrpm = svm->msrpm;
609
610 svm->vmcb->control.lbr_ctl = 0;
611 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
612 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
613 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
614 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
615}
616
6aa8b732
AK		 617static __init int svm_hardware_setup(void)
618{
619 int cpu;
620 struct page *iopm_pages;
f65c229c 621 void *iopm_va;
6aa8b732
AK		 622 int r;
623
6aa8b732
AK		 624 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
625
626 if (!iopm_pages)
627 return -ENOMEM;
c8681339
AL		 628
629 iopm_va = page_address(iopm_pages);
630 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 631 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
632
323c3d80
JR		 633 init_msrpm_offsets();
634
50a37eb4
JR		 635 if (boot_cpu_has(X86_FEATURE_NX))
636 kvm_enable_efer_bits(EFER_NX);
637
1b2fd70c
AG		 638 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
639 kvm_enable_efer_bits(EFER_FFXSR);
640
236de055
AG		 641 if (nested) {
642 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 643 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 644 }
645
3230bb47 646 for_each_possible_cpu(cpu) {
6aa8b732
AK		 647 r = svm_cpu_init(cpu);
648 if (r)
f65c229c 649 goto err;
6aa8b732 650 }
33bd6a0b
JR		 651
652 svm_features = cpuid_edx(SVM_CPUID_FUNC);
653
e3da3acd
JR		 654 if (!svm_has(SVM_FEATURE_NPT))
655 npt_enabled = false;
656
6c7dac72
JR		 657 if (npt_enabled && !npt) {
658 printk(KERN_INFO "kvm: Nested Paging disabled\n");
659 npt_enabled = false;
660 }
661
18552672 662 if (npt_enabled) {
e3da3acd 663 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 664 kvm_enable_tdp();
5f4cb662
JR		 665 } else
666 kvm_disable_tdp();
e3da3acd 667
6aa8b732
AK		 668 return 0;
669
f65c229c 670err:
6aa8b732
AK		 671 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
672 iopm_base = 0;
673 return r;
674}
675
676static __exit void svm_hardware_unsetup(void)
677{
0da1db75
JR		 678 int cpu;
679
3230bb47 680 for_each_possible_cpu(cpu)
0da1db75
JR		 681 svm_cpu_uninit(cpu);
682
6aa8b732 683 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 684 iopm_base = 0;
6aa8b732
AK		 685}
686
687static void init_seg(struct vmcb_seg *seg)
688{
689 seg->selector = 0;
690 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 691 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 692 seg->limit = 0xffff;
693 seg->base = 0;
694}
695
696static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
697{
698 seg->selector = 0;
699 seg->attrib = SVM_SELECTOR_P_MASK | type;
700 seg->limit = 0xffff;
701 seg->base = 0;
702}
703
f4e1b3c8
ZA		 704static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
705{
706 struct vcpu_svm *svm = to_svm(vcpu);
707 u64 g_tsc_offset = 0;
708
709 if (is_nested(svm)) {
710 g_tsc_offset = svm->vmcb->control.tsc_offset -
711 svm->nested.hsave->control.tsc_offset;
712 svm->nested.hsave->control.tsc_offset = offset;
713 }
714
715 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
716}
717
e48672fa
ZA		 718static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
719{
720 struct vcpu_svm *svm = to_svm(vcpu);
721
722 svm->vmcb->control.tsc_offset += adjustment;
723 if (is_nested(svm))
724 svm->nested.hsave->control.tsc_offset += adjustment;
725}
726
e6101a96 727static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 728{
e6101a96
JR		 729 struct vmcb_control_area *control = &svm->vmcb->control;
730 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 731
bff78274
AK		 732 svm->vcpu.fpu_active = 1;
733
e0231715 734 control->intercept_cr_read = INTERCEPT_CR0_MASK |
6aa8b732 735 INTERCEPT_CR3_MASK |
649d6864 736 INTERCEPT_CR4_MASK;
6aa8b732 737
e0231715 738 control->intercept_cr_write = INTERCEPT_CR0_MASK |
6aa8b732 739 INTERCEPT_CR3_MASK |
80a8119c
AK		 740 INTERCEPT_CR4_MASK |
741 INTERCEPT_CR8_MASK;
6aa8b732 742
e0231715 743 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 744 INTERCEPT_DR1_MASK |
745 INTERCEPT_DR2_MASK |
727f5a23
JK		 746 INTERCEPT_DR3_MASK |
747 INTERCEPT_DR4_MASK |
748 INTERCEPT_DR5_MASK |
749 INTERCEPT_DR6_MASK |
750 INTERCEPT_DR7_MASK;
6aa8b732 751
e0231715 752 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 753 INTERCEPT_DR1_MASK |
754 INTERCEPT_DR2_MASK |
755 INTERCEPT_DR3_MASK |
727f5a23 756 INTERCEPT_DR4_MASK |
6aa8b732 757 INTERCEPT_DR5_MASK |
727f5a23 758 INTERCEPT_DR6_MASK |
6aa8b732
AK		 759 INTERCEPT_DR7_MASK;
760
7aa81cc0 761 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 762 (1 << UD_VECTOR) |
763 (1 << MC_VECTOR);
6aa8b732
AK		 764
765
e0231715 766 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 767 (1ULL << INTERCEPT_NMI) |
0152527b 768 (1ULL << INTERCEPT_SMI) |
d225157b 769 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 770 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 771 (1ULL << INTERCEPT_INVD) |
6aa8b732 772 (1ULL << INTERCEPT_HLT) |
a7052897 773 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 774 (1ULL << INTERCEPT_INVLPGA) |
775 (1ULL << INTERCEPT_IOIO_PROT) |
776 (1ULL << INTERCEPT_MSR_PROT) |
777 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 778 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 779 (1ULL << INTERCEPT_VMRUN) |
780 (1ULL << INTERCEPT_VMMCALL) |
781 (1ULL << INTERCEPT_VMLOAD) |
782 (1ULL << INTERCEPT_VMSAVE) |
783 (1ULL << INTERCEPT_STGI) |
784 (1ULL << INTERCEPT_CLGI) |
916ce236 785 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 786 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 787 (1ULL << INTERCEPT_MONITOR) |
788 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 789
790 control->iopm_base_pa = iopm_base;
f65c229c 791 control->msrpm_base_pa = __pa(svm->msrpm);
6aa8b732
AK		 792 control->int_ctl = V_INTR_MASKING_MASK;
793
794 init_seg(&save->es);
795 init_seg(&save->ss);
796 init_seg(&save->ds);
797 init_seg(&save->fs);
798 init_seg(&save->gs);
799
800 save->cs.selector = 0xf000;
801 /* Executable/Readable Code Segment */
802 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
803 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
804 save->cs.limit = 0xffff;
d92899a0
AK		 805 /*
806 * cs.base should really be 0xffff0000, but vmx can't handle that, so
807 * be consistent with it.
808 *
809 * Replace when we have real mode working for vmx.
810 */
811 save->cs.base = 0xf0000;
6aa8b732
AK		 812
813 save->gdtr.limit = 0xffff;
814 save->idtr.limit = 0xffff;
815
816 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
817 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
818
9962d032 819 save->efer = EFER_SVME;
d77c26fc 820 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 821 save->dr7 = 0x400;
822 save->rflags = 2;
823 save->rip = 0x0000fff0;
5fdbf976 824 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 825
e0231715
JR		 826 /*
827 * This is the guest-visible cr0 value.
18fa000a 828 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 829 */
678041ad
MT		 830 svm->vcpu.arch.cr0 = 0;
831 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
18fa000a 832
66aee91a 833 save->cr4 = X86_CR4_PAE;
6aa8b732 834 /* rdx = ?? */
709ddebf
JR		 835
836 if (npt_enabled) {
837 /* Setup VMCB for Nested Paging */
838 control->nested_ctl = 1;
a7052897
MT		 839 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
840 (1ULL << INTERCEPT_INVLPG));
709ddebf 841 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 842 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
843 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 844 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 845 save->cr3 = 0;
846 save->cr4 = 0;
847 }
a79d2f18 848 force_new_asid(&svm->vcpu);
1371d904 849
e6aa9abd 850 svm->nested.vmcb = 0;
2af9194d
JR		 851 svm->vcpu.arch.hflags = 0;
852
565d0998
ML		 853 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
854 control->pause_filter_count = 3000;
855 control->intercept |= (1ULL << INTERCEPT_PAUSE);
856 }
857
2af9194d 858 enable_gif(svm);
6aa8b732
AK		 859}
860
e00c8cf2 861static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 862{
863 struct vcpu_svm *svm = to_svm(vcpu);
864
e6101a96 865 init_vmcb(svm);
70433389 866
c5af89b6 867 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 868 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 869 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
870 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 871 }
5fdbf976
MT		 872 vcpu->arch.regs_avail = ~0;
873 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 874
875 return 0;
04d2cc77
AK		 876}
877
fb3f0f51 878static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 879{
a2fa3e9f 880 struct vcpu_svm *svm;
6aa8b732 881 struct page *page;
f65c229c 882 struct page *msrpm_pages;
b286d5d8 883 struct page *hsave_page;
3d6368ef 884 struct page *nested_msrpm_pages;
fb3f0f51 885 int err;
6aa8b732 886
c16f862d 887 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 888 if (!svm) {
889 err = -ENOMEM;
890 goto out;
891 }
892
893 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
894 if (err)
895 goto free_svm;
896
b7af4043 897 err = -ENOMEM;
6aa8b732 898 page = alloc_page(GFP_KERNEL);
b7af4043 899 if (!page)
fb3f0f51 900 goto uninit;
6aa8b732 901
f65c229c
JR		 902 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
903 if (!msrpm_pages)
b7af4043 904 goto free_page1;
3d6368ef
AG		 905
906 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
907 if (!nested_msrpm_pages)
b7af4043 908 goto free_page2;
f65c229c 909
b286d5d8
AG		 910 hsave_page = alloc_page(GFP_KERNEL);
911 if (!hsave_page)
b7af4043
TY		 912 goto free_page3;
913
e6aa9abd 914 svm->nested.hsave = page_address(hsave_page);
b286d5d8 915
b7af4043
TY		 916 svm->msrpm = page_address(msrpm_pages);
917 svm_vcpu_init_msrpm(svm->msrpm);
918
e6aa9abd 919 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 920 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 921
a2fa3e9f
GH		 922 svm->vmcb = page_address(page);
923 clear_page(svm->vmcb);
924 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
925 svm->asid_generation = 0;
e6101a96 926 init_vmcb(svm);
99e3e30a 927 kvm_write_tsc(&svm->vcpu, 0);
a2fa3e9f 928
10ab25cd
JK		 929 err = fx_init(&svm->vcpu);
930 if (err)
931 goto free_page4;
932
ad312c7c 933 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 934 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 935 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 936
fb3f0f51 937 return &svm->vcpu;
36241b8c 938
10ab25cd
JK		 939free_page4:
940 __free_page(hsave_page);
b7af4043
TY		 941free_page3:
942 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
943free_page2:
944 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
945free_page1:
946 __free_page(page);
fb3f0f51
RR		 947uninit:
948 kvm_vcpu_uninit(&svm->vcpu);
949free_svm:
a4770347 950 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 951out:
952 return ERR_PTR(err);
6aa8b732
AK		 953}
954
955static void svm_free_vcpu(struct kvm_vcpu *vcpu)
956{
a2fa3e9f
GH		 957 struct vcpu_svm *svm = to_svm(vcpu);
958
fb3f0f51 959 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 960 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 961 __free_page(virt_to_page(svm->nested.hsave));
962 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 963 kvm_vcpu_uninit(vcpu);
a4770347 964 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 965}
966
15ad7146 967static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 968{
a2fa3e9f 969 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 970 int i;
0cc5064d 971
0cc5064d 972 if (unlikely(cpu != vcpu->cpu)) {
4b656b12 973 svm->asid_generation = 0;
0cc5064d 974 }
94dfbdb3
AL		 975
976 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 977 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 978}
979
980static void svm_vcpu_put(struct kvm_vcpu *vcpu)
981{
a2fa3e9f 982 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 983 int i;
984
e1beb1d3 985 ++vcpu->stat.host_state_reload;
94dfbdb3 986 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 987 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 988}
989
6aa8b732
AK		 990static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
991{
a2fa3e9f 992 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 993}
994
995static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
996{
a2fa3e9f 997 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 998}
999
6de4f3ad
AK		 1000static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1001{
1002 switch (reg) {
1003 case VCPU_EXREG_PDPTR:
1004 BUG_ON(!npt_enabled);
1005 load_pdptrs(vcpu, vcpu->arch.cr3);
1006 break;
1007 default:
1008 BUG();
1009 }
1010}
1011
f0b85051
AG		 1012static void svm_set_vintr(struct vcpu_svm *svm)
1013{
1014 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1015}
1016
1017static void svm_clear_vintr(struct vcpu_svm *svm)
1018{
1019 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1020}
1021
6aa8b732
AK		 1022static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1023{
a2fa3e9f 1024 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1025
1026 switch (seg) {
1027 case VCPU_SREG_CS: return &save->cs;
1028 case VCPU_SREG_DS: return &save->ds;
1029 case VCPU_SREG_ES: return &save->es;
1030 case VCPU_SREG_FS: return &save->fs;
1031 case VCPU_SREG_GS: return &save->gs;
1032 case VCPU_SREG_SS: return &save->ss;
1033 case VCPU_SREG_TR: return &save->tr;
1034 case VCPU_SREG_LDTR: return &save->ldtr;
1035 }
1036 BUG();
8b6d44c7 1037 return NULL;
6aa8b732
AK		 1038}
1039
1040static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1041{
1042 struct vmcb_seg *s = svm_seg(vcpu, seg);
1043
1044 return s->base;
1045}
1046
1047static void svm_get_segment(struct kvm_vcpu *vcpu,
1048 struct kvm_segment *var, int seg)
1049{
1050 struct vmcb_seg *s = svm_seg(vcpu, seg);
1051
1052 var->base = s->base;
1053 var->limit = s->limit;
1054 var->selector = s->selector;
1055 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1056 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1057 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1058 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1059 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1060 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1061 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1062 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1063
e0231715
JR		 1064 /*
1065 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1066 * for cross vendor migration purposes by "not present"
1067 */
1068 var->unusable = !var->present || (var->type == 0);
1069
1fbdc7a5
AP		 1070 switch (seg) {
1071 case VCPU_SREG_CS:
1072 /*
1073 * SVM always stores 0 for the 'G' bit in the CS selector in
1074 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1075 * Intel's VMENTRY has a check on the 'G' bit.
1076 */
25022acc 1077 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1078 break;
1079 case VCPU_SREG_TR:
1080 /*
1081 * Work around a bug where the busy flag in the tr selector
1082 * isn't exposed
1083 */
c0d09828 1084 var->type |= 0x2;
1fbdc7a5
AP		 1085 break;
1086 case VCPU_SREG_DS:
1087 case VCPU_SREG_ES:
1088 case VCPU_SREG_FS:
1089 case VCPU_SREG_GS:
1090 /*
1091 * The accessed bit must always be set in the segment
1092 * descriptor cache, although it can be cleared in the
1093 * descriptor, the cached bit always remains at 1. Since
1094 * Intel has a check on this, set it here to support
1095 * cross-vendor migration.
1096 */
1097 if (!var->unusable)
1098 var->type |= 0x1;
1099 break;
b586eb02 1100 case VCPU_SREG_SS:
e0231715
JR		 1101 /*
1102 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1103 * descriptor is left as 1, although the whole segment has
1104 * been made unusable. Clear it here to pass an Intel VMX
1105 * entry check when cross vendor migrating.
1106 */
1107 if (var->unusable)
1108 var->db = 0;
1109 break;
1fbdc7a5 1110 }
6aa8b732
AK		 1111}
1112
2e4d2653
IE		 1113static int svm_get_cpl(struct kvm_vcpu *vcpu)
1114{
1115 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1116
1117 return save->cpl;
1118}
1119
89a27f4d 1120static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1121{
a2fa3e9f
GH		 1122 struct vcpu_svm *svm = to_svm(vcpu);
1123
89a27f4d
GN		 1124 dt->size = svm->vmcb->save.idtr.limit;
1125 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1126}
1127
89a27f4d 1128static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1129{
a2fa3e9f
GH		 1130 struct vcpu_svm *svm = to_svm(vcpu);
1131
89a27f4d
GN		 1132 svm->vmcb->save.idtr.limit = dt->size;
1133 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1134}
1135
89a27f4d 1136static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1137{
a2fa3e9f
GH		 1138 struct vcpu_svm *svm = to_svm(vcpu);
1139
89a27f4d
GN		 1140 dt->size = svm->vmcb->save.gdtr.limit;
1141 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1142}
1143
89a27f4d 1144static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1145{
a2fa3e9f
GH		 1146 struct vcpu_svm *svm = to_svm(vcpu);
1147
89a27f4d
GN		 1148 svm->vmcb->save.gdtr.limit = dt->size;
1149 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1150}
1151
e8467fda
AK		 1152static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1153{
1154}
1155
25c4c276 1156static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1157{
1158}
1159
d225157b
AK		 1160static void update_cr0_intercept(struct vcpu_svm *svm)
1161{
66a562f7 1162 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1163 ulong gcr0 = svm->vcpu.arch.cr0;
1164 u64 *hcr0 = &svm->vmcb->save.cr0;
1165
1166 if (!svm->vcpu.fpu_active)
1167 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1168 else
1169 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1170 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1171
1172
1173 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1174 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1175 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1176 if (is_nested(svm)) {
1177 struct vmcb *hsave = svm->nested.hsave;
1178
1179 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1180 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1181 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1182 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1183 }
d225157b
AK		 1184 } else {
1185 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1186 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
66a562f7
JR		 1187 if (is_nested(svm)) {
1188 struct vmcb *hsave = svm->nested.hsave;
1189
1190 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1191 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1192 }
d225157b
AK		 1193 }
1194}
1195
6aa8b732
AK		 1196static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1197{
a2fa3e9f
GH		 1198 struct vcpu_svm *svm = to_svm(vcpu);
1199
7f5d8b56
JR		 1200 if (is_nested(svm)) {
1201 /*
1202 * We are here because we run in nested mode, the host kvm
1203 * intercepts cr0 writes but the l1 hypervisor does not.
1204 * But the L1 hypervisor may intercept selective cr0 writes.
1205 * This needs to be checked here.
1206 */
1207 unsigned long old, new;
1208
1209 /* Remove bits that would trigger a real cr0 write intercept */
1210 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1211 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1212
1213 if (old == new) {
1214 /* cr0 write with ts and mp unchanged */
1215 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1216 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1217 return;
1218 }
1219 }
1220
05b3e0c2 1221#ifdef CONFIG_X86_64
f6801dff 1222 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1223 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1224 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1225 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1226 }
1227
d77c26fc 1228 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1229 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1230 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1231 }
1232 }
1233#endif
ad312c7c 1234 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1235
1236 if (!npt_enabled)
1237 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1238
1239 if (!vcpu->fpu_active)
334df50a 1240 cr0 |= X86_CR0_TS;
709ddebf
JR		 1241 /*
1242 * re-enable caching here because the QEMU bios
1243 * does not do it - this results in some delay at
1244 * reboot
1245 */
1246 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1247 svm->vmcb->save.cr0 = cr0;
d225157b 1248 update_cr0_intercept(svm);
6aa8b732
AK		 1249}
1250
1251static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1252{
6394b649 1253 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1254 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1255
1256 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1257 force_new_asid(vcpu);
6394b649 1258
ec077263
JR		 1259 vcpu->arch.cr4 = cr4;
1260 if (!npt_enabled)
1261 cr4 |= X86_CR4_PAE;
6394b649 1262 cr4 |= host_cr4_mce;
ec077263 1263 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1264}
1265
1266static void svm_set_segment(struct kvm_vcpu *vcpu,
1267 struct kvm_segment *var, int seg)
1268{
a2fa3e9f 1269 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1270 struct vmcb_seg *s = svm_seg(vcpu, seg);
1271
1272 s->base = var->base;
1273 s->limit = var->limit;
1274 s->selector = var->selector;
1275 if (var->unusable)
1276 s->attrib = 0;
1277 else {
1278 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1279 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1280 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1281 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1282 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1283 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1284 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1285 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1286 }
1287 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1288 svm->vmcb->save.cpl
1289 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1290 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1291
1292}
1293
44c11430 1294static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1295{
d0bfb940
JK		 1296 struct vcpu_svm *svm = to_svm(vcpu);
1297
d0bfb940
JK		 1298 svm->vmcb->control.intercept_exceptions &=
1299 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1300
6be7d306 1301 if (svm->nmi_singlestep)
44c11430
GN		 1302 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1303
d0bfb940
JK		 1304 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1305 if (vcpu->guest_debug &
1306 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1307 svm->vmcb->control.intercept_exceptions |=
1308 1 << DB_VECTOR;
1309 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1310 svm->vmcb->control.intercept_exceptions |=
1311 1 << BP_VECTOR;
1312 } else
1313 vcpu->guest_debug = 0;
44c11430
GN		 1314}
1315
355be0b9 1316static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1317{
44c11430
GN		 1318 struct vcpu_svm *svm = to_svm(vcpu);
1319
ae675ef0
JK		 1320 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1321 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1322 else
1323 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1324
355be0b9 1325 update_db_intercept(vcpu);
6aa8b732
AK		 1326}
1327
1328static void load_host_msrs(struct kvm_vcpu *vcpu)
1329{
94dfbdb3 1330#ifdef CONFIG_X86_64
a2fa3e9f 1331 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1332#endif
6aa8b732
AK		 1333}
1334
1335static void save_host_msrs(struct kvm_vcpu *vcpu)
1336{
94dfbdb3 1337#ifdef CONFIG_X86_64
a2fa3e9f 1338 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1339#endif
6aa8b732
AK		 1340}
1341
0fe1e009 1342static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1343{
0fe1e009
TH		 1344 if (sd->next_asid > sd->max_asid) {
1345 ++sd->asid_generation;
1346 sd->next_asid = 1;
a2fa3e9f 1347 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1348 }
1349
0fe1e009
TH		 1350 svm->asid_generation = sd->asid_generation;
1351 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1352}
1353
020df079 1354static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1355{
42dbaa5a 1356 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1357
020df079 1358 svm->vmcb->save.dr7 = value;
6aa8b732
AK		 1359}
1360
851ba692 1361static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1362{
6aa8b732
AK		 1363 u64 fault_address;
1364 u32 error_code;
6aa8b732 1365
a2fa3e9f
GH		 1366 fault_address = svm->vmcb->control.exit_info_2;
1367 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1368
229456fc 1369 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1370 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1371 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1372 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1373}
1374
851ba692 1375static int db_interception(struct vcpu_svm *svm)
d0bfb940 1376{
851ba692
AK		 1377 struct kvm_run *kvm_run = svm->vcpu.run;
1378
d0bfb940 1379 if (!(svm->vcpu.guest_debug &
44c11430 1380 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1381 !svm->nmi_singlestep) {
d0bfb940
JK		 1382 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1383 return 1;
1384 }
44c11430 1385
6be7d306
JK		 1386 if (svm->nmi_singlestep) {
1387 svm->nmi_singlestep = false;
44c11430
GN		 1388 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1389 svm->vmcb->save.rflags &=
1390 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1391 update_db_intercept(&svm->vcpu);
1392 }
1393
1394 if (svm->vcpu.guest_debug &
e0231715 1395 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1396 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1397 kvm_run->debug.arch.pc =
1398 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1399 kvm_run->debug.arch.exception = DB_VECTOR;
1400 return 0;
1401 }
1402
1403 return 1;
d0bfb940
JK		 1404}
1405
851ba692 1406static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1407{
851ba692
AK		 1408 struct kvm_run *kvm_run = svm->vcpu.run;
1409
d0bfb940
JK		 1410 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1411 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1412 kvm_run->debug.arch.exception = BP_VECTOR;
1413 return 0;
1414}
1415
851ba692 1416static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1417{
1418 int er;
1419
851ba692 1420 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1421 if (er != EMULATE_DONE)
7ee5d940 1422 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1423 return 1;
1424}
1425
6b52d186 1426static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1427{
6b52d186 1428 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1429 u32 excp;
1430
1431 if (is_nested(svm)) {
1432 u32 h_excp, n_excp;
1433
1434 h_excp = svm->nested.hsave->control.intercept_exceptions;
1435 n_excp = svm->nested.intercept_exceptions;
1436 h_excp &= ~(1 << NM_VECTOR);
1437 excp = h_excp | n_excp;
1438 } else {
1439 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1440 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1441 }
1442
1443 svm->vmcb->control.intercept_exceptions = excp;
1444
e756fc62 1445 svm->vcpu.fpu_active = 1;
d225157b 1446 update_cr0_intercept(svm);
6b52d186 1447}
a2fa3e9f 1448
6b52d186
AK		 1449static int nm_interception(struct vcpu_svm *svm)
1450{
1451 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1452 return 1;
7807fa6c
AL		 1453}
1454
67ec6607
JR		 1455static bool is_erratum_383(void)
1456{
1457 int err, i;
1458 u64 value;
1459
1460 if (!erratum_383_found)
1461 return false;
1462
1463 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1464 if (err)
1465 return false;
1466
1467 /* Bit 62 may or may not be set for this mce */
1468 value &= ~(1ULL << 62);
1469
1470 if (value != 0xb600000000010015ULL)
1471 return false;
1472
1473 /* Clear MCi_STATUS registers */
1474 for (i = 0; i < 6; ++i)
1475 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1476
1477 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1478 if (!err) {
1479 u32 low, high;
1480
1481 value &= ~(1ULL << 2);
1482 low = lower_32_bits(value);
1483 high = upper_32_bits(value);
1484
1485 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1486 }
1487
1488 /* Flush tlb to evict multi-match entries */
1489 __flush_tlb_all();
1490
1491 return true;
1492}
1493
fe5913e4 1494static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1495{
67ec6607
JR		 1496 if (is_erratum_383()) {
1497 /*
1498 * Erratum 383 triggered. Guest state is corrupt so kill the
1499 * guest.
1500 */
1501 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1502
a8eeb04a 1503 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1504
1505 return;
1506 }
1507
53371b50
JR		 1508 /*
1509 * On an #MC intercept the MCE handler is not called automatically in
1510 * the host. So do it by hand here.
1511 */
1512 asm volatile (
1513 "int $0x12\n");
1514 /* not sure if we ever come back to this point */
1515
fe5913e4
JR		 1516 return;
1517}
1518
1519static int mc_interception(struct vcpu_svm *svm)
1520{
53371b50
JR		 1521 return 1;
1522}
1523
851ba692 1524static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1525{
851ba692
AK		 1526 struct kvm_run *kvm_run = svm->vcpu.run;
1527
46fe4ddd
JR		 1528 /*
1529 * VMCB is undefined after a SHUTDOWN intercept
1530 * so reinitialize it.
1531 */
a2fa3e9f 1532 clear_page(svm->vmcb);
e6101a96 1533 init_vmcb(svm);
46fe4ddd
JR		 1534
1535 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1536 return 0;
1537}
1538
851ba692 1539static int io_interception(struct vcpu_svm *svm)
6aa8b732 1540{
cf8f70bf 1541 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1542 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1543 int size, in, string;
039576c0 1544 unsigned port;
6aa8b732 1545
e756fc62 1546 ++svm->vcpu.stat.io_exits;
e70669ab 1547 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1548 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
cf8f70bf 1549 if (string || in)
6d77dbfc 1550 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
cf8f70bf 1551
039576c0
AK		 1552 port = io_info >> 16;
1553 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1554 svm->next_rip = svm->vmcb->control.exit_info_2;
e93f36bc 1555 skip_emulated_instruction(&svm->vcpu);
cf8f70bf
GN		 1556
1557 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 1558}
1559
851ba692 1560static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1561{
1562 return 1;
1563}
1564
851ba692 1565static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1566{
1567 ++svm->vcpu.stat.irq_exits;
1568 return 1;
1569}
1570
851ba692 1571static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1572{
1573 return 1;
1574}
1575
851ba692 1576static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1577{
5fdbf976 1578 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1579 skip_emulated_instruction(&svm->vcpu);
1580 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1581}
1582
851ba692 1583static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1584{
5fdbf976 1585 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1586 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1587 kvm_emulate_hypercall(&svm->vcpu);
1588 return 1;
02e235bc
AK		 1589}
1590
c0725420
AG		 1591static int nested_svm_check_permissions(struct vcpu_svm *svm)
1592{
f6801dff 1593 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1594 || !is_paging(&svm->vcpu)) {
1595 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1596 return 1;
1597 }
1598
1599 if (svm->vmcb->save.cpl) {
1600 kvm_inject_gp(&svm->vcpu, 0);
1601 return 1;
1602 }
1603
1604 return 0;
1605}
1606
cf74a78b
AG		 1607static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1608 bool has_error_code, u32 error_code)
1609{
b8e88bc8
JR		 1610 int vmexit;
1611
0295ad7d
JR		 1612 if (!is_nested(svm))
1613 return 0;
cf74a78b 1614
0295ad7d
JR		 1615 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1616 svm->vmcb->control.exit_code_hi = 0;
1617 svm->vmcb->control.exit_info_1 = error_code;
1618 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1619
b8e88bc8
JR		 1620 vmexit = nested_svm_intercept(svm);
1621 if (vmexit == NESTED_EXIT_DONE)
1622 svm->nested.exit_required = true;
1623
1624 return vmexit;
cf74a78b
AG		 1625}
1626
8fe54654
JR		 1627/* This function returns true if it is save to enable the irq window */
1628static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1629{
26666957 1630 if (!is_nested(svm))
8fe54654 1631 return true;
cf74a78b 1632
26666957 1633 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1634 return true;
cf74a78b 1635
26666957 1636 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1637 return false;
cf74a78b 1638
197717d5
JR		 1639 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1640 svm->vmcb->control.exit_info_1 = 0;
1641 svm->vmcb->control.exit_info_2 = 0;
26666957 1642
cd3ff653
JR		 1643 if (svm->nested.intercept & 1ULL) {
1644 /*
1645 * The #vmexit can't be emulated here directly because this
1646 * code path runs with irqs and preemtion disabled. A
1647 * #vmexit emulation might sleep. Only signal request for
1648 * the #vmexit here.
1649 */
1650 svm->nested.exit_required = true;
236649de 1651 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1652 return false;
cf74a78b
AG		 1653 }
1654
8fe54654 1655 return true;
cf74a78b
AG		 1656}
1657
887f500c
JR		 1658/* This function returns true if it is save to enable the nmi window */
1659static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1660{
1661 if (!is_nested(svm))
1662 return true;
1663
1664 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1665 return true;
1666
1667 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1668 svm->nested.exit_required = true;
1669
1670 return false;
cf74a78b
AG		 1671}
1672
7597f129 1673static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1674{
1675 struct page *page;
1676
6c3bd3d7
JR		 1677 might_sleep();
1678
34f80cfa 1679 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1680 if (is_error_page(page))
1681 goto error;
1682
7597f129
JR		 1683 *_page = page;
1684
1685 return kmap(page);
34f80cfa
JR		 1686
1687error:
1688 kvm_release_page_clean(page);
1689 kvm_inject_gp(&svm->vcpu, 0);
1690
1691 return NULL;
1692}
1693
7597f129 1694static void nested_svm_unmap(struct page *page)
34f80cfa 1695{
7597f129 1696 kunmap(page);
34f80cfa
JR		 1697 kvm_release_page_dirty(page);
1698}
34f80cfa 1699
ce2ac085
JR		 1700static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1701{
1702 unsigned port;
1703 u8 val, bit;
1704 u64 gpa;
34f80cfa 1705
ce2ac085
JR		 1706 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1707 return NESTED_EXIT_HOST;
34f80cfa 1708
ce2ac085
JR		 1709 port = svm->vmcb->control.exit_info_1 >> 16;
1710 gpa = svm->nested.vmcb_iopm + (port / 8);
1711 bit = port % 8;
1712 val = 0;
1713
1714 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1715 val &= (1 << bit);
1716
1717 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
34f80cfa
JR		 1718}
1719
d2477826 1720static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1721{
0d6b3537
JR		 1722 u32 offset, msr, value;
1723 int write, mask;
4c2161ae 1724
3d62d9aa 1725 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1726 return NESTED_EXIT_HOST;
3d62d9aa 1727
0d6b3537
JR		 1728 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1729 offset = svm_msrpm_offset(msr);
1730 write = svm->vmcb->control.exit_info_1 & 1;
1731 mask = 1 << ((2 * (msr & 0xf)) + write);
3d62d9aa 1732
0d6b3537
JR		 1733 if (offset == MSR_INVALID)
1734 return NESTED_EXIT_DONE;
4c2161ae 1735
0d6b3537
JR		 1736 /* Offset is in 32 bit units but need in 8 bit units */
1737 offset *= 4;
4c2161ae 1738
0d6b3537
JR		 1739 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1740 return NESTED_EXIT_DONE;
3d62d9aa 1741
0d6b3537 1742 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1743}
1744
410e4d57 1745static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1746{
cf74a78b 1747 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1748
410e4d57
JR		 1749 switch (exit_code) {
1750 case SVM_EXIT_INTR:
1751 case SVM_EXIT_NMI:
ff47a49b 1752 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
410e4d57 1753 return NESTED_EXIT_HOST;
410e4d57 1754 case SVM_EXIT_NPF:
e0231715 1755 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1756 if (npt_enabled)
1757 return NESTED_EXIT_HOST;
1758 break;
410e4d57 1759 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
e0231715 1760 /* When we're shadowing, trap PFs */
410e4d57
JR		 1761 if (!npt_enabled)
1762 return NESTED_EXIT_HOST;
1763 break;
66a562f7
JR		 1764 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1765 nm_interception(svm);
1766 break;
410e4d57
JR		 1767 default:
1768 break;
cf74a78b
AG		 1769 }
1770
410e4d57
JR		 1771 return NESTED_EXIT_CONTINUE;
1772}
1773
1774/*
1775 * If this function returns true, this #vmexit was already handled
1776 */
b8e88bc8 1777static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1778{
1779 u32 exit_code = svm->vmcb->control.exit_code;
1780 int vmexit = NESTED_EXIT_HOST;
1781
cf74a78b 1782 switch (exit_code) {
9c4e40b9 1783 case SVM_EXIT_MSR:
3d62d9aa 1784 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1785 break;
ce2ac085
JR		 1786 case SVM_EXIT_IOIO:
1787 vmexit = nested_svm_intercept_ioio(svm);
1788 break;
cf74a78b
AG		 1789 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1790 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1791 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1792 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1793 break;
1794 }
1795 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1796 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1797 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1798 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1799 break;
1800 }
1801 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1802 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1803 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1804 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1805 break;
1806 }
1807 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1808 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1809 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1810 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1811 break;
1812 }
1813 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1814 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1815 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1816 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1817 break;
1818 }
228070b1
JR		 1819 case SVM_EXIT_ERR: {
1820 vmexit = NESTED_EXIT_DONE;
1821 break;
1822 }
cf74a78b
AG		 1823 default: {
1824 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1825 if (svm->nested.intercept & exit_bits)
410e4d57 1826 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1827 }
1828 }
1829
b8e88bc8
JR		 1830 return vmexit;
1831}
1832
1833static int nested_svm_exit_handled(struct vcpu_svm *svm)
1834{
1835 int vmexit;
1836
1837 vmexit = nested_svm_intercept(svm);
1838
1839 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1840 nested_svm_vmexit(svm);
9c4e40b9
JR		 1841
1842 return vmexit;
cf74a78b
AG		 1843}
1844
0460a979
JR		 1845static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1846{
1847 struct vmcb_control_area *dst = &dst_vmcb->control;
1848 struct vmcb_control_area *from = &from_vmcb->control;
1849
1850 dst->intercept_cr_read = from->intercept_cr_read;
1851 dst->intercept_cr_write = from->intercept_cr_write;
1852 dst->intercept_dr_read = from->intercept_dr_read;
1853 dst->intercept_dr_write = from->intercept_dr_write;
1854 dst->intercept_exceptions = from->intercept_exceptions;
1855 dst->intercept = from->intercept;
1856 dst->iopm_base_pa = from->iopm_base_pa;
1857 dst->msrpm_base_pa = from->msrpm_base_pa;
1858 dst->tsc_offset = from->tsc_offset;
1859 dst->asid = from->asid;
1860 dst->tlb_ctl = from->tlb_ctl;
1861 dst->int_ctl = from->int_ctl;
1862 dst->int_vector = from->int_vector;
1863 dst->int_state = from->int_state;
1864 dst->exit_code = from->exit_code;
1865 dst->exit_code_hi = from->exit_code_hi;
1866 dst->exit_info_1 = from->exit_info_1;
1867 dst->exit_info_2 = from->exit_info_2;
1868 dst->exit_int_info = from->exit_int_info;
1869 dst->exit_int_info_err = from->exit_int_info_err;
1870 dst->nested_ctl = from->nested_ctl;
1871 dst->event_inj = from->event_inj;
1872 dst->event_inj_err = from->event_inj_err;
1873 dst->nested_cr3 = from->nested_cr3;
1874 dst->lbr_ctl = from->lbr_ctl;
1875}
1876
34f80cfa 1877static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1878{
34f80cfa 1879 struct vmcb *nested_vmcb;
e6aa9abd 1880 struct vmcb *hsave = svm->nested.hsave;
33740e40 1881 struct vmcb *vmcb = svm->vmcb;
7597f129 1882 struct page *page;
cf74a78b 1883
17897f36
JR		 1884 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1885 vmcb->control.exit_info_1,
1886 vmcb->control.exit_info_2,
1887 vmcb->control.exit_int_info,
1888 vmcb->control.exit_int_info_err);
1889
7597f129 1890 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1891 if (!nested_vmcb)
1892 return 1;
1893
06fc7772
JR		 1894 /* Exit nested SVM mode */
1895 svm->nested.vmcb = 0;
1896
cf74a78b 1897 /* Give the current vmcb to the guest */
33740e40
JR		 1898 disable_gif(svm);
1899
1900 nested_vmcb->save.es = vmcb->save.es;
1901 nested_vmcb->save.cs = vmcb->save.cs;
1902 nested_vmcb->save.ss = vmcb->save.ss;
1903 nested_vmcb->save.ds = vmcb->save.ds;
1904 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1905 nested_vmcb->save.idtr = vmcb->save.idtr;
3f6a9d16 1906 nested_vmcb->save.efer = svm->vcpu.arch.efer;
cdbbdc12 1907 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2be4fc7a 1908 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 1909 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 1910 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 1911 nested_vmcb->save.rflags = vmcb->save.rflags;
1912 nested_vmcb->save.rip = vmcb->save.rip;
1913 nested_vmcb->save.rsp = vmcb->save.rsp;
1914 nested_vmcb->save.rax = vmcb->save.rax;
1915 nested_vmcb->save.dr7 = vmcb->save.dr7;
1916 nested_vmcb->save.dr6 = vmcb->save.dr6;
1917 nested_vmcb->save.cpl = vmcb->save.cpl;
1918
1919 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1920 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1921 nested_vmcb->control.int_state = vmcb->control.int_state;
1922 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1923 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1924 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1925 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1926 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1927 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
7a190667 1928 nested_vmcb->control.next_rip = vmcb->control.next_rip;
8d23c466
AG		 1929
1930 /*
1931 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1932 * to make sure that we do not lose injected events. So check event_inj
1933 * here and copy it to exit_int_info if it is valid.
1934 * Exit_int_info and event_inj can't be both valid because the case
1935 * below only happens on a VMRUN instruction intercept which has
1936 * no valid exit_int_info set.
1937 */
1938 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1939 struct vmcb_control_area *nc = &nested_vmcb->control;
1940
1941 nc->exit_int_info = vmcb->control.event_inj;
1942 nc->exit_int_info_err = vmcb->control.event_inj_err;
1943 }
1944
33740e40
JR		 1945 nested_vmcb->control.tlb_ctl = 0;
1946 nested_vmcb->control.event_inj = 0;
1947 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1948
1949 /* We always set V_INTR_MASKING and remember the old value in hflags */
1950 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1951 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1952
cf74a78b 1953 /* Restore the original control entries */
0460a979 1954 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1955
219b65dc
AG		 1956 kvm_clear_exception_queue(&svm->vcpu);
1957 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1958
1959 /* Restore selected save entries */
1960 svm->vmcb->save.es = hsave->save.es;
1961 svm->vmcb->save.cs = hsave->save.cs;
1962 svm->vmcb->save.ss = hsave->save.ss;
1963 svm->vmcb->save.ds = hsave->save.ds;
1964 svm->vmcb->save.gdtr = hsave->save.gdtr;
1965 svm->vmcb->save.idtr = hsave->save.idtr;
1966 svm->vmcb->save.rflags = hsave->save.rflags;
1967 svm_set_efer(&svm->vcpu, hsave->save.efer);
1968 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1969 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1970 if (npt_enabled) {
1971 svm->vmcb->save.cr3 = hsave->save.cr3;
1972 svm->vcpu.arch.cr3 = hsave->save.cr3;
1973 } else {
2390218b 1974 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
cf74a78b
AG		 1975 }
1976 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1977 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1978 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1979 svm->vmcb->save.dr7 = 0;
1980 svm->vmcb->save.cpl = 0;
1981 svm->vmcb->control.exit_int_info = 0;
1982
7597f129 1983 nested_svm_unmap(page);
cf74a78b
AG		 1984
1985 kvm_mmu_reset_context(&svm->vcpu);
1986 kvm_mmu_load(&svm->vcpu);
1987
1988 return 0;
1989}
3d6368ef 1990
9738b2c9 1991static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1992{
323c3d80
JR		 1993 /*
1994 * This function merges the msr permission bitmaps of kvm and the
1995 * nested vmcb. It is omptimized in that it only merges the parts where
1996 * the kvm msr permission bitmap may contain zero bits
1997 */
3d6368ef 1998 int i;
9738b2c9 1999
323c3d80
JR		 2000 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2001 return true;
9738b2c9 2002
323c3d80
JR		 2003 for (i = 0; i < MSRPM_OFFSETS; i++) {
2004 u32 value, p;
2005 u64 offset;
9738b2c9 2006
323c3d80
JR		 2007 if (msrpm_offsets[i] == 0xffffffff)
2008 break;
3d6368ef 2009
0d6b3537
JR		 2010 p = msrpm_offsets[i];
2011 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 2012
2013 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2014 return false;
2015
2016 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2017 }
3d6368ef 2018
323c3d80 2019 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 2020
2021 return true;
3d6368ef
AG		 2022}
2023
52c65a30
JR		 2024static bool nested_vmcb_checks(struct vmcb *vmcb)
2025{
2026 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2027 return false;
2028
dbe77584
JR		 2029 if (vmcb->control.asid == 0)
2030 return false;
2031
52c65a30
JR		 2032 return true;
2033}
2034
9738b2c9 2035static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 2036{
9738b2c9 2037 struct vmcb *nested_vmcb;
e6aa9abd 2038 struct vmcb *hsave = svm->nested.hsave;
defbba56 2039 struct vmcb *vmcb = svm->vmcb;
7597f129 2040 struct page *page;
06fc7772 2041 u64 vmcb_gpa;
3d6368ef 2042
06fc7772 2043 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 2044
7597f129 2045 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 2046 if (!nested_vmcb)
2047 return false;
2048
52c65a30
JR		 2049 if (!nested_vmcb_checks(nested_vmcb)) {
2050 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2051 nested_vmcb->control.exit_code_hi = 0;
2052 nested_vmcb->control.exit_info_1 = 0;
2053 nested_vmcb->control.exit_info_2 = 0;
2054
2055 nested_svm_unmap(page);
2056
2057 return false;
2058 }
2059
ecf1405d 2060 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
0ac406de
JR		 2061 nested_vmcb->save.rip,
2062 nested_vmcb->control.int_ctl,
2063 nested_vmcb->control.event_inj,
2064 nested_vmcb->control.nested_ctl);
2065
2e554e8d
JR		 2066 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2067 nested_vmcb->control.intercept_cr_write,
2068 nested_vmcb->control.intercept_exceptions,
2069 nested_vmcb->control.intercept);
2070
3d6368ef 2071 /* Clear internal status */
219b65dc
AG		 2072 kvm_clear_exception_queue(&svm->vcpu);
2073 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 2074
e0231715
JR		 2075 /*
2076 * Save the old vmcb, so we don't need to pick what we save, but can
2077 * restore everything when a VMEXIT occurs
2078 */
defbba56
JR		 2079 hsave->save.es = vmcb->save.es;
2080 hsave->save.cs = vmcb->save.cs;
2081 hsave->save.ss = vmcb->save.ss;
2082 hsave->save.ds = vmcb->save.ds;
2083 hsave->save.gdtr = vmcb->save.gdtr;
2084 hsave->save.idtr = vmcb->save.idtr;
f6801dff 2085 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 2086 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 2087 hsave->save.cr4 = svm->vcpu.arch.cr4;
2088 hsave->save.rflags = vmcb->save.rflags;
2089 hsave->save.rip = svm->next_rip;
2090 hsave->save.rsp = vmcb->save.rsp;
2091 hsave->save.rax = vmcb->save.rax;
2092 if (npt_enabled)
2093 hsave->save.cr3 = vmcb->save.cr3;
2094 else
2095 hsave->save.cr3 = svm->vcpu.arch.cr3;
2096
0460a979 2097 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 2098
2099 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2100 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2101 else
2102 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2103
2104 /* Load the nested guest state */
2105 svm->vmcb->save.es = nested_vmcb->save.es;
2106 svm->vmcb->save.cs = nested_vmcb->save.cs;
2107 svm->vmcb->save.ss = nested_vmcb->save.ss;
2108 svm->vmcb->save.ds = nested_vmcb->save.ds;
2109 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2110 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2111 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2112 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2113 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2114 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2115 if (npt_enabled) {
2116 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2117 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2118 } else
2390218b 2119 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2120
2121 /* Guest paging mode is active - reset mmu */
2122 kvm_mmu_reset_context(&svm->vcpu);
2123
defbba56 2124 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2125 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2126 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2127 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2128
3d6368ef
AG		 2129 /* In case we don't even reach vcpu_run, the fields are not updated */
2130 svm->vmcb->save.rax = nested_vmcb->save.rax;
2131 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2132 svm->vmcb->save.rip = nested_vmcb->save.rip;
2133 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2134 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2135 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2136
f7138538 2137 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2138 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2139
aad42c64
JR		 2140 /* cache intercepts */
2141 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2142 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2143 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2144 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2145 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2146 svm->nested.intercept = nested_vmcb->control.intercept;
2147
3d6368ef 2148 force_new_asid(&svm->vcpu);
3d6368ef 2149 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2150 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2151 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2152 else
2153 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2154
88ab24ad
JR		 2155 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2156 /* We only want the cr8 intercept bits of the guest */
2157 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2158 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2159 }
2160
0d945bd9
JR		 2161 /* We don't want to see VMMCALLs from a nested guest */
2162 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2163
e0231715
JR		 2164 /*
2165 * We don't want a nested guest to be more powerful than the guest, so
2166 * all intercepts are ORed
2167 */
88ab24ad
JR		 2168 svm->vmcb->control.intercept_cr_read |=
2169 nested_vmcb->control.intercept_cr_read;
2170 svm->vmcb->control.intercept_cr_write |=
2171 nested_vmcb->control.intercept_cr_write;
2172 svm->vmcb->control.intercept_dr_read |=
2173 nested_vmcb->control.intercept_dr_read;
2174 svm->vmcb->control.intercept_dr_write |=
2175 nested_vmcb->control.intercept_dr_write;
2176 svm->vmcb->control.intercept_exceptions |=
2177 nested_vmcb->control.intercept_exceptions;
2178
2179 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2180
2181 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2182 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2183 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2184 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2185 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2186 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2187
7597f129 2188 nested_svm_unmap(page);
9738b2c9 2189
06fc7772
JR		 2190 /* nested_vmcb is our indicator if nested SVM is activated */
2191 svm->nested.vmcb = vmcb_gpa;
9738b2c9 2192
2af9194d 2193 enable_gif(svm);
3d6368ef 2194
9738b2c9 2195 return true;
3d6368ef
AG		 2196}
2197
9966bf68 2198static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2199{
2200 to_vmcb->save.fs = from_vmcb->save.fs;
2201 to_vmcb->save.gs = from_vmcb->save.gs;
2202 to_vmcb->save.tr = from_vmcb->save.tr;
2203 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2204 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2205 to_vmcb->save.star = from_vmcb->save.star;
2206 to_vmcb->save.lstar = from_vmcb->save.lstar;
2207 to_vmcb->save.cstar = from_vmcb->save.cstar;
2208 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2209 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2210 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2211 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2212}
2213
851ba692 2214static int vmload_interception(struct vcpu_svm *svm)
5542675b 2215{
9966bf68 2216 struct vmcb *nested_vmcb;
7597f129 2217 struct page *page;
9966bf68 2218
5542675b
AG		 2219 if (nested_svm_check_permissions(svm))
2220 return 1;
2221
2222 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2223 skip_emulated_instruction(&svm->vcpu);
2224
7597f129 2225 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2226 if (!nested_vmcb)
2227 return 1;
2228
2229 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2230 nested_svm_unmap(page);
5542675b
AG		 2231
2232 return 1;
2233}
2234
851ba692 2235static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2236{
9966bf68 2237 struct vmcb *nested_vmcb;
7597f129 2238 struct page *page;
9966bf68 2239
5542675b
AG		 2240 if (nested_svm_check_permissions(svm))
2241 return 1;
2242
2243 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2244 skip_emulated_instruction(&svm->vcpu);
2245
7597f129 2246 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2247 if (!nested_vmcb)
2248 return 1;
2249
2250 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2251 nested_svm_unmap(page);
5542675b
AG		 2252
2253 return 1;
2254}
2255
851ba692 2256static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2257{
3d6368ef
AG		 2258 if (nested_svm_check_permissions(svm))
2259 return 1;
2260
2261 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2262 skip_emulated_instruction(&svm->vcpu);
2263
9738b2c9 2264 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2265 return 1;
2266
9738b2c9 2267 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2268 goto failed;
2269
2270 return 1;
2271
2272failed:
2273
2274 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2275 svm->vmcb->control.exit_code_hi = 0;
2276 svm->vmcb->control.exit_info_1 = 0;
2277 svm->vmcb->control.exit_info_2 = 0;
2278
2279 nested_svm_vmexit(svm);
3d6368ef
AG		 2280
2281 return 1;
2282}
2283
851ba692 2284static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2285{
2286 if (nested_svm_check_permissions(svm))
2287 return 1;
2288
2289 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2290 skip_emulated_instruction(&svm->vcpu);
2291
2af9194d 2292 enable_gif(svm);
1371d904
AG		 2293
2294 return 1;
2295}
2296
851ba692 2297static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2298{
2299 if (nested_svm_check_permissions(svm))
2300 return 1;
2301
2302 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2303 skip_emulated_instruction(&svm->vcpu);
2304
2af9194d 2305 disable_gif(svm);
1371d904
AG		 2306
2307 /* After a CLGI no interrupts should come */
2308 svm_clear_vintr(svm);
2309 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2310
2311 return 1;
2312}
2313
851ba692 2314static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2315{
2316 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2317
ec1ff790
JR		 2318 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2319 vcpu->arch.regs[VCPU_REGS_RAX]);
2320
ff092385
AG		 2321 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2322 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2323
2324 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2325 skip_emulated_instruction(&svm->vcpu);
2326 return 1;
2327}
2328
532a46b9
JR		 2329static int skinit_interception(struct vcpu_svm *svm)
2330{
2331 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2332
2333 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2334 return 1;
2335}
2336
851ba692 2337static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2338{
7ee5d940 2339 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2340 return 1;
2341}
2342
851ba692 2343static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2344{
37817f29 2345 u16 tss_selector;
64a7ec06
GN		 2346 int reason;
2347 int int_type = svm->vmcb->control.exit_int_info &
2348 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2349 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2350 uint32_t type =
2351 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2352 uint32_t idt_v =
2353 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2354 bool has_error_code = false;
2355 u32 error_code = 0;
37817f29
IE		 2356
2357 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2358
37817f29
IE		 2359 if (svm->vmcb->control.exit_info_2 &
2360 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2361 reason = TASK_SWITCH_IRET;
2362 else if (svm->vmcb->control.exit_info_2 &
2363 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2364 reason = TASK_SWITCH_JMP;
fe8e7f83 2365 else if (idt_v)
64a7ec06
GN		 2366 reason = TASK_SWITCH_GATE;
2367 else
2368 reason = TASK_SWITCH_CALL;
2369
fe8e7f83
GN		 2370 if (reason == TASK_SWITCH_GATE) {
2371 switch (type) {
2372 case SVM_EXITINTINFO_TYPE_NMI:
2373 svm->vcpu.arch.nmi_injected = false;
2374 break;
2375 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2376 if (svm->vmcb->control.exit_info_2 &
2377 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2378 has_error_code = true;
2379 error_code =
2380 (u32)svm->vmcb->control.exit_info_2;
2381 }
fe8e7f83
GN		 2382 kvm_clear_exception_queue(&svm->vcpu);
2383 break;
2384 case SVM_EXITINTINFO_TYPE_INTR:
2385 kvm_clear_interrupt_queue(&svm->vcpu);
2386 break;
2387 default:
2388 break;
2389 }
2390 }
64a7ec06 2391
8317c298
GN		 2392 if (reason != TASK_SWITCH_GATE ||
2393 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2394 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2395 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2396 skip_emulated_instruction(&svm->vcpu);
64a7ec06 2397
acb54517
GN		 2398 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2399 has_error_code, error_code) == EMULATE_FAIL) {
2400 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2401 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2402 svm->vcpu.run->internal.ndata = 0;
2403 return 0;
2404 }
2405 return 1;
6aa8b732
AK		 2406}
2407
851ba692 2408static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2409{
5fdbf976 2410 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2411 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2412 return 1;
6aa8b732
AK		 2413}
2414
851ba692 2415static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2416{
2417 ++svm->vcpu.stat.nmi_window_exits;
061e2fd1 2418 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
44c11430 2419 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2420 return 1;
2421}
2422
851ba692 2423static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2424{
6d77dbfc 2425 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
a7052897
MT		 2426}
2427
851ba692 2428static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2429{
6d77dbfc 2430 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
6aa8b732
AK		 2431}
2432
851ba692 2433static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2434{
851ba692
AK		 2435 struct kvm_run *kvm_run = svm->vcpu.run;
2436
0a5fff19
GN		 2437 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2438 /* instruction emulation calls kvm_set_cr8() */
851ba692 2439 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2440 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2441 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2442 return 1;
95ba8273 2443 }
0a5fff19
GN		 2444 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2445 return 1;
1d075434
JR		 2446 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2447 return 0;
2448}
2449
6aa8b732
AK		 2450static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2451{
a2fa3e9f
GH		 2452 struct vcpu_svm *svm = to_svm(vcpu);
2453
6aa8b732 2454 switch (ecx) {
af24a4e4 2455 case MSR_IA32_TSC: {
20824f30 2456 u64 tsc_offset;
6aa8b732 2457
20824f30
JR		 2458 if (is_nested(svm))
2459 tsc_offset = svm->nested.hsave->control.tsc_offset;
2460 else
2461 tsc_offset = svm->vmcb->control.tsc_offset;
2462
2463 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2464 break;
2465 }
8c06585d 2466 case MSR_STAR:
a2fa3e9f 2467 *data = svm->vmcb->save.star;
6aa8b732 2468 break;
0e859cac 2469#ifdef CONFIG_X86_64
6aa8b732 2470 case MSR_LSTAR:
a2fa3e9f 2471 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2472 break;
2473 case MSR_CSTAR:
a2fa3e9f 2474 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2475 break;
2476 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2477 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2478 break;
2479 case MSR_SYSCALL_MASK:
a2fa3e9f 2480 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2481 break;
2482#endif
2483 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2484 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2485 break;
2486 case MSR_IA32_SYSENTER_EIP:
017cb99e 2487 *data = svm->sysenter_eip;
6aa8b732
AK		 2488 break;
2489 case MSR_IA32_SYSENTER_ESP:
017cb99e 2490 *data = svm->sysenter_esp;
6aa8b732 2491 break;
e0231715
JR		 2492 /*
2493 * Nobody will change the following 5 values in the VMCB so we can
2494 * safely return them on rdmsr. They will always be 0 until LBRV is
2495 * implemented.
2496 */
a2938c80
JR		 2497 case MSR_IA32_DEBUGCTLMSR:
2498 *data = svm->vmcb->save.dbgctl;
2499 break;
2500 case MSR_IA32_LASTBRANCHFROMIP:
2501 *data = svm->vmcb->save.br_from;
2502 break;
2503 case MSR_IA32_LASTBRANCHTOIP:
2504 *data = svm->vmcb->save.br_to;
2505 break;
2506 case MSR_IA32_LASTINTFROMIP:
2507 *data = svm->vmcb->save.last_excp_from;
2508 break;
2509 case MSR_IA32_LASTINTTOIP:
2510 *data = svm->vmcb->save.last_excp_to;
2511 break;
b286d5d8 2512 case MSR_VM_HSAVE_PA:
e6aa9abd 2513 *data = svm->nested.hsave_msr;
b286d5d8 2514 break;
eb6f302e 2515 case MSR_VM_CR:
4a810181 2516 *data = svm->nested.vm_cr_msr;
eb6f302e 2517 break;
c8a73f18
AG		 2518 case MSR_IA32_UCODE_REV:
2519 *data = 0x01000065;
2520 break;
6aa8b732 2521 default:
3bab1f5d 2522 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2523 }
2524 return 0;
2525}
2526
851ba692 2527static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2528{
ad312c7c 2529 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2530 u64 data;
2531
59200273
AK		 2532 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2533 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2534 kvm_inject_gp(&svm->vcpu, 0);
59200273 2535 } else {
229456fc 2536 trace_kvm_msr_read(ecx, data);
af9ca2d7 2537
5fdbf976 2538 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2539 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2540 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2541 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2542 }
2543 return 1;
2544}
2545
4a810181
JR		 2546static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2547{
2548 struct vcpu_svm *svm = to_svm(vcpu);
2549 int svm_dis, chg_mask;
2550
2551 if (data & ~SVM_VM_CR_VALID_MASK)
2552 return 1;
2553
2554 chg_mask = SVM_VM_CR_VALID_MASK;
2555
2556 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2557 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2558
2559 svm->nested.vm_cr_msr &= ~chg_mask;
2560 svm->nested.vm_cr_msr |= (data & chg_mask);
2561
2562 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2563
2564 /* check for svm_disable while efer.svme is set */
2565 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2566 return 1;
2567
2568 return 0;
2569}
2570
6aa8b732
AK		 2571static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2572{
a2fa3e9f
GH		 2573 struct vcpu_svm *svm = to_svm(vcpu);
2574
6aa8b732 2575 switch (ecx) {
f4e1b3c8 2576 case MSR_IA32_TSC:
99e3e30a 2577 kvm_write_tsc(vcpu, data);
6aa8b732 2578 break;
8c06585d 2579 case MSR_STAR:
a2fa3e9f 2580 svm->vmcb->save.star = data;
6aa8b732 2581 break;
49b14f24 2582#ifdef CONFIG_X86_64
6aa8b732 2583 case MSR_LSTAR:
a2fa3e9f 2584 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2585 break;
2586 case MSR_CSTAR:
a2fa3e9f 2587 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2588 break;
2589 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2590 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2591 break;
2592 case MSR_SYSCALL_MASK:
a2fa3e9f 2593 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2594 break;
2595#endif
2596 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2597 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2598 break;
2599 case MSR_IA32_SYSENTER_EIP:
017cb99e 2600 svm->sysenter_eip = data;
a2fa3e9f 2601 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2602 break;
2603 case MSR_IA32_SYSENTER_ESP:
017cb99e 2604 svm->sysenter_esp = data;
a2fa3e9f 2605 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2606 break;
a2938c80 2607 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2608 if (!svm_has(SVM_FEATURE_LBRV)) {
2609 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2610 __func__, data);
24e09cbf
JR		 2611 break;
2612 }
2613 if (data & DEBUGCTL_RESERVED_BITS)
2614 return 1;
2615
2616 svm->vmcb->save.dbgctl = data;
2617 if (data & (1ULL<<0))
2618 svm_enable_lbrv(svm);
2619 else
2620 svm_disable_lbrv(svm);
a2938c80 2621 break;
b286d5d8 2622 case MSR_VM_HSAVE_PA:
e6aa9abd 2623 svm->nested.hsave_msr = data;
62b9abaa 2624 break;
3c5d0a44 2625 case MSR_VM_CR:
4a810181 2626 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2627 case MSR_VM_IGNNE:
3c5d0a44
AG		 2628 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2629 break;
6aa8b732 2630 default:
3bab1f5d 2631 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2632 }
2633 return 0;
2634}
2635
851ba692 2636static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2637{
ad312c7c 2638 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2639 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2640 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2641
af9ca2d7 2642
5fdbf976 2643 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2644 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2645 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2646 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2647 } else {
2648 trace_kvm_msr_write(ecx, data);
e756fc62 2649 skip_emulated_instruction(&svm->vcpu);
59200273 2650 }
6aa8b732
AK		 2651 return 1;
2652}
2653
851ba692 2654static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2655{
e756fc62 2656 if (svm->vmcb->control.exit_info_1)
851ba692 2657 return wrmsr_interception(svm);
6aa8b732 2658 else
851ba692 2659 return rdmsr_interception(svm);
6aa8b732
AK		 2660}
2661
851ba692 2662static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2663{
851ba692
AK		 2664 struct kvm_run *kvm_run = svm->vcpu.run;
2665
f0b85051 2666 svm_clear_vintr(svm);
85f455f7 2667 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2668 /*
2669 * If the user space waits to inject interrupts, exit as soon as
2670 * possible
2671 */
8061823a
GN		 2672 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2673 kvm_run->request_interrupt_window &&
2674 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2675 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2676 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2677 return 0;
2678 }
2679
2680 return 1;
2681}
2682
565d0998
ML		 2683static int pause_interception(struct vcpu_svm *svm)
2684{
2685 kvm_vcpu_on_spin(&(svm->vcpu));
2686 return 1;
2687}
2688
851ba692 2689static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2690 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2691 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2692 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2693 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2694 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
e0231715
JR		 2695 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2696 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2697 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2698 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2699 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2700 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2701 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2702 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2703 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2704 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2705 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2706 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2707 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2708 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2709 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2710 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2711 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2712 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2713 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2714 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2715 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2716 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2717 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2718 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2719 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2720 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2721 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2722 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2723 [SVM_EXIT_SMI] = nop_on_interception,
2724 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2725 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2726 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2727 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2728 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2729 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2730 [SVM_EXIT_HLT] = halt_interception,
a7052897 2731 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2732 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2733 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2734 [SVM_EXIT_MSR] = msr_interception,
2735 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2736 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2737 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2738 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2739 [SVM_EXIT_VMLOAD] = vmload_interception,
2740 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2741 [SVM_EXIT_STGI] = stgi_interception,
2742 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2743 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2744 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2745 [SVM_EXIT_MONITOR] = invalid_op_interception,
2746 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2747 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2748};
2749
3f10c846
JR		 2750void dump_vmcb(struct kvm_vcpu *vcpu)
2751{
2752 struct vcpu_svm *svm = to_svm(vcpu);
2753 struct vmcb_control_area *control = &svm->vmcb->control;
2754 struct vmcb_save_area *save = &svm->vmcb->save;
2755
2756 pr_err("VMCB Control Area:\n");
2757 pr_err("cr_read: %04x\n", control->intercept_cr_read);
2758 pr_err("cr_write: %04x\n", control->intercept_cr_write);
2759 pr_err("dr_read: %04x\n", control->intercept_dr_read);
2760 pr_err("dr_write: %04x\n", control->intercept_dr_write);
2761 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2762 pr_err("intercepts: %016llx\n", control->intercept);
2763 pr_err("pause filter count: %d\n", control->pause_filter_count);
2764 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2765 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2766 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2767 pr_err("asid: %d\n", control->asid);
2768 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2769 pr_err("int_ctl: %08x\n", control->int_ctl);
2770 pr_err("int_vector: %08x\n", control->int_vector);
2771 pr_err("int_state: %08x\n", control->int_state);
2772 pr_err("exit_code: %08x\n", control->exit_code);
2773 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2774 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2775 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2776 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2777 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2778 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2779 pr_err("event_inj: %08x\n", control->event_inj);
2780 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2781 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2782 pr_err("next_rip: %016llx\n", control->next_rip);
2783 pr_err("VMCB State Save Area:\n");
2784 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2785 save->es.selector, save->es.attrib,
2786 save->es.limit, save->es.base);
2787 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2788 save->cs.selector, save->cs.attrib,
2789 save->cs.limit, save->cs.base);
2790 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2791 save->ss.selector, save->ss.attrib,
2792 save->ss.limit, save->ss.base);
2793 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2794 save->ds.selector, save->ds.attrib,
2795 save->ds.limit, save->ds.base);
2796 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2797 save->fs.selector, save->fs.attrib,
2798 save->fs.limit, save->fs.base);
2799 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2800 save->gs.selector, save->gs.attrib,
2801 save->gs.limit, save->gs.base);
2802 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2803 save->gdtr.selector, save->gdtr.attrib,
2804 save->gdtr.limit, save->gdtr.base);
2805 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2806 save->ldtr.selector, save->ldtr.attrib,
2807 save->ldtr.limit, save->ldtr.base);
2808 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2809 save->idtr.selector, save->idtr.attrib,
2810 save->idtr.limit, save->idtr.base);
2811 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2812 save->tr.selector, save->tr.attrib,
2813 save->tr.limit, save->tr.base);
2814 pr_err("cpl: %d efer: %016llx\n",
2815 save->cpl, save->efer);
2816 pr_err("cr0: %016llx cr2: %016llx\n",
2817 save->cr0, save->cr2);
2818 pr_err("cr3: %016llx cr4: %016llx\n",
2819 save->cr3, save->cr4);
2820 pr_err("dr6: %016llx dr7: %016llx\n",
2821 save->dr6, save->dr7);
2822 pr_err("rip: %016llx rflags: %016llx\n",
2823 save->rip, save->rflags);
2824 pr_err("rsp: %016llx rax: %016llx\n",
2825 save->rsp, save->rax);
2826 pr_err("star: %016llx lstar: %016llx\n",
2827 save->star, save->lstar);
2828 pr_err("cstar: %016llx sfmask: %016llx\n",
2829 save->cstar, save->sfmask);
2830 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2831 save->kernel_gs_base, save->sysenter_cs);
2832 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2833 save->sysenter_esp, save->sysenter_eip);
2834 pr_err("gpat: %016llx dbgctl: %016llx\n",
2835 save->g_pat, save->dbgctl);
2836 pr_err("br_from: %016llx br_to: %016llx\n",
2837 save->br_from, save->br_to);
2838 pr_err("excp_from: %016llx excp_to: %016llx\n",
2839 save->last_excp_from, save->last_excp_to);
2840
2841}
2842
851ba692 2843static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2844{
04d2cc77 2845 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2846 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2847 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2848
5bfd8b54 2849 trace_kvm_exit(exit_code, vcpu);
af9ca2d7 2850
2be4fc7a
JR		 2851 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2852 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2853 if (npt_enabled)
2854 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 2855
cd3ff653
JR		 2856 if (unlikely(svm->nested.exit_required)) {
2857 nested_svm_vmexit(svm);
2858 svm->nested.exit_required = false;
2859
2860 return 1;
2861 }
2862
cf74a78b 2863 if (is_nested(svm)) {
410e4d57
JR		 2864 int vmexit;
2865
d8cabddf
JR		 2866 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2867 svm->vmcb->control.exit_info_1,
2868 svm->vmcb->control.exit_info_2,
2869 svm->vmcb->control.exit_int_info,
2870 svm->vmcb->control.exit_int_info_err);
2871
410e4d57
JR		 2872 vmexit = nested_svm_exit_special(svm);
2873
2874 if (vmexit == NESTED_EXIT_CONTINUE)
2875 vmexit = nested_svm_exit_handled(svm);
2876
2877 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2878 return 1;
cf74a78b
AG		 2879 }
2880
a5c3832d
JR		 2881 svm_complete_interrupts(svm);
2882
04d2cc77
AK		 2883 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2884 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2885 kvm_run->fail_entry.hardware_entry_failure_reason
2886 = svm->vmcb->control.exit_code;
3f10c846
JR		 2887 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
2888 dump_vmcb(vcpu);
04d2cc77
AK		 2889 return 0;
2890 }
2891
a2fa3e9f 2892 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2893 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2894 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2895 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2896 "exit_code 0x%x\n",
b8688d51 2897 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2898 exit_code);
2899
9d8f549d 2900 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2901 || !svm_exit_handlers[exit_code]) {
6aa8b732 2902 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2903 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2904 return 0;
2905 }
2906
851ba692 2907 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2908}
2909
2910static void reload_tss(struct kvm_vcpu *vcpu)
2911{
2912 int cpu = raw_smp_processor_id();
2913
0fe1e009
TH		 2914 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2915 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2916 load_TR_desc();
2917}
2918
e756fc62 2919static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2920{
2921 int cpu = raw_smp_processor_id();
2922
0fe1e009 2923 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2924
a2fa3e9f 2925 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2926 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2927 if (svm->asid_generation != sd->asid_generation)
2928 new_asid(svm, sd);
6aa8b732
AK		 2929}
2930
95ba8273
GN		 2931static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2932{
2933 struct vcpu_svm *svm = to_svm(vcpu);
2934
2935 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2936 vcpu->arch.hflags |= HF_NMI_MASK;
061e2fd1 2937 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
95ba8273
GN		 2938 ++vcpu->stat.nmi_injections;
2939}
6aa8b732 2940
85f455f7 2941static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2942{
2943 struct vmcb_control_area *control;
2944
e756fc62 2945 control = &svm->vmcb->control;
85f455f7 2946 control->int_vector = irq;
6aa8b732
AK		 2947 control->int_ctl &= ~V_INTR_PRIO_MASK;
2948 control->int_ctl |= V_IRQ_MASK |
2949 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2950}
2951
66fd3f7f 2952static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2953{
2954 struct vcpu_svm *svm = to_svm(vcpu);
2955
2af9194d 2956 BUG_ON(!(gif_set(svm)));
cf74a78b 2957
9fb2d2b4
GN		 2958 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
2959 ++vcpu->stat.irq_injections;
2960
219b65dc
AG		 2961 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2962 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2963}
2964
95ba8273 2965static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2966{
2967 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2968
88ab24ad
JR		 2969 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2970 return;
2971
95ba8273 2972 if (irr == -1)
aaacfc9a
JR		 2973 return;
2974
95ba8273
GN		 2975 if (tpr >= irr)
2976 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2977}
aaacfc9a 2978
95ba8273
GN		 2979static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2980{
2981 struct vcpu_svm *svm = to_svm(vcpu);
2982 struct vmcb *vmcb = svm->vmcb;
924584cc
JR		 2983 int ret;
2984 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2985 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2986 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
2987
2988 return ret;
aaacfc9a
JR		 2989}
2990
3cfc3092
JK		 2991static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2992{
2993 struct vcpu_svm *svm = to_svm(vcpu);
2994
2995 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2996}
2997
2998static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2999{
3000 struct vcpu_svm *svm = to_svm(vcpu);
3001
3002 if (masked) {
3003 svm->vcpu.arch.hflags |= HF_NMI_MASK;
061e2fd1 3004 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3005 } else {
3006 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
061e2fd1 3007 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3008 }
3009}
3010
78646121
GN		 3011static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3012{
3013 struct vcpu_svm *svm = to_svm(vcpu);
3014 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 3015 int ret;
3016
3017 if (!gif_set(svm) ||
3018 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3019 return 0;
3020
3021 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3022
3023 if (is_nested(svm))
3024 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3025
3026 return ret;
78646121
GN		 3027}
3028
9222be18 3029static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3030{
219b65dc 3031 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3032
e0231715
JR		 3033 /*
3034 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3035 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3036 * get that intercept, this function will be called again though and
3037 * we'll get the vintr intercept.
3038 */
8fe54654 3039 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 3040 svm_set_vintr(svm);
3041 svm_inject_irq(svm, 0x0);
3042 }
85f455f7
ED		 3043}
3044
95ba8273 3045static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3046{
04d2cc77 3047 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3048
44c11430
GN		 3049 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3050 == HF_NMI_MASK)
3051 return; /* IRET will cause a vm exit */
3052
e0231715
JR		 3053 /*
3054 * Something prevents NMI from been injected. Single step over possible
3055 * problem (IRET or exception injection or interrupt shadow)
3056 */
6be7d306 3057 svm->nmi_singlestep = true;
44c11430
GN		 3058 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3059 update_db_intercept(vcpu);
c1150d8c
DL		 3060}
3061
cbc94022
IE		 3062static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3063{
3064 return 0;
3065}
3066
d9e368d6
AK		 3067static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3068{
3069 force_new_asid(vcpu);
3070}
3071
04d2cc77
AK		 3072static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3073{
3074}
3075
d7bf8221
JR		 3076static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3077{
3078 struct vcpu_svm *svm = to_svm(vcpu);
3079
88ab24ad
JR		 3080 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3081 return;
3082
d7bf8221
JR		 3083 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3084 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3085 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3086 }
3087}
3088
649d6864
JR		 3089static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3090{
3091 struct vcpu_svm *svm = to_svm(vcpu);
3092 u64 cr8;
3093
88ab24ad
JR		 3094 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3095 return;
3096
649d6864
JR		 3097 cr8 = kvm_get_cr8(vcpu);
3098 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3099 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3100}
3101
9222be18
GN		 3102static void svm_complete_interrupts(struct vcpu_svm *svm)
3103{
3104 u8 vector;
3105 int type;
3106 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3107 unsigned int3_injected = svm->int3_injected;
3108
3109 svm->int3_injected = 0;
9222be18 3110
44c11430
GN		 3111 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
3112 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3113
9222be18
GN		 3114 svm->vcpu.arch.nmi_injected = false;
3115 kvm_clear_exception_queue(&svm->vcpu);
3116 kvm_clear_interrupt_queue(&svm->vcpu);
3117
3118 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3119 return;
3120
3121 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3122 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3123
3124 switch (type) {
3125 case SVM_EXITINTINFO_TYPE_NMI:
3126 svm->vcpu.arch.nmi_injected = true;
3127 break;
3128 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3129 /*
3130 * In case of software exceptions, do not reinject the vector,
3131 * but re-execute the instruction instead. Rewind RIP first
3132 * if we emulated INT3 before.
3133 */
3134 if (kvm_exception_is_soft(vector)) {
3135 if (vector == BP_VECTOR && int3_injected &&
3136 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3137 kvm_rip_write(&svm->vcpu,
3138 kvm_rip_read(&svm->vcpu) -
3139 int3_injected);
9222be18 3140 break;
66b7138f 3141 }
9222be18
GN		 3142 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3143 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3144 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3145
3146 } else
ce7ddec4 3147 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3148 break;
3149 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3150 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3151 break;
3152 default:
3153 break;
3154 }
3155}
3156
80e31d4f
AK		 3157#ifdef CONFIG_X86_64
3158#define R "r"
3159#else
3160#define R "e"
3161#endif
3162
851ba692 3163static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3164{
a2fa3e9f 3165 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 3166 u16 fs_selector;
3167 u16 gs_selector;
3168 u16 ldt_selector;
d9e368d6 3169
2041a06a
JR		 3170 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3171 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3172 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3173
cd3ff653
JR		 3174 /*
3175 * A vmexit emulation is required before the vcpu can be executed
3176 * again.
3177 */
3178 if (unlikely(svm->nested.exit_required))
3179 return;
3180
e756fc62 3181 pre_svm_run(svm);
6aa8b732 3182
649d6864
JR		 3183 sync_lapic_to_cr8(vcpu);
3184
6aa8b732 3185 save_host_msrs(vcpu);
9581d442
AK		 3186 savesegment(fs, fs_selector);
3187 savesegment(gs, gs_selector);
d6e88aec 3188 ldt_selector = kvm_read_ldt();
cda0ffdd 3189 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 3190 /* required for live migration with NPT */
3191 if (npt_enabled)
3192 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 3193
04d2cc77
AK		 3194 clgi();
3195
3196 local_irq_enable();
36241b8c 3197
6aa8b732 3198 asm volatile (
80e31d4f
AK		 3199 "push %%"R"bp; \n\t"
3200 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3201 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3202 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3203 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3204 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3205 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3206#ifdef CONFIG_X86_64
fb3f0f51
RR		 3207 "mov %c[r8](%[svm]), %%r8 \n\t"
3208 "mov %c[r9](%[svm]), %%r9 \n\t"
3209 "mov %c[r10](%[svm]), %%r10 \n\t"
3210 "mov %c[r11](%[svm]), %%r11 \n\t"
3211 "mov %c[r12](%[svm]), %%r12 \n\t"
3212 "mov %c[r13](%[svm]), %%r13 \n\t"
3213 "mov %c[r14](%[svm]), %%r14 \n\t"
3214 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3215#endif
3216
6aa8b732 3217 /* Enter guest mode */
80e31d4f
AK		 3218 "push %%"R"ax \n\t"
3219 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3220 __ex(SVM_VMLOAD) "\n\t"
3221 __ex(SVM_VMRUN) "\n\t"
3222 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3223 "pop %%"R"ax \n\t"
6aa8b732
AK		 3224
3225 /* Save guest registers, load host registers */
80e31d4f
AK		 3226 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3227 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3228 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3229 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3230 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3231 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3232#ifdef CONFIG_X86_64
fb3f0f51
RR		 3233 "mov %%r8, %c[r8](%[svm]) \n\t"
3234 "mov %%r9, %c[r9](%[svm]) \n\t"
3235 "mov %%r10, %c[r10](%[svm]) \n\t"
3236 "mov %%r11, %c[r11](%[svm]) \n\t"
3237 "mov %%r12, %c[r12](%[svm]) \n\t"
3238 "mov %%r13, %c[r13](%[svm]) \n\t"
3239 "mov %%r14, %c[r14](%[svm]) \n\t"
3240 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3241#endif
80e31d4f 3242 "pop %%"R"bp"
6aa8b732 3243 :
fb3f0f51 3244 : [svm]"a"(svm),
6aa8b732 3245 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3246 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3247 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3248 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3249 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3250 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3251 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3252#ifdef CONFIG_X86_64
ad312c7c
ZX		 3253 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3254 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3255 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3256 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3257 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3258 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3259 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3260 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3261#endif
54a08c04 3262 : "cc", "memory"
80e31d4f 3263 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3264#ifdef CONFIG_X86_64
54a08c04
LV		 3265 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3266#endif
3267 );
6aa8b732 3268
ad312c7c 3269 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 3270 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3271 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3272 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 3273
6aa8b732 3274 load_host_msrs(vcpu);
9581d442
AK		 3275 loadsegment(fs, fs_selector);
3276#ifdef CONFIG_X86_64
3277 load_gs_index(gs_selector);
3278 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
3279#else
3280 loadsegment(gs, gs_selector);
3281#endif
3282 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 3283
3284 reload_tss(vcpu);
3285
56ba47dd
AK		 3286 local_irq_disable();
3287
3288 stgi();
3289
d7bf8221
JR		 3290 sync_cr8_to_lapic(vcpu);
3291
a2fa3e9f 3292 svm->next_rip = 0;
9222be18 3293
6de4f3ad
AK		 3294 if (npt_enabled) {
3295 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3296 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3297 }
fe5913e4
JR		 3298
3299 /*
3300 * We need to handle MC intercepts here before the vcpu has a chance to
3301 * change the physical cpu
3302 */
3303 if (unlikely(svm->vmcb->control.exit_code ==
3304 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3305 svm_handle_mce(svm);
6aa8b732
AK		 3306}
3307
80e31d4f
AK		 3308#undef R
3309
6aa8b732
AK		 3310static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3311{
a2fa3e9f
GH		 3312 struct vcpu_svm *svm = to_svm(vcpu);
3313
709ddebf
JR		 3314 if (npt_enabled) {
3315 svm->vmcb->control.nested_cr3 = root;
3316 force_new_asid(vcpu);
3317 return;
3318 }
3319
a2fa3e9f 3320 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3321 force_new_asid(vcpu);
3322}
3323
6aa8b732
AK		 3324static int is_disabled(void)
3325{
6031a61c
JR		 3326 u64 vm_cr;
3327
3328 rdmsrl(MSR_VM_CR, vm_cr);
3329 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3330 return 1;
3331
6aa8b732
AK		 3332 return 0;
3333}
3334
102d8325
IM		 3335static void
3336svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3337{
3338 /*
3339 * Patch in the VMMCALL instruction:
3340 */
3341 hypercall[0] = 0x0f;
3342 hypercall[1] = 0x01;
3343 hypercall[2] = 0xd9;
102d8325
IM		 3344}
3345
002c7f7c
YS		 3346static void svm_check_processor_compat(void *rtn)
3347{
3348 *(int *)rtn = 0;
3349}
3350
774ead3a
AK		 3351static bool svm_cpu_has_accelerated_tpr(void)
3352{
3353 return false;
3354}
3355
67253af5
SY		 3356static int get_npt_level(void)
3357{
3358#ifdef CONFIG_X86_64
3359 return PT64_ROOT_LEVEL;
3360#else
3361 return PT32E_ROOT_LEVEL;
3362#endif
3363}
3364
4b12f0de 3365static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3366{
3367 return 0;
3368}
3369
0e851880
SY		 3370static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3371{
3372}
3373
d4330ef2
JR		 3374static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3375{
c2c63a49
JR		 3376 switch (func) {
3377 case 0x8000000A:
3378 entry->eax = 1; /* SVM revision 1 */
3379 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3380 ASID emulation to nested SVM */
3381 entry->ecx = 0; /* Reserved */
7a190667
JR		 3382 entry->edx = 0; /* Per default do not support any
3383 additional features */
3384
3385 /* Support next_rip if host supports it */
3386 if (svm_has(SVM_FEATURE_NRIP))
3387 entry->edx |= SVM_FEATURE_NRIP;
c2c63a49
JR		 3388
3389 break;
3390 }
d4330ef2
JR		 3391}
3392
229456fc 3393static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3394 { SVM_EXIT_READ_CR0, "read_cr0" },
3395 { SVM_EXIT_READ_CR3, "read_cr3" },
3396 { SVM_EXIT_READ_CR4, "read_cr4" },
3397 { SVM_EXIT_READ_CR8, "read_cr8" },
3398 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3399 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3400 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3401 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3402 { SVM_EXIT_READ_DR0, "read_dr0" },
3403 { SVM_EXIT_READ_DR1, "read_dr1" },
3404 { SVM_EXIT_READ_DR2, "read_dr2" },
3405 { SVM_EXIT_READ_DR3, "read_dr3" },
3406 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3407 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3408 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3409 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3410 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3411 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3412 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3413 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3414 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3415 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3416 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3417 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3418 { SVM_EXIT_INTR, "interrupt" },
3419 { SVM_EXIT_NMI, "nmi" },
3420 { SVM_EXIT_SMI, "smi" },
3421 { SVM_EXIT_INIT, "init" },
3422 { SVM_EXIT_VINTR, "vintr" },
3423 { SVM_EXIT_CPUID, "cpuid" },
3424 { SVM_EXIT_INVD, "invd" },
3425 { SVM_EXIT_HLT, "hlt" },
3426 { SVM_EXIT_INVLPG, "invlpg" },
3427 { SVM_EXIT_INVLPGA, "invlpga" },
3428 { SVM_EXIT_IOIO, "io" },
3429 { SVM_EXIT_MSR, "msr" },
3430 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3431 { SVM_EXIT_SHUTDOWN, "shutdown" },
3432 { SVM_EXIT_VMRUN, "vmrun" },
3433 { SVM_EXIT_VMMCALL, "hypercall" },
3434 { SVM_EXIT_VMLOAD, "vmload" },
3435 { SVM_EXIT_VMSAVE, "vmsave" },
3436 { SVM_EXIT_STGI, "stgi" },
3437 { SVM_EXIT_CLGI, "clgi" },
3438 { SVM_EXIT_SKINIT, "skinit" },
3439 { SVM_EXIT_WBINVD, "wbinvd" },
3440 { SVM_EXIT_MONITOR, "monitor" },
3441 { SVM_EXIT_MWAIT, "mwait" },
3442 { SVM_EXIT_NPF, "npf" },
3443 { -1, NULL }
3444};
3445
17cc3935 3446static int svm_get_lpage_level(void)
344f414f 3447{
17cc3935 3448 return PT_PDPE_LEVEL;
344f414f
JR		 3449}
3450
4e47c7a6
SY		 3451static bool svm_rdtscp_supported(void)
3452{
3453 return false;
3454}
3455
f5f48ee1
SY		 3456static bool svm_has_wbinvd_exit(void)
3457{
3458 return true;
3459}
3460
02daab21
AK		 3461static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3462{
3463 struct vcpu_svm *svm = to_svm(vcpu);
3464
02daab21 3465 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
66a562f7
JR		 3466 if (is_nested(svm))
3467 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3468 update_cr0_intercept(svm);
02daab21
AK		 3469}
3470
cbdd1bea 3471static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3472 .cpu_has_kvm_support = has_svm,
3473 .disabled_by_bios = is_disabled,
3474 .hardware_setup = svm_hardware_setup,
3475 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3476 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3477 .hardware_enable = svm_hardware_enable,
3478 .hardware_disable = svm_hardware_disable,
774ead3a 3479 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3480
3481 .vcpu_create = svm_create_vcpu,
3482 .vcpu_free = svm_free_vcpu,
04d2cc77 3483 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3484
04d2cc77 3485 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3486 .vcpu_load = svm_vcpu_load,
3487 .vcpu_put = svm_vcpu_put,
3488
3489 .set_guest_debug = svm_guest_debug,
3490 .get_msr = svm_get_msr,
3491 .set_msr = svm_set_msr,
3492 .get_segment_base = svm_get_segment_base,
3493 .get_segment = svm_get_segment,
3494 .set_segment = svm_set_segment,
2e4d2653 3495 .get_cpl = svm_get_cpl,
1747fb71 3496 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3497 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3498 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3499 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3500 .set_cr3 = svm_set_cr3,
3501 .set_cr4 = svm_set_cr4,
3502 .set_efer = svm_set_efer,
3503 .get_idt = svm_get_idt,
3504 .set_idt = svm_set_idt,
3505 .get_gdt = svm_get_gdt,
3506 .set_gdt = svm_set_gdt,
020df079 3507 .set_dr7 = svm_set_dr7,
6de4f3ad 3508 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3509 .get_rflags = svm_get_rflags,
3510 .set_rflags = svm_set_rflags,
6b52d186 3511 .fpu_activate = svm_fpu_activate,
02daab21 3512 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3513
6aa8b732 3514 .tlb_flush = svm_flush_tlb,
6aa8b732 3515
6aa8b732 3516 .run = svm_vcpu_run,
04d2cc77 3517 .handle_exit = handle_exit,
6aa8b732 3518 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3519 .set_interrupt_shadow = svm_set_interrupt_shadow,
3520 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3521 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3522 .set_irq = svm_set_irq,
95ba8273 3523 .set_nmi = svm_inject_nmi,
298101da 3524 .queue_exception = svm_queue_exception,
78646121 3525 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3526 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3527 .get_nmi_mask = svm_get_nmi_mask,
3528 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3529 .enable_nmi_window = enable_nmi_window,
3530 .enable_irq_window = enable_irq_window,
3531 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3532
3533 .set_tss_addr = svm_set_tss_addr,
67253af5 3534 .get_tdp_level = get_npt_level,
4b12f0de 3535 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3536
3537 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3538 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3539
3540 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3541
3542 .rdtscp_supported = svm_rdtscp_supported,
d4330ef2
JR		 3543
3544 .set_supported_cpuid = svm_set_supported_cpuid,
f5f48ee1
SY		 3545
3546 .has_wbinvd_exit = svm_has_wbinvd_exit,
99e3e30a
ZA		 3547
3548 .write_tsc_offset = svm_write_tsc_offset,
e48672fa 3549 .adjust_tsc_offset = svm_adjust_tsc_offset,
6aa8b732
AK		 3550};
3551
3552static int __init svm_init(void)
3553{
cb498ea2 3554 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
0ee75bea 3555 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 3556}
3557
3558static void __exit svm_exit(void)
3559{
cb498ea2 3560 kvm_exit();
6aa8b732
AK		 3561}
3562
3563module_init(svm_init)
3564module_exit(svm_exit)
Empty description
This page took 1.166644 seconds and 4 git commands to generate.