[linux.git] / drivers / watchdog / omap_wdt.c

/*
 * omap_wdt.c
 *
 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
 *
 * Author: MontaVista Software, Inc.
 *	 <[email protected]> or <[email protected]>
 *
 * 2003 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * History:
 *
 * 20030527: George G. Davis <[email protected]>
 *	Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
 *	(c) Copyright 2000 Oleg Drokin <[email protected]>
 *	Based on SoftDog driver by Alan Cox <[email protected]>
 *
 * Copyright (c) 2004 Texas Instruments.
 *	1. Modified to support OMAP1610 32-KHz watchdog timer
 *	2. Ported to 2.6 kernel
 *
 * Copyright (c) 2005 David Brownell
 *	Use the driver model and standard identifiers; handle bigger timeouts.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/watchdog.h>
#include <linux/reboot.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/moduleparam.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/platform_data/omap-wd-timer.h>

#include "omap_wdt.h"

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

static unsigned timer_margin;
module_param(timer_margin, uint, 0);
MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");

#define to_omap_wdt_dev(_wdog)	container_of(_wdog, struct omap_wdt_dev, wdog)

static bool early_enable;
module_param(early_enable, bool, 0);
MODULE_PARM_DESC(early_enable,
	"Watchdog is started on module insertion (default=0)");

struct omap_wdt_dev {
	struct watchdog_device wdog;
	void __iomem    *base;          /* physical */
	struct device   *dev;
	bool		omap_wdt_users;
	int		wdt_trgr_pattern;
	struct mutex	lock;		/* to avoid races with PM */
};

static void omap_wdt_reload(struct omap_wdt_dev *wdev)
{
	void __iomem    *base = wdev->base;

	/* wait for posted write to complete */
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
		cpu_relax();

	wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern;
	writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));

	/* wait for posted write to complete */
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
		cpu_relax();
	/* reloaded WCRR from WLDR */
}

static void omap_wdt_enable(struct omap_wdt_dev *wdev)
{
	void __iomem *base = wdev->base;

	/* Sequence to enable the watchdog */
	writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR);
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
		cpu_relax();

	writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR);
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
		cpu_relax();
}

static void omap_wdt_disable(struct omap_wdt_dev *wdev)
{
	void __iomem *base = wdev->base;

	/* sequence required to disable watchdog */
	writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR);	/* TIMER_MODE */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
		cpu_relax();

	writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR);	/* TIMER_MODE */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
		cpu_relax();
}

static void omap_wdt_set_timer(struct omap_wdt_dev *wdev,
				   unsigned int timeout)
{
	u32 pre_margin = GET_WLDR_VAL(timeout);
	void __iomem *base = wdev->base;

	/* just count up at 32 KHz */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
		cpu_relax();

	writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR);
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
		cpu_relax();
}

static int omap_wdt_start(struct watchdog_device *wdog)
{
	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
	void __iomem *base = wdev->base;

	mutex_lock(&wdev->lock);

	wdev->omap_wdt_users = true;

	pm_runtime_get_sync(wdev->dev);

	/*
	 * Make sure the watchdog is disabled. This is unfortunately required
	 * because writing to various registers with the watchdog running has no
	 * effect.
	 */
	omap_wdt_disable(wdev);

	/* initialize prescaler */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
		cpu_relax();

	writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
		cpu_relax();

	omap_wdt_set_timer(wdev, wdog->timeout);
	omap_wdt_reload(wdev); /* trigger loading of new timeout value */
	omap_wdt_enable(wdev);

	mutex_unlock(&wdev->lock);

	return 0;
}

static int omap_wdt_stop(struct watchdog_device *wdog)
{
	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);

	mutex_lock(&wdev->lock);
	omap_wdt_disable(wdev);
	pm_runtime_put_sync(wdev->dev);
	wdev->omap_wdt_users = false;
	mutex_unlock(&wdev->lock);
	return 0;
}

static int omap_wdt_ping(struct watchdog_device *wdog)
{
	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);

	mutex_lock(&wdev->lock);
	omap_wdt_reload(wdev);
	mutex_unlock(&wdev->lock);

	return 0;
}

static int omap_wdt_set_timeout(struct watchdog_device *wdog,
				unsigned int timeout)
{
	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);

	mutex_lock(&wdev->lock);
	omap_wdt_disable(wdev);
	omap_wdt_set_timer(wdev, timeout);
	omap_wdt_enable(wdev);
	omap_wdt_reload(wdev);
	wdog->timeout = timeout;
	mutex_unlock(&wdev->lock);

	return 0;
}

static unsigned int omap_wdt_get_timeleft(struct watchdog_device *wdog)
{
	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
	void __iomem *base = wdev->base;
	u32 value;

	value = readl_relaxed(base + OMAP_WATCHDOG_CRR);
	return GET_WCCR_SECS(value);
}

static const struct watchdog_info omap_wdt_info = {
	.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
	.identity = "OMAP Watchdog",
};

static const struct watchdog_ops omap_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= omap_wdt_start,
	.stop		= omap_wdt_stop,
	.ping		= omap_wdt_ping,
	.set_timeout	= omap_wdt_set_timeout,
	.get_timeleft	= omap_wdt_get_timeleft,
};

static int omap_wdt_probe(struct platform_device *pdev)
{
	struct omap_wd_timer_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct resource *res;
	struct omap_wdt_dev *wdev;
	int ret;

	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	if (!wdev)
		return -ENOMEM;

	wdev->omap_wdt_users	= false;
	wdev->dev		= &pdev->dev;
	wdev->wdt_trgr_pattern	= 0x1234;
	mutex_init(&wdev->lock);

	/* reserve static register mappings */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	wdev->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(wdev->base))
		return PTR_ERR(wdev->base);

	wdev->wdog.info = &omap_wdt_info;
	wdev->wdog.ops = &omap_wdt_ops;
	wdev->wdog.min_timeout = TIMER_MARGIN_MIN;
	wdev->wdog.max_timeout = TIMER_MARGIN_MAX;
	wdev->wdog.parent = &pdev->dev;

	if (watchdog_init_timeout(&wdev->wdog, timer_margin, &pdev->dev) < 0)
		wdev->wdog.timeout = TIMER_MARGIN_DEFAULT;

	watchdog_set_nowayout(&wdev->wdog, nowayout);

	platform_set_drvdata(pdev, wdev);

	pm_runtime_enable(wdev->dev);
	pm_runtime_get_sync(wdev->dev);

	if (pdata && pdata->read_reset_sources) {
		u32 rs = pdata->read_reset_sources();
		if (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT))
			wdev->wdog.bootstatus = WDIOF_CARDRESET;
	}

	if (!early_enable)
		omap_wdt_disable(wdev);

	ret = watchdog_register_device(&wdev->wdog);
	if (ret) {
		pm_runtime_disable(wdev->dev);
		return ret;
	}

	pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
		readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
		wdev->wdog.timeout);

	if (early_enable)
		omap_wdt_start(&wdev->wdog);

	pm_runtime_put(wdev->dev);

	return 0;
}

static void omap_wdt_shutdown(struct platform_device *pdev)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);

	mutex_lock(&wdev->lock);
	if (wdev->omap_wdt_users) {
		omap_wdt_disable(wdev);
		pm_runtime_put_sync(wdev->dev);
	}
	mutex_unlock(&wdev->lock);
}

static int omap_wdt_remove(struct platform_device *pdev)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);

	pm_runtime_disable(wdev->dev);
	watchdog_unregister_device(&wdev->wdog);

	return 0;
}

#ifdef	CONFIG_PM

/* REVISIT ... not clear this is the best way to handle system suspend; and
 * it's very inappropriate for selective device suspend (e.g. suspending this
 * through sysfs rather than by stopping the watchdog daemon).  Also, this
 * may not play well enough with NOWAYOUT...
 */

static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);

	mutex_lock(&wdev->lock);
	if (wdev->omap_wdt_users) {
		omap_wdt_disable(wdev);
		pm_runtime_put_sync(wdev->dev);
	}
	mutex_unlock(&wdev->lock);

	return 0;
}

static int omap_wdt_resume(struct platform_device *pdev)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);

	mutex_lock(&wdev->lock);
	if (wdev->omap_wdt_users) {
		pm_runtime_get_sync(wdev->dev);
		omap_wdt_enable(wdev);
		omap_wdt_reload(wdev);
	}
	mutex_unlock(&wdev->lock);

	return 0;
}

#else
#define	omap_wdt_suspend	NULL
#define	omap_wdt_resume		NULL
#endif

static const struct of_device_id omap_wdt_of_match[] = {
	{ .compatible = "ti,omap3-wdt", },
	{},
};
MODULE_DEVICE_TABLE(of, omap_wdt_of_match);

static struct platform_driver omap_wdt_driver = {
	.probe		= omap_wdt_probe,
	.remove		= omap_wdt_remove,
	.shutdown	= omap_wdt_shutdown,
	.suspend	= omap_wdt_suspend,
	.resume		= omap_wdt_resume,
	.driver		= {
		.name	= "omap_wdt",
		.of_match_table = omap_wdt_of_match,
	},
};

module_platform_driver(omap_wdt_driver);

MODULE_AUTHOR("George G. Davis");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:omap_wdt");
Commit	Line	Data
7768a13c	1	/*
2817142f	2	* omap_wdt.c
7768a13c	3	*
2817142f	4	* Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
7768a13c KS	5	*
	6	* Author: MontaVista Software, Inc.
	7	* <[email protected]> or <[email protected]>
	8	*
	9	* 2003 (c) MontaVista Software, Inc. This file is licensed under the
	10	* terms of the GNU General Public License version 2. This program is
	11	* licensed "as is" without any warranty of any kind, whether express
	12	* or implied.
	13	*
	14	* History:
	15	*
	16	* 20030527: George G. Davis <[email protected]>
	17	* Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
	18	* (c) Copyright 2000 Oleg Drokin <[email protected]>
29fa0586	19	* Based on SoftDog driver by Alan Cox <[email protected]>
7768a13c KS	20	*
	21	* Copyright (c) 2004 Texas Instruments.
	22	* 1. Modified to support OMAP1610 32-KHz watchdog timer
	23	* 2. Ported to 2.6 kernel
	24	*
	25	* Copyright (c) 2005 David Brownell
	26	* Use the driver model and standard identifiers; handle bigger timeouts.
	27	*/
	28
27c766aa JP	29	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	30
7768a13c	31	#include <linux/module.h>
7768a13c KS	32	#include <linux/types.h>
7768a13c KS	33	#include <linux/kernel.h>
7768a13c	34	#include <linux/mm.h>
7768a13c KS	35	#include <linux/watchdog.h>
7768a13c KS	36	#include <linux/reboot.h>
7768a13c KS	37	#include <linux/err.h>
	38	#include <linux/platform_device.h>
	39	#include <linux/moduleparam.h>
089ab079	40	#include <linux/io.h>
5a0e3ad6	41	#include <linux/slab.h>
7ec5ad0f	42	#include <linux/pm_runtime.h>
129f5577	43	#include <linux/platform_data/omap-wd-timer.h>
7768a13c KS	44
	45	#include "omap_wdt.h"
	46
2dd7b244 PR	47	static bool nowayout = WATCHDOG_NOWAYOUT;
	48	module_param(nowayout, bool, 0);
	49	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
	50	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	51
7768a13c KS	52	static unsigned timer_margin;
	53	module_param(timer_margin, uint, 0);
	54	MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
	55
d2f78268 UKK	56	#define to_omap_wdt_dev(_wdog) container_of(_wdog, struct omap_wdt_dev, wdog)
d2f78268 UKK	57
b2102eb3 LP	58	static bool early_enable;
	59	module_param(early_enable, bool, 0);
	60	MODULE_PARM_DESC(early_enable,
	61	"Watchdog is started on module insertion (default=0)");
	62
2817142f	63	struct omap_wdt_dev {
d2f78268	64	struct watchdog_device wdog;
2817142f FB	65	void __iomem base; / physical */
2817142f FB	66	struct device *dev;
67c0f554	67	bool omap_wdt_users;
67c0f554 AK	68	int wdt_trgr_pattern;
67c0f554 AK	69	struct mutex lock; /* to avoid races with PM */
2817142f FB	70	};
2817142f FB	71
67c0f554	72	static void omap_wdt_reload(struct omap_wdt_dev *wdev)
7768a13c	73	{
2817142f	74	void __iomem *base = wdev->base;
b3112180	75
7768a13c	76	/* wait for posted write to complete */
4a7e94a0	77	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
7768a13c	78	cpu_relax();
b3112180	79
67c0f554	80	wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern;
4a7e94a0	81	writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
b3112180	82
7768a13c	83	/* wait for posted write to complete */
4a7e94a0	84	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
7768a13c KS	85	cpu_relax();
	86	/* reloaded WCRR from WLDR */
	87	}
	88
2817142f	89	static void omap_wdt_enable(struct omap_wdt_dev *wdev)
7768a13c	90	{
b3112180 FB	91	void __iomem *base = wdev->base;
b3112180 FB	92
7768a13c	93	/* Sequence to enable the watchdog */
4a7e94a0 VK	94	writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR);
4a7e94a0 VK	95	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
7768a13c	96	cpu_relax();
b3112180	97
4a7e94a0 VK	98	writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR);
4a7e94a0 VK	99	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
7768a13c KS	100	cpu_relax();
	101	}
	102
2817142f	103	static void omap_wdt_disable(struct omap_wdt_dev *wdev)
7768a13c	104	{
b3112180 FB	105	void __iomem *base = wdev->base;
b3112180 FB	106
7768a13c	107	/* sequence required to disable watchdog */
4a7e94a0 VK	108	writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
4a7e94a0 VK	109	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
7768a13c	110	cpu_relax();
b3112180	111
4a7e94a0 VK	112	writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
4a7e94a0 VK	113	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
7768a13c KS	114	cpu_relax();
	115	}
	116
67c0f554 AK	117	static void omap_wdt_set_timer(struct omap_wdt_dev *wdev,
67c0f554 AK	118	unsigned int timeout)
7768a13c	119	{
67c0f554	120	u32 pre_margin = GET_WLDR_VAL(timeout);
b3112180	121	void __iomem *base = wdev->base;
7768a13c KS	122
7768a13c KS	123	/* just count up at 32 KHz */
4a7e94a0	124	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
7768a13c	125	cpu_relax();
b3112180	126
4a7e94a0 VK	127	writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR);
4a7e94a0 VK	128	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
7768a13c KS	129	cpu_relax();
	130	}
	131
67c0f554	132	static int omap_wdt_start(struct watchdog_device *wdog)
7768a13c	133	{
d2f78268	134	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
b3112180 FB	135	void __iomem *base = wdev->base;
b3112180 FB	136
67c0f554 AK	137	mutex_lock(&wdev->lock);
	138
	139	wdev->omap_wdt_users = true;
7768a13c	140
7ec5ad0f	141	pm_runtime_get_sync(wdev->dev);
7768a13c	142
530c11d4 UKK	143	/*
	144	* Make sure the watchdog is disabled. This is unfortunately required
	145	* because writing to various registers with the watchdog running has no
	146	* effect.
	147	*/
	148	omap_wdt_disable(wdev);
	149
7768a13c	150	/* initialize prescaler */
4a7e94a0	151	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
7768a13c	152	cpu_relax();
b3112180	153
4a7e94a0 VK	154	writel_relaxed((1 << 5) \| (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
4a7e94a0 VK	155	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
7768a13c KS	156	cpu_relax();
7768a13c KS	157
67c0f554 AK	158	omap_wdt_set_timer(wdev, wdog->timeout);
67c0f554 AK	159	omap_wdt_reload(wdev); /* trigger loading of new timeout value */
2817142f	160	omap_wdt_enable(wdev);
b3112180	161
67c0f554 AK	162	mutex_unlock(&wdev->lock);
	163
	164	return 0;
7768a13c KS	165	}
7768a13c KS	166
67c0f554	167	static int omap_wdt_stop(struct watchdog_device *wdog)
7768a13c	168	{
d2f78268	169	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
b3112180	170
67c0f554	171	mutex_lock(&wdev->lock);
2817142f	172	omap_wdt_disable(wdev);
7ec5ad0f	173	pm_runtime_put_sync(wdev->dev);
67c0f554 AK	174	wdev->omap_wdt_users = false;
67c0f554 AK	175	mutex_unlock(&wdev->lock);
7768a13c KS	176	return 0;
	177	}
	178
67c0f554	179	static int omap_wdt_ping(struct watchdog_device *wdog)
7768a13c	180	{
d2f78268	181	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
b3112180	182
67c0f554 AK	183	mutex_lock(&wdev->lock);
	184	omap_wdt_reload(wdev);
	185	mutex_unlock(&wdev->lock);
	186
	187	return 0;
7768a13c KS	188	}
7768a13c KS	189
67c0f554 AK	190	static int omap_wdt_set_timeout(struct watchdog_device *wdog,
67c0f554 AK	191	unsigned int timeout)
7768a13c	192	{
d2f78268	193	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
7768a13c	194
67c0f554 AK	195	mutex_lock(&wdev->lock);
	196	omap_wdt_disable(wdev);
	197	omap_wdt_set_timer(wdev, timeout);
	198	omap_wdt_enable(wdev);
	199	omap_wdt_reload(wdev);
	200	wdog->timeout = timeout;
	201	mutex_unlock(&wdev->lock);
	202
	203	return 0;
7768a13c KS	204	}
7768a13c KS	205
452fafed LP	206	static unsigned int omap_wdt_get_timeleft(struct watchdog_device *wdog)
452fafed LP	207	{
de55acd1	208	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
452fafed LP	209	void __iomem *base = wdev->base;
	210	u32 value;
	211
	212	value = readl_relaxed(base + OMAP_WATCHDOG_CRR);
	213	return GET_WCCR_SECS(value);
	214	}
	215
67c0f554	216	static const struct watchdog_info omap_wdt_info = {
fb1cbeae	217	.options = WDIOF_SETTIMEOUT \| WDIOF_MAGICCLOSE \| WDIOF_KEEPALIVEPING,
67c0f554 AK	218	.identity = "OMAP Watchdog",
	219	};
	220
	221	static const struct watchdog_ops omap_wdt_ops = {
	222	.owner = THIS_MODULE,
	223	.start = omap_wdt_start,
	224	.stop = omap_wdt_stop,
	225	.ping = omap_wdt_ping,
	226	.set_timeout = omap_wdt_set_timeout,
452fafed	227	.get_timeleft = omap_wdt_get_timeleft,
7768a13c KS	228	};
7768a13c KS	229
2d991a16	230	static int omap_wdt_probe(struct platform_device *pdev)
7768a13c	231	{
bc8fdfbe	232	struct omap_wd_timer_platform_data *pdata = dev_get_platdata(&pdev->dev);
6e272061	233	struct resource *res;
2817142f	234	struct omap_wdt_dev *wdev;
b3112180	235	int ret;
7768a13c	236
4f4753d9 AK	237	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	238	if (!wdev)
	239	return -ENOMEM;
b3112180	240
67c0f554	241	wdev->omap_wdt_users = false;
67c0f554 AK	242	wdev->dev = &pdev->dev;
	243	wdev->wdt_trgr_pattern = 0x1234;
	244	mutex_init(&wdev->lock);
2817142f	245
6e272061 JH	246	/* reserve static register mappings */
	247	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	248	wdev->base = devm_ioremap_resource(&pdev->dev, res);
	249	if (IS_ERR(wdev->base))
	250	return PTR_ERR(wdev->base);
9f69e3b0	251
d2f78268 UKK	252	wdev->wdog.info = &omap_wdt_info;
	253	wdev->wdog.ops = &omap_wdt_ops;
	254	wdev->wdog.min_timeout = TIMER_MARGIN_MIN;
	255	wdev->wdog.max_timeout = TIMER_MARGIN_MAX;
6551881c	256	wdev->wdog.parent = &pdev->dev;
67c0f554	257
d2f78268 UKK	258	if (watchdog_init_timeout(&wdev->wdog, timer_margin, &pdev->dev) < 0)
d2f78268 UKK	259	wdev->wdog.timeout = TIMER_MARGIN_DEFAULT;
67c0f554	260
d2f78268	261	watchdog_set_nowayout(&wdev->wdog, nowayout);
67c0f554	262
d2f78268	263	platform_set_drvdata(pdev, wdev);
7768a13c	264
7ec5ad0f VC	265	pm_runtime_enable(wdev->dev);
7ec5ad0f VC	266	pm_runtime_get_sync(wdev->dev);
789cd470	267
0b3330f3 UKK	268	if (pdata && pdata->read_reset_sources) {
	269	u32 rs = pdata->read_reset_sources();
	270	if (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT))
	271	wdev->wdog.bootstatus = WDIOF_CARDRESET;
	272	}
7768a13c	273
8605fec1 UKK	274	if (!early_enable)
8605fec1 UKK	275	omap_wdt_disable(wdev);
2817142f	276
d2f78268	277	ret = watchdog_register_device(&wdev->wdog);
1ba85387 AK	278	if (ret) {
	279	pm_runtime_disable(wdev->dev);
	280	return ret;
	281	}
7768a13c	282
2817142f	283	pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
4a7e94a0	284	readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
d2f78268	285	wdev->wdog.timeout);
7768a13c	286
b2102eb3 LP	287	if (early_enable)
	288	omap_wdt_start(&wdev->wdog);
	289
a6392490 UKK	290	pm_runtime_put(wdev->dev);
a6392490 UKK	291
7768a13c	292	return 0;
7768a13c KS	293	}
	294
	295	static void omap_wdt_shutdown(struct platform_device *pdev)
	296	{
d2f78268	297	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
2817142f	298
67c0f554	299	mutex_lock(&wdev->lock);
0503add9	300	if (wdev->omap_wdt_users) {
2817142f	301	omap_wdt_disable(wdev);
0503add9 PW	302	pm_runtime_put_sync(wdev->dev);
0503add9 PW	303	}
67c0f554	304	mutex_unlock(&wdev->lock);
7768a13c KS	305	}
7768a13c KS	306
4b12b896	307	static int omap_wdt_remove(struct platform_device *pdev)
7768a13c	308	{
d2f78268	309	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
2817142f	310
12c583d8	311	pm_runtime_disable(wdev->dev);
d2f78268	312	watchdog_unregister_device(&wdev->wdog);
b3112180	313
7768a13c KS	314	return 0;
	315	}
	316
	317	#ifdef CONFIG_PM
	318
	319	/* REVISIT ... not clear this is the best way to handle system suspend; and
	320	* it's very inappropriate for selective device suspend (e.g. suspending this
	321	* through sysfs rather than by stopping the watchdog daemon). Also, this
	322	* may not play well enough with NOWAYOUT...
	323	*/
	324
	325	static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
	326	{
d2f78268	327	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
b3112180	328
67c0f554	329	mutex_lock(&wdev->lock);
0503add9	330	if (wdev->omap_wdt_users) {
2817142f	331	omap_wdt_disable(wdev);
0503add9 PW	332	pm_runtime_put_sync(wdev->dev);
0503add9 PW	333	}
67c0f554	334	mutex_unlock(&wdev->lock);
b3112180	335
7768a13c KS	336	return 0;
	337	}
	338
	339	static int omap_wdt_resume(struct platform_device *pdev)
	340	{
d2f78268	341	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
b3112180	342
67c0f554	343	mutex_lock(&wdev->lock);
2817142f	344	if (wdev->omap_wdt_users) {
0503add9	345	pm_runtime_get_sync(wdev->dev);
2817142f	346	omap_wdt_enable(wdev);
67c0f554	347	omap_wdt_reload(wdev);
7768a13c	348	}
67c0f554	349	mutex_unlock(&wdev->lock);
b3112180	350
7768a13c KS	351	return 0;
	352	}
	353
	354	#else
	355	#define omap_wdt_suspend NULL
	356	#define omap_wdt_resume NULL
	357	#endif
	358
e6ca04ea XJ	359	static const struct of_device_id omap_wdt_of_match[] = {
	360	{ .compatible = "ti,omap3-wdt", },
	361	{},
	362	};
	363	MODULE_DEVICE_TABLE(of, omap_wdt_of_match);
	364
7768a13c KS	365	static struct platform_driver omap_wdt_driver = {
7768a13c KS	366	.probe = omap_wdt_probe,
82268714	367	.remove = omap_wdt_remove,
7768a13c KS	368	.shutdown = omap_wdt_shutdown,
	369	.suspend = omap_wdt_suspend,
	370	.resume = omap_wdt_resume,
	371	.driver = {
7768a13c	372	.name = "omap_wdt",
e6ca04ea	373	.of_match_table = omap_wdt_of_match,
7768a13c KS	374	},
	375	};
	376
b8ec6118	377	module_platform_driver(omap_wdt_driver);
7768a13c KS	378
	379	MODULE_AUTHOR("George G. Davis");
	380	MODULE_LICENSE("GPL");
f37d193c	381	MODULE_ALIAS("platform:omap_wdt");