[linux.git] / drivers / s390 / cio / ioasm.h

#ifndef S390_CIO_IOASM_H
#define S390_CIO_IOASM_H

#include <asm/chpid.h>
#include "schid.h"

/*
 * TPI info structure
 */
struct tpi_info {
	struct subchannel_id schid;
	__u32 intparm;		 /* interruption parameter */
	__u32 adapter_IO : 1;
	__u32 reserved2	 : 1;
	__u32 isc	 : 3;
	__u32 reserved3	 : 12;
	__u32 int_type	 : 3;
	__u32 reserved4	 : 12;
} __attribute__ ((packed));


/*
 * Some S390 specific IO instructions as inline
 */

static inline int stsch(struct subchannel_id schid,
			    volatile struct schib *addr)
{
	register struct subchannel_id reg1 asm ("1") = schid;
	int ccode;

	asm volatile(
		"	stsch	0(%2)\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
	return ccode;
}

static inline int stsch_err(struct subchannel_id schid,
				volatile struct schib *addr)
{
	register struct subchannel_id reg1 asm ("1") = schid;
	int ccode = -EIO;

	asm volatile(
		"	stsch	0(%2)\n"
		"0:	ipm	%0\n"
		"	srl	%0,28\n"
		"1:\n"
		EX_TABLE(0b,1b)
		: "+d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
	return ccode;
}

static inline int msch(struct subchannel_id schid,
			   volatile struct schib *addr)
{
	register struct subchannel_id reg1 asm ("1") = schid;
	int ccode;

	asm volatile(
		"	msch	0(%2)\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
	return ccode;
}

static inline int msch_err(struct subchannel_id schid,
			       volatile struct schib *addr)
{
	register struct subchannel_id reg1 asm ("1") = schid;
	int ccode = -EIO;

	asm volatile(
		"	msch	0(%2)\n"
		"0:	ipm	%0\n"
		"	srl	%0,28\n"
		"1:\n"
		EX_TABLE(0b,1b)
		: "+d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
	return ccode;
}

static inline int tsch(struct subchannel_id schid,
			   volatile struct irb *addr)
{
	register struct subchannel_id reg1 asm ("1") = schid;
	int ccode;

	asm volatile(
		"	tsch	0(%2)\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
	return ccode;
}

static inline int tpi( volatile struct tpi_info *addr)
{
	int ccode;

	asm volatile(
		"	tpi	0(%1)\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode) : "a" (addr), "m" (*addr) : "cc");
	return ccode;
}

static inline int ssch(struct subchannel_id schid,
			   volatile struct orb *addr)
{
	register struct subchannel_id reg1 asm ("1") = schid;
	int ccode;

	asm volatile(
		"	ssch	0(%2)\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
	return ccode;
}

static inline int rsch(struct subchannel_id schid)
{
	register struct subchannel_id reg1 asm ("1") = schid;
	int ccode;

	asm volatile(
		"	rsch\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode) : "d" (reg1) : "cc");
	return ccode;
}

static inline int csch(struct subchannel_id schid)
{
	register struct subchannel_id reg1 asm ("1") = schid;
	int ccode;

	asm volatile(
		"	csch\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode) : "d" (reg1) : "cc");
	return ccode;
}

static inline int hsch(struct subchannel_id schid)
{
	register struct subchannel_id reg1 asm ("1") = schid;
	int ccode;

	asm volatile(
		"	hsch\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode) : "d" (reg1) : "cc");
	return ccode;
}

static inline int xsch(struct subchannel_id schid)
{
	register struct subchannel_id reg1 asm ("1") = schid;
	int ccode;

	asm volatile(
		"	.insn	rre,0xb2760000,%1,0\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode) : "d" (reg1) : "cc");
	return ccode;
}

static inline int chsc(void *chsc_area)
{
	typedef struct { char _[4096]; } addr_type;
	int cc;

	asm volatile(
		"	.insn	rre,0xb25f0000,%2,0\n"
		"	ipm	%0\n"
		"	srl	%0,28\n"
		: "=d" (cc), "=m" (*(addr_type *) chsc_area)
		: "d" (chsc_area), "m" (*(addr_type *) chsc_area)
		: "cc");
	return cc;
}

static inline int rchp(struct chp_id chpid)
{
	register struct chp_id reg1 asm ("1") = chpid;
	int ccode;

	asm volatile(
		"	lr	1,%1\n"
		"	rchp\n"
		"	ipm	%0\n"
		"	srl	%0,28"
		: "=d" (ccode) : "d" (reg1) : "cc");
	return ccode;
}

#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef S390_CIO_IOASM_H
	2	#define S390_CIO_IOASM_H
	3
e5854a58	4	#include <asm/chpid.h>
a8237fc4 CH	5	#include "schid.h"
a8237fc4 CH	6
1da177e4 LT	7	/*
	8	* TPI info structure
	9	*/
	10	struct tpi_info {
a8237fc4	11	struct subchannel_id schid;
1da177e4 LT	12	__u32 intparm; /* interruption parameter */
	13	__u32 adapter_IO : 1;
	14	__u32 reserved2 : 1;
	15	__u32 isc : 3;
	16	__u32 reserved3 : 12;
	17	__u32 int_type : 3;
	18	__u32 reserved4 : 12;
	19	} __attribute__ ((packed));
	20
	21
	22	/*
	23	* Some S390 specific IO instructions as inline
	24	*/
	25
a8237fc4 CH	26	static inline int stsch(struct subchannel_id schid,
a8237fc4 CH	27	volatile struct schib *addr)
1da177e4	28	{
94c12cc7	29	register struct subchannel_id reg1 asm ("1") = schid;
1da177e4 LT	30	int ccode;
1da177e4 LT	31
94c12cc7 MS	32	asm volatile(
	33	" stsch 0(%2)\n"
	34	" ipm %0\n"
	35	" srl %0,28"
	36	: "=d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
1da177e4 LT	37	return ccode;
	38	}
	39
fb6958a5 CH	40	static inline int stsch_err(struct subchannel_id schid,
	41	volatile struct schib *addr)
	42	{
94c12cc7 MS	43	register struct subchannel_id reg1 asm ("1") = schid;
94c12cc7 MS	44	int ccode = -EIO;
fb6958a5	45
94c12cc7 MS	46	asm volatile(
	47	" stsch 0(%2)\n"
	48	"0: ipm %0\n"
	49	" srl %0,28\n"
fb6958a5	50	"1:\n"
94c12cc7 MS	51	EX_TABLE(0b,1b)
94c12cc7 MS	52	: "+d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
fb6958a5 CH	53	return ccode;
	54	}
	55
a8237fc4 CH	56	static inline int msch(struct subchannel_id schid,
a8237fc4 CH	57	volatile struct schib *addr)
1da177e4	58	{
94c12cc7	59	register struct subchannel_id reg1 asm ("1") = schid;
1da177e4 LT	60	int ccode;
1da177e4 LT	61
94c12cc7 MS	62	asm volatile(
	63	" msch 0(%2)\n"
	64	" ipm %0\n"
	65	" srl %0,28"
	66	: "=d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
1da177e4 LT	67	return ccode;
	68	}
	69
a8237fc4 CH	70	static inline int msch_err(struct subchannel_id schid,
a8237fc4 CH	71	volatile struct schib *addr)
1da177e4	72	{
94c12cc7 MS	73	register struct subchannel_id reg1 asm ("1") = schid;
94c12cc7 MS	74	int ccode = -EIO;
1da177e4	75
94c12cc7 MS	76	asm volatile(
	77	" msch 0(%2)\n"
	78	"0: ipm %0\n"
	79	" srl %0,28\n"
1da177e4	80	"1:\n"
94c12cc7 MS	81	EX_TABLE(0b,1b)
94c12cc7 MS	82	: "+d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
1da177e4 LT	83	return ccode;
	84	}
	85
a8237fc4 CH	86	static inline int tsch(struct subchannel_id schid,
a8237fc4 CH	87	volatile struct irb *addr)
1da177e4	88	{
94c12cc7	89	register struct subchannel_id reg1 asm ("1") = schid;
1da177e4 LT	90	int ccode;
1da177e4 LT	91
94c12cc7 MS	92	asm volatile(
	93	" tsch 0(%2)\n"
	94	" ipm %0\n"
	95	" srl %0,28"
	96	: "=d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
1da177e4 LT	97	return ccode;
	98	}
	99
4c24da79	100	static inline int tpi( volatile struct tpi_info *addr)
1da177e4 LT	101	{
	102	int ccode;
	103
94c12cc7 MS	104	asm volatile(
	105	" tpi 0(%1)\n"
	106	" ipm %0\n"
	107	" srl %0,28"
	108	: "=d" (ccode) : "a" (addr), "m" (*addr) : "cc");
1da177e4 LT	109	return ccode;
	110	}
	111
a8237fc4 CH	112	static inline int ssch(struct subchannel_id schid,
a8237fc4 CH	113	volatile struct orb *addr)
1da177e4	114	{
94c12cc7	115	register struct subchannel_id reg1 asm ("1") = schid;
1da177e4 LT	116	int ccode;
1da177e4 LT	117
94c12cc7 MS	118	asm volatile(
	119	" ssch 0(%2)\n"
	120	" ipm %0\n"
	121	" srl %0,28"
	122	: "=d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
1da177e4 LT	123	return ccode;
	124	}
	125
a8237fc4	126	static inline int rsch(struct subchannel_id schid)
1da177e4	127	{
94c12cc7	128	register struct subchannel_id reg1 asm ("1") = schid;
1da177e4 LT	129	int ccode;
1da177e4 LT	130
94c12cc7 MS	131	asm volatile(
	132	" rsch\n"
	133	" ipm %0\n"
	134	" srl %0,28"
	135	: "=d" (ccode) : "d" (reg1) : "cc");
1da177e4 LT	136	return ccode;
	137	}
	138
a8237fc4	139	static inline int csch(struct subchannel_id schid)
1da177e4	140	{
94c12cc7	141	register struct subchannel_id reg1 asm ("1") = schid;
1da177e4 LT	142	int ccode;
1da177e4 LT	143
94c12cc7 MS	144	asm volatile(
	145	" csch\n"
	146	" ipm %0\n"
	147	" srl %0,28"
	148	: "=d" (ccode) : "d" (reg1) : "cc");
1da177e4 LT	149	return ccode;
	150	}
	151
a8237fc4	152	static inline int hsch(struct subchannel_id schid)
1da177e4	153	{
94c12cc7	154	register struct subchannel_id reg1 asm ("1") = schid;
1da177e4 LT	155	int ccode;
1da177e4 LT	156
94c12cc7 MS	157	asm volatile(
	158	" hsch\n"
	159	" ipm %0\n"
	160	" srl %0,28"
	161	: "=d" (ccode) : "d" (reg1) : "cc");
1da177e4 LT	162	return ccode;
	163	}
	164
a8237fc4	165	static inline int xsch(struct subchannel_id schid)
1da177e4	166	{
94c12cc7	167	register struct subchannel_id reg1 asm ("1") = schid;
1da177e4 LT	168	int ccode;
1da177e4 LT	169
94c12cc7 MS	170	asm volatile(
	171	" .insn rre,0xb2760000,%1,0\n"
	172	" ipm %0\n"
	173	" srl %0,28"
	174	: "=d" (ccode) : "d" (reg1) : "cc");
1da177e4 LT	175	return ccode;
	176	}
	177
4c24da79	178	static inline int chsc(void *chsc_area)
1da177e4	179	{
a8237fc4	180	typedef struct { char _[4096]; } addr_type;
1da177e4 LT	181	int cc;
1da177e4 LT	182
94c12cc7 MS	183	asm volatile(
	184	" .insn rre,0xb25f0000,%2,0\n"
	185	" ipm %0\n"
	186	" srl %0,28\n"
a8237fc4 CH	187	: "=d" (cc), "=m" ((addr_type ) chsc_area)
a8237fc4 CH	188	: "d" (chsc_area), "m" ((addr_type ) chsc_area)
94c12cc7	189	: "cc");
1da177e4 LT	190	return cc;
	191	}
	192
f86635fa	193	static inline int rchp(struct chp_id chpid)
1da177e4	194	{
f86635fa	195	register struct chp_id reg1 asm ("1") = chpid;
1da177e4 LT	196	int ccode;
1da177e4 LT	197
94c12cc7 MS	198	asm volatile(
	199	" lr 1,%1\n"
	200	" rchp\n"
	201	" ipm %0\n"
	202	" srl %0,28"
	203	: "=d" (ccode) : "d" (reg1) : "cc");
1da177e4 LT	204	return ccode;
	205	}
	206
	207	#endif