[linux.git] / drivers / gpio / gpio-lynxpoint.c

/*
 * GPIO controller driver for Intel Lynxpoint PCH chipset>
 * Copyright (c) 2012, Intel Corporation.
 *
 * Author: Mathias Nyman <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
#include <linux/acpi.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/io.h>

/* LynxPoint chipset has support for 94 gpio pins */

#define LP_NUM_GPIO	94

/* Bitmapped register offsets */
#define LP_ACPI_OWNED	0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */
#define LP_GC		0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */
#define LP_INT_STAT	0x80
#define LP_INT_ENABLE	0x90

/* Each pin has two 32 bit config registers, starting at 0x100 */
#define LP_CONFIG1	0x100
#define LP_CONFIG2	0x104

/* LP_CONFIG1 reg bits */
#define OUT_LVL_BIT	BIT(31)
#define IN_LVL_BIT	BIT(30)
#define TRIG_SEL_BIT	BIT(4) /* 0: Edge, 1: Level */
#define INT_INV_BIT	BIT(3) /* Invert interrupt triggering */
#define DIR_BIT		BIT(2) /* 0: Output, 1: Input */
#define USE_SEL_BIT	BIT(0) /* 0: Native, 1: GPIO */

/* LP_CONFIG2 reg bits */
#define GPINDIS_BIT	BIT(2) /* disable input sensing */
#define GPIWP_BIT	(BIT(0) | BIT(1)) /* weak pull options */

struct lp_gpio {
	struct gpio_chip	chip;
	struct platform_device	*pdev;
	spinlock_t		lock;
	unsigned long		reg_base;
};

/*
 * Lynxpoint gpios are controlled through both bitmapped registers and
 * per gpio specific registers. The bitmapped registers are in chunks of
 * 3 x 32bit registers to cover all 94 gpios
 *
 * per gpio specific registers consist of two 32bit registers per gpio
 * (LP_CONFIG1 and LP_CONFIG2), with 94 gpios there's a total of
 * 188 config registers.
 *
 * A simplified view of the register layout look like this:
 *
 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31  (bitmapped registers)
 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
 * ...
 * LP_INT_ENABLE[31:0] ...
 * LP_INT_ENABLE[63:31] ...
 * LP_INT_ENABLE[94:64] ...
 * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers)
 * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0
 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1
 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1
 * LP2_CONFIG1 (gpio 2) ...
 * LP2_CONFIG2 (gpio 2) ...
 * ...
 * LP94_CONFIG1 (gpio 94) ...
 * LP94_CONFIG2 (gpio 94) ...
 */

static unsigned long lp_gpio_reg(struct gpio_chip *chip, unsigned offset,
				 int reg)
{
	struct lp_gpio *lg = gpiochip_get_data(chip);
	int reg_offset;

	if (reg == LP_CONFIG1 || reg == LP_CONFIG2)
		/* per gpio specific config registers */
		reg_offset = offset * 8;
	else
		/* bitmapped registers */
		reg_offset = (offset / 32) * 4;

	return lg->reg_base + reg + reg_offset;
}

static int lp_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	struct lp_gpio *lg = gpiochip_get_data(chip);
	unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
	unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
	unsigned long acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED);

	pm_runtime_get(&lg->pdev->dev); /* should we put if failed */

	/* Fail if BIOS reserved pin for ACPI use */
	if (!(inl(acpi_use) & BIT(offset % 32))) {
		dev_err(&lg->pdev->dev, "gpio %d reserved for ACPI\n", offset);
		return -EBUSY;
	}
	/* Fail if pin is in alternate function mode (not GPIO mode) */
	if (!(inl(reg) & USE_SEL_BIT))
		return -ENODEV;

	/* enable input sensing */
	outl(inl(conf2) & ~GPINDIS_BIT, conf2);


	return 0;
}

static void lp_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	struct lp_gpio *lg = gpiochip_get_data(chip);
	unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);

	/* disable input sensing */
	outl(inl(conf2) | GPINDIS_BIT, conf2);

	pm_runtime_put(&lg->pdev->dev);
}

static int lp_irq_type(struct irq_data *d, unsigned type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct lp_gpio *lg = gpiochip_get_data(gc);
	u32 hwirq = irqd_to_hwirq(d);
	unsigned long flags;
	u32 value;
	unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);

	if (hwirq >= lg->chip.ngpio)
		return -EINVAL;

	spin_lock_irqsave(&lg->lock, flags);
	value = inl(reg);

	/* set both TRIG_SEL and INV bits to 0 for rising edge */
	if (type & IRQ_TYPE_EDGE_RISING)
		value &= ~(TRIG_SEL_BIT | INT_INV_BIT);

	/* TRIG_SEL bit 0, INV bit 1 for falling edge */
	if (type & IRQ_TYPE_EDGE_FALLING)
		value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT;

	/* TRIG_SEL bit 1, INV bit 0 for level low */
	if (type & IRQ_TYPE_LEVEL_LOW)
		value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT;

	/* TRIG_SEL bit 1, INV bit 1 for level high */
	if (type & IRQ_TYPE_LEVEL_HIGH)
		value |= TRIG_SEL_BIT | INT_INV_BIT;

	outl(value, reg);
	spin_unlock_irqrestore(&lg->lock, flags);

	return 0;
}

static int lp_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
	return !!(inl(reg) & IN_LVL_BIT);
}

static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct lp_gpio *lg = gpiochip_get_data(chip);
	unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
	unsigned long flags;

	spin_lock_irqsave(&lg->lock, flags);

	if (value)
		outl(inl(reg) | OUT_LVL_BIT, reg);
	else
		outl(inl(reg) & ~OUT_LVL_BIT, reg);

	spin_unlock_irqrestore(&lg->lock, flags);
}

static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct lp_gpio *lg = gpiochip_get_data(chip);
	unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
	unsigned long flags;

	spin_lock_irqsave(&lg->lock, flags);
	outl(inl(reg) | DIR_BIT, reg);
	spin_unlock_irqrestore(&lg->lock, flags);

	return 0;
}

static int lp_gpio_direction_output(struct gpio_chip *chip,
				      unsigned offset, int value)
{
	struct lp_gpio *lg = gpiochip_get_data(chip);
	unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
	unsigned long flags;

	lp_gpio_set(chip, offset, value);

	spin_lock_irqsave(&lg->lock, flags);
	outl(inl(reg) & ~DIR_BIT, reg);
	spin_unlock_irqrestore(&lg->lock, flags);

	return 0;
}

static void lp_gpio_irq_handler(struct irq_desc *desc)
{
	struct irq_data *data = irq_desc_get_irq_data(desc);
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	struct lp_gpio *lg = gpiochip_get_data(gc);
	struct irq_chip *chip = irq_data_get_irq_chip(data);
	u32 base, pin, mask;
	unsigned long reg, ena, pending;

	/* check from GPIO controller which pin triggered the interrupt */
	for (base = 0; base < lg->chip.ngpio; base += 32) {
		reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
		ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);

		while ((pending = (inl(reg) & inl(ena)))) {
			unsigned irq;

			pin = __ffs(pending);
			mask = BIT(pin);
			/* Clear before handling so we don't lose an edge */
			outl(mask, reg);
			irq = irq_find_mapping(lg->chip.irq.domain, base + pin);
			generic_handle_irq(irq);
		}
	}
	chip->irq_eoi(data);
}

static void lp_irq_unmask(struct irq_data *d)
{
}

static void lp_irq_mask(struct irq_data *d)
{
}

static void lp_irq_enable(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct lp_gpio *lg = gpiochip_get_data(gc);
	u32 hwirq = irqd_to_hwirq(d);
	unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
	unsigned long flags;

	spin_lock_irqsave(&lg->lock, flags);
	outl(inl(reg) | BIT(hwirq % 32), reg);
	spin_unlock_irqrestore(&lg->lock, flags);
}

static void lp_irq_disable(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct lp_gpio *lg = gpiochip_get_data(gc);
	u32 hwirq = irqd_to_hwirq(d);
	unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
	unsigned long flags;

	spin_lock_irqsave(&lg->lock, flags);
	outl(inl(reg) & ~BIT(hwirq % 32), reg);
	spin_unlock_irqrestore(&lg->lock, flags);
}

static struct irq_chip lp_irqchip = {
	.name = "LP-GPIO",
	.irq_mask = lp_irq_mask,
	.irq_unmask = lp_irq_unmask,
	.irq_enable = lp_irq_enable,
	.irq_disable = lp_irq_disable,
	.irq_set_type = lp_irq_type,
	.flags = IRQCHIP_SKIP_SET_WAKE,
};

static void lp_gpio_irq_init_hw(struct lp_gpio *lg)
{
	unsigned long reg;
	unsigned base;

	for (base = 0; base < lg->chip.ngpio; base += 32) {
		/* disable gpio pin interrupts */
		reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
		outl(0, reg);
		/* Clear interrupt status register */
		reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
		outl(0xffffffff, reg);
	}
}

static int lp_gpio_probe(struct platform_device *pdev)
{
	struct lp_gpio *lg;
	struct gpio_chip *gc;
	struct resource *io_rc, *irq_rc;
	struct device *dev = &pdev->dev;
	unsigned long reg_len;
	int ret = -ENODEV;

	lg = devm_kzalloc(dev, sizeof(struct lp_gpio), GFP_KERNEL);
	if (!lg)
		return -ENOMEM;

	lg->pdev = pdev;
	platform_set_drvdata(pdev, lg);

	io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
	irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);

	if (!io_rc) {
		dev_err(dev, "missing IO resources\n");
		return -EINVAL;
	}

	lg->reg_base = io_rc->start;
	reg_len = resource_size(io_rc);

	if (!devm_request_region(dev, lg->reg_base, reg_len, "lp-gpio")) {
		dev_err(dev, "failed requesting IO region 0x%x\n",
			(unsigned int)lg->reg_base);
		return -EBUSY;
	}

	spin_lock_init(&lg->lock);

	gc = &lg->chip;
	gc->label = dev_name(dev);
	gc->owner = THIS_MODULE;
	gc->request = lp_gpio_request;
	gc->free = lp_gpio_free;
	gc->direction_input = lp_gpio_direction_input;
	gc->direction_output = lp_gpio_direction_output;
	gc->get = lp_gpio_get;
	gc->set = lp_gpio_set;
	gc->base = -1;
	gc->ngpio = LP_NUM_GPIO;
	gc->can_sleep = false;
	gc->parent = dev;

	ret = devm_gpiochip_add_data(dev, gc, lg);
	if (ret) {
		dev_err(dev, "failed adding lp-gpio chip\n");
		return ret;
	}

	/* set up interrupts  */
	if (irq_rc && irq_rc->start) {
		lp_gpio_irq_init_hw(lg);
		ret = gpiochip_irqchip_add(gc, &lp_irqchip, 0,
					   handle_simple_irq, IRQ_TYPE_NONE);
		if (ret) {
			dev_err(dev, "failed to add irqchip\n");
			return ret;
		}

		gpiochip_set_chained_irqchip(gc, &lp_irqchip,
					     (unsigned)irq_rc->start,
					     lp_gpio_irq_handler);
	}

	pm_runtime_enable(dev);

	return 0;
}

static int lp_gpio_runtime_suspend(struct device *dev)
{
	return 0;
}

static int lp_gpio_runtime_resume(struct device *dev)
{
	return 0;
}

static int lp_gpio_resume(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct lp_gpio *lg = platform_get_drvdata(pdev);
	unsigned long reg;
	int i;

	/* on some hardware suspend clears input sensing, re-enable it here */
	for (i = 0; i < lg->chip.ngpio; i++) {
		if (gpiochip_is_requested(&lg->chip, i) != NULL) {
			reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2);
			outl(inl(reg) & ~GPINDIS_BIT, reg);
		}
	}
	return 0;
}

static const struct dev_pm_ops lp_gpio_pm_ops = {
	.runtime_suspend = lp_gpio_runtime_suspend,
	.runtime_resume = lp_gpio_runtime_resume,
	.resume = lp_gpio_resume,
};

static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
	{ "INT33C7", 0 },
	{ "INT3437", 0 },
	{ }
};
MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);

static int lp_gpio_remove(struct platform_device *pdev)
{
	pm_runtime_disable(&pdev->dev);
	return 0;
}

static struct platform_driver lp_gpio_driver = {
	.probe          = lp_gpio_probe,
	.remove         = lp_gpio_remove,
	.driver         = {
		.name   = "lp_gpio",
		.pm	= &lp_gpio_pm_ops,
		.acpi_match_table = ACPI_PTR(lynxpoint_gpio_acpi_match),
	},
};

static int __init lp_gpio_init(void)
{
	return platform_driver_register(&lp_gpio_driver);
}

static void __exit lp_gpio_exit(void)
{
	platform_driver_unregister(&lp_gpio_driver);
}

subsys_initcall(lp_gpio_init);
module_exit(lp_gpio_exit);

MODULE_AUTHOR("Mathias Nyman (Intel)");
MODULE_DESCRIPTION("GPIO interface for Intel Lynxpoint");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:lp_gpio");
Commit	Line	Data
1d09aaa6 MN	1	/*
	2	* GPIO controller driver for Intel Lynxpoint PCH chipset>
	3	* Copyright (c) 2012, Intel Corporation.
	4	*
	5	* Author: Mathias Nyman <[email protected]>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	19	*
	20	*/
	21
	22	#include <linux/kernel.h>
	23	#include <linux/module.h>
	24	#include <linux/init.h>
	25	#include <linux/types.h>
	26	#include <linux/bitops.h>
	27	#include <linux/interrupt.h>
cec93b02	28	#include <linux/gpio/driver.h>
1d09aaa6 MN	29	#include <linux/slab.h>
	30	#include <linux/acpi.h>
	31	#include <linux/platform_device.h>
	32	#include <linux/pm_runtime.h>
977d16b8	33	#include <linux/io.h>
1d09aaa6 MN	34
	35	/* LynxPoint chipset has support for 94 gpio pins */
	36
	37	#define LP_NUM_GPIO 94
	38
	39	/* Bitmapped register offsets */
	40	#define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */
	41	#define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */
	42	#define LP_INT_STAT 0x80
	43	#define LP_INT_ENABLE 0x90
	44
	45	/* Each pin has two 32 bit config registers, starting at 0x100 */
	46	#define LP_CONFIG1 0x100
	47	#define LP_CONFIG2 0x104
	48
	49	/* LP_CONFIG1 reg bits */
	50	#define OUT_LVL_BIT BIT(31)
	51	#define IN_LVL_BIT BIT(30)
	52	#define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */
	53	#define INT_INV_BIT BIT(3) /* Invert interrupt triggering */
	54	#define DIR_BIT BIT(2) /* 0: Output, 1: Input */
	55	#define USE_SEL_BIT BIT(0) /* 0: Native, 1: GPIO */
	56
	57	/* LP_CONFIG2 reg bits */
	58	#define GPINDIS_BIT BIT(2) /* disable input sensing */
	59	#define GPIWP_BIT (BIT(0) \| BIT(1)) /* weak pull options */
	60
	61	struct lp_gpio {
	62	struct gpio_chip chip;
1d09aaa6 MN	63	struct platform_device *pdev;
	64	spinlock_t lock;
	65	unsigned long reg_base;
	66	};
	67
	68	/*
	69	* Lynxpoint gpios are controlled through both bitmapped registers and
	70	* per gpio specific registers. The bitmapped registers are in chunks of
	71	* 3 x 32bit registers to cover all 94 gpios
	72	*
	73	* per gpio specific registers consist of two 32bit registers per gpio
	74	* (LP_CONFIG1 and LP_CONFIG2), with 94 gpios there's a total of
20a8a968	75	* 188 config registers.
1d09aaa6 MN	76	*
	77	* A simplified view of the register layout look like this:
	78	*
	79	* LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers)
	80	* LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
	81	* LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
	82	* ...
	83	* LP_INT_ENABLE[31:0] ...
	84	* LP_INT_ENABLE[63:31] ...
	85	* LP_INT_ENABLE[94:64] ...
	86	* LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers)
	87	* LP0_CONFIG2 (gpio 0) config2 reg for gpio 0
	88	* LP1_CONFIG1 (gpio 1) config1 reg for gpio 1
	89	* LP1_CONFIG2 (gpio 1) config2 reg for gpio 1
	90	* LP2_CONFIG1 (gpio 2) ...
	91	* LP2_CONFIG2 (gpio 2) ...
	92	* ...
	93	* LP94_CONFIG1 (gpio 94) ...
	94	* LP94_CONFIG2 (gpio 94) ...
	95	*/
	96
	97	static unsigned long lp_gpio_reg(struct gpio_chip *chip, unsigned offset,
	98	int reg)
	99	{
f291e006	100	struct lp_gpio *lg = gpiochip_get_data(chip);
1d09aaa6 MN	101	int reg_offset;
	102
	103	if (reg == LP_CONFIG1 \|\| reg == LP_CONFIG2)
	104	/* per gpio specific config registers */
	105	reg_offset = offset * 8;
	106	else
	107	/* bitmapped registers */
	108	reg_offset = (offset / 32) * 4;
	109
	110	return lg->reg_base + reg + reg_offset;
	111	}
	112
	113	static int lp_gpio_request(struct gpio_chip *chip, unsigned offset)
	114	{
f291e006	115	struct lp_gpio *lg = gpiochip_get_data(chip);
1d09aaa6 MN	116	unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
	117	unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
	118	unsigned long acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED);
	119
	120	pm_runtime_get(&lg->pdev->dev); /* should we put if failed */
	121
	122	/* Fail if BIOS reserved pin for ACPI use */
	123	if (!(inl(acpi_use) & BIT(offset % 32))) {
	124	dev_err(&lg->pdev->dev, "gpio %d reserved for ACPI\n", offset);
	125	return -EBUSY;
	126	}
	127	/* Fail if pin is in alternate function mode (not GPIO mode) */
	128	if (!(inl(reg) & USE_SEL_BIT))
	129	return -ENODEV;
	130
	131	/* enable input sensing */
	132	outl(inl(conf2) & ~GPINDIS_BIT, conf2);
	133
	134
	135	return 0;
	136	}
	137
	138	static void lp_gpio_free(struct gpio_chip *chip, unsigned offset)
	139	{
f291e006	140	struct lp_gpio *lg = gpiochip_get_data(chip);
1d09aaa6 MN	141	unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
	142
	143	/* disable input sensing */
	144	outl(inl(conf2) \| GPINDIS_BIT, conf2);
	145
	146	pm_runtime_put(&lg->pdev->dev);
	147	}
	148
	149	static int lp_irq_type(struct irq_data *d, unsigned type)
	150	{
7f87210e	151	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
f291e006	152	struct lp_gpio *lg = gpiochip_get_data(gc);
1d09aaa6 MN	153	u32 hwirq = irqd_to_hwirq(d);
	154	unsigned long flags;
	155	u32 value;
	156	unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
	157
	158	if (hwirq >= lg->chip.ngpio)
	159	return -EINVAL;
	160
	161	spin_lock_irqsave(&lg->lock, flags);
	162	value = inl(reg);
	163
	164	/* set both TRIG_SEL and INV bits to 0 for rising edge */
	165	if (type & IRQ_TYPE_EDGE_RISING)
	166	value &= ~(TRIG_SEL_BIT \| INT_INV_BIT);
	167
	168	/* TRIG_SEL bit 0, INV bit 1 for falling edge */
	169	if (type & IRQ_TYPE_EDGE_FALLING)
	170	value = (value \| INT_INV_BIT) & ~TRIG_SEL_BIT;
	171
	172	/* TRIG_SEL bit 1, INV bit 0 for level low */
	173	if (type & IRQ_TYPE_LEVEL_LOW)
	174	value = (value \| TRIG_SEL_BIT) & ~INT_INV_BIT;
	175
	176	/* TRIG_SEL bit 1, INV bit 1 for level high */
	177	if (type & IRQ_TYPE_LEVEL_HIGH)
	178	value \|= TRIG_SEL_BIT \| INT_INV_BIT;
	179
	180	outl(value, reg);
	181	spin_unlock_irqrestore(&lg->lock, flags);
	182
	183	return 0;
	184	}
	185
	186	static int lp_gpio_get(struct gpio_chip *chip, unsigned offset)
	187	{
	188	unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
8650ea1e	189	return !!(inl(reg) & IN_LVL_BIT);
1d09aaa6 MN	190	}
	191
	192	static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	193	{
f291e006	194	struct lp_gpio *lg = gpiochip_get_data(chip);
1d09aaa6 MN	195	unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
	196	unsigned long flags;
	197
	198	spin_lock_irqsave(&lg->lock, flags);
	199
	200	if (value)
	201	outl(inl(reg) \| OUT_LVL_BIT, reg);
	202	else
	203	outl(inl(reg) & ~OUT_LVL_BIT, reg);
	204
	205	spin_unlock_irqrestore(&lg->lock, flags);
	206	}
	207
	208	static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	209	{
f291e006	210	struct lp_gpio *lg = gpiochip_get_data(chip);
1d09aaa6 MN	211	unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
	212	unsigned long flags;
	213
	214	spin_lock_irqsave(&lg->lock, flags);
	215	outl(inl(reg) \| DIR_BIT, reg);
	216	spin_unlock_irqrestore(&lg->lock, flags);
	217
	218	return 0;
	219	}
	220
	221	static int lp_gpio_direction_output(struct gpio_chip *chip,
	222	unsigned offset, int value)
	223	{
f291e006	224	struct lp_gpio *lg = gpiochip_get_data(chip);
1d09aaa6 MN	225	unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
	226	unsigned long flags;
	227
	228	lp_gpio_set(chip, offset, value);
	229
	230	spin_lock_irqsave(&lg->lock, flags);
	231	outl(inl(reg) & ~DIR_BIT, reg);
	232	spin_unlock_irqrestore(&lg->lock, flags);
	233
	234	return 0;
	235	}
	236
bd0b9ac4	237	static void lp_gpio_irq_handler(struct irq_desc *desc)
1d09aaa6 MN	238	{
1d09aaa6 MN	239	struct irq_data *data = irq_desc_get_irq_data(desc);
7f87210e	240	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
f291e006	241	struct lp_gpio *lg = gpiochip_get_data(gc);
1d09aaa6 MN	242	struct irq_chip *chip = irq_data_get_irq_chip(data);
1d09aaa6 MN	243	u32 base, pin, mask;
03d152d5	244	unsigned long reg, ena, pending;
1d09aaa6 MN	245
	246	/* check from GPIO controller which pin triggered the interrupt */
	247	for (base = 0; base < lg->chip.ngpio; base += 32) {
	248	reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
03d152d5	249	ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
1d09aaa6	250
03d152d5	251	while ((pending = (inl(reg) & inl(ena)))) {
b551b023 LW	252	unsigned irq;
b551b023 LW	253
1d09aaa6 MN	254	pin = __ffs(pending);
	255	mask = BIT(pin);
	256	/* Clear before handling so we don't lose an edge */
	257	outl(mask, reg);
f0fbe7bc	258	irq = irq_find_mapping(lg->chip.irq.domain, base + pin);
b551b023	259	generic_handle_irq(irq);
1d09aaa6 MN	260	}
	261	}
	262	chip->irq_eoi(data);
	263	}
	264
	265	static void lp_irq_unmask(struct irq_data *d)
	266	{
	267	}
	268
	269	static void lp_irq_mask(struct irq_data *d)
	270	{
	271	}
	272
	273	static void lp_irq_enable(struct irq_data *d)
	274	{
7f87210e	275	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
f291e006	276	struct lp_gpio *lg = gpiochip_get_data(gc);
1d09aaa6 MN	277	u32 hwirq = irqd_to_hwirq(d);
	278	unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
	279	unsigned long flags;
	280
	281	spin_lock_irqsave(&lg->lock, flags);
	282	outl(inl(reg) \| BIT(hwirq % 32), reg);
	283	spin_unlock_irqrestore(&lg->lock, flags);
	284	}
	285
	286	static void lp_irq_disable(struct irq_data *d)
	287	{
7f87210e	288	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
f291e006	289	struct lp_gpio *lg = gpiochip_get_data(gc);
1d09aaa6 MN	290	u32 hwirq = irqd_to_hwirq(d);
	291	unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
	292	unsigned long flags;
	293
	294	spin_lock_irqsave(&lg->lock, flags);
	295	outl(inl(reg) & ~BIT(hwirq % 32), reg);
	296	spin_unlock_irqrestore(&lg->lock, flags);
	297	}
	298
	299	static struct irq_chip lp_irqchip = {
	300	.name = "LP-GPIO",
	301	.irq_mask = lp_irq_mask,
	302	.irq_unmask = lp_irq_unmask,
	303	.irq_enable = lp_irq_enable,
	304	.irq_disable = lp_irq_disable,
	305	.irq_set_type = lp_irq_type,
	306	.flags = IRQCHIP_SKIP_SET_WAKE,
	307	};
	308
	309	static void lp_gpio_irq_init_hw(struct lp_gpio *lg)
	310	{
	311	unsigned long reg;
	312	unsigned base;
	313
	314	for (base = 0; base < lg->chip.ngpio; base += 32) {
	315	/* disable gpio pin interrupts */
	316	reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
	317	outl(0, reg);
	318	/* Clear interrupt status register */
	319	reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
	320	outl(0xffffffff, reg);
	321	}
	322	}
	323
1d09aaa6 MN	324	static int lp_gpio_probe(struct platform_device *pdev)
	325	{
	326	struct lp_gpio *lg;
	327	struct gpio_chip *gc;
	328	struct resource io_rc, irq_rc;
	329	struct device *dev = &pdev->dev;
	330	unsigned long reg_len;
1d09aaa6 MN	331	int ret = -ENODEV;
	332
	333	lg = devm_kzalloc(dev, sizeof(struct lp_gpio), GFP_KERNEL);
1981d084	334	if (!lg)
1d09aaa6	335	return -ENOMEM;
1d09aaa6 MN	336
	337	lg->pdev = pdev;
	338	platform_set_drvdata(pdev, lg);
	339
	340	io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
	341	irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	342
	343	if (!io_rc) {
	344	dev_err(dev, "missing IO resources\n");
	345	return -EINVAL;
	346	}
	347
	348	lg->reg_base = io_rc->start;
	349	reg_len = resource_size(io_rc);
	350
	351	if (!devm_request_region(dev, lg->reg_base, reg_len, "lp-gpio")) {
	352	dev_err(dev, "failed requesting IO region 0x%x\n",
	353	(unsigned int)lg->reg_base);
	354	return -EBUSY;
	355	}
	356
	357	spin_lock_init(&lg->lock);
	358
	359	gc = &lg->chip;
	360	gc->label = dev_name(dev);
	361	gc->owner = THIS_MODULE;
	362	gc->request = lp_gpio_request;
	363	gc->free = lp_gpio_free;
	364	gc->direction_input = lp_gpio_direction_input;
	365	gc->direction_output = lp_gpio_direction_output;
	366	gc->get = lp_gpio_get;
	367	gc->set = lp_gpio_set;
	368	gc->base = -1;
	369	gc->ngpio = LP_NUM_GPIO;
9fb1f39e	370	gc->can_sleep = false;
58383c78	371	gc->parent = dev;
1d09aaa6	372
efa3ffcd	373	ret = devm_gpiochip_add_data(dev, gc, lg);
7f87210e MW	374	if (ret) {
	375	dev_err(dev, "failed adding lp-gpio chip\n");
	376	return ret;
	377	}
	378
1d09aaa6 MN	379	/* set up interrupts */
1d09aaa6 MN	380	if (irq_rc && irq_rc->start) {
1d09aaa6	381	lp_gpio_irq_init_hw(lg);
7f87210e MW	382	ret = gpiochip_irqchip_add(gc, &lp_irqchip, 0,
	383	handle_simple_irq, IRQ_TYPE_NONE);
	384	if (ret) {
	385	dev_err(dev, "failed to add irqchip\n");
7f87210e MW	386	return ret;
7f87210e MW	387	}
1d09aaa6	388
7f87210e MW	389	gpiochip_set_chained_irqchip(gc, &lp_irqchip,
	390	(unsigned)irq_rc->start,
	391	lp_gpio_irq_handler);
1d09aaa6 MN	392	}
1d09aaa6 MN	393
1d09aaa6 MN	394	pm_runtime_enable(dev);
	395
	396	return 0;
	397	}
	398
	399	static int lp_gpio_runtime_suspend(struct device *dev)
	400	{
	401	return 0;
	402	}
	403
	404	static int lp_gpio_runtime_resume(struct device *dev)
	405	{
	406	return 0;
	407	}
	408
8117bd53 MN	409	static int lp_gpio_resume(struct device *dev)
	410	{
	411	struct platform_device *pdev = to_platform_device(dev);
	412	struct lp_gpio *lg = platform_get_drvdata(pdev);
	413	unsigned long reg;
	414	int i;
	415
	416	/* on some hardware suspend clears input sensing, re-enable it here */
	417	for (i = 0; i < lg->chip.ngpio; i++) {
	418	if (gpiochip_is_requested(&lg->chip, i) != NULL) {
	419	reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2);
	420	outl(inl(reg) & ~GPINDIS_BIT, reg);
	421	}
	422	}
	423	return 0;
	424	}
	425
1d09aaa6 MN	426	static const struct dev_pm_ops lp_gpio_pm_ops = {
	427	.runtime_suspend = lp_gpio_runtime_suspend,
	428	.runtime_resume = lp_gpio_runtime_resume,
8117bd53	429	.resume = lp_gpio_resume,
1d09aaa6 MN	430	};
	431
	432	static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
	433	{ "INT33C7", 0 },
4edd7901	434	{ "INT3437", 0 },
1d09aaa6 MN	435	{ }
	436	};
	437	MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);
	438
	439	static int lp_gpio_remove(struct platform_device *pdev)
	440	{
b168386e	441	pm_runtime_disable(&pdev->dev);
1d09aaa6 MN	442	return 0;
	443	}
	444
	445	static struct platform_driver lp_gpio_driver = {
	446	.probe = lp_gpio_probe,
	447	.remove = lp_gpio_remove,
	448	.driver = {
	449	.name = "lp_gpio",
1d09aaa6 MN	450	.pm = &lp_gpio_pm_ops,
	451	.acpi_match_table = ACPI_PTR(lynxpoint_gpio_acpi_match),
	452	},
	453	};
	454
	455	static int __init lp_gpio_init(void)
	456	{
	457	return platform_driver_register(&lp_gpio_driver);
	458	}
	459
d463c6ff JD	460	static void __exit lp_gpio_exit(void)
	461	{
	462	platform_driver_unregister(&lp_gpio_driver);
	463	}
	464
1d09aaa6	465	subsys_initcall(lp_gpio_init);
d463c6ff JD	466	module_exit(lp_gpio_exit);
	467
	468	MODULE_AUTHOR("Mathias Nyman (Intel)");
	469	MODULE_DESCRIPTION("GPIO interface for Intel Lynxpoint");
	470	MODULE_LICENSE("GPL");
	471	MODULE_ALIAS("platform:lp_gpio");