[linux.git] / drivers / hwmon / k10temp.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h
 *		processor hardware monitoring
 *
 * Copyright (c) 2009 Clemens Ladisch <[email protected]>
 * Copyright (c) 2020 Guenter Roeck <[email protected]>
 *
 * Implementation notes:
 * - CCD register address information as well as the calculation to
 *   convert raw register values is from https://github.com/ocerman/zenpower.
 *   The information is not confirmed from chip datasheets, but experiments
 *   suggest that it provides reasonable temperature values.
 * - Register addresses to read chip voltage and current are also from
 *   https://github.com/ocerman/zenpower, and not confirmed from chip
 *   datasheets. Current calibration is board specific and not typically
 *   shared by board vendors. For this reason, current values are
 *   normalized to report 1A/LSB for core current and and 0.25A/LSB for SoC
 *   current. Reported values can be adjusted using the sensors configuration
 *   file.
 */

#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <asm/amd_nb.h>
#include <asm/processor.h>

MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
MODULE_AUTHOR("Clemens Ladisch <[email protected]>");
MODULE_LICENSE("GPL");

static bool force;
module_param(force, bool, 0444);
MODULE_PARM_DESC(force, "force loading on processors with erratum 319");

/* Provide lock for writing to NB_SMU_IND_ADDR */
static DEFINE_MUTEX(nb_smu_ind_mutex);

#ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3	0x15b3
#endif

/* CPUID function 0x80000001, ebx */
#define CPUID_PKGTYPE_MASK	GENMASK(31, 28)
#define CPUID_PKGTYPE_F		0x00000000
#define CPUID_PKGTYPE_AM2R2_AM3	0x10000000

/* DRAM controller (PCI function 2) */
#define REG_DCT0_CONFIG_HIGH		0x094
#define  DDR3_MODE			BIT(8)

/* miscellaneous (PCI function 3) */
#define REG_HARDWARE_THERMAL_CONTROL	0x64
#define  HTC_ENABLE			BIT(0)

#define REG_REPORTED_TEMPERATURE	0xa4

#define REG_NORTHBRIDGE_CAPABILITIES	0xe8
#define  NB_CAP_HTC			BIT(10)

/*
 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
 * and REG_REPORTED_TEMPERATURE have been moved to
 * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
 * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
 */
#define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET	0xd8200c64
#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET	0xd8200ca4

/* Common for Zen CPU families (Family 17h and 18h) */
#define ZEN_REPORTED_TEMP_CTRL_OFFSET		0x00059800

#define ZEN_CCD_TEMP(x)				(0x00059954 + ((x) * 4))
#define ZEN_CCD_TEMP_VALID			BIT(11)
#define ZEN_CCD_TEMP_MASK			GENMASK(10, 0)

#define ZEN_CUR_TEMP_SHIFT			21
#define ZEN_CUR_TEMP_RANGE_SEL_MASK		BIT(19)

#define ZEN_SVI_BASE				0x0005A000

/* F17h thermal registers through SMN */
#define F17H_M01H_SVI_TEL_PLANE0		(ZEN_SVI_BASE + 0xc)
#define F17H_M01H_SVI_TEL_PLANE1		(ZEN_SVI_BASE + 0x10)
#define F17H_M31H_SVI_TEL_PLANE0		(ZEN_SVI_BASE + 0x14)
#define F17H_M31H_SVI_TEL_PLANE1		(ZEN_SVI_BASE + 0x10)

#define F17H_M01H_CFACTOR_ICORE			1000000	/* 1A / LSB	*/
#define F17H_M01H_CFACTOR_ISOC			250000	/* 0.25A / LSB	*/
#define F17H_M31H_CFACTOR_ICORE			1000000	/* 1A / LSB	*/
#define F17H_M31H_CFACTOR_ISOC			310000	/* 0.31A / LSB	*/

/* F19h thermal registers through SMN */
#define F19H_M01_SVI_TEL_PLANE0			(ZEN_SVI_BASE + 0x14)
#define F19H_M01_SVI_TEL_PLANE1			(ZEN_SVI_BASE + 0x10)

#define F19H_M01H_CFACTOR_ICORE			1000000	/* 1A / LSB	*/
#define F19H_M01H_CFACTOR_ISOC			310000	/* 0.31A / LSB	*/

struct k10temp_data {
	struct pci_dev *pdev;
	void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
	void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
	int temp_offset;
	u32 temp_adjust_mask;
	u32 show_temp;
	u32 svi_addr[2];
	bool is_zen;
	bool show_current;
	int cfactor[2];
};

#define TCTL_BIT	0
#define TDIE_BIT	1
#define TCCD_BIT(x)	((x) + 2)

#define HAVE_TEMP(d, channel)	((d)->show_temp & BIT(channel))
#define HAVE_TDIE(d)		HAVE_TEMP(d, TDIE_BIT)

struct tctl_offset {
	u8 model;
	char const *id;
	int offset;
};

static const struct tctl_offset tctl_offset_table[] = {
	{ 0x17, "AMD Ryzen 5 1600X", 20000 },
	{ 0x17, "AMD Ryzen 7 1700X", 20000 },
	{ 0x17, "AMD Ryzen 7 1800X", 20000 },
	{ 0x17, "AMD Ryzen 7 2700X", 10000 },
	{ 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
	{ 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
};

static bool is_threadripper(void)
{
	return strstr(boot_cpu_data.x86_model_id, "Threadripper");
}

static bool is_epyc(void)
{
	return strstr(boot_cpu_data.x86_model_id, "EPYC");
}

static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
{
	pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
}

static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
{
	pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
}

static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
			      unsigned int base, int offset, u32 *val)
{
	mutex_lock(&nb_smu_ind_mutex);
	pci_bus_write_config_dword(pdev->bus, devfn,
				   base, offset);
	pci_bus_read_config_dword(pdev->bus, devfn,
				  base + 4, val);
	mutex_unlock(&nb_smu_ind_mutex);
}

static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
{
	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
			  F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
}

static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
{
	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
			  F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
}

static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval)
{
	amd_smn_read(amd_pci_dev_to_node_id(pdev),
		     ZEN_REPORTED_TEMP_CTRL_OFFSET, regval);
}

static long get_raw_temp(struct k10temp_data *data)
{
	u32 regval;
	long temp;

	data->read_tempreg(data->pdev, &regval);
	temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125;
	if (regval & data->temp_adjust_mask)
		temp -= 49000;
	return temp;
}

static const char *k10temp_temp_label[] = {
	"Tctl",
	"Tdie",
	"Tccd1",
	"Tccd2",
	"Tccd3",
	"Tccd4",
	"Tccd5",
	"Tccd6",
	"Tccd7",
	"Tccd8",
};

static const char *k10temp_in_label[] = {
	"Vcore",
	"Vsoc",
};

static const char *k10temp_curr_label[] = {
	"Icore",
	"Isoc",
};

static int k10temp_read_labels(struct device *dev,
			       enum hwmon_sensor_types type,
			       u32 attr, int channel, const char **str)
{
	switch (type) {
	case hwmon_temp:
		*str = k10temp_temp_label[channel];
		break;
	case hwmon_in:
		*str = k10temp_in_label[channel];
		break;
	case hwmon_curr:
		*str = k10temp_curr_label[channel];
		break;
	default:
		return -EOPNOTSUPP;
	}
	return 0;
}

static int k10temp_read_curr(struct device *dev, u32 attr, int channel,
			     long *val)
{
	struct k10temp_data *data = dev_get_drvdata(dev);
	u32 regval;

	switch (attr) {
	case hwmon_curr_input:
		amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
			     data->svi_addr[channel], &regval);
		*val = DIV_ROUND_CLOSEST(data->cfactor[channel] *
					 (regval & 0xff),
					 1000);
		break;
	default:
		return -EOPNOTSUPP;
	}
	return 0;
}

static int k10temp_read_in(struct device *dev, u32 attr, int channel, long *val)
{
	struct k10temp_data *data = dev_get_drvdata(dev);
	u32 regval;

	switch (attr) {
	case hwmon_in_input:
		amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
			     data->svi_addr[channel], &regval);
		regval = (regval >> 16) & 0xff;
		*val = DIV_ROUND_CLOSEST(155000 - regval * 625, 100);
		break;
	default:
		return -EOPNOTSUPP;
	}
	return 0;
}

static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
			     long *val)
{
	struct k10temp_data *data = dev_get_drvdata(dev);
	u32 regval;

	switch (attr) {
	case hwmon_temp_input:
		switch (channel) {
		case 0:		/* Tctl */
			*val = get_raw_temp(data);
			if (*val < 0)
				*val = 0;
			break;
		case 1:		/* Tdie */
			*val = get_raw_temp(data) - data->temp_offset;
			if (*val < 0)
				*val = 0;
			break;
		case 2 ... 9:		/* Tccd{1-8} */
			amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
				     ZEN_CCD_TEMP(channel - 2), &regval);
			*val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000;
			break;
		default:
			return -EOPNOTSUPP;
		}
		break;
	case hwmon_temp_max:
		*val = 70 * 1000;
		break;
	case hwmon_temp_crit:
		data->read_htcreg(data->pdev, &regval);
		*val = ((regval >> 16) & 0x7f) * 500 + 52000;
		break;
	case hwmon_temp_crit_hyst:
		data->read_htcreg(data->pdev, &regval);
		*val = (((regval >> 16) & 0x7f)
			- ((regval >> 24) & 0xf)) * 500 + 52000;
		break;
	default:
		return -EOPNOTSUPP;
	}
	return 0;
}

static int k10temp_read(struct device *dev, enum hwmon_sensor_types type,
			u32 attr, int channel, long *val)
{
	switch (type) {
	case hwmon_temp:
		return k10temp_read_temp(dev, attr, channel, val);
	case hwmon_in:
		return k10temp_read_in(dev, attr, channel, val);
	case hwmon_curr:
		return k10temp_read_curr(dev, attr, channel, val);
	default:
		return -EOPNOTSUPP;
	}
}

static umode_t k10temp_is_visible(const void *_data,
				  enum hwmon_sensor_types type,
				  u32 attr, int channel)
{
	const struct k10temp_data *data = _data;
	struct pci_dev *pdev = data->pdev;
	u32 reg;

	switch (type) {
	case hwmon_temp:
		switch (attr) {
		case hwmon_temp_input:
			if (!HAVE_TEMP(data, channel))
				return 0;
			break;
		case hwmon_temp_max:
			if (channel || data->is_zen)
				return 0;
			break;
		case hwmon_temp_crit:
		case hwmon_temp_crit_hyst:
			if (channel || !data->read_htcreg)
				return 0;

			pci_read_config_dword(pdev,
					      REG_NORTHBRIDGE_CAPABILITIES,
					      &reg);
			if (!(reg & NB_CAP_HTC))
				return 0;

			data->read_htcreg(data->pdev, &reg);
			if (!(reg & HTC_ENABLE))
				return 0;
			break;
		case hwmon_temp_label:
			/* Show temperature labels only on Zen CPUs */
			if (!data->is_zen || !HAVE_TEMP(data, channel))
				return 0;
			break;
		default:
			return 0;
		}
		break;
	case hwmon_in:
	case hwmon_curr:
		if (!data->show_current)
			return 0;
		break;
	default:
		return 0;
	}
	return 0444;
}

static bool has_erratum_319(struct pci_dev *pdev)
{
	u32 pkg_type, reg_dram_cfg;

	if (boot_cpu_data.x86 != 0x10)
		return false;

	/*
	 * Erratum 319: The thermal sensor of Socket F/AM2+ processors
	 *              may be unreliable.
	 */
	pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
	if (pkg_type == CPUID_PKGTYPE_F)
		return true;
	if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
		return false;

	/* DDR3 memory implies socket AM3, which is good */
	pci_bus_read_config_dword(pdev->bus,
				  PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
				  REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
	if (reg_dram_cfg & DDR3_MODE)
		return false;

	/*
	 * Unfortunately it is possible to run a socket AM3 CPU with DDR2
	 * memory. We blacklist all the cores which do exist in socket AM2+
	 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
	 * and AM3 formats, but that's the best we can do.
	 */
	return boot_cpu_data.x86_model < 4 ||
	       (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
}

static const struct hwmon_channel_info *k10temp_info[] = {
	HWMON_CHANNEL_INFO(temp,
			   HWMON_T_INPUT | HWMON_T_MAX |
			   HWMON_T_CRIT | HWMON_T_CRIT_HYST |
			   HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL),
	HWMON_CHANNEL_INFO(in,
			   HWMON_I_INPUT | HWMON_I_LABEL,
			   HWMON_I_INPUT | HWMON_I_LABEL),
	HWMON_CHANNEL_INFO(curr,
			   HWMON_C_INPUT | HWMON_C_LABEL,
			   HWMON_C_INPUT | HWMON_C_LABEL),
	NULL
};

static const struct hwmon_ops k10temp_hwmon_ops = {
	.is_visible = k10temp_is_visible,
	.read = k10temp_read,
	.read_string = k10temp_read_labels,
};

static const struct hwmon_chip_info k10temp_chip_info = {
	.ops = &k10temp_hwmon_ops,
	.info = k10temp_info,
};

static void k10temp_get_ccd_support(struct pci_dev *pdev,
				    struct k10temp_data *data, int limit)
{
	u32 regval;
	int i;

	for (i = 0; i < limit; i++) {
		amd_smn_read(amd_pci_dev_to_node_id(pdev),
			     ZEN_CCD_TEMP(i), &regval);
		if (regval & ZEN_CCD_TEMP_VALID)
			data->show_temp |= BIT(TCCD_BIT(i));
	}
}

static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
	int unreliable = has_erratum_319(pdev);
	struct device *dev = &pdev->dev;
	struct k10temp_data *data;
	struct device *hwmon_dev;
	int i;

	if (unreliable) {
		if (!force) {
			dev_err(dev,
				"unreliable CPU thermal sensor; monitoring disabled\n");
			return -ENODEV;
		}
		dev_warn(dev,
			 "unreliable CPU thermal sensor; check erratum 319\n");
	}

	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->pdev = pdev;
	data->show_temp |= BIT(TCTL_BIT);	/* Always show Tctl */

	if (boot_cpu_data.x86 == 0x15 &&
	    ((boot_cpu_data.x86_model & 0xf0) == 0x60 ||
	     (boot_cpu_data.x86_model & 0xf0) == 0x70)) {
		data->read_htcreg = read_htcreg_nb_f15;
		data->read_tempreg = read_tempreg_nb_f15;
	} else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
		data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
		data->read_tempreg = read_tempreg_nb_zen;
		data->show_temp |= BIT(TDIE_BIT);	/* show Tdie */
		data->is_zen = true;

		switch (boot_cpu_data.x86_model) {
		case 0x1:	/* Zen */
		case 0x8:	/* Zen+ */
		case 0x11:	/* Zen APU */
		case 0x18:	/* Zen+ APU */
			data->show_current = !is_threadripper() && !is_epyc();
			data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE0;
			data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE1;
			data->cfactor[0] = F17H_M01H_CFACTOR_ICORE;
			data->cfactor[1] = F17H_M01H_CFACTOR_ISOC;
			k10temp_get_ccd_support(pdev, data, 4);
			break;
		case 0x31:	/* Zen2 Threadripper */
		case 0x71:	/* Zen2 */
			data->show_current = !is_threadripper() && !is_epyc();
			data->cfactor[0] = F17H_M31H_CFACTOR_ICORE;
			data->cfactor[1] = F17H_M31H_CFACTOR_ISOC;
			data->svi_addr[0] = F17H_M31H_SVI_TEL_PLANE0;
			data->svi_addr[1] = F17H_M31H_SVI_TEL_PLANE1;
			k10temp_get_ccd_support(pdev, data, 8);
			break;
		}
	} else if (boot_cpu_data.x86 == 0x19) {
		data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
		data->read_tempreg = read_tempreg_nb_zen;
		data->show_temp |= BIT(TDIE_BIT);
		data->is_zen = true;

		switch (boot_cpu_data.x86_model) {
		case 0x0 ... 0x1:	/* Zen3 */
			data->show_current = true;
			data->svi_addr[0] = F19H_M01_SVI_TEL_PLANE0;
			data->svi_addr[1] = F19H_M01_SVI_TEL_PLANE1;
			data->cfactor[0] = F19H_M01H_CFACTOR_ICORE;
			data->cfactor[1] = F19H_M01H_CFACTOR_ISOC;
			k10temp_get_ccd_support(pdev, data, 8);
			break;
		}
	} else {
		data->read_htcreg = read_htcreg_pci;
		data->read_tempreg = read_tempreg_pci;
	}

	for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
		const struct tctl_offset *entry = &tctl_offset_table[i];

		if (boot_cpu_data.x86 == entry->model &&
		    strstr(boot_cpu_data.x86_model_id, entry->id)) {
			data->temp_offset = entry->offset;
			break;
		}
	}

	hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data,
							 &k10temp_chip_info,
							 NULL);
	return PTR_ERR_OR_ZERO(hwmon_dev);
}

static const struct pci_device_id k10temp_id_table[] = {
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
	{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
	{}
};
MODULE_DEVICE_TABLE(pci, k10temp_id_table);

static struct pci_driver k10temp_driver = {
	.name = "k10temp",
	.id_table = k10temp_id_table,
	.probe = k10temp_probe,
};

module_pci_driver(k10temp_driver);
Commit	Line	Data
6e7c1094	1	// SPDX-License-Identifier: GPL-2.0-or-later
3c57e89b	2	/*
d547552a GR	3	* k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h
d547552a GR	4	* processor hardware monitoring
3c57e89b CL	5	*
3c57e89b CL	6	* Copyright (c) 2009 Clemens Ladisch <[email protected]>
d547552a	7	* Copyright (c) 2020 Guenter Roeck <[email protected]>
c7579389 GR	8	*
c7579389 GR	9	* Implementation notes:
fd8bdb23	10	* - CCD register address information as well as the calculation to
c7579389 GR	11	* convert raw register values is from https://github.com/ocerman/zenpower.
	12	* The information is not confirmed from chip datasheets, but experiments
	13	* suggest that it provides reasonable temperature values.
b00647c4 GR	14	* - Register addresses to read chip voltage and current are also from
	15	* https://github.com/ocerman/zenpower, and not confirmed from chip
	16	* datasheets. Current calibration is board specific and not typically
	17	* shared by board vendors. For this reason, current values are
	18	* normalized to report 1A/LSB for core current and and 0.25A/LSB for SoC
	19	* current. Reported values can be adjusted using the sensors configuration
	20	* file.
3c57e89b CL	21	*/
3c57e89b CL	22
a6d210da	23	#include <linux/bitops.h>
3c57e89b CL	24	#include <linux/err.h>
3c57e89b CL	25	#include <linux/hwmon.h>
3c57e89b CL	26	#include <linux/init.h>
	27	#include <linux/module.h>
	28	#include <linux/pci.h>
dedf7dce	29	#include <linux/pci_ids.h>
3b031622	30	#include <asm/amd_nb.h>
3c57e89b CL	31	#include <asm/processor.h>
3c57e89b CL	32
9e581311	33	MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
3c57e89b CL	34	MODULE_AUTHOR("Clemens Ladisch <[email protected]>");
	35	MODULE_LICENSE("GPL");
	36
	37	static bool force;
	38	module_param(force, bool, 0444);
	39	MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
	40
f89ce270 AG	41	/* Provide lock for writing to NB_SMU_IND_ADDR */
	42	static DEFINE_MUTEX(nb_smu_ind_mutex);
	43
ccaf63b4 GR	44	#ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
	45	#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
	46	#endif
	47
c5114a1c	48	/* CPUID function 0x80000001, ebx */
a6d210da	49	#define CPUID_PKGTYPE_MASK GENMASK(31, 28)
c5114a1c CL	50	#define CPUID_PKGTYPE_F 0x00000000
	51	#define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
	52
	53	/* DRAM controller (PCI function 2) */
	54	#define REG_DCT0_CONFIG_HIGH 0x094
a6d210da	55	#define DDR3_MODE BIT(8)
c5114a1c CL	56
c5114a1c CL	57	/* miscellaneous (PCI function 3) */
3c57e89b	58	#define REG_HARDWARE_THERMAL_CONTROL 0x64
a6d210da	59	#define HTC_ENABLE BIT(0)
3c57e89b CL	60
	61	#define REG_REPORTED_TEMPERATURE 0xa4
	62
	63	#define REG_NORTHBRIDGE_CAPABILITIES 0xe8
a6d210da	64	#define NB_CAP_HTC BIT(10)
3c57e89b	65
f89ce270	66	/*
40626a1b GR	67	* For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
	68	* and REG_REPORTED_TEMPERATURE have been moved to
	69	* D0F0xBC_xD820_0C64 [Hardware Temperature Control]
	70	* D0F0xBC_xD820_0CA4 [Reported Temperature Control]
f89ce270	71	*/
40626a1b	72	#define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
f89ce270	73	#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
f89ce270	74
17822417 WH	75	/* Common for Zen CPU families (Family 17h and 18h) */
17822417 WH	76	#define ZEN_REPORTED_TEMP_CTRL_OFFSET 0x00059800
fd8bdb23	77
17822417 WH	78	#define ZEN_CCD_TEMP(x) (0x00059954 + ((x) * 4))
	79	#define ZEN_CCD_TEMP_VALID BIT(11)
	80	#define ZEN_CCD_TEMP_MASK GENMASK(10, 0)
9af0a9ae	81
17822417 WH	82	#define ZEN_CUR_TEMP_SHIFT 21
17822417 WH	83	#define ZEN_CUR_TEMP_RANGE_SEL_MASK BIT(19)
b00647c4	84
17822417	85	#define ZEN_SVI_BASE 0x0005A000
a6d210da	86
17822417 WH	87	/* F17h thermal registers through SMN */
	88	#define F17H_M01H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0xc)
	89	#define F17H_M01H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10)
d6144a40 WH	90	#define F17H_M31H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14)
d6144a40 WH	91	#define F17H_M31H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10)
17822417	92
d6144a40 WH	93	#define F17H_M01H_CFACTOR_ICORE 1000000 /* 1A / LSB */
	94	#define F17H_M01H_CFACTOR_ISOC 250000 /* 0.25A / LSB */
	95	#define F17H_M31H_CFACTOR_ICORE 1000000 /* 1A / LSB */
	96	#define F17H_M31H_CFACTOR_ISOC 310000 /* 0.31A / LSB */
b00647c4	97
55163a1c WH	98	/* F19h thermal registers through SMN */
	99	#define F19H_M01_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14)
	100	#define F19H_M01_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10)
	101
	102	#define F19H_M01H_CFACTOR_ICORE 1000000 /* 1A / LSB */
	103	#define F19H_M01H_CFACTOR_ISOC 310000 /* 0.31A / LSB */
	104
68546abf GR	105	struct k10temp_data {
68546abf GR	106	struct pci_dev *pdev;
40626a1b	107	void (read_htcreg)(struct pci_dev pdev, u32 *regval);
68546abf	108	void (read_tempreg)(struct pci_dev pdev, u32 *regval);
1b50b776	109	int temp_offset;
1b597889	110	u32 temp_adjust_mask;
60465245	111	u32 show_temp;
b00647c4	112	u32 svi_addr[2];
60465245	113	bool is_zen;
b00647c4 GR	114	bool show_current;
b00647c4 GR	115	int cfactor[2];
1b50b776 GR	116	};
1b50b776 GR	117
60465245 GR	118	#define TCTL_BIT 0
	119	#define TDIE_BIT 1
	120	#define TCCD_BIT(x) ((x) + 2)
	121
	122	#define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel))
	123	#define HAVE_TDIE(d) HAVE_TEMP(d, TDIE_BIT)
	124
1b50b776 GR	125	struct tctl_offset {
	126	u8 model;
	127	char const *id;
	128	int offset;
	129	};
	130
	131	static const struct tctl_offset tctl_offset_table[] = {
ab5ee246	132	{ 0x17, "AMD Ryzen 5 1600X", 20000 },
1b50b776 GR	133	{ 0x17, "AMD Ryzen 7 1700X", 20000 },
1b50b776 GR	134	{ 0x17, "AMD Ryzen 7 1800X", 20000 },
1b597889	135	{ 0x17, "AMD Ryzen 7 2700X", 10000 },
cd6a2064 GR	136	{ 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
cd6a2064 GR	137	{ 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
68546abf GR	138	};
68546abf GR	139
b00647c4 GR	140	static bool is_threadripper(void)
	141	{
	142	return strstr(boot_cpu_data.x86_model_id, "Threadripper");
	143	}
	144
	145	static bool is_epyc(void)
	146	{
	147	return strstr(boot_cpu_data.x86_model_id, "EPYC");
	148	}
	149
40626a1b GR	150	static void read_htcreg_pci(struct pci_dev pdev, u32 regval)
	151	{
	152	pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
	153	}
	154
68546abf GR	155	static void read_tempreg_pci(struct pci_dev pdev, u32 regval)
	156	{
	157	pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
	158	}
	159
	160	static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
	161	unsigned int base, int offset, u32 *val)
f89ce270 AG	162	{
	163	mutex_lock(&nb_smu_ind_mutex);
	164	pci_bus_write_config_dword(pdev->bus, devfn,
68546abf	165	base, offset);
f89ce270	166	pci_bus_read_config_dword(pdev->bus, devfn,
68546abf	167	base + 4, val);
f89ce270 AG	168	mutex_unlock(&nb_smu_ind_mutex);
	169	}
	170
40626a1b GR	171	static void read_htcreg_nb_f15(struct pci_dev pdev, u32 regval)
	172	{
	173	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
	174	F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
	175	}
	176
68546abf GR	177	static void read_tempreg_nb_f15(struct pci_dev pdev, u32 regval)
	178	{
	179	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
	180	F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
	181	}
	182
17822417	183	static void read_tempreg_nb_zen(struct pci_dev pdev, u32 regval)
9af0a9ae	184	{
3b031622	185	amd_smn_read(amd_pci_dev_to_node_id(pdev),
17822417	186	ZEN_REPORTED_TEMP_CTRL_OFFSET, regval);
9af0a9ae GR	187	}
9af0a9ae GR	188
d547552a	189	static long get_raw_temp(struct k10temp_data *data)
3c57e89b	190	{
f934c059	191	u32 regval;
d547552a	192	long temp;
68546abf GR	193
68546abf GR	194	data->read_tempreg(data->pdev, &regval);
17822417	195	temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125;
1b597889 GR	196	if (regval & data->temp_adjust_mask)
1b597889 GR	197	temp -= 49000;
f934c059 GR	198	return temp;
	199	}
	200
0e786f32	201	static const char *k10temp_temp_label[] = {
d547552a	202	"Tctl",
b02c6857	203	"Tdie",
c7579389 GR	204	"Tccd1",
c7579389 GR	205	"Tccd2",
fd8bdb23 GR	206	"Tccd3",
	207	"Tccd4",
	208	"Tccd5",
	209	"Tccd6",
	210	"Tccd7",
	211	"Tccd8",
d547552a	212	};
f934c059	213
0e786f32	214	static const char *k10temp_in_label[] = {
b00647c4 GR	215	"Vcore",
	216	"Vsoc",
	217	};
	218
0e786f32	219	static const char *k10temp_curr_label[] = {
b00647c4 GR	220	"Icore",
	221	"Isoc",
	222	};
	223
d547552a GR	224	static int k10temp_read_labels(struct device *dev,
	225	enum hwmon_sensor_types type,
	226	u32 attr, int channel, const char **str)
3c57e89b	227	{
b00647c4 GR	228	switch (type) {
	229	case hwmon_temp:
	230	*str = k10temp_temp_label[channel];
	231	break;
	232	case hwmon_in:
	233	*str = k10temp_in_label[channel];
	234	break;
	235	case hwmon_curr:
	236	*str = k10temp_curr_label[channel];
	237	break;
	238	default:
	239	return -EOPNOTSUPP;
	240	}
d547552a	241	return 0;
3c57e89b CL	242	}
3c57e89b CL	243
b00647c4 GR	244	static int k10temp_read_curr(struct device *dev, u32 attr, int channel,
	245	long *val)
	246	{
	247	struct k10temp_data *data = dev_get_drvdata(dev);
	248	u32 regval;
	249
	250	switch (attr) {
	251	case hwmon_curr_input:
	252	amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
	253	data->svi_addr[channel], &regval);
	254	val = DIV_ROUND_CLOSEST(data->cfactor[channel]
	255	(regval & 0xff),
	256	1000);
	257	break;
	258	default:
	259	return -EOPNOTSUPP;
	260	}
	261	return 0;
	262	}
	263
	264	static int k10temp_read_in(struct device dev, u32 attr, int channel, long val)
	265	{
	266	struct k10temp_data *data = dev_get_drvdata(dev);
	267	u32 regval;
	268
	269	switch (attr) {
	270	case hwmon_in_input:
	271	amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
	272	data->svi_addr[channel], &regval);
	273	regval = (regval >> 16) & 0xff;
	274	val = DIV_ROUND_CLOSEST(155000 - regval 625, 100);
	275	break;
	276	default:
	277	return -EOPNOTSUPP;
	278	}
	279	return 0;
	280	}
	281
	282	static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
	283	long *val)
3c57e89b	284	{
68546abf	285	struct k10temp_data *data = dev_get_drvdata(dev);
3c57e89b	286	u32 regval;
3c57e89b	287
d547552a GR	288	switch (attr) {
	289	case hwmon_temp_input:
	290	switch (channel) {
b02c6857 GR	291	case 0: /* Tctl */
b02c6857 GR	292	*val = get_raw_temp(data);
d547552a GR	293	if (*val < 0)
	294	*val = 0;
	295	break;
b02c6857 GR	296	case 1: /* Tdie */
b02c6857 GR	297	*val = get_raw_temp(data) - data->temp_offset;
d547552a GR	298	if (*val < 0)
	299	*val = 0;
	300	break;
fd8bdb23	301	case 2 ... 9: /* Tccd{1-8} */
c7579389	302	amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
17822417 WH	303	ZEN_CCD_TEMP(channel - 2), &regval);
17822417 WH	304	val = (regval & ZEN_CCD_TEMP_MASK) 125 - 49000;
c7579389	305	break;
d547552a GR	306	default:
	307	return -EOPNOTSUPP;
	308	}
	309	break;
	310	case hwmon_temp_max:
	311	val = 70 1000;
	312	break;
	313	case hwmon_temp_crit:
	314	data->read_htcreg(data->pdev, &regval);
	315	val = ((regval >> 16) & 0x7f) 500 + 52000;
	316	break;
	317	case hwmon_temp_crit_hyst:
	318	data->read_htcreg(data->pdev, &regval);
	319	*val = (((regval >> 16) & 0x7f)
	320	- ((regval >> 24) & 0xf)) * 500 + 52000;
	321	break;
	322	default:
	323	return -EOPNOTSUPP;
	324	}
	325	return 0;
3c57e89b CL	326	}
3c57e89b CL	327
b00647c4 GR	328	static int k10temp_read(struct device *dev, enum hwmon_sensor_types type,
	329	u32 attr, int channel, long *val)
	330	{
	331	switch (type) {
	332	case hwmon_temp:
	333	return k10temp_read_temp(dev, attr, channel, val);
	334	case hwmon_in:
	335	return k10temp_read_in(dev, attr, channel, val);
	336	case hwmon_curr:
	337	return k10temp_read_curr(dev, attr, channel, val);
	338	default:
	339	return -EOPNOTSUPP;
	340	}
	341	}
	342
d547552a GR	343	static umode_t k10temp_is_visible(const void *_data,
	344	enum hwmon_sensor_types type,
	345	u32 attr, int channel)
3e3e1022	346	{
d547552a	347	const struct k10temp_data *data = _data;
68546abf	348	struct pci_dev *pdev = data->pdev;
f934c059	349	u32 reg;
3e3e1022	350
d547552a GR	351	switch (type) {
	352	case hwmon_temp:
	353	switch (attr) {
	354	case hwmon_temp_input:
60465245	355	if (!HAVE_TEMP(data, channel))
d547552a GR	356	return 0;
	357	break;
	358	case hwmon_temp_max:
60465245	359	if (channel \|\| data->is_zen)
d547552a GR	360	return 0;
	361	break;
	362	case hwmon_temp_crit:
	363	case hwmon_temp_crit_hyst:
	364	if (channel \|\| !data->read_htcreg)
	365	return 0;
	366
	367	pci_read_config_dword(pdev,
	368	REG_NORTHBRIDGE_CAPABILITIES,
	369	&reg);
	370	if (!(reg & NB_CAP_HTC))
	371	return 0;
	372
	373	data->read_htcreg(data->pdev, &reg);
	374	if (!(reg & HTC_ENABLE))
	375	return 0;
	376	break;
	377	case hwmon_temp_label:
60465245 GR	378	/* Show temperature labels only on Zen CPUs */
60465245 GR	379	if (!data->is_zen \|\| !HAVE_TEMP(data, channel))
c7579389	380	return 0;
d547552a GR	381	break;
d547552a GR	382	default:
f934c059	383	return 0;
d547552a	384	}
f934c059	385	break;
b00647c4 GR	386	case hwmon_in:
	387	case hwmon_curr:
	388	if (!data->show_current)
	389	return 0;
	390	break;
d547552a GR	391	default:
d547552a GR	392	return 0;
3e3e1022	393	}
d547552a	394	return 0444;
3e3e1022 GR	395	}
3e3e1022 GR	396
6c931ae1	397	static bool has_erratum_319(struct pci_dev *pdev)
3c57e89b	398	{
c5114a1c CL	399	u32 pkg_type, reg_dram_cfg;
	400
	401	if (boot_cpu_data.x86 != 0x10)
	402	return false;
	403
3c57e89b	404	/*
c5114a1c CL	405	* Erratum 319: The thermal sensor of Socket F/AM2+ processors
c5114a1c CL	406	* may be unreliable.
3c57e89b	407	*/
c5114a1c CL	408	pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
	409	if (pkg_type == CPUID_PKGTYPE_F)
	410	return true;
	411	if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
	412	return false;
	413
eefc2d9e	414	/* DDR3 memory implies socket AM3, which is good */
c5114a1c CL	415	pci_bus_read_config_dword(pdev->bus,
	416	PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
	417	REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
eefc2d9e JD	418	if (reg_dram_cfg & DDR3_MODE)
	419	return false;
	420
	421	/*
	422	* Unfortunately it is possible to run a socket AM3 CPU with DDR2
	423	* memory. We blacklist all the cores which do exist in socket AM2+
	424	* format. It still isn't perfect, as RB-C2 cores exist in both AM2+
	425	* and AM3 formats, but that's the best we can do.
	426	*/
	427	return boot_cpu_data.x86_model < 4 \|\|
b399151c	428	(boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
3c57e89b CL	429	}
3c57e89b CL	430
d547552a GR	431	static const struct hwmon_channel_info *k10temp_info[] = {
	432	HWMON_CHANNEL_INFO(temp,
	433	HWMON_T_INPUT \| HWMON_T_MAX \|
	434	HWMON_T_CRIT \| HWMON_T_CRIT_HYST \|
	435	HWMON_T_LABEL,
c7579389 GR	436	HWMON_T_INPUT \| HWMON_T_LABEL,
c7579389 GR	437	HWMON_T_INPUT \| HWMON_T_LABEL,
fd8bdb23 GR	438	HWMON_T_INPUT \| HWMON_T_LABEL,
	439	HWMON_T_INPUT \| HWMON_T_LABEL,
	440	HWMON_T_INPUT \| HWMON_T_LABEL,
	441	HWMON_T_INPUT \| HWMON_T_LABEL,
	442	HWMON_T_INPUT \| HWMON_T_LABEL,
	443	HWMON_T_INPUT \| HWMON_T_LABEL,
d547552a	444	HWMON_T_INPUT \| HWMON_T_LABEL),
b00647c4 GR	445	HWMON_CHANNEL_INFO(in,
	446	HWMON_I_INPUT \| HWMON_I_LABEL,
	447	HWMON_I_INPUT \| HWMON_I_LABEL),
	448	HWMON_CHANNEL_INFO(curr,
	449	HWMON_C_INPUT \| HWMON_C_LABEL,
	450	HWMON_C_INPUT \| HWMON_C_LABEL),
d547552a GR	451	NULL
	452	};
	453
	454	static const struct hwmon_ops k10temp_hwmon_ops = {
	455	.is_visible = k10temp_is_visible,
	456	.read = k10temp_read,
	457	.read_string = k10temp_read_labels,
	458	};
	459
	460	static const struct hwmon_chip_info k10temp_chip_info = {
	461	.ops = &k10temp_hwmon_ops,
	462	.info = k10temp_info,
	463	};
	464
fd8bdb23 GR	465	static void k10temp_get_ccd_support(struct pci_dev *pdev,
	466	struct k10temp_data *data, int limit)
	467	{
	468	u32 regval;
	469	int i;
	470
	471	for (i = 0; i < limit; i++) {
	472	amd_smn_read(amd_pci_dev_to_node_id(pdev),
17822417 WH	473	ZEN_CCD_TEMP(i), &regval);
17822417 WH	474	if (regval & ZEN_CCD_TEMP_VALID)
60465245	475	data->show_temp \|= BIT(TCCD_BIT(i));
fd8bdb23 GR	476	}
	477	}
	478
d547552a	479	static int k10temp_probe(struct pci_dev pdev, const struct pci_device_id id)
3c57e89b	480	{
c5114a1c	481	int unreliable = has_erratum_319(pdev);
3e3e1022	482	struct device *dev = &pdev->dev;
68546abf	483	struct k10temp_data *data;
3e3e1022	484	struct device *hwmon_dev;
1b50b776	485	int i;
3c57e89b	486
3e3e1022 GR	487	if (unreliable) {
	488	if (!force) {
	489	dev_err(dev,
	490	"unreliable CPU thermal sensor; monitoring disabled\n");
	491	return -ENODEV;
	492	}
	493	dev_warn(dev,
3c57e89b	494	"unreliable CPU thermal sensor; check erratum 319\n");
3e3e1022	495	}
3c57e89b	496
68546abf GR	497	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	498	if (!data)
	499	return -ENOMEM;
	500
	501	data->pdev = pdev;
60465245	502	data->show_temp \|= BIT(TCTL_BIT); /* Always show Tctl */
68546abf	503
53dfa008 GR	504	if (boot_cpu_data.x86 == 0x15 &&
	505	((boot_cpu_data.x86_model & 0xf0) == 0x60 \|\|
	506	(boot_cpu_data.x86_model & 0xf0) == 0x70)) {
40626a1b	507	data->read_htcreg = read_htcreg_nb_f15;
68546abf	508	data->read_tempreg = read_tempreg_nb_f15;
d93217d8	509	} else if (boot_cpu_data.x86 == 0x17 \|\| boot_cpu_data.x86 == 0x18) {
17822417 WH	510	data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
17822417 WH	511	data->read_tempreg = read_tempreg_nb_zen;
60465245 GR	512	data->show_temp \|= BIT(TDIE_BIT); /* show Tdie */
60465245 GR	513	data->is_zen = true;
c7579389 GR	514
	515	switch (boot_cpu_data.x86_model) {
	516	case 0x1: /* Zen */
	517	case 0x8: /* Zen+ */
	518	case 0x11: /* Zen APU */
	519	case 0x18: /* Zen+ APU */
b00647c4 GR	520	data->show_current = !is_threadripper() && !is_epyc();
	521	data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE0;
	522	data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE1;
d6144a40 WH	523	data->cfactor[0] = F17H_M01H_CFACTOR_ICORE;
d6144a40 WH	524	data->cfactor[1] = F17H_M01H_CFACTOR_ISOC;
fd8bdb23	525	k10temp_get_ccd_support(pdev, data, 4);
c7579389 GR	526	break;
	527	case 0x31: /* Zen2 Threadripper */
	528	case 0x71: /* Zen2 */
b00647c4	529	data->show_current = !is_threadripper() && !is_epyc();
d6144a40 WH	530	data->cfactor[0] = F17H_M31H_CFACTOR_ICORE;
	531	data->cfactor[1] = F17H_M31H_CFACTOR_ISOC;
	532	data->svi_addr[0] = F17H_M31H_SVI_TEL_PLANE0;
	533	data->svi_addr[1] = F17H_M31H_SVI_TEL_PLANE1;
fd8bdb23	534	k10temp_get_ccd_support(pdev, data, 8);
c7579389 GR	535	break;
c7579389 GR	536	}
55163a1c WH	537	} else if (boot_cpu_data.x86 == 0x19) {
	538	data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
	539	data->read_tempreg = read_tempreg_nb_zen;
	540	data->show_temp \|= BIT(TDIE_BIT);
	541	data->is_zen = true;
	542
	543	switch (boot_cpu_data.x86_model) {
	544	case 0x0 ... 0x1: /* Zen3 */
	545	data->show_current = true;
	546	data->svi_addr[0] = F19H_M01_SVI_TEL_PLANE0;
	547	data->svi_addr[1] = F19H_M01_SVI_TEL_PLANE1;
	548	data->cfactor[0] = F19H_M01H_CFACTOR_ICORE;
	549	data->cfactor[1] = F19H_M01H_CFACTOR_ISOC;
	550	k10temp_get_ccd_support(pdev, data, 8);
	551	break;
	552	}
1b597889	553	} else {
40626a1b	554	data->read_htcreg = read_htcreg_pci;
68546abf	555	data->read_tempreg = read_tempreg_pci;
1b597889	556	}
68546abf	557
1b50b776 GR	558	for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
	559	const struct tctl_offset *entry = &tctl_offset_table[i];
	560
	561	if (boot_cpu_data.x86 == entry->model &&
	562	strstr(boot_cpu_data.x86_model_id, entry->id)) {
	563	data->temp_offset = entry->offset;
	564	break;
	565	}
	566	}
	567
d547552a GR	568	hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data,
	569	&k10temp_chip_info,
	570	NULL);
8999eabf	571	return PTR_ERR_OR_ZERO(hwmon_dev);
3c57e89b CL	572	}
3c57e89b CL	573
cd9bb056	574	static const struct pci_device_id k10temp_id_table[] = {
3c57e89b CL	575	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
3c57e89b CL	576	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
aa4790a6	577	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
9e581311	578	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
24214449	579	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
d303b1b5	580	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
f89ce270	581	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
ccaf63b4	582	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
30b146d1	583	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
ec015950	584	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
9af0a9ae	585	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
3b031622	586	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
210ba120	587	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
279f0b3a	588	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
12163cfb	589	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
55163a1c	590	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
d93217d8	591	{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
3c57e89b CL	592	{}
	593	};
	594	MODULE_DEVICE_TABLE(pci, k10temp_id_table);
	595
	596	static struct pci_driver k10temp_driver = {
	597	.name = "k10temp",
	598	.id_table = k10temp_id_table,
	599	.probe = k10temp_probe,
3c57e89b CL	600	};
3c57e89b CL	601
f71f5a55	602	module_pci_driver(k10temp_driver);