[linux.git] / drivers / spi / spi-txx9.c

/*
 * TXx9 SPI controller driver.
 *
 * Based on linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
 * Copyright (C) 2000-2001 Toshiba Corporation
 *
 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * Support for TX4938 in 2.6 - Manish Lachwani ([email protected])
 *
 * Convert to generic SPI framework - Atsushi Nemoto ([email protected])
 */
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/spi/spi.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/gpio.h>


#define SPI_FIFO_SIZE 4
#define SPI_MAX_DIVIDER 0xff	/* Max. value for SPCR1.SER */
#define SPI_MIN_DIVIDER 1	/* Min. value for SPCR1.SER */

#define TXx9_SPMCR		0x00
#define TXx9_SPCR0		0x04
#define TXx9_SPCR1		0x08
#define TXx9_SPFS		0x0c
#define TXx9_SPSR		0x14
#define TXx9_SPDR		0x18

/* SPMCR : SPI Master Control */
#define TXx9_SPMCR_OPMODE	0xc0
#define TXx9_SPMCR_CONFIG	0x40
#define TXx9_SPMCR_ACTIVE	0x80
#define TXx9_SPMCR_SPSTP	0x02
#define TXx9_SPMCR_BCLR		0x01

/* SPCR0 : SPI Control 0 */
#define TXx9_SPCR0_TXIFL_MASK	0xc000
#define TXx9_SPCR0_RXIFL_MASK	0x3000
#define TXx9_SPCR0_SIDIE	0x0800
#define TXx9_SPCR0_SOEIE	0x0400
#define TXx9_SPCR0_RBSIE	0x0200
#define TXx9_SPCR0_TBSIE	0x0100
#define TXx9_SPCR0_IFSPSE	0x0010
#define TXx9_SPCR0_SBOS		0x0004
#define TXx9_SPCR0_SPHA		0x0002
#define TXx9_SPCR0_SPOL		0x0001

/* SPSR : SPI Status */
#define TXx9_SPSR_TBSI		0x8000
#define TXx9_SPSR_RBSI		0x4000
#define TXx9_SPSR_TBS_MASK	0x3800
#define TXx9_SPSR_RBS_MASK	0x0700
#define TXx9_SPSR_SPOE		0x0080
#define TXx9_SPSR_IFSD		0x0008
#define TXx9_SPSR_SIDLE		0x0004
#define TXx9_SPSR_STRDY		0x0002
#define TXx9_SPSR_SRRDY		0x0001


struct txx9spi {
	struct workqueue_struct	*workqueue;
	struct work_struct work;
	spinlock_t lock;	/* protect 'queue' */
	struct list_head queue;
	wait_queue_head_t waitq;
	void __iomem *membase;
	int baseclk;
	struct clk *clk;
	u32 max_speed_hz, min_speed_hz;
	int last_chipselect;
	int last_chipselect_val;
};

static u32 txx9spi_rd(struct txx9spi *c, int reg)
{
	return __raw_readl(c->membase + reg);
}
static void txx9spi_wr(struct txx9spi *c, u32 val, int reg)
{
	__raw_writel(val, c->membase + reg);
}

static void txx9spi_cs_func(struct spi_device *spi, struct txx9spi *c,
		int on, unsigned int cs_delay)
{
	int val = (spi->mode & SPI_CS_HIGH) ? on : !on;
	if (on) {
		/* deselect the chip with cs_change hint in last transfer */
		if (c->last_chipselect >= 0)
			gpio_set_value(c->last_chipselect,
					!c->last_chipselect_val);
		c->last_chipselect = spi->chip_select;
		c->last_chipselect_val = val;
	} else {
		c->last_chipselect = -1;
		ndelay(cs_delay);	/* CS Hold Time */
	}
	gpio_set_value(spi->chip_select, val);
	ndelay(cs_delay);	/* CS Setup Time / CS Recovery Time */
}

static int txx9spi_setup(struct spi_device *spi)
{
	struct txx9spi *c = spi_master_get_devdata(spi->master);

	if (!spi->max_speed_hz
			|| spi->max_speed_hz > c->max_speed_hz
			|| spi->max_speed_hz < c->min_speed_hz)
		return -EINVAL;

	if (gpio_direction_output(spi->chip_select,
			!(spi->mode & SPI_CS_HIGH))) {
		dev_err(&spi->dev, "Cannot setup GPIO for chipselect.\n");
		return -EINVAL;
	}

	/* deselect chip */
	spin_lock(&c->lock);
	txx9spi_cs_func(spi, c, 0, (NSEC_PER_SEC / 2) / spi->max_speed_hz);
	spin_unlock(&c->lock);

	return 0;
}

static irqreturn_t txx9spi_interrupt(int irq, void *dev_id)
{
	struct txx9spi *c = dev_id;

	/* disable rx intr */
	txx9spi_wr(c, txx9spi_rd(c, TXx9_SPCR0) & ~TXx9_SPCR0_RBSIE,
			TXx9_SPCR0);
	wake_up(&c->waitq);
	return IRQ_HANDLED;
}

static void txx9spi_work_one(struct txx9spi *c, struct spi_message *m)
{
	struct spi_device *spi = m->spi;
	struct spi_transfer *t;
	unsigned int cs_delay;
	unsigned int cs_change = 1;
	int status = 0;
	u32 mcr;
	u32 prev_speed_hz = 0;
	u8 prev_bits_per_word = 0;

	/* CS setup/hold/recovery time in nsec */
	cs_delay = 100 + (NSEC_PER_SEC / 2) / spi->max_speed_hz;

	mcr = txx9spi_rd(c, TXx9_SPMCR);
	if (unlikely((mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE)) {
		dev_err(&spi->dev, "Bad mode.\n");
		status = -EIO;
		goto exit;
	}
	mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);

	/* enter config mode */
	txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
	txx9spi_wr(c, TXx9_SPCR0_SBOS
			| ((spi->mode & SPI_CPOL) ? TXx9_SPCR0_SPOL : 0)
			| ((spi->mode & SPI_CPHA) ? TXx9_SPCR0_SPHA : 0)
			| 0x08,
			TXx9_SPCR0);

	list_for_each_entry (t, &m->transfers, transfer_list) {
		const void *txbuf = t->tx_buf;
		void *rxbuf = t->rx_buf;
		u32 data;
		unsigned int len = t->len;
		unsigned int wsize;
		u32 speed_hz = t->speed_hz ? : spi->max_speed_hz;
		u8 bits_per_word = t->bits_per_word;

		wsize = bits_per_word >> 3; /* in bytes */

		if (prev_speed_hz != speed_hz
				|| prev_bits_per_word != bits_per_word) {
			int n = DIV_ROUND_UP(c->baseclk, speed_hz) - 1;
			n = clamp(n, SPI_MIN_DIVIDER, SPI_MAX_DIVIDER);
			/* enter config mode */
			txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR,
					TXx9_SPMCR);
			txx9spi_wr(c, (n << 8) | bits_per_word, TXx9_SPCR1);
			/* enter active mode */
			txx9spi_wr(c, mcr | TXx9_SPMCR_ACTIVE, TXx9_SPMCR);

			prev_speed_hz = speed_hz;
			prev_bits_per_word = bits_per_word;
		}

		if (cs_change)
			txx9spi_cs_func(spi, c, 1, cs_delay);
		cs_change = t->cs_change;
		while (len) {
			unsigned int count = SPI_FIFO_SIZE;
			int i;
			u32 cr0;

			if (len < count * wsize)
				count = len / wsize;
			/* now tx must be idle... */
			while (!(txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_SIDLE))
				cpu_relax();
			cr0 = txx9spi_rd(c, TXx9_SPCR0);
			cr0 &= ~TXx9_SPCR0_RXIFL_MASK;
			cr0 |= (count - 1) << 12;
			/* enable rx intr */
			cr0 |= TXx9_SPCR0_RBSIE;
			txx9spi_wr(c, cr0, TXx9_SPCR0);
			/* send */
			for (i = 0; i < count; i++) {
				if (txbuf) {
					data = (wsize == 1)
						? *(const u8 *)txbuf
						: *(const u16 *)txbuf;
					txx9spi_wr(c, data, TXx9_SPDR);
					txbuf += wsize;
				} else
					txx9spi_wr(c, 0, TXx9_SPDR);
			}
			/* wait all rx data */
			wait_event(c->waitq,
				txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_RBSI);
			/* receive */
			for (i = 0; i < count; i++) {
				data = txx9spi_rd(c, TXx9_SPDR);
				if (rxbuf) {
					if (wsize == 1)
						*(u8 *)rxbuf = data;
					else
						*(u16 *)rxbuf = data;
					rxbuf += wsize;
				}
			}
			len -= count * wsize;
		}
		m->actual_length += t->len;
		if (t->delay_usecs)
			udelay(t->delay_usecs);

		if (!cs_change)
			continue;
		if (t->transfer_list.next == &m->transfers)
			break;
		/* sometimes a short mid-message deselect of the chip
		 * may be needed to terminate a mode or command
		 */
		txx9spi_cs_func(spi, c, 0, cs_delay);
	}

exit:
	m->status = status;
	m->complete(m->context);

	/* normally deactivate chipselect ... unless no error and
	 * cs_change has hinted that the next message will probably
	 * be for this chip too.
	 */
	if (!(status == 0 && cs_change))
		txx9spi_cs_func(spi, c, 0, cs_delay);

	/* enter config mode */
	txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
}

static void txx9spi_work(struct work_struct *work)
{
	struct txx9spi *c = container_of(work, struct txx9spi, work);
	unsigned long flags;

	spin_lock_irqsave(&c->lock, flags);
	while (!list_empty(&c->queue)) {
		struct spi_message *m;

		m = container_of(c->queue.next, struct spi_message, queue);
		list_del_init(&m->queue);
		spin_unlock_irqrestore(&c->lock, flags);

		txx9spi_work_one(c, m);

		spin_lock_irqsave(&c->lock, flags);
	}
	spin_unlock_irqrestore(&c->lock, flags);
}

static int txx9spi_transfer(struct spi_device *spi, struct spi_message *m)
{
	struct spi_master *master = spi->master;
	struct txx9spi *c = spi_master_get_devdata(master);
	struct spi_transfer *t;
	unsigned long flags;

	m->actual_length = 0;

	/* check each transfer's parameters */
	list_for_each_entry (t, &m->transfers, transfer_list) {
		u32 speed_hz = t->speed_hz ? : spi->max_speed_hz;
		u8 bits_per_word = t->bits_per_word;

		if (!t->tx_buf && !t->rx_buf && t->len)
			return -EINVAL;
		if (t->len & ((bits_per_word >> 3) - 1))
			return -EINVAL;
		if (speed_hz < c->min_speed_hz || speed_hz > c->max_speed_hz)
			return -EINVAL;
	}

	spin_lock_irqsave(&c->lock, flags);
	list_add_tail(&m->queue, &c->queue);
	queue_work(c->workqueue, &c->work);
	spin_unlock_irqrestore(&c->lock, flags);

	return 0;
}

static int txx9spi_probe(struct platform_device *dev)
{
	struct spi_master *master;
	struct txx9spi *c;
	struct resource *res;
	int ret = -ENODEV;
	u32 mcr;
	int irq;

	master = spi_alloc_master(&dev->dev, sizeof(*c));
	if (!master)
		return ret;
	c = spi_master_get_devdata(master);
	platform_set_drvdata(dev, master);

	INIT_WORK(&c->work, txx9spi_work);
	spin_lock_init(&c->lock);
	INIT_LIST_HEAD(&c->queue);
	init_waitqueue_head(&c->waitq);

	c->clk = clk_get(&dev->dev, "spi-baseclk");
	if (IS_ERR(c->clk)) {
		ret = PTR_ERR(c->clk);
		c->clk = NULL;
		goto exit;
	}
	ret = clk_enable(c->clk);
	if (ret) {
		clk_put(c->clk);
		c->clk = NULL;
		goto exit;
	}
	c->baseclk = clk_get_rate(c->clk);
	c->min_speed_hz = DIV_ROUND_UP(c->baseclk, SPI_MAX_DIVIDER + 1);
	c->max_speed_hz = c->baseclk / (SPI_MIN_DIVIDER + 1);

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (!res)
		goto exit_busy;
	if (!devm_request_mem_region(&dev->dev, res->start, resource_size(res),
				     "spi_txx9"))
		goto exit_busy;
	c->membase = devm_ioremap(&dev->dev, res->start, resource_size(res));
	if (!c->membase)
		goto exit_busy;

	/* enter config mode */
	mcr = txx9spi_rd(c, TXx9_SPMCR);
	mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);
	txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);

	irq = platform_get_irq(dev, 0);
	if (irq < 0)
		goto exit_busy;
	ret = devm_request_irq(&dev->dev, irq, txx9spi_interrupt, 0,
			       "spi_txx9", c);
	if (ret)
		goto exit;

	c->workqueue = create_singlethread_workqueue(
				dev_name(master->dev.parent));
	if (!c->workqueue)
		goto exit_busy;
	c->last_chipselect = -1;

	dev_info(&dev->dev, "at %#llx, irq %d, %dMHz\n",
		 (unsigned long long)res->start, irq,
		 (c->baseclk + 500000) / 1000000);

	/* the spi->mode bits understood by this driver: */
	master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;

	master->bus_num = dev->id;
	master->setup = txx9spi_setup;
	master->transfer = txx9spi_transfer;
	master->num_chipselect = (u16)UINT_MAX; /* any GPIO numbers */
	master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);

	ret = spi_register_master(master);
	if (ret)
		goto exit;
	return 0;
exit_busy:
	ret = -EBUSY;
exit:
	if (c->workqueue)
		destroy_workqueue(c->workqueue);
	if (c->clk) {
		clk_disable(c->clk);
		clk_put(c->clk);
	}
	spi_master_put(master);
	return ret;
}

static int txx9spi_remove(struct platform_device *dev)
{
	struct spi_master *master = spi_master_get(platform_get_drvdata(dev));
	struct txx9spi *c = spi_master_get_devdata(master);

	spi_unregister_master(master);
	destroy_workqueue(c->workqueue);
	clk_disable(c->clk);
	clk_put(c->clk);
	spi_master_put(master);
	return 0;
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:spi_txx9");

static struct platform_driver txx9spi_driver = {
	.remove = txx9spi_remove,
	.driver = {
		.name = "spi_txx9",
		.owner = THIS_MODULE,
	},
};

static int __init txx9spi_init(void)
{
	return platform_driver_probe(&txx9spi_driver, txx9spi_probe);
}
subsys_initcall(txx9spi_init);

static void __exit txx9spi_exit(void)
{
	platform_driver_unregister(&txx9spi_driver);
}
module_exit(txx9spi_exit);

MODULE_DESCRIPTION("TXx9 SPI Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
f2cac67d	1	/*
ca632f55	2	* TXx9 SPI controller driver.
f2cac67d AN	3	*
	4	* Based on linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
	5	* Copyright (C) 2000-2001 Toshiba Corporation
	6	*
	7	* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
	8	* terms of the GNU General Public License version 2. This program is
	9	* licensed "as is" without any warranty of any kind, whether express
	10	* or implied.
	11	*
	12	* Support for TX4938 in 2.6 - Manish Lachwani ([email protected])
	13	*
	14	* Convert to generic SPI framework - Atsushi Nemoto ([email protected])
	15	*/
	16	#include <linux/init.h>
	17	#include <linux/delay.h>
	18	#include <linux/errno.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/sched.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/workqueue.h>
	24	#include <linux/spi/spi.h>
	25	#include <linux/err.h>
	26	#include <linux/clk.h>
ba0a7f39	27	#include <linux/io.h>
d7614de4	28	#include <linux/module.h>
e221fa40	29	#include <linux/gpio.h>
f2cac67d AN	30
	31
	32	#define SPI_FIFO_SIZE 4
dbf763a2 AN	33	#define SPI_MAX_DIVIDER 0xff /* Max. value for SPCR1.SER */
dbf763a2 AN	34	#define SPI_MIN_DIVIDER 1 /* Min. value for SPCR1.SER */
f2cac67d AN	35
	36	#define TXx9_SPMCR 0x00
	37	#define TXx9_SPCR0 0x04
	38	#define TXx9_SPCR1 0x08
	39	#define TXx9_SPFS 0x0c
	40	#define TXx9_SPSR 0x14
	41	#define TXx9_SPDR 0x18
	42
	43	/* SPMCR : SPI Master Control */
	44	#define TXx9_SPMCR_OPMODE 0xc0
	45	#define TXx9_SPMCR_CONFIG 0x40
	46	#define TXx9_SPMCR_ACTIVE 0x80
	47	#define TXx9_SPMCR_SPSTP 0x02
	48	#define TXx9_SPMCR_BCLR 0x01
	49
	50	/* SPCR0 : SPI Control 0 */
	51	#define TXx9_SPCR0_TXIFL_MASK 0xc000
	52	#define TXx9_SPCR0_RXIFL_MASK 0x3000
	53	#define TXx9_SPCR0_SIDIE 0x0800
	54	#define TXx9_SPCR0_SOEIE 0x0400
	55	#define TXx9_SPCR0_RBSIE 0x0200
	56	#define TXx9_SPCR0_TBSIE 0x0100
	57	#define TXx9_SPCR0_IFSPSE 0x0010
	58	#define TXx9_SPCR0_SBOS 0x0004
	59	#define TXx9_SPCR0_SPHA 0x0002
	60	#define TXx9_SPCR0_SPOL 0x0001
	61
	62	/* SPSR : SPI Status */
	63	#define TXx9_SPSR_TBSI 0x8000
	64	#define TXx9_SPSR_RBSI 0x4000
	65	#define TXx9_SPSR_TBS_MASK 0x3800
	66	#define TXx9_SPSR_RBS_MASK 0x0700
	67	#define TXx9_SPSR_SPOE 0x0080
	68	#define TXx9_SPSR_IFSD 0x0008
	69	#define TXx9_SPSR_SIDLE 0x0004
	70	#define TXx9_SPSR_STRDY 0x0002
	71	#define TXx9_SPSR_SRRDY 0x0001
	72
	73
	74	struct txx9spi {
	75	struct workqueue_struct *workqueue;
	76	struct work_struct work;
	77	spinlock_t lock; /* protect 'queue' */
	78	struct list_head queue;
	79	wait_queue_head_t waitq;
	80	void __iomem *membase;
f2cac67d AN	81	int baseclk;
	82	struct clk *clk;
	83	u32 max_speed_hz, min_speed_hz;
	84	int last_chipselect;
	85	int last_chipselect_val;
	86	};
	87
	88	static u32 txx9spi_rd(struct txx9spi *c, int reg)
	89	{
	90	return __raw_readl(c->membase + reg);
	91	}
	92	static void txx9spi_wr(struct txx9spi *c, u32 val, int reg)
	93	{
	94	__raw_writel(val, c->membase + reg);
	95	}
	96
	97	static void txx9spi_cs_func(struct spi_device spi, struct txx9spi c,
	98	int on, unsigned int cs_delay)
	99	{
	100	int val = (spi->mode & SPI_CS_HIGH) ? on : !on;
	101	if (on) {
	102	/* deselect the chip with cs_change hint in last transfer */
	103	if (c->last_chipselect >= 0)
	104	gpio_set_value(c->last_chipselect,
	105	!c->last_chipselect_val);
	106	c->last_chipselect = spi->chip_select;
	107	c->last_chipselect_val = val;
	108	} else {
	109	c->last_chipselect = -1;
	110	ndelay(cs_delay); /* CS Hold Time */
	111	}
	112	gpio_set_value(spi->chip_select, val);
	113	ndelay(cs_delay); /* CS Setup Time / CS Recovery Time */
	114	}
	115
f2cac67d AN	116	static int txx9spi_setup(struct spi_device *spi)
	117	{
	118	struct txx9spi *c = spi_master_get_devdata(spi->master);
f2cac67d	119
f2cac67d AN	120	if (!spi->max_speed_hz
	121	\|\| spi->max_speed_hz > c->max_speed_hz
	122	\|\| spi->max_speed_hz < c->min_speed_hz)
	123	return -EINVAL;
	124
f2cac67d AN	125	if (gpio_direction_output(spi->chip_select,
	126	!(spi->mode & SPI_CS_HIGH))) {
	127	dev_err(&spi->dev, "Cannot setup GPIO for chipselect.\n");
	128	return -EINVAL;
	129	}
	130
	131	/* deselect chip */
	132	spin_lock(&c->lock);
	133	txx9spi_cs_func(spi, c, 0, (NSEC_PER_SEC / 2) / spi->max_speed_hz);
	134	spin_unlock(&c->lock);
	135
	136	return 0;
	137	}
	138
	139	static irqreturn_t txx9spi_interrupt(int irq, void *dev_id)
	140	{
	141	struct txx9spi *c = dev_id;
	142
	143	/* disable rx intr */
	144	txx9spi_wr(c, txx9spi_rd(c, TXx9_SPCR0) & ~TXx9_SPCR0_RBSIE,
	145	TXx9_SPCR0);
	146	wake_up(&c->waitq);
	147	return IRQ_HANDLED;
	148	}
	149
	150	static void txx9spi_work_one(struct txx9spi c, struct spi_message m)
	151	{
	152	struct spi_device *spi = m->spi;
	153	struct spi_transfer *t;
	154	unsigned int cs_delay;
	155	unsigned int cs_change = 1;
	156	int status = 0;
	157	u32 mcr;
	158	u32 prev_speed_hz = 0;
	159	u8 prev_bits_per_word = 0;
	160
	161	/* CS setup/hold/recovery time in nsec */
	162	cs_delay = 100 + (NSEC_PER_SEC / 2) / spi->max_speed_hz;
	163
	164	mcr = txx9spi_rd(c, TXx9_SPMCR);
	165	if (unlikely((mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE)) {
	166	dev_err(&spi->dev, "Bad mode.\n");
	167	status = -EIO;
	168	goto exit;
	169	}
	170	mcr &= ~(TXx9_SPMCR_OPMODE \| TXx9_SPMCR_SPSTP \| TXx9_SPMCR_BCLR);
	171
	172	/* enter config mode */
	173	txx9spi_wr(c, mcr \| TXx9_SPMCR_CONFIG \| TXx9_SPMCR_BCLR, TXx9_SPMCR);
	174	txx9spi_wr(c, TXx9_SPCR0_SBOS
	175	\| ((spi->mode & SPI_CPOL) ? TXx9_SPCR0_SPOL : 0)
	176	\| ((spi->mode & SPI_CPHA) ? TXx9_SPCR0_SPHA : 0)
	177	\| 0x08,
	178	TXx9_SPCR0);
	179
	180	list_for_each_entry (t, &m->transfers, transfer_list) {
	181	const void *txbuf = t->tx_buf;
	182	void *rxbuf = t->rx_buf;
	183	u32 data;
	184	unsigned int len = t->len;
	185	unsigned int wsize;
	186	u32 speed_hz = t->speed_hz ? : spi->max_speed_hz;
766ed704	187	u8 bits_per_word = t->bits_per_word;
f2cac67d	188
f2cac67d AN	189	wsize = bits_per_word >> 3; /* in bytes */
	190
	191	if (prev_speed_hz != speed_hz
	192	\|\| prev_bits_per_word != bits_per_word) {
dbf763a2 AN	193	int n = DIV_ROUND_UP(c->baseclk, speed_hz) - 1;
dbf763a2 AN	194	n = clamp(n, SPI_MIN_DIVIDER, SPI_MAX_DIVIDER);
f2cac67d AN	195	/* enter config mode */
	196	txx9spi_wr(c, mcr \| TXx9_SPMCR_CONFIG \| TXx9_SPMCR_BCLR,
	197	TXx9_SPMCR);
	198	txx9spi_wr(c, (n << 8) \| bits_per_word, TXx9_SPCR1);
	199	/* enter active mode */
	200	txx9spi_wr(c, mcr \| TXx9_SPMCR_ACTIVE, TXx9_SPMCR);
	201
	202	prev_speed_hz = speed_hz;
	203	prev_bits_per_word = bits_per_word;
	204	}
	205
	206	if (cs_change)
	207	txx9spi_cs_func(spi, c, 1, cs_delay);
	208	cs_change = t->cs_change;
	209	while (len) {
	210	unsigned int count = SPI_FIFO_SIZE;
	211	int i;
	212	u32 cr0;
	213
	214	if (len < count * wsize)
	215	count = len / wsize;
	216	/* now tx must be idle... */
	217	while (!(txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_SIDLE))
	218	cpu_relax();
	219	cr0 = txx9spi_rd(c, TXx9_SPCR0);
	220	cr0 &= ~TXx9_SPCR0_RXIFL_MASK;
	221	cr0 \|= (count - 1) << 12;
	222	/* enable rx intr */
	223	cr0 \|= TXx9_SPCR0_RBSIE;
	224	txx9spi_wr(c, cr0, TXx9_SPCR0);
	225	/* send */
	226	for (i = 0; i < count; i++) {
	227	if (txbuf) {
	228	data = (wsize == 1)
	229	? (const u8 )txbuf
	230	: (const u16 )txbuf;
	231	txx9spi_wr(c, data, TXx9_SPDR);
	232	txbuf += wsize;
	233	} else
	234	txx9spi_wr(c, 0, TXx9_SPDR);
	235	}
	236	/* wait all rx data */
	237	wait_event(c->waitq,
	238	txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_RBSI);
	239	/* receive */
	240	for (i = 0; i < count; i++) {
	241	data = txx9spi_rd(c, TXx9_SPDR);
	242	if (rxbuf) {
	243	if (wsize == 1)
	244	(u8 )rxbuf = data;
	245	else
	246	(u16 )rxbuf = data;
	247	rxbuf += wsize;
	248	}
	249	}
	250	len -= count * wsize;
	251	}
	252	m->actual_length += t->len;
	253	if (t->delay_usecs)
	254	udelay(t->delay_usecs);
	255
	256	if (!cs_change)
	257	continue;
	258	if (t->transfer_list.next == &m->transfers)
259	break;
260	/* sometimes a short mid-message deselect of the chip
261	* may be needed to terminate a mode or command
262	*/
263	txx9spi_cs_func(spi, c, 0, cs_delay);
264	}
265
266	exit:
267	m->status = status;
268	m->complete(m->context);
269
270	/* normally deactivate chipselect ... unless no error and
271	* cs_change has hinted that the next message will probably
272	* be for this chip too.
273	*/
274	if (!(status == 0 && cs_change))
275	txx9spi_cs_func(spi, c, 0, cs_delay);
276
277	/* enter config mode */
278	txx9spi_wr(c, mcr \| TXx9_SPMCR_CONFIG \| TXx9_SPMCR_BCLR, TXx9_SPMCR);
279	}
280
281	static void txx9spi_work(struct work_struct *work)
282	{
283	struct txx9spi *c = container_of(work, struct txx9spi, work);
284	unsigned long flags;
285
286	spin_lock_irqsave(&c->lock, flags);
287	while (!list_empty(&c->queue)) {
288	struct spi_message *m;
289
290	m = container_of(c->queue.next, struct spi_message, queue);
291	list_del_init(&m->queue);
292	spin_unlock_irqrestore(&c->lock, flags);
293
294	txx9spi_work_one(c, m);
295
296	spin_lock_irqsave(&c->lock, flags);
297	}
298	spin_unlock_irqrestore(&c->lock, flags);
299	}
300
301	static int txx9spi_transfer(struct spi_device spi, struct spi_message m)
302	{
303	struct spi_master *master = spi->master;
304	struct txx9spi *c = spi_master_get_devdata(master);
305	struct spi_transfer *t;
306	unsigned long flags;
307
308	m->actual_length = 0;
309
310	/* check each transfer's parameters */
311	list_for_each_entry (t, &m->transfers, transfer_list) {
312	u32 speed_hz = t->speed_hz ? : spi->max_speed_hz;
766ed704	313	u8 bits_per_word = t->bits_per_word;
f2cac67d	314
f2cac67d AN	315	if (!t->tx_buf && !t->rx_buf && t->len)
f2cac67d AN	316	return -EINVAL;
f2cac67d AN	317	if (t->len & ((bits_per_word >> 3) - 1))
	318	return -EINVAL;
	319	if (speed_hz < c->min_speed_hz \|\| speed_hz > c->max_speed_hz)
	320	return -EINVAL;
	321	}
	322
	323	spin_lock_irqsave(&c->lock, flags);
	324	list_add_tail(&m->queue, &c->queue);
	325	queue_work(c->workqueue, &c->work);
	326	spin_unlock_irqrestore(&c->lock, flags);
	327
	328	return 0;
	329	}
	330
2deff8d6	331	static int txx9spi_probe(struct platform_device *dev)
f2cac67d AN	332	{
	333	struct spi_master *master;
	334	struct txx9spi *c;
	335	struct resource *res;
	336	int ret = -ENODEV;
	337	u32 mcr;
ba0a7f39	338	int irq;
f2cac67d AN	339
	340	master = spi_alloc_master(&dev->dev, sizeof(*c));
	341	if (!master)
	342	return ret;
	343	c = spi_master_get_devdata(master);
f2cac67d AN	344	platform_set_drvdata(dev, master);
	345
	346	INIT_WORK(&c->work, txx9spi_work);
	347	spin_lock_init(&c->lock);
	348	INIT_LIST_HEAD(&c->queue);
	349	init_waitqueue_head(&c->waitq);
	350
	351	c->clk = clk_get(&dev->dev, "spi-baseclk");
	352	if (IS_ERR(c->clk)) {
	353	ret = PTR_ERR(c->clk);
	354	c->clk = NULL;
	355	goto exit;
	356	}
	357	ret = clk_enable(c->clk);
	358	if (ret) {
	359	clk_put(c->clk);
	360	c->clk = NULL;
	361	goto exit;
	362	}
	363	c->baseclk = clk_get_rate(c->clk);
dbf763a2 AN	364	c->min_speed_hz = DIV_ROUND_UP(c->baseclk, SPI_MAX_DIVIDER + 1);
dbf763a2 AN	365	c->max_speed_hz = c->baseclk / (SPI_MIN_DIVIDER + 1);
f2cac67d AN	366
	367	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	368	if (!res)
ba0a7f39	369	goto exit_busy;
d53342bf	370	if (!devm_request_mem_region(&dev->dev, res->start, resource_size(res),
ba0a7f39 AN	371	"spi_txx9"))
ba0a7f39 AN	372	goto exit_busy;
d53342bf	373	c->membase = devm_ioremap(&dev->dev, res->start, resource_size(res));
f2cac67d	374	if (!c->membase)
ba0a7f39	375	goto exit_busy;
f2cac67d AN	376
	377	/* enter config mode */
	378	mcr = txx9spi_rd(c, TXx9_SPMCR);
	379	mcr &= ~(TXx9_SPMCR_OPMODE \| TXx9_SPMCR_SPSTP \| TXx9_SPMCR_BCLR);
	380	txx9spi_wr(c, mcr \| TXx9_SPMCR_CONFIG \| TXx9_SPMCR_BCLR, TXx9_SPMCR);
	381
ba0a7f39 AN	382	irq = platform_get_irq(dev, 0);
	383	if (irq < 0)
	384	goto exit_busy;
	385	ret = devm_request_irq(&dev->dev, irq, txx9spi_interrupt, 0,
	386	"spi_txx9", c);
	387	if (ret)
f2cac67d	388	goto exit;
f2cac67d	389
6c7377ab KS	390	c->workqueue = create_singlethread_workqueue(
6c7377ab KS	391	dev_name(master->dev.parent));
f2cac67d	392	if (!c->workqueue)
ba0a7f39	393	goto exit_busy;
f2cac67d AN	394	c->last_chipselect = -1;
	395
	396	dev_info(&dev->dev, "at %#llx, irq %d, %dMHz\n",
ba0a7f39	397	(unsigned long long)res->start, irq,
f2cac67d AN	398	(c->baseclk + 500000) / 1000000);
f2cac67d AN	399
e7db06b5 DB	400	/* the spi->mode bits understood by this driver: */
	401	master->mode_bits = SPI_CS_HIGH \| SPI_CPOL \| SPI_CPHA;
	402
f2cac67d AN	403	master->bus_num = dev->id;
	404	master->setup = txx9spi_setup;
	405	master->transfer = txx9spi_transfer;
	406	master->num_chipselect = (u16)UINT_MAX; /* any GPIO numbers */
24778be2	407	master->bits_per_word_mask = SPI_BPW_MASK(8) \| SPI_BPW_MASK(16);
f2cac67d AN	408
	409	ret = spi_register_master(master);
	410	if (ret)
	411	goto exit;
	412	return 0;
ba0a7f39 AN	413	exit_busy:
ba0a7f39 AN	414	ret = -EBUSY;
f2cac67d AN	415	exit:
	416	if (c->workqueue)
	417	destroy_workqueue(c->workqueue);
f2cac67d AN	418	if (c->clk) {
	419	clk_disable(c->clk);
	420	clk_put(c->clk);
	421	}
f2cac67d AN	422	spi_master_put(master);
	423	return ret;
	424	}
	425
2deff8d6	426	static int txx9spi_remove(struct platform_device *dev)
f2cac67d AN	427	{
	428	struct spi_master *master = spi_master_get(platform_get_drvdata(dev));
	429	struct txx9spi *c = spi_master_get_devdata(master);
	430
	431	spi_unregister_master(master);
f2cac67d	432	destroy_workqueue(c->workqueue);
f2cac67d AN	433	clk_disable(c->clk);
	434	clk_put(c->clk);
	435	spi_master_put(master);
	436	return 0;
	437	}
	438
7e38c3c4 KS	439	/* work with hotplug and coldplug */
	440	MODULE_ALIAS("platform:spi_txx9");
	441
f2cac67d	442	static struct platform_driver txx9spi_driver = {
2deff8d6	443	.remove = txx9spi_remove,
f2cac67d	444	.driver = {
4ccdb4c8	445	.name = "spi_txx9",
f2cac67d AN	446	.owner = THIS_MODULE,
	447	},
	448	};
	449
	450	static int __init txx9spi_init(void)
	451	{
	452	return platform_driver_probe(&txx9spi_driver, txx9spi_probe);
	453	}
	454	subsys_initcall(txx9spi_init);
	455
	456	static void __exit txx9spi_exit(void)
	457	{
	458	platform_driver_unregister(&txx9spi_driver);
	459	}
	460	module_exit(txx9spi_exit);
	461
	462	MODULE_DESCRIPTION("TXx9 SPI Driver");
	463	MODULE_LICENSE("GPL");