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Merge tag 'drm-intel-gt-next-2023-10-12' of git://anongit.freedesktop.org/drm/drm...
[linux.git] / drivers / pinctrl / sunxi / pinctrl-sun5i.c
CommitLineData
858f559f
MR		 1/*
2 * Allwinner sun5i SoCs pinctrl driver.
3 *
4 * Copyright (C) 2014-2016 Maxime Ripard <[email protected]>
5 * Copyright (C) 2016 Mylene Josserand <[email protected]>
6 *
cff1f7a9 7 * This file is licensed under the terms of the GNU General Public
858f559f
MR		 8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
cff1f7a9 12#include <linux/init.h>
858f559f
MR		 13#include <linux/platform_device.h>
14#include <linux/of.h>
858f559f
MR		 15#include <linux/pinctrl/pinctrl.h>
16
17#include "pinctrl-sunxi.h"
18
19static const struct sunxi_desc_pin sun5i_pins[] = {
20 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 0),
21 PINCTRL_SUN5I_A10S,
22 SUNXI_FUNCTION(0x0, "gpio_in"),
23 SUNXI_FUNCTION(0x1, "gpio_out"),
24 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
25 SUNXI_FUNCTION(0x3, "ts0"), /* CLK */
26 SUNXI_FUNCTION(0x5, "keypad")), /* IN0 */
27 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 1),
28 PINCTRL_SUN5I_A10S,
29 SUNXI_FUNCTION(0x0, "gpio_in"),
30 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
32 SUNXI_FUNCTION(0x3, "ts0"), /* ERR */
33 SUNXI_FUNCTION(0x5, "keypad")), /* IN1 */
34 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 2),
35 PINCTRL_SUN5I_A10S,
36 SUNXI_FUNCTION(0x0, "gpio_in"),
37 SUNXI_FUNCTION(0x1, "gpio_out"),
38 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
39 SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */
40 SUNXI_FUNCTION(0x5, "keypad")), /* IN2 */
41 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 3),
42 PINCTRL_SUN5I_A10S,
43 SUNXI_FUNCTION(0x0, "gpio_in"),
44 SUNXI_FUNCTION(0x1, "gpio_out"),
45 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
46 SUNXI_FUNCTION(0x3, "ts0"), /* DLVD */
47 SUNXI_FUNCTION(0x5, "keypad")), /* IN3 */
48 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 4),
49 PINCTRL_SUN5I_A10S,
50 SUNXI_FUNCTION(0x0, "gpio_in"),
51 SUNXI_FUNCTION(0x1, "gpio_out"),
52 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
53 SUNXI_FUNCTION(0x3, "ts0"), /* D0 */
54 SUNXI_FUNCTION(0x5, "keypad")), /* IN4 */
55 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 5),
56 PINCTRL_SUN5I_A10S,
57 SUNXI_FUNCTION(0x0, "gpio_in"),
58 SUNXI_FUNCTION(0x1, "gpio_out"),
59 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
60 SUNXI_FUNCTION(0x3, "ts0"), /* D1 */
61 SUNXI_FUNCTION(0x5, "keypad")), /* IN5 */
62 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 6),
63 PINCTRL_SUN5I_A10S,
64 SUNXI_FUNCTION(0x0, "gpio_in"),
65 SUNXI_FUNCTION(0x1, "gpio_out"),
66 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
67 SUNXI_FUNCTION(0x3, "ts0"), /* D2 */
68 SUNXI_FUNCTION(0x5, "keypad")), /* IN6 */
69 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 7),
70 PINCTRL_SUN5I_A10S,
71 SUNXI_FUNCTION(0x0, "gpio_in"),
72 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
74 SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
75 SUNXI_FUNCTION(0x5, "keypad")), /* IN7 */
76 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 8),
77 PINCTRL_SUN5I_A10S,
78 SUNXI_FUNCTION(0x0, "gpio_in"),
79 SUNXI_FUNCTION(0x1, "gpio_out"),
80 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
81 SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
82 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
83 SUNXI_FUNCTION(0x5, "keypad")), /* OUT0 */
84 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 9),
85 PINCTRL_SUN5I_A10S,
86 SUNXI_FUNCTION(0x0, "gpio_in"),
87 SUNXI_FUNCTION(0x1, "gpio_out"),
88 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
89 SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
90 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
91 SUNXI_FUNCTION(0x5, "keypad")), /* OUT1 */
92 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 10),
93 PINCTRL_SUN5I_A10S,
94 SUNXI_FUNCTION(0x0, "gpio_in"),
95 SUNXI_FUNCTION(0x1, "gpio_out"),
96 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
97 SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
98 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
99 SUNXI_FUNCTION(0x5, "keypad")), /* OUT2 */
100 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 11),
101 PINCTRL_SUN5I_A10S,
102 SUNXI_FUNCTION(0x0, "gpio_in"),
103 SUNXI_FUNCTION(0x1, "gpio_out"),
104 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
105 SUNXI_FUNCTION(0x3, "ts0"), /* D7 */
106 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
107 SUNXI_FUNCTION(0x5, "keypad")), /* OUT3 */
108 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 12),
109 PINCTRL_SUN5I_A10S,
110 SUNXI_FUNCTION(0x0, "gpio_in"),
111 SUNXI_FUNCTION(0x1, "gpio_out"),
112 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
113 SUNXI_FUNCTION(0x3, "uart1"), /* TX */
114 SUNXI_FUNCTION(0x5, "keypad")), /* OUT4 */
115 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 13),
116 PINCTRL_SUN5I_A10S,
117 SUNXI_FUNCTION(0x0, "gpio_in"),
118 SUNXI_FUNCTION(0x1, "gpio_out"),
119 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
120 SUNXI_FUNCTION(0x3, "uart1"), /* RX */
121 SUNXI_FUNCTION(0x5, "keypad")), /* OUT5 */
122 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 14),
123 PINCTRL_SUN5I_A10S,
124 SUNXI_FUNCTION(0x0, "gpio_in"),
125 SUNXI_FUNCTION(0x1, "gpio_out"),
126 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
127 SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
128 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
129 SUNXI_FUNCTION(0x5, "keypad")), /* OUT6 */
130 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 15),
131 PINCTRL_SUN5I_A10S,
132 SUNXI_FUNCTION(0x0, "gpio_in"),
133 SUNXI_FUNCTION(0x1, "gpio_out"),
134 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
135 SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
136 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
137 SUNXI_FUNCTION(0x5, "keypad")), /* OUT7 */
138 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 16),
139 PINCTRL_SUN5I_A10S,
140 SUNXI_FUNCTION(0x0, "gpio_in"),
141 SUNXI_FUNCTION(0x1, "gpio_out"),
142 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
143 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
144 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 17),
145 PINCTRL_SUN5I_A10S,
146 SUNXI_FUNCTION(0x0, "gpio_in"),
147 SUNXI_FUNCTION(0x1, "gpio_out"),
148 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
149 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
150 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
151 /* Hole */
152 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
153 SUNXI_FUNCTION(0x0, "gpio_in"),
154 SUNXI_FUNCTION(0x1, "gpio_out"),
155 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
156 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
157 SUNXI_FUNCTION(0x0, "gpio_in"),
158 SUNXI_FUNCTION(0x1, "gpio_out"),
159 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
160 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
161 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
164 SUNXI_FUNCTION_VARIANT(0x3,
165 "spdif", /* DO */
166 PINCTRL_SUN5I_GR8),
167 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
168 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
169 SUNXI_FUNCTION(0x0, "gpio_in"),
170 SUNXI_FUNCTION(0x1, "gpio_out"),
171 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
172 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
173 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
174 SUNXI_FUNCTION(0x0, "gpio_in"),
175 SUNXI_FUNCTION(0x1, "gpio_out"),
176 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
177 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
178 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 5),
179 PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
180 SUNXI_FUNCTION(0x0, "gpio_in"),
181 SUNXI_FUNCTION(0x1, "gpio_out"),
182 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
183 SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */
184 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 6),
185 PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
186 SUNXI_FUNCTION(0x0, "gpio_in"),
187 SUNXI_FUNCTION(0x1, "gpio_out"),
188 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
189 SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */
190 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 7),
191 PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
192 SUNXI_FUNCTION(0x0, "gpio_in"),
193 SUNXI_FUNCTION(0x1, "gpio_out"),
194 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
195 SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */
196 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 8),
197 PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
198 SUNXI_FUNCTION(0x0, "gpio_in"),
199 SUNXI_FUNCTION(0x1, "gpio_out"),
200 SUNXI_FUNCTION(0x2, "i2s"), /* DO */
201 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
202 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 9),
203 PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
204 SUNXI_FUNCTION(0x0, "gpio_in"),
205 SUNXI_FUNCTION(0x1, "gpio_out"),
206 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
207 SUNXI_FUNCTION_VARIANT(0x3,
208 "spdif", /* DI */
209 PINCTRL_SUN5I_GR8),
210 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
211 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
212 SUNXI_FUNCTION(0x0, "gpio_in"),
213 SUNXI_FUNCTION(0x1, "gpio_out"),
214 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
215 SUNXI_FUNCTION_VARIANT(0x3,
216 "spdif", /* DO */
217 PINCTRL_SUN5I_GR8),
218 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
219 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 11),
220 PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
221 SUNXI_FUNCTION(0x0, "gpio_in"),
222 SUNXI_FUNCTION(0x1, "gpio_out"),
223 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
224 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
225 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
226 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 12),
227 PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
228 SUNXI_FUNCTION(0x0, "gpio_in"),
229 SUNXI_FUNCTION(0x1, "gpio_out"),
230 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
231 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
232 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
233 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 13),
234 PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
235 SUNXI_FUNCTION(0x0, "gpio_in"),
236 SUNXI_FUNCTION(0x1, "gpio_out"),
237 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
238 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
239 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
240 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 14),
241 PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
242 SUNXI_FUNCTION(0x0, "gpio_in"),
243 SUNXI_FUNCTION(0x1, "gpio_out"),
244 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
245 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
246 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
247 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
248 SUNXI_FUNCTION(0x0, "gpio_in"),
249 SUNXI_FUNCTION(0x1, "gpio_out"),
250 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
251 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
252 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x1, "gpio_out"),
254 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
255 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
256 SUNXI_FUNCTION(0x0, "gpio_in"),
257 SUNXI_FUNCTION(0x1, "gpio_out"),
258 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
259 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
260 SUNXI_FUNCTION(0x0, "gpio_in"),
261 SUNXI_FUNCTION(0x1, "gpio_out"),
262 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
263 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 19),
264 PINCTRL_SUN5I_A10S,
265 SUNXI_FUNCTION(0x0, "gpio_in"),
266 SUNXI_FUNCTION(0x1, "gpio_out"),
267 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
268 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
269 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 20),
270 PINCTRL_SUN5I_A10S,
271 SUNXI_FUNCTION(0x0, "gpio_in"),
272 SUNXI_FUNCTION(0x1, "gpio_out"),
273 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
274 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
275 /* Hole */
276 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
277 SUNXI_FUNCTION(0x0, "gpio_in"),
278 SUNXI_FUNCTION(0x1, "gpio_out"),
279 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
280 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
281 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
282 SUNXI_FUNCTION(0x0, "gpio_in"),
283 SUNXI_FUNCTION(0x1, "gpio_out"),
284 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
285 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
286 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
287 SUNXI_FUNCTION(0x0, "gpio_in"),
288 SUNXI_FUNCTION(0x1, "gpio_out"),
289 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
290 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
291 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
292 SUNXI_FUNCTION(0x0, "gpio_in"),
293 SUNXI_FUNCTION(0x1, "gpio_out"),
294 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
295 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
296 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
297 SUNXI_FUNCTION(0x0, "gpio_in"),
298 SUNXI_FUNCTION(0x1, "gpio_out"),
299 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
300 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
301 SUNXI_FUNCTION(0x0, "gpio_in"),
302 SUNXI_FUNCTION(0x1, "gpio_out"),
303 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
304 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
305 SUNXI_FUNCTION(0x0, "gpio_in"),
306 SUNXI_FUNCTION(0x1, "gpio_out"),
307 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
308 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
309 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
310 SUNXI_FUNCTION(0x0, "gpio_in"),
311 SUNXI_FUNCTION(0x1, "gpio_out"),
312 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
313 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
314 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
315 SUNXI_FUNCTION(0x0, "gpio_in"),
316 SUNXI_FUNCTION(0x1, "gpio_out"),
317 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
318 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
319 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
320 SUNXI_FUNCTION(0x0, "gpio_in"),
321 SUNXI_FUNCTION(0x1, "gpio_out"),
322 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
323 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
324 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
325 SUNXI_FUNCTION(0x0, "gpio_in"),
326 SUNXI_FUNCTION(0x1, "gpio_out"),
327 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
328 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
329 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
330 SUNXI_FUNCTION(0x0, "gpio_in"),
331 SUNXI_FUNCTION(0x1, "gpio_out"),
332 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
333 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
334 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
335 SUNXI_FUNCTION(0x0, "gpio_in"),
336 SUNXI_FUNCTION(0x1, "gpio_out"),
337 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
338 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
339 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
340 SUNXI_FUNCTION(0x0, "gpio_in"),
341 SUNXI_FUNCTION(0x1, "gpio_out"),
342 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
343 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
344 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
345 SUNXI_FUNCTION(0x0, "gpio_in"),
346 SUNXI_FUNCTION(0x1, "gpio_out"),
347 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
348 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
349 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
350 SUNXI_FUNCTION(0x0, "gpio_in"),
351 SUNXI_FUNCTION(0x1, "gpio_out"),
352 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
353 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
354 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 16),
355 PINCTRL_SUN5I_A10S,
356 SUNXI_FUNCTION(0x0, "gpio_in"),
357 SUNXI_FUNCTION(0x1, "gpio_out"),
358 SUNXI_FUNCTION(0x2, "nand0"), /* NWP */
359 SUNXI_FUNCTION(0x4, "uart3")), /* TX */
360 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 17),
361 PINCTRL_SUN5I_A10S,
362 SUNXI_FUNCTION(0x0, "gpio_in"),
363 SUNXI_FUNCTION(0x1, "gpio_out"),
364 SUNXI_FUNCTION(0x2, "nand0"), /* NCE2 */
365 SUNXI_FUNCTION(0x4, "uart3")), /* RX */
366 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 18),
367 PINCTRL_SUN5I_A10S,
368 SUNXI_FUNCTION(0x0, "gpio_in"),
369 SUNXI_FUNCTION(0x1, "gpio_out"),
370 SUNXI_FUNCTION(0x2, "nand0"), /* NCE3 */
371 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
372 SUNXI_FUNCTION(0x4, "uart3")), /* CTS */
373 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
374 SUNXI_FUNCTION(0x0, "gpio_in"),
375 SUNXI_FUNCTION(0x1, "gpio_out"),
376 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
377 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
378 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
379 /* Hole */
380 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 0),
381 PINCTRL_SUN5I_A10S,
382 SUNXI_FUNCTION(0x0, "gpio_in"),
383 SUNXI_FUNCTION(0x1, "gpio_out"),
384 SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */
385 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 1),
386 PINCTRL_SUN5I_A10S,
387 SUNXI_FUNCTION(0x0, "gpio_in"),
388 SUNXI_FUNCTION(0x1, "gpio_out"),
389 SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */
390 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
391 SUNXI_FUNCTION(0x0, "gpio_in"),
392 SUNXI_FUNCTION(0x1, "gpio_out"),
393 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
394 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
395 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
396 SUNXI_FUNCTION(0x0, "gpio_in"),
397 SUNXI_FUNCTION(0x1, "gpio_out"),
398 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
399 SUNXI_FUNCTION(0x3, "uart2")), /* RX */
400 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
401 SUNXI_FUNCTION(0x0, "gpio_in"),
402 SUNXI_FUNCTION(0x1, "gpio_out"),
403 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
404 SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
405 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
406 SUNXI_FUNCTION(0x0, "gpio_in"),
407 SUNXI_FUNCTION(0x1, "gpio_out"),
408 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
409 SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
410 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
411 SUNXI_FUNCTION(0x0, "gpio_in"),
412 SUNXI_FUNCTION(0x1, "gpio_out"),
413 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
414 SUNXI_FUNCTION(0x3, "emac")), /* ECRS */
415 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
416 SUNXI_FUNCTION(0x0, "gpio_in"),
417 SUNXI_FUNCTION(0x1, "gpio_out"),
418 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
419 SUNXI_FUNCTION(0x3, "emac")), /* ECOL */
420 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 8),
421 PINCTRL_SUN5I_A10S,
422 SUNXI_FUNCTION(0x0, "gpio_in"),
423 SUNXI_FUNCTION(0x1, "gpio_out"),
424 SUNXI_FUNCTION(0x2, "lcd0")), /* D8 */
425 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 9),
426 PINCTRL_SUN5I_A10S,
427 SUNXI_FUNCTION(0x0, "gpio_in"),
428 SUNXI_FUNCTION(0x1, "gpio_out"),
429 SUNXI_FUNCTION(0x2, "lcd0")), /* D9 */
430 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
431 SUNXI_FUNCTION(0x0, "gpio_in"),
432 SUNXI_FUNCTION(0x1, "gpio_out"),
433 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
434 SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */
435 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
436 SUNXI_FUNCTION(0x0, "gpio_in"),
437 SUNXI_FUNCTION(0x1, "gpio_out"),
438 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
439 SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */
440 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
441 SUNXI_FUNCTION(0x0, "gpio_in"),
442 SUNXI_FUNCTION(0x1, "gpio_out"),
443 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
444 SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */
445 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
446 SUNXI_FUNCTION(0x0, "gpio_in"),
447 SUNXI_FUNCTION(0x1, "gpio_out"),
448 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
449 SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */
450 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
451 SUNXI_FUNCTION(0x0, "gpio_in"),
452 SUNXI_FUNCTION(0x1, "gpio_out"),
453 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
454 SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */
455 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
456 SUNXI_FUNCTION(0x0, "gpio_in"),
457 SUNXI_FUNCTION(0x1, "gpio_out"),
458 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
459 SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */
460 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 16),
461 PINCTRL_SUN5I_A10S,
462 SUNXI_FUNCTION(0x0, "gpio_in"),
463 SUNXI_FUNCTION(0x1, "gpio_out"),
464 SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
465 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 17),
466 PINCTRL_SUN5I_A10S,
467 SUNXI_FUNCTION(0x0, "gpio_in"),
468 SUNXI_FUNCTION(0x1, "gpio_out"),
469 SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
470 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
471 SUNXI_FUNCTION(0x0, "gpio_in"),
472 SUNXI_FUNCTION(0x1, "gpio_out"),
473 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
474 SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */
475 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
476 SUNXI_FUNCTION(0x0, "gpio_in"),
477 SUNXI_FUNCTION(0x1, "gpio_out"),
478 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
479 SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */
480 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
481 SUNXI_FUNCTION(0x0, "gpio_in"),
482 SUNXI_FUNCTION(0x1, "gpio_out"),
483 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
484 SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */
485 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
486 SUNXI_FUNCTION(0x0, "gpio_in"),
487 SUNXI_FUNCTION(0x1, "gpio_out"),
488 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
489 SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */
490 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
491 SUNXI_FUNCTION(0x0, "gpio_in"),
492 SUNXI_FUNCTION(0x1, "gpio_out"),
493 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
494 SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */
495 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
496 SUNXI_FUNCTION(0x0, "gpio_in"),
497 SUNXI_FUNCTION(0x1, "gpio_out"),
498 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
499 SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */
500 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
501 SUNXI_FUNCTION(0x0, "gpio_in"),
502 SUNXI_FUNCTION(0x1, "gpio_out"),
503 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
504 SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */
505 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
506 SUNXI_FUNCTION(0x0, "gpio_in"),
507 SUNXI_FUNCTION(0x1, "gpio_out"),
508 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
509 SUNXI_FUNCTION(0x3, "emac")), /* ETXERR */
510 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
511 SUNXI_FUNCTION(0x0, "gpio_in"),
512 SUNXI_FUNCTION(0x1, "gpio_out"),
513 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
514 SUNXI_FUNCTION(0x3, "emac")), /* EMDC */
515 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
516 SUNXI_FUNCTION(0x0, "gpio_in"),
517 SUNXI_FUNCTION(0x1, "gpio_out"),
518 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
519 SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */
520 /* Hole */
521 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
522 SUNXI_FUNCTION(0x0, "gpio_in"),
523 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
524 SUNXI_FUNCTION(0x3, "csi0"), /* PCK */
525 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
526 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
527 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
528 SUNXI_FUNCTION(0x0, "gpio_in"),
529 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
530 SUNXI_FUNCTION(0x3, "csi0"), /* CK */
531 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
532 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
533 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
534 SUNXI_FUNCTION(0x0, "gpio_in"),
535 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
536 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
537 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
538 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
539 SUNXI_FUNCTION(0x0, "gpio_in"),
540 SUNXI_FUNCTION(0x1, "gpio_out"),
541 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
542 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
543 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
544 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
545 SUNXI_FUNCTION(0x0, "gpio_in"),
546 SUNXI_FUNCTION(0x1, "gpio_out"),
547 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
548 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
549 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
550 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
551 SUNXI_FUNCTION(0x0, "gpio_in"),
552 SUNXI_FUNCTION(0x1, "gpio_out"),
553 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
554 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
555 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
556 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
557 SUNXI_FUNCTION(0x0, "gpio_in"),
558 SUNXI_FUNCTION(0x1, "gpio_out"),
559 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
560 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
561 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
562 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
563 SUNXI_FUNCTION(0x0, "gpio_in"),
564 SUNXI_FUNCTION(0x1, "gpio_out"),
565 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
566 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
567 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
568 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
569 SUNXI_FUNCTION(0x0, "gpio_in"),
570 SUNXI_FUNCTION(0x1, "gpio_out"),
571 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
572 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
573 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
574 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
575 SUNXI_FUNCTION(0x0, "gpio_in"),
576 SUNXI_FUNCTION(0x1, "gpio_out"),
577 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
578 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
579 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
580 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
581 SUNXI_FUNCTION(0x0, "gpio_in"),
582 SUNXI_FUNCTION(0x1, "gpio_out"),
583 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
584 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
585 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
586 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
587 SUNXI_FUNCTION(0x0, "gpio_in"),
588 SUNXI_FUNCTION(0x1, "gpio_out"),
589 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
590 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
591 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
592 /* Hole */
593 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
594 SUNXI_FUNCTION(0x0, "gpio_in"),
595 SUNXI_FUNCTION(0x1, "gpio_out"),
596 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
597 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
598 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
599 SUNXI_FUNCTION(0x0, "gpio_in"),
600 SUNXI_FUNCTION(0x1, "gpio_out"),
601 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
602 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
603 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
604 SUNXI_FUNCTION(0x0, "gpio_in"),
605 SUNXI_FUNCTION(0x1, "gpio_out"),
606 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
607 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
608 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
609 SUNXI_FUNCTION(0x0, "gpio_in"),
610 SUNXI_FUNCTION(0x1, "gpio_out"),
611 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
612 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
613 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
614 SUNXI_FUNCTION(0x0, "gpio_in"),
615 SUNXI_FUNCTION(0x1, "gpio_out"),
616 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
617 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
618 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
619 SUNXI_FUNCTION(0x0, "gpio_in"),
620 SUNXI_FUNCTION(0x1, "gpio_out"),
621 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
622 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
623 /* Hole */
624 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
625 SUNXI_FUNCTION(0x0, "gpio_in"),
626 SUNXI_FUNCTION(0x2, "gps"), /* CLK */
627 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
628 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
629 SUNXI_FUNCTION(0x0, "gpio_in"),
630 SUNXI_FUNCTION(0x2, "gps"), /* SIGN */
631 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
632 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
633 SUNXI_FUNCTION(0x0, "gpio_in"),
634 SUNXI_FUNCTION(0x2, "gps"), /* MAG */
635 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
636 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
637 SUNXI_FUNCTION(0x0, "gpio_in"),
638 SUNXI_FUNCTION(0x1, "gpio_out"),
639 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
640 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
641 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
642 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
643 SUNXI_FUNCTION(0x0, "gpio_in"),
644 SUNXI_FUNCTION(0x1, "gpio_out"),
645 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
646 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
647 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
648 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 5),
649 PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
650 SUNXI_FUNCTION(0x0, "gpio_in"),
651 SUNXI_FUNCTION(0x1, "gpio_out"),
652 SUNXI_FUNCTION(0x2, "mmc1"), /* DO */
653 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
654 SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */
655 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 6),
656 PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
657 SUNXI_FUNCTION(0x0, "gpio_in"),
658 SUNXI_FUNCTION(0x1, "gpio_out"),
659 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
660 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
661 SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
662 SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */
663 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 7),
664 PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
665 SUNXI_FUNCTION(0x0, "gpio_in"),
666 SUNXI_FUNCTION(0x1, "gpio_out"),
667 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
668 SUNXI_FUNCTION(0x5, "uart2"), /* TX */
669 SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */
670 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 8),
671 PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
672 SUNXI_FUNCTION(0x0, "gpio_in"),
673 SUNXI_FUNCTION(0x1, "gpio_out"),
674 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
675 SUNXI_FUNCTION(0x5, "uart2"), /* RX */
676 SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */
677 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
678 SUNXI_FUNCTION(0x0, "gpio_in"),
679 SUNXI_FUNCTION(0x1, "gpio_out"),
680 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
681 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
682 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
683 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
684 SUNXI_FUNCTION(0x0, "gpio_in"),
685 SUNXI_FUNCTION(0x1, "gpio_out"),
686 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
687 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
688 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
689 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
690 SUNXI_FUNCTION(0x0, "gpio_in"),
691 SUNXI_FUNCTION(0x1, "gpio_out"),
692 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
693 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
694 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
695 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
696 SUNXI_FUNCTION(0x0, "gpio_in"),
697 SUNXI_FUNCTION(0x1, "gpio_out"),
698 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
699 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
700 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
701 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 13),
702 PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
703 SUNXI_FUNCTION(0x0, "gpio_in"),
704 SUNXI_FUNCTION(0x1, "gpio_out"),
705 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
706 SUNXI_FUNCTION(0x3, "pwm"), /* PWM1 */
707 SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
708 SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
709};
710
711static const struct sunxi_pinctrl_desc sun5i_pinctrl_data = {
712 .pins = sun5i_pins,
713 .npins = ARRAY_SIZE(sun5i_pins),
714 .irq_banks = 1,
cd70387f 715 .disable_strict_mode = true,
858f559f
MR		 716};
717
718static int sun5i_pinctrl_probe(struct platform_device *pdev)
719{
720 unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev);
721
858f559f
MR		 722 return sunxi_pinctrl_init_with_variant(pdev, &sun5i_pinctrl_data,
723 variant);
724}
725
726static const struct of_device_id sun5i_pinctrl_match[] = {
727 {
728 .compatible = "allwinner,sun5i-a10s-pinctrl",
729 .data = (void *)PINCTRL_SUN5I_A10S
730 },
731 {
732 .compatible = "allwinner,sun5i-a13-pinctrl",
733 .data = (void *)PINCTRL_SUN5I_A13
734 },
735 {
736 .compatible = "nextthing,gr8-pinctrl",
737 .data = (void *)PINCTRL_SUN5I_GR8
738 },
739 { },
740};
858f559f
MR		 741
742static struct platform_driver sun5i_pinctrl_driver = {
743 .probe = sun5i_pinctrl_probe,
744 .driver = {
745 .name = "sun5i-pinctrl",
746 .of_match_table = sun5i_pinctrl_match,
747 },
748};
cff1f7a9 749builtin_platform_driver(sun5i_pinctrl_driver);
Empty description
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