projects / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| fe56b9e6 | 1 | /* QLogic qed NIC Driver |
| e8f1cb50 | 2 | * Copyright (c) 2015-2017 QLogic Corporation |
| fe56b9e6 | 3 | * |
| e8f1cb50 MY |
4 | * This software is available to you under a choice of one of two |
| 5 | * licenses. You may choose to be licensed under the terms of the GNU | |
| 6 | * General Public License (GPL) Version 2, available from the file | |
| 7 | * COPYING in the main directory of this source tree, or the | |
| 8 | * OpenIB.org BSD license below: | |
| 9 | * | |
| 10 | * Redistribution and use in source and binary forms, with or | |
| 11 | * without modification, are permitted provided that the following | |
| 12 | * conditions are met: | |
| 13 | * | |
| 14 | * - Redistributions of source code must retain the above | |
| 15 | * copyright notice, this list of conditions and the following | |
| 16 | * disclaimer. | |
| 17 | * | |
| 18 | * - Redistributions in binary form must reproduce the above | |
| 19 | * copyright notice, this list of conditions and the following | |
| 20 | * disclaimer in the documentation and /or other materials | |
| 21 | * provided with the distribution. | |
| 22 | * | |
| 23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
| 25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
| 27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
| 28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
| 29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
| 30 | * SOFTWARE. | |
| fe56b9e6 YM |
31 | */ |
| 32 | ||
| 33 | #ifndef REG_ADDR_H | |
| 34 | #define REG_ADDR_H | |
| 35 | ||
| 36 | #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \ | |
| 37 | 0 | |
| 38 | ||
| 39 | #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \ | |
| 40 | 0xfff << 0) | |
| 41 | ||
| 42 | #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \ | |
| 43 | 12 | |
| 44 | ||
| 45 | #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \ | |
| 46 | 0xfff << 12) | |
| 47 | ||
| 48 | #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \ | |
| 49 | 24 | |
| 50 | ||
| 51 | #define CDU_REG_CID_ADDR_PARAMS_NCIB ( \ | |
| 52 | 0xff << 24) | |
| 53 | ||
| dbb799c3 YM |
54 | #define CDU_REG_SEGMENT0_PARAMS \ |
| 55 | 0x580904UL | |
| 56 | #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \ | |
| 57 | (0xfff << 0) | |
| 58 | #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \ | |
| 59 | 0 | |
| 60 | #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \ | |
| 61 | (0xff << 16) | |
| 62 | #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \ | |
| 63 | 16 | |
| 64 | #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \ | |
| 65 | (0xff << 24) | |
| 66 | #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \ | |
| 67 | 24 | |
| 68 | #define CDU_REG_SEGMENT1_PARAMS \ | |
| 69 | 0x580908UL | |
| 70 | #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \ | |
| 71 | (0xfff << 0) | |
| 72 | #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \ | |
| 73 | 0 | |
| 74 | #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \ | |
| 75 | (0xff << 16) | |
| 76 | #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \ | |
| 77 | 16 | |
| 78 | #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \ | |
| 79 | (0xff << 24) | |
| 80 | #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \ | |
| 81 | 24 | |
| 82 | ||
| fe56b9e6 YM |
83 | #define XSDM_REG_OPERATION_GEN \ |
| 84 | 0xf80408UL | |
| 85 | #define NIG_REG_RX_BRB_OUT_EN \ | |
| 86 | 0x500e18UL | |
| 87 | #define NIG_REG_STORM_OUT_EN \ | |
| 88 | 0x500e08UL | |
| 89 | #define PSWRQ2_REG_L2P_VALIDATE_VFID \ | |
| 90 | 0x240c50UL | |
| 91 | #define PGLUE_B_REG_USE_CLIENTID_IN_TAG \ | |
| 92 | 0x2aae04UL | |
| 93 | #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \ | |
| 94 | 0x2aa16cUL | |
| 1408cc1f YM |
95 | #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \ |
| 96 | 0x2aa118UL | |
| 0b55e27d YM |
97 | #define PSWHST_REG_ZONE_PERMISSION_TABLE \ |
| 98 | 0x2a0800UL | |
| fe56b9e6 YM |
99 | #define BAR0_MAP_REG_MSDM_RAM \ |
| 100 | 0x1d00000UL | |
| 101 | #define BAR0_MAP_REG_USDM_RAM \ | |
| 102 | 0x1d80000UL | |
| 103 | #define BAR0_MAP_REG_PSDM_RAM \ | |
| 104 | 0x1f00000UL | |
| 105 | #define BAR0_MAP_REG_TSDM_RAM \ | |
| 106 | 0x1c80000UL | |
| 722003ac SRK |
107 | #define BAR0_MAP_REG_XSDM_RAM \ |
| 108 | 0x1e00000UL | |
| fc831825 YM |
109 | #define BAR0_MAP_REG_YSDM_RAM \ |
| 110 | 0x1e80000UL | |
| fe56b9e6 YM |
111 | #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \ |
| 112 | 0x5011f4UL | |
| 1e128c81 AE |
113 | #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE \ |
| 114 | 0x1f0164UL | |
| fe56b9e6 YM |
115 | #define PRS_REG_SEARCH_TCP \ |
| 116 | 0x1f0400UL | |
| 117 | #define PRS_REG_SEARCH_UDP \ | |
| 118 | 0x1f0404UL | |
| 119 | #define PRS_REG_SEARCH_FCOE \ | |
| 120 | 0x1f0408UL | |
| 121 | #define PRS_REG_SEARCH_ROCE \ | |
| 122 | 0x1f040cUL | |
| 123 | #define PRS_REG_SEARCH_OPENFLOW \ | |
| 124 | 0x1f0434UL | |
| 1e128c81 AE |
125 | #define PRS_REG_SEARCH_TAG1 \ |
| 126 | 0x1f0444UL | |
| da090917 TT |
127 | #define PRS_REG_SEARCH_TENANT_ID \ |
| 128 | 0x1f044cUL | |
| 1e128c81 AE |
129 | #define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST \ |
| 130 | 0x1f0a0cUL | |
| 131 | #define PRS_REG_SEARCH_TCP_FIRST_FRAG \ | |
| 132 | 0x1f0410UL | |
| fe56b9e6 YM |
133 | #define TM_REG_PF_ENABLE_CONN \ |
| 134 | 0x2c043cUL | |
| 135 | #define TM_REG_PF_ENABLE_TASK \ | |
| 136 | 0x2c0444UL | |
| 137 | #define TM_REG_PF_SCAN_ACTIVE_CONN \ | |
| 138 | 0x2c04fcUL | |
| 139 | #define TM_REG_PF_SCAN_ACTIVE_TASK \ | |
| 140 | 0x2c0500UL | |
| 141 | #define IGU_REG_LEADING_EDGE_LATCH \ | |
| 142 | 0x18082cUL | |
| 143 | #define IGU_REG_TRAILING_EDGE_LATCH \ | |
| 144 | 0x180830UL | |
| 145 | #define QM_REG_USG_CNT_PF_TX \ | |
| 146 | 0x2f2eacUL | |
| 147 | #define QM_REG_USG_CNT_PF_OTHER \ | |
| 148 | 0x2f2eb0UL | |
| 149 | #define DORQ_REG_PF_DB_ENABLE \ | |
| 150 | 0x100508UL | |
| 0b55e27d YM |
151 | #define DORQ_REG_VF_USAGE_CNT \ |
| 152 | 0x1009c4UL | |
| fe56b9e6 YM |
153 | #define QM_REG_PF_EN \ |
| 154 | 0x2f2ea4UL | |
| 05fafbfb YM |
155 | #define TCFC_REG_WEAK_ENABLE_VF \ |
| 156 | 0x2d0704UL | |
| fe56b9e6 YM |
157 | #define TCFC_REG_STRONG_ENABLE_PF \ |
| 158 | 0x2d0708UL | |
| 05fafbfb YM |
159 | #define TCFC_REG_STRONG_ENABLE_VF \ |
| 160 | 0x2d070cUL | |
| 161 | #define CCFC_REG_WEAK_ENABLE_VF \ | |
| 162 | 0x2e0704UL | |
| fe56b9e6 YM |
163 | #define CCFC_REG_STRONG_ENABLE_PF \ |
| 164 | 0x2e0708UL | |
| 9c79ddaa | 165 | #define PGLUE_B_REG_PGL_ADDR_88_F0_BB \ |
| fe56b9e6 | 166 | 0x2aa404UL |
| 9c79ddaa | 167 | #define PGLUE_B_REG_PGL_ADDR_8C_F0_BB \ |
| fe56b9e6 | 168 | 0x2aa408UL |
| 9c79ddaa | 169 | #define PGLUE_B_REG_PGL_ADDR_90_F0_BB \ |
| fe56b9e6 | 170 | 0x2aa40cUL |
| 9c79ddaa | 171 | #define PGLUE_B_REG_PGL_ADDR_94_F0_BB \ |
| fe56b9e6 YM |
172 | 0x2aa410UL |
| 173 | #define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \ | |
| 174 | 0x2aa138UL | |
| 175 | #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \ | |
| 176 | 0x2aa174UL | |
| 177 | #define MISC_REG_GEN_PURP_CR0 \ | |
| 178 | 0x008c80UL | |
| 179 | #define MCP_REG_SCRATCH \ | |
| 180 | 0xe20000UL | |
| d52c89f1 | 181 | #define CNIG_REG_NW_PORT_MODE_BB \ |
| fe56b9e6 YM |
182 | 0x218200UL |
| 183 | #define MISCS_REG_CHIP_NUM \ | |
| 184 | 0x00976cUL | |
| 185 | #define MISCS_REG_CHIP_REV \ | |
| 186 | 0x009770UL | |
| 187 | #define MISCS_REG_CMT_ENABLED_FOR_PAIR \ | |
| 188 | 0x00971cUL | |
| 189 | #define MISCS_REG_CHIP_TEST_REG \ | |
| 190 | 0x009778UL | |
| 191 | #define MISCS_REG_CHIP_METAL \ | |
| 192 | 0x009774UL | |
| 1408cc1f YM |
193 | #define MISCS_REG_FUNCTION_HIDE \ |
| 194 | 0x0096f0UL | |
| fe56b9e6 YM |
195 | #define BRB_REG_HEADER_SIZE \ |
| 196 | 0x340804UL | |
| 197 | #define BTB_REG_HEADER_SIZE \ | |
| 198 | 0xdb0804UL | |
| 199 | #define CAU_REG_LONG_TIMEOUT_THRESHOLD \ | |
| 200 | 0x1c0708UL | |
| 201 | #define CCFC_REG_ACTIVITY_COUNTER \ | |
| 202 | 0x2e8800UL | |
| 1408cc1f YM |
203 | #define CCFC_REG_STRONG_ENABLE_VF \ |
| 204 | 0x2e070cUL | |
| da090917 TT |
205 | #define CDU_REG_CCFC_CTX_VALID0 \ |
| 206 | 0x580400UL | |
| 207 | #define CDU_REG_CCFC_CTX_VALID1 \ | |
| 208 | 0x580404UL | |
| 209 | #define CDU_REG_TCFC_CTX_VALID0 \ | |
| 210 | 0x580408UL | |
| 211 | #define CDU_REG_CID_ADDR_PARAMS \ | |
| fe56b9e6 YM |
212 | 0x580900UL |
| 213 | #define DBG_REG_CLIENT_ENABLE \ | |
| 214 | 0x010004UL | |
| 215 | #define DMAE_REG_INIT \ | |
| 216 | 0x00c000UL | |
| 217 | #define DORQ_REG_IFEN \ | |
| 218 | 0x100040UL | |
| 7e3e375c SRK |
219 | #define DORQ_REG_TAG1_OVRD_MODE \ |
| 220 | 0x1008b4UL | |
| 221 | #define DORQ_REG_PF_PCP_BB_K2 \ | |
| 222 | 0x1008c4UL | |
| 223 | #define DORQ_REG_PF_EXT_VID_BB_K2 \ | |
| 224 | 0x1008c8UL | |
| b4149dc7 YM |
225 | #define DORQ_REG_DB_DROP_REASON \ |
| 226 | 0x100a2cUL | |
| 227 | #define DORQ_REG_DB_DROP_DETAILS \ | |
| 228 | 0x100a24UL | |
| 229 | #define DORQ_REG_DB_DROP_DETAILS_ADDRESS \ | |
| 230 | 0x100a1cUL | |
| fe56b9e6 YM |
231 | #define GRC_REG_TIMEOUT_EN \ |
| 232 | 0x050404UL | |
| b4149dc7 YM |
233 | #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \ |
| 234 | 0x050054UL | |
| 235 | #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \ | |
| 236 | 0x05004cUL | |
| 237 | #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \ | |
| 238 | 0x050050UL | |
| fe56b9e6 YM |
239 | #define IGU_REG_BLOCK_CONFIGURATION \ |
| 240 | 0x180040UL | |
| 241 | #define MCM_REG_INIT \ | |
| 242 | 0x1200000UL | |
| 243 | #define MCP2_REG_DBG_DWORD_ENABLE \ | |
| 244 | 0x052404UL | |
| 245 | #define MISC_REG_PORT_MODE \ | |
| 246 | 0x008c00UL | |
| 247 | #define MISCS_REG_CLK_100G_MODE \ | |
| 248 | 0x009070UL | |
| 249 | #define MSDM_REG_ENABLE_IN1 \ | |
| 250 | 0xfc0004UL | |
| 251 | #define MSEM_REG_ENABLE_IN \ | |
| 252 | 0x1800004UL | |
| 253 | #define NIG_REG_CM_HDR \ | |
| 254 | 0x500840UL | |
| 351a4ded YM |
255 | #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \ |
| 256 | 0x50196cUL | |
| 257 | #define NIG_REG_LLH_CLS_TYPE_DUALMODE \ | |
| 258 | 0x501964UL | |
| 2a351fd9 MY |
259 | #define NIG_REG_LLH_FUNC_TAG_EN 0x5019b0UL |
| 260 | #define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL | |
| 0a7fb11c YM |
261 | #define NIG_REG_LLH_FUNC_FILTER_VALUE \ |
| 262 | 0x501a00UL | |
| 263 | #define NIG_REG_LLH_FUNC_FILTER_VALUE_SIZE \ | |
| 264 | 32 | |
| 265 | #define NIG_REG_LLH_FUNC_FILTER_EN \ | |
| 266 | 0x501a80UL | |
| 267 | #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE \ | |
| 268 | 16 | |
| 269 | #define NIG_REG_LLH_FUNC_FILTER_MODE \ | |
| 270 | 0x501ac0UL | |
| 271 | #define NIG_REG_LLH_FUNC_FILTER_MODE_SIZE \ | |
| 272 | 16 | |
| 273 | #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE \ | |
| 274 | 0x501b00UL | |
| 275 | #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_SIZE \ | |
| 276 | 16 | |
| 277 | #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL \ | |
| 278 | 0x501b40UL | |
| 279 | #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_SIZE \ | |
| 280 | 16 | |
| fe56b9e6 YM |
281 | #define NCSI_REG_CONFIG \ |
| 282 | 0x040200UL | |
| 283 | #define PBF_REG_INIT \ | |
| 284 | 0xd80000UL | |
| 0b55e27d YM |
285 | #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \ |
| 286 | 0xd806c8UL | |
| 287 | #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \ | |
| 288 | 0xd806ccUL | |
| fe56b9e6 YM |
289 | #define PTU_REG_ATC_INIT_ARRAY \ |
| 290 | 0x560000UL | |
| 291 | #define PCM_REG_INIT \ | |
| 292 | 0x1100000UL | |
| 293 | #define PGLUE_B_REG_ADMIN_PER_PF_REGION \ | |
| 294 | 0x2a9000UL | |
| b4149dc7 YM |
295 | #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \ |
| 296 | 0x2aa150UL | |
| 297 | #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \ | |
| 298 | 0x2aa144UL | |
| 299 | #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \ | |
| 300 | 0x2aa148UL | |
| 301 | #define PGLUE_B_REG_TX_ERR_WR_DETAILS \ | |
| 302 | 0x2aa14cUL | |
| 303 | #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \ | |
| 304 | 0x2aa154UL | |
| 305 | #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \ | |
| 306 | 0x2aa158UL | |
| 307 | #define PGLUE_B_REG_TX_ERR_RD_DETAILS \ | |
| 308 | 0x2aa15cUL | |
| 309 | #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \ | |
| 310 | 0x2aa160UL | |
| 311 | #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \ | |
| 312 | 0x2aa164UL | |
| 313 | #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \ | |
| 314 | 0x2aa54cUL | |
| 315 | #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \ | |
| 316 | 0x2aa544UL | |
| 317 | #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \ | |
| 318 | 0x2aa548UL | |
| 319 | #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \ | |
| 320 | 0x2aae74UL | |
| 321 | #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \ | |
| 322 | 0x2aae78UL | |
| 323 | #define PGLUE_B_REG_VF_ILT_ERR_DETAILS \ | |
| 324 | 0x2aae7cUL | |
| 325 | #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \ | |
| 326 | 0x2aae80UL | |
| 327 | #define PGLUE_B_REG_LATCHED_ERRORS_CLR \ | |
| 328 | 0x2aa3bcUL | |
| fe56b9e6 YM |
329 | #define PRM_REG_DISABLE_PRM \ |
| 330 | 0x230000UL | |
| 331 | #define PRS_REG_SOFT_RST \ | |
| 332 | 0x1f0000UL | |
| 351a4ded YM |
333 | #define PRS_REG_MSG_INFO \ |
| 334 | 0x1f0a1cUL | |
| dbb799c3 YM |
335 | #define PRS_REG_ROCE_DEST_QP_MAX_PF \ |
| 336 | 0x1f0430UL | |
| 0a7fb11c YM |
337 | #define PRS_REG_USE_LIGHT_L2 \ |
| 338 | 0x1f096cUL | |
| fe56b9e6 YM |
339 | #define PSDM_REG_ENABLE_IN1 \ |
| 340 | 0xfa0004UL | |
| 341 | #define PSEM_REG_ENABLE_IN \ | |
| 342 | 0x1600004UL | |
| 343 | #define PSWRQ_REG_DBG_SELECT \ | |
| 344 | 0x280020UL | |
| 345 | #define PSWRQ2_REG_CDUT_P_SIZE \ | |
| 346 | 0x24000cUL | |
| dbb799c3 YM |
347 | #define PSWRQ2_REG_ILT_MEMORY \ |
| 348 | 0x260000UL | |
| fe56b9e6 YM |
349 | #define PSWHST_REG_DISCARD_INTERNAL_WRITES \ |
| 350 | 0x2a0040UL | |
| 351 | #define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \ | |
| 352 | 0x29e050UL | |
| b4149dc7 YM |
353 | #define PSWHST_REG_INCORRECT_ACCESS_VALID \ |
| 354 | 0x2a0070UL | |
| 355 | #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \ | |
| 356 | 0x2a0074UL | |
| 357 | #define PSWHST_REG_INCORRECT_ACCESS_DATA \ | |
| 358 | 0x2a0068UL | |
| 359 | #define PSWHST_REG_INCORRECT_ACCESS_LENGTH \ | |
| 360 | 0x2a006cUL | |
| fe56b9e6 YM |
361 | #define PSWRD_REG_DBG_SELECT \ |
| 362 | 0x29c040UL | |
| 363 | #define PSWRD2_REG_CONF11 \ | |
| 364 | 0x29d064UL | |
| 365 | #define PSWWR_REG_USDM_FULL_TH \ | |
| 366 | 0x29a040UL | |
| 367 | #define PSWWR2_REG_CDU_FULL_TH2 \ | |
| 368 | 0x29b040UL | |
| 369 | #define QM_REG_MAXPQSIZE_0 \ | |
| 370 | 0x2f0434UL | |
| 371 | #define RSS_REG_RSS_INIT_EN \ | |
| 372 | 0x238804UL | |
| 373 | #define RDIF_REG_STOP_ON_ERROR \ | |
| 374 | 0x300040UL | |
| be086e7c MY |
375 | #define RDIF_REG_DEBUG_ERROR_INFO \ |
| 376 | 0x300400UL | |
| 377 | #define RDIF_REG_DEBUG_ERROR_INFO_SIZE \ | |
| 378 | 64 | |
| fe56b9e6 YM |
379 | #define SRC_REG_SOFT_RST \ |
| 380 | 0x23874cUL | |
| 381 | #define TCFC_REG_ACTIVITY_COUNTER \ | |
| 382 | 0x2d8800UL | |
| 383 | #define TCM_REG_INIT \ | |
| 384 | 0x1180000UL | |
| 385 | #define TM_REG_PXP_READ_DATA_FIFO_INIT \ | |
| 386 | 0x2c0014UL | |
| 387 | #define TSDM_REG_ENABLE_IN1 \ | |
| 388 | 0xfb0004UL | |
| 389 | #define TSEM_REG_ENABLE_IN \ | |
| 390 | 0x1700004UL | |
| 391 | #define TDIF_REG_STOP_ON_ERROR \ | |
| 392 | 0x310040UL | |
| be086e7c MY |
393 | #define TDIF_REG_DEBUG_ERROR_INFO \ |
| 394 | 0x310400UL | |
| 395 | #define TDIF_REG_DEBUG_ERROR_INFO_SIZE \ | |
| 396 | 64 | |
| fe56b9e6 YM |
397 | #define UCM_REG_INIT \ |
| 398 | 0x1280000UL | |
| 399 | #define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \ | |
| 400 | 0x051004UL | |
| 401 | #define USDM_REG_ENABLE_IN1 \ | |
| 402 | 0xfd0004UL | |
| 403 | #define USEM_REG_ENABLE_IN \ | |
| 404 | 0x1900004UL | |
| 405 | #define XCM_REG_INIT \ | |
| 406 | 0x1000000UL | |
| 407 | #define XSDM_REG_ENABLE_IN1 \ | |
| 408 | 0xf80004UL | |
| 409 | #define XSEM_REG_ENABLE_IN \ | |
| 410 | 0x1400004UL | |
| 411 | #define YCM_REG_INIT \ | |
| 412 | 0x1080000UL | |
| 413 | #define YSDM_REG_ENABLE_IN1 \ | |
| 414 | 0xf90004UL | |
| 415 | #define YSEM_REG_ENABLE_IN \ | |
| 416 | 0x1500004UL | |
| 417 | #define XYLD_REG_SCBD_STRICT_PRIO \ | |
| 418 | 0x4c0000UL | |
| 419 | #define TMLD_REG_SCBD_STRICT_PRIO \ | |
| 420 | 0x4d0000UL | |
| 421 | #define MULD_REG_SCBD_STRICT_PRIO \ | |
| 422 | 0x4e0000UL | |
| 423 | #define YULD_REG_SCBD_STRICT_PRIO \ | |
| 424 | 0x4c8000UL | |
| 425 | #define MISC_REG_SHARED_MEM_ADDR \ | |
| 426 | 0x008c20UL | |
| 427 | #define DMAE_REG_GO_C0 \ | |
| 428 | 0x00c048UL | |
| 429 | #define DMAE_REG_GO_C1 \ | |
| 430 | 0x00c04cUL | |
| 431 | #define DMAE_REG_GO_C2 \ | |
| 432 | 0x00c050UL | |
| 433 | #define DMAE_REG_GO_C3 \ | |
| 434 | 0x00c054UL | |
| 435 | #define DMAE_REG_GO_C4 \ | |
| 436 | 0x00c058UL | |
| 437 | #define DMAE_REG_GO_C5 \ | |
| 438 | 0x00c05cUL | |
| 439 | #define DMAE_REG_GO_C6 \ | |
| 440 | 0x00c060UL | |
| 441 | #define DMAE_REG_GO_C7 \ | |
| 442 | 0x00c064UL | |
| 443 | #define DMAE_REG_GO_C8 \ | |
| 444 | 0x00c068UL | |
| 445 | #define DMAE_REG_GO_C9 \ | |
| 446 | 0x00c06cUL | |
| 447 | #define DMAE_REG_GO_C10 \ | |
| 448 | 0x00c070UL | |
| 449 | #define DMAE_REG_GO_C11 \ | |
| 450 | 0x00c074UL | |
| 451 | #define DMAE_REG_GO_C12 \ | |
| 452 | 0x00c078UL | |
| 453 | #define DMAE_REG_GO_C13 \ | |
| 454 | 0x00c07cUL | |
| 455 | #define DMAE_REG_GO_C14 \ | |
| 456 | 0x00c080UL | |
| 457 | #define DMAE_REG_GO_C15 \ | |
| 458 | 0x00c084UL | |
| 459 | #define DMAE_REG_GO_C16 \ | |
| 460 | 0x00c088UL | |
| 461 | #define DMAE_REG_GO_C17 \ | |
| 462 | 0x00c08cUL | |
| 463 | #define DMAE_REG_GO_C18 \ | |
| 464 | 0x00c090UL | |
| 465 | #define DMAE_REG_GO_C19 \ | |
| 466 | 0x00c094UL | |
| 467 | #define DMAE_REG_GO_C20 \ | |
| 468 | 0x00c098UL | |
| 469 | #define DMAE_REG_GO_C21 \ | |
| 470 | 0x00c09cUL | |
| 471 | #define DMAE_REG_GO_C22 \ | |
| 472 | 0x00c0a0UL | |
| 473 | #define DMAE_REG_GO_C23 \ | |
| 474 | 0x00c0a4UL | |
| 475 | #define DMAE_REG_GO_C24 \ | |
| 476 | 0x00c0a8UL | |
| 477 | #define DMAE_REG_GO_C25 \ | |
| 478 | 0x00c0acUL | |
| 479 | #define DMAE_REG_GO_C26 \ | |
| 480 | 0x00c0b0UL | |
| 481 | #define DMAE_REG_GO_C27 \ | |
| 482 | 0x00c0b4UL | |
| 483 | #define DMAE_REG_GO_C28 \ | |
| 484 | 0x00c0b8UL | |
| 485 | #define DMAE_REG_GO_C29 \ | |
| 486 | 0x00c0bcUL | |
| 487 | #define DMAE_REG_GO_C30 \ | |
| 488 | 0x00c0c0UL | |
| 489 | #define DMAE_REG_GO_C31 \ | |
| 490 | 0x00c0c4UL | |
| 491 | #define DMAE_REG_CMD_MEM \ | |
| 492 | 0x00c800UL | |
| 493 | #define QM_REG_MAXPQSIZETXSEL_0 \ | |
| 494 | 0x2f0440UL | |
| 495 | #define QM_REG_SDMCMDREADY \ | |
| 496 | 0x2f1e10UL | |
| 497 | #define QM_REG_SDMCMDADDR \ | |
| 498 | 0x2f1e04UL | |
| 499 | #define QM_REG_SDMCMDDATALSB \ | |
| 500 | 0x2f1e08UL | |
| 501 | #define QM_REG_SDMCMDDATAMSB \ | |
| 502 | 0x2f1e0cUL | |
| 503 | #define QM_REG_SDMCMDGO \ | |
| 504 | 0x2f1e14UL | |
| 505 | #define QM_REG_RLPFCRD \ | |
| 506 | 0x2f4d80UL | |
| 507 | #define QM_REG_RLPFINCVAL \ | |
| 508 | 0x2f4c80UL | |
| 509 | #define QM_REG_RLGLBLCRD \ | |
| 510 | 0x2f4400UL | |
| 511 | #define QM_REG_RLGLBLINCVAL \ | |
| 512 | 0x2f3400UL | |
| 513 | #define IGU_REG_ATTENTION_ENABLE \ | |
| 514 | 0x18083cUL | |
| 515 | #define IGU_REG_ATTN_MSG_ADDR_L \ | |
| 516 | 0x180820UL | |
| 517 | #define IGU_REG_ATTN_MSG_ADDR_H \ | |
| 518 | 0x180824UL | |
| 519 | #define MISC_REG_AEU_GENERAL_ATTN_0 \ | |
| 520 | 0x008400UL | |
| 521 | #define CAU_REG_SB_ADDR_MEMORY \ | |
| 522 | 0x1c8000UL | |
| 523 | #define CAU_REG_SB_VAR_MEMORY \ | |
| 524 | 0x1c6000UL | |
| 525 | #define CAU_REG_PI_MEMORY \ | |
| 526 | 0x1d0000UL | |
| 527 | #define IGU_REG_PF_CONFIGURATION \ | |
| 528 | 0x180800UL | |
| 0b55e27d YM |
529 | #define IGU_REG_VF_CONFIGURATION \ |
| 530 | 0x180804UL | |
| fe56b9e6 YM |
531 | #define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \ |
| 532 | 0x00849cUL | |
| 0d956e8a YM |
533 | #define MISC_REG_AEU_AFTER_INVERT_1_IGU \ |
| 534 | 0x0087b4UL | |
| fe56b9e6 YM |
535 | #define MISC_REG_AEU_MASK_ATTN_IGU \ |
| 536 | 0x008494UL | |
| 537 | #define IGU_REG_CLEANUP_STATUS_0 \ | |
| 538 | 0x180980UL | |
| 539 | #define IGU_REG_CLEANUP_STATUS_1 \ | |
| 540 | 0x180a00UL | |
| 541 | #define IGU_REG_CLEANUP_STATUS_2 \ | |
| 542 | 0x180a80UL | |
| 543 | #define IGU_REG_CLEANUP_STATUS_3 \ | |
| 544 | 0x180b00UL | |
| 545 | #define IGU_REG_CLEANUP_STATUS_4 \ | |
| 546 | 0x180b80UL | |
| 547 | #define IGU_REG_COMMAND_REG_32LSB_DATA \ | |
| 548 | 0x180840UL | |
| 549 | #define IGU_REG_COMMAND_REG_CTRL \ | |
| 550 | 0x180848UL | |
| 551 | #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \ | |
| 552 | 0x1 << 1) | |
| 553 | #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \ | |
| 554 | 0x1 << 0) | |
| 555 | #define IGU_REG_MAPPING_MEMORY \ | |
| 556 | 0x184000UL | |
| dacd88d6 YM |
557 | #define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \ |
| 558 | 0x180408UL | |
| b2b897eb YM |
559 | #define IGU_REG_WRITE_DONE_PENDING \ |
| 560 | 0x180900UL | |
| fe56b9e6 YM |
561 | #define MISCS_REG_GENERIC_POR_0 \ |
| 562 | 0x0096d4UL | |
| 563 | #define MCP_REG_NVM_CFG4 \ | |
| 564 | 0xe0642cUL | |
| 565 | #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \ | |
| 566 | 0x7 << 0) | |
| 567 | #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \ | |
| 568 | 0 | |
| b4149dc7 YM |
569 | #define MCP_REG_CPU_STATE \ |
| 570 | 0xe05004UL | |
| 76271809 | 571 | #define MCP_REG_CPU_STATE_SOFT_HALTED (0x1UL << 10) |
| b4149dc7 YM |
572 | #define MCP_REG_CPU_EVENT_MASK \ |
| 573 | 0xe05008UL | |
| b310974e | 574 | #define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL |
| c78df14e AE |
575 | #define PGLUE_B_REG_PF_BAR0_SIZE \ |
| 576 | 0x2aae60UL | |
| 577 | #define PGLUE_B_REG_PF_BAR1_SIZE \ | |
| 578 | 0x2aae64UL | |
| 1a850bfc | 579 | #define PGLUE_B_REG_VF_BAR1_SIZE 0x2aae68UL |
| 464f6645 MC |
580 | #define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL |
| 581 | #define PRS_REG_GRE_PROTOCOL 0x1f0734UL | |
| 582 | #define PRS_REG_VXLAN_PORT 0x1f0738UL | |
| 21dd79e8 | 583 | #define PRS_REG_OUTPUT_FORMAT_4_0_BB_K2 0x1f099cUL |
| 464f6645 MC |
584 | #define NIG_REG_ENC_TYPE_ENABLE 0x501058UL |
| 585 | ||
| 586 | #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0) | |
| 587 | #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0 | |
| 588 | #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1) | |
| 589 | #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1 | |
| 590 | #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2) | |
| 591 | #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2 | |
| 592 | ||
| 351a4ded | 593 | #define NIG_REG_VXLAN_CTRL 0x50105cUL |
| 464f6645 MC |
594 | #define PBF_REG_VXLAN_PORT 0xd80518UL |
| 595 | #define PBF_REG_NGE_PORT 0xd8051cUL | |
| 596 | #define PRS_REG_NGE_PORT 0x1f086cUL | |
| 597 | #define NIG_REG_NGE_PORT 0x508b38UL | |
| 598 | ||
| 21dd79e8 TT |
599 | #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL |
| 600 | #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL | |
| 601 | #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL | |
| 602 | #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5 0x10092cUL | |
| 603 | #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5 0x100930UL | |
| 464f6645 MC |
604 | |
| 605 | #define NIG_REG_NGE_IP_ENABLE 0x508b28UL | |
| 606 | #define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL | |
| 607 | #define NIG_REG_NGE_COMP_VER 0x508b30UL | |
| 608 | #define PBF_REG_NGE_COMP_VER 0xd80524UL | |
| 609 | #define PRS_REG_NGE_COMP_VER 0x1f0878UL | |
| 610 | ||
| a64b02d5 | 611 | #define QM_REG_WFQPFWEIGHT 0x2f4e80UL |
| bcd197c8 | 612 | #define QM_REG_WFQVPWEIGHT 0x2fa000UL |
| 4102426f | 613 | |
| 21dd79e8 | 614 | #define PGLCS_REG_DBG_SELECT_K2_E5 \ |
| c965db44 | 615 | 0x001d14UL |
| 21dd79e8 | 616 | #define PGLCS_REG_DBG_DWORD_ENABLE_K2_E5 \ |
| c965db44 | 617 | 0x001d18UL |
| 21dd79e8 | 618 | #define PGLCS_REG_DBG_SHIFT_K2_E5 \ |
| c965db44 | 619 | 0x001d1cUL |
| 21dd79e8 | 620 | #define PGLCS_REG_DBG_FORCE_VALID_K2_E5 \ |
| c965db44 | 621 | 0x001d20UL |
| 21dd79e8 | 622 | #define PGLCS_REG_DBG_FORCE_FRAME_K2_E5 \ |
| c965db44 TT |
623 | 0x001d24UL |
| 624 | #define MISC_REG_RESET_PL_PDA_VMAIN_1 \ | |
| 625 | 0x008070UL | |
| 626 | #define MISC_REG_RESET_PL_PDA_VMAIN_2 \ | |
| 627 | 0x008080UL | |
| 628 | #define MISC_REG_RESET_PL_PDA_VAUX \ | |
| 629 | 0x008090UL | |
| 630 | #define MISCS_REG_RESET_PL_UA \ | |
| 631 | 0x009050UL | |
| 632 | #define MISCS_REG_RESET_PL_HV \ | |
| 633 | 0x009060UL | |
| 21dd79e8 | 634 | #define MISCS_REG_RESET_PL_HV_2_K2_E5 \ |
| c965db44 TT |
635 | 0x009150UL |
| 636 | #define DMAE_REG_DBG_SELECT \ | |
| 637 | 0x00c510UL | |
| 638 | #define DMAE_REG_DBG_DWORD_ENABLE \ | |
| 639 | 0x00c514UL | |
| 640 | #define DMAE_REG_DBG_SHIFT \ | |
| 641 | 0x00c518UL | |
| 642 | #define DMAE_REG_DBG_FORCE_VALID \ | |
| 643 | 0x00c51cUL | |
| 644 | #define DMAE_REG_DBG_FORCE_FRAME \ | |
| 645 | 0x00c520UL | |
| 646 | #define NCSI_REG_DBG_SELECT \ | |
| 647 | 0x040474UL | |
| 648 | #define NCSI_REG_DBG_DWORD_ENABLE \ | |
| 649 | 0x040478UL | |
| 650 | #define NCSI_REG_DBG_SHIFT \ | |
| 651 | 0x04047cUL | |
| 652 | #define NCSI_REG_DBG_FORCE_VALID \ | |
| 653 | 0x040480UL | |
| 654 | #define NCSI_REG_DBG_FORCE_FRAME \ | |
| 655 | 0x040484UL | |
| 656 | #define GRC_REG_DBG_SELECT \ | |
| 657 | 0x0500a4UL | |
| 658 | #define GRC_REG_DBG_DWORD_ENABLE \ | |
| 659 | 0x0500a8UL | |
| 660 | #define GRC_REG_DBG_SHIFT \ | |
| 661 | 0x0500acUL | |
| 662 | #define GRC_REG_DBG_FORCE_VALID \ | |
| 663 | 0x0500b0UL | |
| 664 | #define GRC_REG_DBG_FORCE_FRAME \ | |
| 665 | 0x0500b4UL | |
| 21dd79e8 | 666 | #define UMAC_REG_DBG_SELECT_K2_E5 \ |
| c965db44 | 667 | 0x051094UL |
| 21dd79e8 | 668 | #define UMAC_REG_DBG_DWORD_ENABLE_K2_E5 \ |
| c965db44 | 669 | 0x051098UL |
| 21dd79e8 | 670 | #define UMAC_REG_DBG_SHIFT_K2_E5 \ |
| c965db44 | 671 | 0x05109cUL |
| 21dd79e8 | 672 | #define UMAC_REG_DBG_FORCE_VALID_K2_E5 \ |
| c965db44 | 673 | 0x0510a0UL |
| 21dd79e8 | 674 | #define UMAC_REG_DBG_FORCE_FRAME_K2_E5 \ |
| c965db44 TT |
675 | 0x0510a4UL |
| 676 | #define MCP2_REG_DBG_SELECT \ | |
| 677 | 0x052400UL | |
| 678 | #define MCP2_REG_DBG_DWORD_ENABLE \ | |
| 679 | 0x052404UL | |
| 680 | #define MCP2_REG_DBG_SHIFT \ | |
| 681 | 0x052408UL | |
| 682 | #define MCP2_REG_DBG_FORCE_VALID \ | |
| 683 | 0x052440UL | |
| 684 | #define MCP2_REG_DBG_FORCE_FRAME \ | |
| 685 | 0x052444UL | |
| 686 | #define PCIE_REG_DBG_SELECT \ | |
| 687 | 0x0547e8UL | |
| 688 | #define PCIE_REG_DBG_DWORD_ENABLE \ | |
| 689 | 0x0547ecUL | |
| 690 | #define PCIE_REG_DBG_SHIFT \ | |
| 691 | 0x0547f0UL | |
| 692 | #define PCIE_REG_DBG_FORCE_VALID \ | |
| 693 | 0x0547f4UL | |
| 694 | #define PCIE_REG_DBG_FORCE_FRAME \ | |
| 695 | 0x0547f8UL | |
| 696 | #define DORQ_REG_DBG_SELECT \ | |
| 697 | 0x100ad0UL | |
| 698 | #define DORQ_REG_DBG_DWORD_ENABLE \ | |
| 699 | 0x100ad4UL | |
| 700 | #define DORQ_REG_DBG_SHIFT \ | |
| 701 | 0x100ad8UL | |
| 702 | #define DORQ_REG_DBG_FORCE_VALID \ | |
| 703 | 0x100adcUL | |
| 704 | #define DORQ_REG_DBG_FORCE_FRAME \ | |
| 705 | 0x100ae0UL | |
| 706 | #define IGU_REG_DBG_SELECT \ | |
| 707 | 0x181578UL | |
| 708 | #define IGU_REG_DBG_DWORD_ENABLE \ | |
| 709 | 0x18157cUL | |
| 710 | #define IGU_REG_DBG_SHIFT \ | |
| 711 | 0x181580UL | |
| 712 | #define IGU_REG_DBG_FORCE_VALID \ | |
| 713 | 0x181584UL | |
| 714 | #define IGU_REG_DBG_FORCE_FRAME \ | |
| 715 | 0x181588UL | |
| 716 | #define CAU_REG_DBG_SELECT \ | |
| 717 | 0x1c0ea8UL | |
| 718 | #define CAU_REG_DBG_DWORD_ENABLE \ | |
| 719 | 0x1c0eacUL | |
| 720 | #define CAU_REG_DBG_SHIFT \ | |
| 721 | 0x1c0eb0UL | |
| 722 | #define CAU_REG_DBG_FORCE_VALID \ | |
| 723 | 0x1c0eb4UL | |
| 724 | #define CAU_REG_DBG_FORCE_FRAME \ | |
| 725 | 0x1c0eb8UL | |
| 726 | #define PRS_REG_DBG_SELECT \ | |
| 727 | 0x1f0b6cUL | |
| 728 | #define PRS_REG_DBG_DWORD_ENABLE \ | |
| 729 | 0x1f0b70UL | |
| 730 | #define PRS_REG_DBG_SHIFT \ | |
| 731 | 0x1f0b74UL | |
| 732 | #define PRS_REG_DBG_FORCE_VALID \ | |
| 733 | 0x1f0ba0UL | |
| 734 | #define PRS_REG_DBG_FORCE_FRAME \ | |
| 735 | 0x1f0ba4UL | |
| 21dd79e8 | 736 | #define CNIG_REG_DBG_SELECT_K2_E5 \ |
| c965db44 | 737 | 0x218254UL |
| 21dd79e8 | 738 | #define CNIG_REG_DBG_DWORD_ENABLE_K2_E5 \ |
| c965db44 | 739 | 0x218258UL |
| 21dd79e8 | 740 | #define CNIG_REG_DBG_SHIFT_K2_E5 \ |
| c965db44 | 741 | 0x21825cUL |
| 21dd79e8 | 742 | #define CNIG_REG_DBG_FORCE_VALID_K2_E5 \ |
| c965db44 | 743 | 0x218260UL |
| 21dd79e8 | 744 | #define CNIG_REG_DBG_FORCE_FRAME_K2_E5 \ |
| c965db44 TT |
745 | 0x218264UL |
| 746 | #define PRM_REG_DBG_SELECT \ | |
| 747 | 0x2306a8UL | |
| 748 | #define PRM_REG_DBG_DWORD_ENABLE \ | |
| 749 | 0x2306acUL | |
| 750 | #define PRM_REG_DBG_SHIFT \ | |
| 751 | 0x2306b0UL | |
| 752 | #define PRM_REG_DBG_FORCE_VALID \ | |
| 753 | 0x2306b4UL | |
| 754 | #define PRM_REG_DBG_FORCE_FRAME \ | |
| 755 | 0x2306b8UL | |
| 756 | #define SRC_REG_DBG_SELECT \ | |
| 757 | 0x238700UL | |
| 758 | #define SRC_REG_DBG_DWORD_ENABLE \ | |
| 759 | 0x238704UL | |
| 760 | #define SRC_REG_DBG_SHIFT \ | |
| 761 | 0x238708UL | |
| 762 | #define SRC_REG_DBG_FORCE_VALID \ | |
| 763 | 0x23870cUL | |
| 764 | #define SRC_REG_DBG_FORCE_FRAME \ | |
| 765 | 0x238710UL | |
| 766 | #define RSS_REG_DBG_SELECT \ | |
| 767 | 0x238c4cUL | |
| 768 | #define RSS_REG_DBG_DWORD_ENABLE \ | |
| 769 | 0x238c50UL | |
| 770 | #define RSS_REG_DBG_SHIFT \ | |
| 771 | 0x238c54UL | |
| 772 | #define RSS_REG_DBG_FORCE_VALID \ | |
| 773 | 0x238c58UL | |
| 774 | #define RSS_REG_DBG_FORCE_FRAME \ | |
| 775 | 0x238c5cUL | |
| 776 | #define RPB_REG_DBG_SELECT \ | |
| 777 | 0x23c728UL | |
| 778 | #define RPB_REG_DBG_DWORD_ENABLE \ | |
| 779 | 0x23c72cUL | |
| 780 | #define RPB_REG_DBG_SHIFT \ | |
| 781 | 0x23c730UL | |
| 782 | #define RPB_REG_DBG_FORCE_VALID \ | |
| 783 | 0x23c734UL | |
| 784 | #define RPB_REG_DBG_FORCE_FRAME \ | |
| 785 | 0x23c738UL | |
| 786 | #define PSWRQ2_REG_DBG_SELECT \ | |
| 787 | 0x240100UL | |
| 788 | #define PSWRQ2_REG_DBG_DWORD_ENABLE \ | |
| 789 | 0x240104UL | |
| 790 | #define PSWRQ2_REG_DBG_SHIFT \ | |
| 791 | 0x240108UL | |
| 792 | #define PSWRQ2_REG_DBG_FORCE_VALID \ | |
| 793 | 0x24010cUL | |
| 794 | #define PSWRQ2_REG_DBG_FORCE_FRAME \ | |
| 795 | 0x240110UL | |
| 796 | #define PSWRQ_REG_DBG_SELECT \ | |
| 797 | 0x280020UL | |
| 798 | #define PSWRQ_REG_DBG_DWORD_ENABLE \ | |
| 799 | 0x280024UL | |
| 800 | #define PSWRQ_REG_DBG_SHIFT \ | |
| 801 | 0x280028UL | |
| 802 | #define PSWRQ_REG_DBG_FORCE_VALID \ | |
| 803 | 0x28002cUL | |
| 804 | #define PSWRQ_REG_DBG_FORCE_FRAME \ | |
| 805 | 0x280030UL | |
| 806 | #define PSWWR_REG_DBG_SELECT \ | |
| 807 | 0x29a084UL | |
| 808 | #define PSWWR_REG_DBG_DWORD_ENABLE \ | |
| 809 | 0x29a088UL | |
| 810 | #define PSWWR_REG_DBG_SHIFT \ | |
| 811 | 0x29a08cUL | |
| 812 | #define PSWWR_REG_DBG_FORCE_VALID \ | |
| 813 | 0x29a090UL | |
| 814 | #define PSWWR_REG_DBG_FORCE_FRAME \ | |
| 815 | 0x29a094UL | |
| 816 | #define PSWRD_REG_DBG_SELECT \ | |
| 817 | 0x29c040UL | |
| 818 | #define PSWRD_REG_DBG_DWORD_ENABLE \ | |
| 819 | 0x29c044UL | |
| 820 | #define PSWRD_REG_DBG_SHIFT \ | |
| 821 | 0x29c048UL | |
| 822 | #define PSWRD_REG_DBG_FORCE_VALID \ | |
| 823 | 0x29c04cUL | |
| 824 | #define PSWRD_REG_DBG_FORCE_FRAME \ | |
| 825 | 0x29c050UL | |
| 826 | #define PSWRD2_REG_DBG_SELECT \ | |
| 827 | 0x29d400UL | |
| 828 | #define PSWRD2_REG_DBG_DWORD_ENABLE \ | |
| 829 | 0x29d404UL | |
| 830 | #define PSWRD2_REG_DBG_SHIFT \ | |
| 831 | 0x29d408UL | |
| 832 | #define PSWRD2_REG_DBG_FORCE_VALID \ | |
| 833 | 0x29d40cUL | |
| 834 | #define PSWRD2_REG_DBG_FORCE_FRAME \ | |
| 835 | 0x29d410UL | |
| 836 | #define PSWHST2_REG_DBG_SELECT \ | |
| 837 | 0x29e058UL | |
| 838 | #define PSWHST2_REG_DBG_DWORD_ENABLE \ | |
| 839 | 0x29e05cUL | |
| 840 | #define PSWHST2_REG_DBG_SHIFT \ | |
| 841 | 0x29e060UL | |
| 842 | #define PSWHST2_REG_DBG_FORCE_VALID \ | |
| 843 | 0x29e064UL | |
| 844 | #define PSWHST2_REG_DBG_FORCE_FRAME \ | |
| 845 | 0x29e068UL | |
| 846 | #define PSWHST_REG_DBG_SELECT \ | |
| 847 | 0x2a0100UL | |
| 848 | #define PSWHST_REG_DBG_DWORD_ENABLE \ | |
| 849 | 0x2a0104UL | |
| 850 | #define PSWHST_REG_DBG_SHIFT \ | |
| 851 | 0x2a0108UL | |
| 852 | #define PSWHST_REG_DBG_FORCE_VALID \ | |
| 853 | 0x2a010cUL | |
| 854 | #define PSWHST_REG_DBG_FORCE_FRAME \ | |
| 855 | 0x2a0110UL | |
| 856 | #define PGLUE_B_REG_DBG_SELECT \ | |
| 857 | 0x2a8400UL | |
| 858 | #define PGLUE_B_REG_DBG_DWORD_ENABLE \ | |
| 859 | 0x2a8404UL | |
| 860 | #define PGLUE_B_REG_DBG_SHIFT \ | |
| 861 | 0x2a8408UL | |
| 862 | #define PGLUE_B_REG_DBG_FORCE_VALID \ | |
| 863 | 0x2a840cUL | |
| 864 | #define PGLUE_B_REG_DBG_FORCE_FRAME \ | |
| 865 | 0x2a8410UL | |
| 866 | #define TM_REG_DBG_SELECT \ | |
| 867 | 0x2c07a8UL | |
| 868 | #define TM_REG_DBG_DWORD_ENABLE \ | |
| 869 | 0x2c07acUL | |
| 870 | #define TM_REG_DBG_SHIFT \ | |
| 871 | 0x2c07b0UL | |
| 872 | #define TM_REG_DBG_FORCE_VALID \ | |
| 873 | 0x2c07b4UL | |
| 874 | #define TM_REG_DBG_FORCE_FRAME \ | |
| 875 | 0x2c07b8UL | |
| 876 | #define TCFC_REG_DBG_SELECT \ | |
| 877 | 0x2d0500UL | |
| 878 | #define TCFC_REG_DBG_DWORD_ENABLE \ | |
| 879 | 0x2d0504UL | |
| 880 | #define TCFC_REG_DBG_SHIFT \ | |
| 881 | 0x2d0508UL | |
| 882 | #define TCFC_REG_DBG_FORCE_VALID \ | |
| 883 | 0x2d050cUL | |
| 884 | #define TCFC_REG_DBG_FORCE_FRAME \ | |
| 885 | 0x2d0510UL | |
| 886 | #define CCFC_REG_DBG_SELECT \ | |
| 887 | 0x2e0500UL | |
| 888 | #define CCFC_REG_DBG_DWORD_ENABLE \ | |
| 889 | 0x2e0504UL | |
| 890 | #define CCFC_REG_DBG_SHIFT \ | |
| 891 | 0x2e0508UL | |
| 892 | #define CCFC_REG_DBG_FORCE_VALID \ | |
| 893 | 0x2e050cUL | |
| 894 | #define CCFC_REG_DBG_FORCE_FRAME \ | |
| 895 | 0x2e0510UL | |
| 896 | #define QM_REG_DBG_SELECT \ | |
| 897 | 0x2f2e74UL | |
| 898 | #define QM_REG_DBG_DWORD_ENABLE \ | |
| 899 | 0x2f2e78UL | |
| 900 | #define QM_REG_DBG_SHIFT \ | |
| 901 | 0x2f2e7cUL | |
| 902 | #define QM_REG_DBG_FORCE_VALID \ | |
| 903 | 0x2f2e80UL | |
| 904 | #define QM_REG_DBG_FORCE_FRAME \ | |
| 905 | 0x2f2e84UL | |
| 906 | #define RDIF_REG_DBG_SELECT \ | |
| 907 | 0x300500UL | |
| 908 | #define RDIF_REG_DBG_DWORD_ENABLE \ | |
| 909 | 0x300504UL | |
| 910 | #define RDIF_REG_DBG_SHIFT \ | |
| 911 | 0x300508UL | |
| 912 | #define RDIF_REG_DBG_FORCE_VALID \ | |
| 913 | 0x30050cUL | |
| 914 | #define RDIF_REG_DBG_FORCE_FRAME \ | |
| 915 | 0x300510UL | |
| 916 | #define TDIF_REG_DBG_SELECT \ | |
| 917 | 0x310500UL | |
| 918 | #define TDIF_REG_DBG_DWORD_ENABLE \ | |
| 919 | 0x310504UL | |
| 920 | #define TDIF_REG_DBG_SHIFT \ | |
| 921 | 0x310508UL | |
| 922 | #define TDIF_REG_DBG_FORCE_VALID \ | |
| 923 | 0x31050cUL | |
| 924 | #define TDIF_REG_DBG_FORCE_FRAME \ | |
| 925 | 0x310510UL | |
| 926 | #define BRB_REG_DBG_SELECT \ | |
| 927 | 0x340ed0UL | |
| 928 | #define BRB_REG_DBG_DWORD_ENABLE \ | |
| 929 | 0x340ed4UL | |
| 930 | #define BRB_REG_DBG_SHIFT \ | |
| 931 | 0x340ed8UL | |
| 932 | #define BRB_REG_DBG_FORCE_VALID \ | |
| 933 | 0x340edcUL | |
| 934 | #define BRB_REG_DBG_FORCE_FRAME \ | |
| 935 | 0x340ee0UL | |
| 936 | #define XYLD_REG_DBG_SELECT \ | |
| 937 | 0x4c1600UL | |
| 938 | #define XYLD_REG_DBG_DWORD_ENABLE \ | |
| 939 | 0x4c1604UL | |
| 940 | #define XYLD_REG_DBG_SHIFT \ | |
| 941 | 0x4c1608UL | |
| 942 | #define XYLD_REG_DBG_FORCE_VALID \ | |
| 943 | 0x4c160cUL | |
| 944 | #define XYLD_REG_DBG_FORCE_FRAME \ | |
| 945 | 0x4c1610UL | |
| 7b6859fb | 946 | #define YULD_REG_DBG_SELECT_BB_K2 \ |
| c965db44 | 947 | 0x4c9600UL |
| 7b6859fb | 948 | #define YULD_REG_DBG_DWORD_ENABLE_BB_K2 \ |
| c965db44 | 949 | 0x4c9604UL |
| 7b6859fb | 950 | #define YULD_REG_DBG_SHIFT_BB_K2 \ |
| c965db44 | 951 | 0x4c9608UL |
| 7b6859fb | 952 | #define YULD_REG_DBG_FORCE_VALID_BB_K2 \ |
| c965db44 | 953 | 0x4c960cUL |
| 7b6859fb | 954 | #define YULD_REG_DBG_FORCE_FRAME_BB_K2 \ |
| c965db44 TT |
955 | 0x4c9610UL |
| 956 | #define TMLD_REG_DBG_SELECT \ | |
| 957 | 0x4d1600UL | |
| 958 | #define TMLD_REG_DBG_DWORD_ENABLE \ | |
| 959 | 0x4d1604UL | |
| 960 | #define TMLD_REG_DBG_SHIFT \ | |
| 961 | 0x4d1608UL | |
| 962 | #define TMLD_REG_DBG_FORCE_VALID \ | |
| 963 | 0x4d160cUL | |
| 964 | #define TMLD_REG_DBG_FORCE_FRAME \ | |
| 965 | 0x4d1610UL | |
| 966 | #define MULD_REG_DBG_SELECT \ | |
| 967 | 0x4e1600UL | |
| 968 | #define MULD_REG_DBG_DWORD_ENABLE \ | |
| 969 | 0x4e1604UL | |
| 970 | #define MULD_REG_DBG_SHIFT \ | |
| 971 | 0x4e1608UL | |
| 972 | #define MULD_REG_DBG_FORCE_VALID \ | |
| 973 | 0x4e160cUL | |
| 974 | #define MULD_REG_DBG_FORCE_FRAME \ | |
| 975 | 0x4e1610UL | |
| 976 | #define NIG_REG_DBG_SELECT \ | |
| 977 | 0x502140UL | |
| 978 | #define NIG_REG_DBG_DWORD_ENABLE \ | |
| 979 | 0x502144UL | |
| 980 | #define NIG_REG_DBG_SHIFT \ | |
| 981 | 0x502148UL | |
| 982 | #define NIG_REG_DBG_FORCE_VALID \ | |
| 983 | 0x50214cUL | |
| 984 | #define NIG_REG_DBG_FORCE_FRAME \ | |
| 985 | 0x502150UL | |
| 986 | #define BMB_REG_DBG_SELECT \ | |
| 987 | 0x540a7cUL | |
| 988 | #define BMB_REG_DBG_DWORD_ENABLE \ | |
| 989 | 0x540a80UL | |
| 990 | #define BMB_REG_DBG_SHIFT \ | |
| 991 | 0x540a84UL | |
| 992 | #define BMB_REG_DBG_FORCE_VALID \ | |
| 993 | 0x540a88UL | |
| 994 | #define BMB_REG_DBG_FORCE_FRAME \ | |
| 995 | 0x540a8cUL | |
| 996 | #define PTU_REG_DBG_SELECT \ | |
| 997 | 0x560100UL | |
| 998 | #define PTU_REG_DBG_DWORD_ENABLE \ | |
| 999 | 0x560104UL | |
| 1000 | #define PTU_REG_DBG_SHIFT \ | |
| 1001 | 0x560108UL | |
| 1002 | #define PTU_REG_DBG_FORCE_VALID \ | |
| 1003 | 0x56010cUL | |
| 1004 | #define PTU_REG_DBG_FORCE_FRAME \ | |
| 1005 | 0x560110UL | |
| 1006 | #define CDU_REG_DBG_SELECT \ | |
| 1007 | 0x580704UL | |
| 1008 | #define CDU_REG_DBG_DWORD_ENABLE \ | |
| 1009 | 0x580708UL | |
| 1010 | #define CDU_REG_DBG_SHIFT \ | |
| 1011 | 0x58070cUL | |
| 1012 | #define CDU_REG_DBG_FORCE_VALID \ | |
| 1013 | 0x580710UL | |
| 1014 | #define CDU_REG_DBG_FORCE_FRAME \ | |
| 1015 | 0x580714UL | |
| 21dd79e8 | 1016 | #define WOL_REG_DBG_SELECT_K2_E5 \ |
| c965db44 | 1017 | 0x600140UL |
| 21dd79e8 | 1018 | #define WOL_REG_DBG_DWORD_ENABLE_K2_E5 \ |
| c965db44 | 1019 | 0x600144UL |
| 21dd79e8 | 1020 | #define WOL_REG_DBG_SHIFT_K2_E5 \ |
| c965db44 | 1021 | 0x600148UL |
| 21dd79e8 | 1022 | #define WOL_REG_DBG_FORCE_VALID_K2_E5 \ |
| c965db44 | 1023 | 0x60014cUL |
| 21dd79e8 | 1024 | #define WOL_REG_DBG_FORCE_FRAME_K2_E5 \ |
| c965db44 | 1025 | 0x600150UL |
| 21dd79e8 | 1026 | #define BMBN_REG_DBG_SELECT_K2_E5 \ |
| c965db44 | 1027 | 0x610140UL |
| 21dd79e8 | 1028 | #define BMBN_REG_DBG_DWORD_ENABLE_K2_E5 \ |
| c965db44 | 1029 | 0x610144UL |
| 21dd79e8 | 1030 | #define BMBN_REG_DBG_SHIFT_K2_E5 \ |
| c965db44 | 1031 | 0x610148UL |
| 21dd79e8 | 1032 | #define BMBN_REG_DBG_FORCE_VALID_K2_E5 \ |
| c965db44 | 1033 | 0x61014cUL |
| 21dd79e8 | 1034 | #define BMBN_REG_DBG_FORCE_FRAME_K2_E5 \ |
| c965db44 | 1035 | 0x610150UL |
| 21dd79e8 | 1036 | #define NWM_REG_DBG_SELECT_K2_E5 \ |
| c965db44 | 1037 | 0x8000ecUL |
| 21dd79e8 | 1038 | #define NWM_REG_DBG_DWORD_ENABLE_K2_E5 \ |
| c965db44 | 1039 | 0x8000f0UL |
| 21dd79e8 | 1040 | #define NWM_REG_DBG_SHIFT_K2_E5 \ |
| c965db44 | 1041 | 0x8000f4UL |
| 21dd79e8 | 1042 | #define NWM_REG_DBG_FORCE_VALID_K2_E5 \ |
| c965db44 | 1043 | 0x8000f8UL |
| 21dd79e8 | 1044 | #define NWM_REG_DBG_FORCE_FRAME_K2_E5 \ |
| c965db44 TT |
1045 | 0x8000fcUL |
| 1046 | #define PBF_REG_DBG_SELECT \ | |
| 1047 | 0xd80060UL | |
| 1048 | #define PBF_REG_DBG_DWORD_ENABLE \ | |
| 1049 | 0xd80064UL | |
| 1050 | #define PBF_REG_DBG_SHIFT \ | |
| 1051 | 0xd80068UL | |
| 1052 | #define PBF_REG_DBG_FORCE_VALID \ | |
| 1053 | 0xd8006cUL | |
| 1054 | #define PBF_REG_DBG_FORCE_FRAME \ | |
| 1055 | 0xd80070UL | |
| 1056 | #define PBF_PB1_REG_DBG_SELECT \ | |
| 1057 | 0xda0728UL | |
| 1058 | #define PBF_PB1_REG_DBG_DWORD_ENABLE \ | |
| 1059 | 0xda072cUL | |
| 1060 | #define PBF_PB1_REG_DBG_SHIFT \ | |
| 1061 | 0xda0730UL | |
| 1062 | #define PBF_PB1_REG_DBG_FORCE_VALID \ | |
| 1063 | 0xda0734UL | |
| 1064 | #define PBF_PB1_REG_DBG_FORCE_FRAME \ | |
| 1065 | 0xda0738UL | |
| 1066 | #define PBF_PB2_REG_DBG_SELECT \ | |
| 1067 | 0xda4728UL | |
| 1068 | #define PBF_PB2_REG_DBG_DWORD_ENABLE \ | |
| 1069 | 0xda472cUL | |
| 1070 | #define PBF_PB2_REG_DBG_SHIFT \ | |
| 1071 | 0xda4730UL | |
| 1072 | #define PBF_PB2_REG_DBG_FORCE_VALID \ | |
| 1073 | 0xda4734UL | |
| 1074 | #define PBF_PB2_REG_DBG_FORCE_FRAME \ | |
| 1075 | 0xda4738UL | |
| 1076 | #define BTB_REG_DBG_SELECT \ | |
| 1077 | 0xdb08c8UL | |
| 1078 | #define BTB_REG_DBG_DWORD_ENABLE \ | |
| 1079 | 0xdb08ccUL | |
| 1080 | #define BTB_REG_DBG_SHIFT \ | |
| 1081 | 0xdb08d0UL | |
| 1082 | #define BTB_REG_DBG_FORCE_VALID \ | |
| 1083 | 0xdb08d4UL | |
| 1084 | #define BTB_REG_DBG_FORCE_FRAME \ | |
| 1085 | 0xdb08d8UL | |
| 1086 | #define XSDM_REG_DBG_SELECT \ | |
| 1087 | 0xf80e28UL | |
| 1088 | #define XSDM_REG_DBG_DWORD_ENABLE \ | |
| 1089 | 0xf80e2cUL | |
| 1090 | #define XSDM_REG_DBG_SHIFT \ | |
| 1091 | 0xf80e30UL | |
| 1092 | #define XSDM_REG_DBG_FORCE_VALID \ | |
| 1093 | 0xf80e34UL | |
| 1094 | #define XSDM_REG_DBG_FORCE_FRAME \ | |
| 1095 | 0xf80e38UL | |
| 1096 | #define YSDM_REG_DBG_SELECT \ | |
| 1097 | 0xf90e28UL | |
| 1098 | #define YSDM_REG_DBG_DWORD_ENABLE \ | |
| 1099 | 0xf90e2cUL | |
| 1100 | #define YSDM_REG_DBG_SHIFT \ | |
| 1101 | 0xf90e30UL | |
| 1102 | #define YSDM_REG_DBG_FORCE_VALID \ | |
| 1103 | 0xf90e34UL | |
| 1104 | #define YSDM_REG_DBG_FORCE_FRAME \ | |
| 1105 | 0xf90e38UL | |
| 1106 | #define PSDM_REG_DBG_SELECT \ | |
| 1107 | 0xfa0e28UL | |
| 1108 | #define PSDM_REG_DBG_DWORD_ENABLE \ | |
| 1109 | 0xfa0e2cUL | |
| 1110 | #define PSDM_REG_DBG_SHIFT \ | |
| 1111 | 0xfa0e30UL | |
| 1112 | #define PSDM_REG_DBG_FORCE_VALID \ | |
| 1113 | 0xfa0e34UL | |
| 1114 | #define PSDM_REG_DBG_FORCE_FRAME \ | |
| 1115 | 0xfa0e38UL | |
| 1116 | #define TSDM_REG_DBG_SELECT \ | |
| 1117 | 0xfb0e28UL | |
| 1118 | #define TSDM_REG_DBG_DWORD_ENABLE \ | |
| 1119 | 0xfb0e2cUL | |
| 1120 | #define TSDM_REG_DBG_SHIFT \ | |
| 1121 | 0xfb0e30UL | |
| 1122 | #define TSDM_REG_DBG_FORCE_VALID \ | |
| 1123 | 0xfb0e34UL | |
| 1124 | #define TSDM_REG_DBG_FORCE_FRAME \ | |
| 1125 | 0xfb0e38UL | |
| 1126 | #define MSDM_REG_DBG_SELECT \ | |
| 1127 | 0xfc0e28UL | |
| 1128 | #define MSDM_REG_DBG_DWORD_ENABLE \ | |
| 1129 | 0xfc0e2cUL | |
| 1130 | #define MSDM_REG_DBG_SHIFT \ | |
| 1131 | 0xfc0e30UL | |
| 1132 | #define MSDM_REG_DBG_FORCE_VALID \ | |
| 1133 | 0xfc0e34UL | |
| 1134 | #define MSDM_REG_DBG_FORCE_FRAME \ | |
| 1135 | 0xfc0e38UL | |
| 1136 | #define USDM_REG_DBG_SELECT \ | |
| 1137 | 0xfd0e28UL | |
| 1138 | #define USDM_REG_DBG_DWORD_ENABLE \ | |
| 1139 | 0xfd0e2cUL | |
| 1140 | #define USDM_REG_DBG_SHIFT \ | |
| 1141 | 0xfd0e30UL | |
| 1142 | #define USDM_REG_DBG_FORCE_VALID \ | |
| 1143 | 0xfd0e34UL | |
| 1144 | #define USDM_REG_DBG_FORCE_FRAME \ | |
| 1145 | 0xfd0e38UL | |
| 1146 | #define XCM_REG_DBG_SELECT \ | |
| 1147 | 0x1000040UL | |
| 1148 | #define XCM_REG_DBG_DWORD_ENABLE \ | |
| 1149 | 0x1000044UL | |
| 1150 | #define XCM_REG_DBG_SHIFT \ | |
| 1151 | 0x1000048UL | |
| 1152 | #define XCM_REG_DBG_FORCE_VALID \ | |
| 1153 | 0x100004cUL | |
| 1154 | #define XCM_REG_DBG_FORCE_FRAME \ | |
| 1155 | 0x1000050UL | |
| 1156 | #define YCM_REG_DBG_SELECT \ | |
| 1157 | 0x1080040UL | |
| 1158 | #define YCM_REG_DBG_DWORD_ENABLE \ | |
| 1159 | 0x1080044UL | |
| 1160 | #define YCM_REG_DBG_SHIFT \ | |
| 1161 | 0x1080048UL | |
| 1162 | #define YCM_REG_DBG_FORCE_VALID \ | |
| 1163 | 0x108004cUL | |
| 1164 | #define YCM_REG_DBG_FORCE_FRAME \ | |
| 1165 | 0x1080050UL | |
| 1166 | #define PCM_REG_DBG_SELECT \ | |
| 1167 | 0x1100040UL | |
| 1168 | #define PCM_REG_DBG_DWORD_ENABLE \ | |
| 1169 | 0x1100044UL | |
| 1170 | #define PCM_REG_DBG_SHIFT \ | |
| 1171 | 0x1100048UL | |
| 1172 | #define PCM_REG_DBG_FORCE_VALID \ | |
| 1173 | 0x110004cUL | |
| 1174 | #define PCM_REG_DBG_FORCE_FRAME \ | |
| 1175 | 0x1100050UL | |
| 1176 | #define TCM_REG_DBG_SELECT \ | |
| 1177 | 0x1180040UL | |
| 1178 | #define TCM_REG_DBG_DWORD_ENABLE \ | |
| 1179 | 0x1180044UL | |
| 1180 | #define TCM_REG_DBG_SHIFT \ | |
| 1181 | 0x1180048UL | |
| 1182 | #define TCM_REG_DBG_FORCE_VALID \ | |
| 1183 | 0x118004cUL | |
| 1184 | #define TCM_REG_DBG_FORCE_FRAME \ | |
| 1185 | 0x1180050UL | |
| 1186 | #define MCM_REG_DBG_SELECT \ | |
| 1187 | 0x1200040UL | |
| 1188 | #define MCM_REG_DBG_DWORD_ENABLE \ | |
| 1189 | 0x1200044UL | |
| 1190 | #define MCM_REG_DBG_SHIFT \ | |
| 1191 | 0x1200048UL | |
| 1192 | #define MCM_REG_DBG_FORCE_VALID \ | |
| 1193 | 0x120004cUL | |
| 1194 | #define MCM_REG_DBG_FORCE_FRAME \ | |
| 1195 | 0x1200050UL | |
| 1196 | #define UCM_REG_DBG_SELECT \ | |
| 1197 | 0x1280050UL | |
| 1198 | #define UCM_REG_DBG_DWORD_ENABLE \ | |
| 1199 | 0x1280054UL | |
| 1200 | #define UCM_REG_DBG_SHIFT \ | |
| 1201 | 0x1280058UL | |
| 1202 | #define UCM_REG_DBG_FORCE_VALID \ | |
| 1203 | 0x128005cUL | |
| 1204 | #define UCM_REG_DBG_FORCE_FRAME \ | |
| 1205 | 0x1280060UL | |
| 1206 | #define XSEM_REG_DBG_SELECT \ | |
| 1207 | 0x1401528UL | |
| 1208 | #define XSEM_REG_DBG_DWORD_ENABLE \ | |
| 1209 | 0x140152cUL | |
| 1210 | #define XSEM_REG_DBG_SHIFT \ | |
| 1211 | 0x1401530UL | |
| 1212 | #define XSEM_REG_DBG_FORCE_VALID \ | |
| 1213 | 0x1401534UL | |
| 1214 | #define XSEM_REG_DBG_FORCE_FRAME \ | |
| 1215 | 0x1401538UL | |
| 1216 | #define YSEM_REG_DBG_SELECT \ | |
| 1217 | 0x1501528UL | |
| 1218 | #define YSEM_REG_DBG_DWORD_ENABLE \ | |
| 1219 | 0x150152cUL | |
| 1220 | #define YSEM_REG_DBG_SHIFT \ | |
| 1221 | 0x1501530UL | |
| 1222 | #define YSEM_REG_DBG_FORCE_VALID \ | |
| 1223 | 0x1501534UL | |
| 1224 | #define YSEM_REG_DBG_FORCE_FRAME \ | |
| 1225 | 0x1501538UL | |
| 1226 | #define PSEM_REG_DBG_SELECT \ | |
| 1227 | 0x1601528UL | |
| 1228 | #define PSEM_REG_DBG_DWORD_ENABLE \ | |
| 1229 | 0x160152cUL | |
| 1230 | #define PSEM_REG_DBG_SHIFT \ | |
| 1231 | 0x1601530UL | |
| 1232 | #define PSEM_REG_DBG_FORCE_VALID \ | |
| 1233 | 0x1601534UL | |
| 1234 | #define PSEM_REG_DBG_FORCE_FRAME \ | |
| 1235 | 0x1601538UL | |
| 1236 | #define TSEM_REG_DBG_SELECT \ | |
| 1237 | 0x1701528UL | |
| 1238 | #define TSEM_REG_DBG_DWORD_ENABLE \ | |
| 1239 | 0x170152cUL | |
| 1240 | #define TSEM_REG_DBG_SHIFT \ | |
| 1241 | 0x1701530UL | |
| 1242 | #define TSEM_REG_DBG_FORCE_VALID \ | |
| 1243 | 0x1701534UL | |
| 1244 | #define TSEM_REG_DBG_FORCE_FRAME \ | |
| 1245 | 0x1701538UL | |
| 1246 | #define MSEM_REG_DBG_SELECT \ | |
| 1247 | 0x1801528UL | |
| 1248 | #define MSEM_REG_DBG_DWORD_ENABLE \ | |
| 1249 | 0x180152cUL | |
| 1250 | #define MSEM_REG_DBG_SHIFT \ | |
| 1251 | 0x1801530UL | |
| 1252 | #define MSEM_REG_DBG_FORCE_VALID \ | |
| 1253 | 0x1801534UL | |
| 1254 | #define MSEM_REG_DBG_FORCE_FRAME \ | |
| 1255 | 0x1801538UL | |
| 1256 | #define USEM_REG_DBG_SELECT \ | |
| 1257 | 0x1901528UL | |
| 1258 | #define USEM_REG_DBG_DWORD_ENABLE \ | |
| 1259 | 0x190152cUL | |
| 1260 | #define USEM_REG_DBG_SHIFT \ | |
| 1261 | 0x1901530UL | |
| 1262 | #define USEM_REG_DBG_FORCE_VALID \ | |
| 1263 | 0x1901534UL | |
| 1264 | #define USEM_REG_DBG_FORCE_FRAME \ | |
| 1265 | 0x1901538UL | |
| 21dd79e8 | 1266 | #define NWS_REG_DBG_SELECT_K2_E5 \ |
| be086e7c | 1267 | 0x700128UL |
| 21dd79e8 | 1268 | #define NWS_REG_DBG_DWORD_ENABLE_K2_E5 \ |
| be086e7c | 1269 | 0x70012cUL |
| 21dd79e8 | 1270 | #define NWS_REG_DBG_SHIFT_K2_E5 \ |
| be086e7c | 1271 | 0x700130UL |
| 21dd79e8 | 1272 | #define NWS_REG_DBG_FORCE_VALID_K2_E5 \ |
| be086e7c | 1273 | 0x700134UL |
| 21dd79e8 | 1274 | #define NWS_REG_DBG_FORCE_FRAME_K2_E5 \ |
| be086e7c | 1275 | 0x700138UL |
| 21dd79e8 | 1276 | #define MS_REG_DBG_SELECT_K2_E5 \ |
| be086e7c | 1277 | 0x6a0228UL |
| 21dd79e8 | 1278 | #define MS_REG_DBG_DWORD_ENABLE_K2_E5 \ |
| be086e7c | 1279 | 0x6a022cUL |
| 21dd79e8 | 1280 | #define MS_REG_DBG_SHIFT_K2_E5 \ |
| be086e7c | 1281 | 0x6a0230UL |
| 21dd79e8 | 1282 | #define MS_REG_DBG_FORCE_VALID_K2_E5 \ |
| be086e7c | 1283 | 0x6a0234UL |
| 21dd79e8 | 1284 | #define MS_REG_DBG_FORCE_FRAME_K2_E5 \ |
| be086e7c | 1285 | 0x6a0238UL |
| 21dd79e8 | 1286 | #define PCIE_REG_DBG_COMMON_SELECT_K2_E5 \ |
| c965db44 | 1287 | 0x054398UL |
| 21dd79e8 | 1288 | #define PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5 \ |
| c965db44 | 1289 | 0x05439cUL |
| 21dd79e8 | 1290 | #define PCIE_REG_DBG_COMMON_SHIFT_K2_E5 \ |
| c965db44 | 1291 | 0x0543a0UL |
| 21dd79e8 | 1292 | #define PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5 \ |
| c965db44 | 1293 | 0x0543a4UL |
| 21dd79e8 | 1294 | #define PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5 \ |
| c965db44 | 1295 | 0x0543a8UL |
| da090917 TT |
1296 | #define PTLD_REG_DBG_SELECT_E5 \ |
| 1297 | 0x5a1600UL | |
| 1298 | #define PTLD_REG_DBG_DWORD_ENABLE_E5 \ | |
| 1299 | 0x5a1604UL | |
| 1300 | #define PTLD_REG_DBG_SHIFT_E5 \ | |
| 1301 | 0x5a1608UL | |
| 1302 | #define PTLD_REG_DBG_FORCE_VALID_E5 \ | |
| 1303 | 0x5a160cUL | |
| 1304 | #define PTLD_REG_DBG_FORCE_FRAME_E5 \ | |
| 1305 | 0x5a1610UL | |
| 1306 | #define YPLD_REG_DBG_SELECT_E5 \ | |
| 1307 | 0x5c1600UL | |
| 1308 | #define YPLD_REG_DBG_DWORD_ENABLE_E5 \ | |
| 1309 | 0x5c1604UL | |
| 1310 | #define YPLD_REG_DBG_SHIFT_E5 \ | |
| 1311 | 0x5c1608UL | |
| 1312 | #define YPLD_REG_DBG_FORCE_VALID_E5 \ | |
| 1313 | 0x5c160cUL | |
| 1314 | #define YPLD_REG_DBG_FORCE_FRAME_E5 \ | |
| 1315 | 0x5c1610UL | |
| 1316 | #define RGSRC_REG_DBG_SELECT_E5 \ | |
| 1317 | 0x320040UL | |
| 1318 | #define RGSRC_REG_DBG_DWORD_ENABLE_E5 \ | |
| 1319 | 0x320044UL | |
| 1320 | #define RGSRC_REG_DBG_SHIFT_E5 \ | |
| 1321 | 0x320048UL | |
| 1322 | #define RGSRC_REG_DBG_FORCE_VALID_E5 \ | |
| 1323 | 0x32004cUL | |
| 1324 | #define RGSRC_REG_DBG_FORCE_FRAME_E5 \ | |
| 1325 | 0x320050UL | |
| 1326 | #define TGSRC_REG_DBG_SELECT_E5 \ | |
| 1327 | 0x322040UL | |
| 1328 | #define TGSRC_REG_DBG_DWORD_ENABLE_E5 \ | |
| 1329 | 0x322044UL | |
| 1330 | #define TGSRC_REG_DBG_SHIFT_E5 \ | |
| 1331 | 0x322048UL | |
| 1332 | #define TGSRC_REG_DBG_FORCE_VALID_E5 \ | |
| 1333 | 0x32204cUL | |
| 1334 | #define TGSRC_REG_DBG_FORCE_FRAME_E5 \ | |
| 1335 | 0x322050UL | |
| c965db44 TT |
1336 | #define MISC_REG_RESET_PL_UA \ |
| 1337 | 0x008050UL | |
| 1338 | #define MISC_REG_RESET_PL_HV \ | |
| 1339 | 0x008060UL | |
| 1340 | #define XCM_REG_CTX_RBC_ACCS \ | |
| 1341 | 0x1001800UL | |
| 1342 | #define XCM_REG_AGG_CON_CTX \ | |
| 1343 | 0x1001804UL | |
| 1344 | #define XCM_REG_SM_CON_CTX \ | |
| 1345 | 0x1001808UL | |
| 1346 | #define YCM_REG_CTX_RBC_ACCS \ | |
| 1347 | 0x1081800UL | |
| 1348 | #define YCM_REG_AGG_CON_CTX \ | |
| 1349 | 0x1081804UL | |
| 1350 | #define YCM_REG_AGG_TASK_CTX \ | |
| 1351 | 0x1081808UL | |
| 1352 | #define YCM_REG_SM_CON_CTX \ | |
| 1353 | 0x108180cUL | |
| 1354 | #define YCM_REG_SM_TASK_CTX \ | |
| 1355 | 0x1081810UL | |
| 1356 | #define PCM_REG_CTX_RBC_ACCS \ | |
| 1357 | 0x1101440UL | |
| 1358 | #define PCM_REG_SM_CON_CTX \ | |
| 1359 | 0x1101444UL | |
| 1360 | #define TCM_REG_CTX_RBC_ACCS \ | |
| 1361 | 0x11814c0UL | |
| 1362 | #define TCM_REG_AGG_CON_CTX \ | |
| 1363 | 0x11814c4UL | |
| 1364 | #define TCM_REG_AGG_TASK_CTX \ | |
| 1365 | 0x11814c8UL | |
| 1366 | #define TCM_REG_SM_CON_CTX \ | |
| 1367 | 0x11814ccUL | |
| 1368 | #define TCM_REG_SM_TASK_CTX \ | |
| 1369 | 0x11814d0UL | |
| 1370 | #define MCM_REG_CTX_RBC_ACCS \ | |
| 1371 | 0x1201800UL | |
| 1372 | #define MCM_REG_AGG_CON_CTX \ | |
| 1373 | 0x1201804UL | |
| 1374 | #define MCM_REG_AGG_TASK_CTX \ | |
| 1375 | 0x1201808UL | |
| 1376 | #define MCM_REG_SM_CON_CTX \ | |
| 1377 | 0x120180cUL | |
| 1378 | #define MCM_REG_SM_TASK_CTX \ | |
| 1379 | 0x1201810UL | |
| 1380 | #define UCM_REG_CTX_RBC_ACCS \ | |
| 1381 | 0x1281700UL | |
| 1382 | #define UCM_REG_AGG_CON_CTX \ | |
| 1383 | 0x1281704UL | |
| 1384 | #define UCM_REG_AGG_TASK_CTX \ | |
| 1385 | 0x1281708UL | |
| 1386 | #define UCM_REG_SM_CON_CTX \ | |
| 1387 | 0x128170cUL | |
| 1388 | #define UCM_REG_SM_TASK_CTX \ | |
| 1389 | 0x1281710UL | |
| 7b6859fb | 1390 | #define XSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ |
| c965db44 TT |
1391 | 0x1401140UL |
| 1392 | #define XSEM_REG_SYNC_DBG_EMPTY \ | |
| 1393 | 0x1401160UL | |
| 7b6859fb | 1394 | #define XSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ |
| c965db44 | 1395 | 0x1401400UL |
| 7b6859fb | 1396 | #define XSEM_REG_SLOW_DBG_MODE_BB_K2 \ |
| c965db44 | 1397 | 0x1401404UL |
| 7b6859fb | 1398 | #define XSEM_REG_DBG_FRAME_MODE_BB_K2 \ |
| c965db44 | 1399 | 0x1401408UL |
| 7b6859fb | 1400 | #define XSEM_REG_DBG_MODE1_CFG_BB_K2 \ |
| c965db44 TT |
1401 | 0x1401420UL |
| 1402 | #define XSEM_REG_FAST_MEMORY \ | |
| 1403 | 0x1440000UL | |
| 1404 | #define YSEM_REG_SYNC_DBG_EMPTY \ | |
| 1405 | 0x1501160UL | |
| 7b6859fb | 1406 | #define YSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ |
| c965db44 | 1407 | 0x1501400UL |
| 7b6859fb | 1408 | #define YSEM_REG_SLOW_DBG_MODE_BB_K2 \ |
| c965db44 | 1409 | 0x1501404UL |
| 7b6859fb | 1410 | #define YSEM_REG_DBG_FRAME_MODE_BB_K2 \ |
| c965db44 | 1411 | 0x1501408UL |
| 7b6859fb | 1412 | #define YSEM_REG_DBG_MODE1_CFG_BB_K2 \ |
| c965db44 TT |
1413 | 0x1501420UL |
| 1414 | #define YSEM_REG_FAST_MEMORY \ | |
| 1415 | 0x1540000UL | |
| 7b6859fb | 1416 | #define PSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ |
| c965db44 TT |
1417 | 0x1601140UL |
| 1418 | #define PSEM_REG_SYNC_DBG_EMPTY \ | |
| 1419 | 0x1601160UL | |
| 7b6859fb | 1420 | #define PSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ |
| c965db44 | 1421 | 0x1601400UL |
| 7b6859fb | 1422 | #define PSEM_REG_SLOW_DBG_MODE_BB_K2 \ |
| c965db44 | 1423 | 0x1601404UL |
| 7b6859fb | 1424 | #define PSEM_REG_DBG_FRAME_MODE_BB_K2 \ |
| c965db44 | 1425 | 0x1601408UL |
| 7b6859fb | 1426 | #define PSEM_REG_DBG_MODE1_CFG_BB_K2 \ |
| c965db44 TT |
1427 | 0x1601420UL |
| 1428 | #define PSEM_REG_FAST_MEMORY \ | |
| 1429 | 0x1640000UL | |
| 7b6859fb | 1430 | #define TSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ |
| c965db44 TT |
1431 | 0x1701140UL |
| 1432 | #define TSEM_REG_SYNC_DBG_EMPTY \ | |
| 1433 | 0x1701160UL | |
| 7b6859fb | 1434 | #define TSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ |
| c965db44 | 1435 | 0x1701400UL |
| 7b6859fb | 1436 | #define TSEM_REG_SLOW_DBG_MODE_BB_K2 \ |
| c965db44 | 1437 | 0x1701404UL |
| 7b6859fb | 1438 | #define TSEM_REG_DBG_FRAME_MODE_BB_K2 \ |
| c965db44 | 1439 | 0x1701408UL |
| 7b6859fb | 1440 | #define TSEM_REG_DBG_MODE1_CFG_BB_K2 \ |
| c965db44 TT |
1441 | 0x1701420UL |
| 1442 | #define TSEM_REG_FAST_MEMORY \ | |
| 1443 | 0x1740000UL | |
| 7b6859fb | 1444 | #define MSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ |
| c965db44 TT |
1445 | 0x1801140UL |
| 1446 | #define MSEM_REG_SYNC_DBG_EMPTY \ | |
| 1447 | 0x1801160UL | |
| 7b6859fb | 1448 | #define MSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ |
| c965db44 | 1449 | 0x1801400UL |
| 7b6859fb | 1450 | #define MSEM_REG_SLOW_DBG_MODE_BB_K2 \ |
| c965db44 | 1451 | 0x1801404UL |
| 7b6859fb | 1452 | #define MSEM_REG_DBG_FRAME_MODE_BB_K2 \ |
| c965db44 | 1453 | 0x1801408UL |
| 7b6859fb | 1454 | #define MSEM_REG_DBG_MODE1_CFG_BB_K2 \ |
| c965db44 TT |
1455 | 0x1801420UL |
| 1456 | #define MSEM_REG_FAST_MEMORY \ | |
| 1457 | 0x1840000UL | |
| 7b6859fb | 1458 | #define USEM_REG_SLOW_DBG_EMPTY_BB_K2 \ |
| c965db44 TT |
1459 | 0x1901140UL |
| 1460 | #define USEM_REG_SYNC_DBG_EMPTY \ | |
| 1461 | 0x1901160UL | |
| 7b6859fb | 1462 | #define USEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ |
| c965db44 | 1463 | 0x1901400UL |
| 7b6859fb | 1464 | #define USEM_REG_SLOW_DBG_MODE_BB_K2 \ |
| c965db44 | 1465 | 0x1901404UL |
| 7b6859fb | 1466 | #define USEM_REG_DBG_FRAME_MODE_BB_K2 \ |
| c965db44 | 1467 | 0x1901408UL |
| 7b6859fb | 1468 | #define USEM_REG_DBG_MODE1_CFG_BB_K2 \ |
| c965db44 TT |
1469 | 0x1901420UL |
| 1470 | #define USEM_REG_FAST_MEMORY \ | |
| 1471 | 0x1940000UL | |
| 1472 | #define SEM_FAST_REG_INT_RAM \ | |
| 1473 | 0x020000UL | |
| 21dd79e8 | 1474 | #define SEM_FAST_REG_INT_RAM_SIZE_BB_K2 \ |
| c965db44 TT |
1475 | 20480 |
| 1476 | #define GRC_REG_TRACE_FIFO_VALID_DATA \ | |
| 1477 | 0x050064UL | |
| 1478 | #define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \ | |
| 1479 | 0x05040cUL | |
| 1480 | #define GRC_REG_PROTECTION_OVERRIDE_WINDOW \ | |
| 1481 | 0x050500UL | |
| 1482 | #define IGU_REG_ERROR_HANDLING_MEMORY \ | |
| 1483 | 0x181520UL | |
| 4102426f TT |
1484 | #define MCP_REG_CPU_MODE \ |
| 1485 | 0xe05000UL | |
| 1486 | #define MCP_REG_CPU_MODE_SOFT_HALT \ | |
| 1487 | (0x1 << 10) | |
| c965db44 TT |
1488 | #define BRB_REG_BIG_RAM_ADDRESS \ |
| 1489 | 0x340800UL | |
| 1490 | #define BRB_REG_BIG_RAM_DATA \ | |
| 1491 | 0x341500UL | |
| da090917 TT |
1492 | #define BRB_REG_BIG_RAM_DATA_SIZE \ |
| 1493 | 64 | |
| 7b6859fb | 1494 | #define SEM_FAST_REG_STALL_0_BB_K2 \ |
| c965db44 TT |
1495 | 0x000488UL |
| 1496 | #define SEM_FAST_REG_STALLED \ | |
| 1497 | 0x000494UL | |
| 1498 | #define BTB_REG_BIG_RAM_ADDRESS \ | |
| 1499 | 0xdb0800UL | |
| 1500 | #define BTB_REG_BIG_RAM_DATA \ | |
| 1501 | 0xdb0c00UL | |
| 1502 | #define BMB_REG_BIG_RAM_ADDRESS \ | |
| 1503 | 0x540800UL | |
| 1504 | #define BMB_REG_BIG_RAM_DATA \ | |
| 1505 | 0x540f00UL | |
| 1506 | #define SEM_FAST_REG_STORM_REG_FILE \ | |
| 1507 | 0x008000UL | |
| 1508 | #define RSS_REG_RSS_RAM_ADDR \ | |
| 1509 | 0x238c30UL | |
| 1510 | #define MISCS_REG_BLOCK_256B_EN \ | |
| 1511 | 0x009074UL | |
| 21dd79e8 | 1512 | #define MCP_REG_SCRATCH_SIZE_BB_K2 \ |
| c965db44 TT |
1513 | 57344 |
| 1514 | #define MCP_REG_CPU_REG_FILE \ | |
| 1515 | 0xe05200UL | |
| 1516 | #define MCP_REG_CPU_REG_FILE_SIZE \ | |
| 1517 | 32 | |
| 1518 | #define DBG_REG_DEBUG_TARGET \ | |
| 1519 | 0x01005cUL | |
| 1520 | #define DBG_REG_FULL_MODE \ | |
| 1521 | 0x010060UL | |
| 1522 | #define DBG_REG_CALENDAR_OUT_DATA \ | |
| 1523 | 0x010480UL | |
| 1524 | #define GRC_REG_TRACE_FIFO \ | |
| 1525 | 0x050068UL | |
| 1526 | #define IGU_REG_ERROR_HANDLING_DATA_VALID \ | |
| 1527 | 0x181530UL | |
| 1528 | #define DBG_REG_DBG_BLOCK_ON \ | |
| 1529 | 0x010454UL | |
| 1530 | #define DBG_REG_FRAMING_MODE \ | |
| 1531 | 0x010058UL | |
| 1532 | #define SEM_FAST_REG_VFC_DATA_WR \ | |
| 1533 | 0x000b40UL | |
| 1534 | #define SEM_FAST_REG_VFC_ADDR \ | |
| 1535 | 0x000b44UL | |
| 1536 | #define SEM_FAST_REG_VFC_DATA_RD \ | |
| 1537 | 0x000b48UL | |
| 1538 | #define RSS_REG_RSS_RAM_DATA \ | |
| 1539 | 0x238c20UL | |
| be086e7c MY |
1540 | #define RSS_REG_RSS_RAM_DATA_SIZE \ |
| 1541 | 4 | |
| c965db44 TT |
1542 | #define MISC_REG_BLOCK_256B_EN \ |
| 1543 | 0x008c14UL | |
| 7b6859fb | 1544 | #define NWS_REG_NWS_CMU_K2 \ |
| c965db44 | 1545 | 0x720000UL |
| 21dd79e8 | 1546 | #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5 \ |
| c965db44 | 1547 | 0x000680UL |
| 21dd79e8 | 1548 | #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5 \ |
| c965db44 | 1549 | 0x000684UL |
| 21dd79e8 | 1550 | #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5 \ |
| c965db44 | 1551 | 0x0006c0UL |
| 21dd79e8 | 1552 | #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5 \ |
| c965db44 | 1553 | 0x0006c4UL |
| 21dd79e8 | 1554 | #define MS_REG_MS_CMU_K2_E5 \ |
| c965db44 | 1555 | 0x6a4000UL |
| 21dd79e8 | 1556 | #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5 \ |
| c965db44 | 1557 | 0x000208UL |
| 21dd79e8 | 1558 | #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 \ |
| c965db44 | 1559 | 0x00020cUL |
| 21dd79e8 | 1560 | #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5 \ |
| 7b6859fb | 1561 | 0x000210UL |
| 21dd79e8 | 1562 | #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5 \ |
| c965db44 | 1563 | 0x000214UL |
| 21dd79e8 | 1564 | #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5 \ |
| c965db44 | 1565 | 0x000208UL |
| 21dd79e8 | 1566 | #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 \ |
| c965db44 | 1567 | 0x00020cUL |
| 21dd79e8 | 1568 | #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5 \ |
| c965db44 | 1569 | 0x000210UL |
| 21dd79e8 | 1570 | #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5 \ |
| c965db44 | 1571 | 0x000214UL |
| 21dd79e8 | 1572 | #define PHY_PCIE_REG_PHY0_K2_E5 \ |
| c965db44 | 1573 | 0x620000UL |
| 21dd79e8 | 1574 | #define PHY_PCIE_REG_PHY1_K2_E5 \ |
| c965db44 | 1575 | 0x624000UL |
| 51ff1725 RA |
1576 | #define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL |
| 1577 | #define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL | |
| 1578 | #define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL | |
| 1579 | #define DORQ_REG_PF_DPM_ENABLE 0x100510UL | |
| 1580 | #define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL | |
| 1581 | #define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL | |
| 1582 | #define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL | |
| c78c70fa SRK |
1583 | #define NIG_REG_RX_PTP_EN 0x501900UL |
| 1584 | #define NIG_REG_TX_PTP_EN 0x501904UL | |
| 1585 | #define NIG_REG_LLH_PTP_TO_HOST 0x501908UL | |
| 1586 | #define NIG_REG_LLH_PTP_TO_MCP 0x50190cUL | |
| 1587 | #define NIG_REG_PTP_SW_TXTSEN 0x501910UL | |
| 1588 | #define NIG_REG_LLH_PTP_ETHERTYPE_1 0x501914UL | |
| 1589 | #define NIG_REG_LLH_PTP_MAC_DA_2_LSB 0x501918UL | |
| 1590 | #define NIG_REG_LLH_PTP_MAC_DA_2_MSB 0x50191cUL | |
| 1591 | #define NIG_REG_LLH_PTP_PARAM_MASK 0x501920UL | |
| 1592 | #define NIG_REG_LLH_PTP_RULE_MASK 0x501924UL | |
| 1593 | #define NIG_REG_TX_LLH_PTP_PARAM_MASK 0x501928UL | |
| 1594 | #define NIG_REG_TX_LLH_PTP_RULE_MASK 0x50192cUL | |
| 1595 | #define NIG_REG_LLH_PTP_HOST_BUF_SEQID 0x501930UL | |
| 1596 | #define NIG_REG_LLH_PTP_HOST_BUF_TS_LSB 0x501934UL | |
| 1597 | #define NIG_REG_LLH_PTP_HOST_BUF_TS_MSB 0x501938UL | |
| 1598 | #define NIG_REG_LLH_PTP_MCP_BUF_SEQID 0x50193cUL | |
| 1599 | #define NIG_REG_LLH_PTP_MCP_BUF_TS_LSB 0x501940UL | |
| 1600 | #define NIG_REG_LLH_PTP_MCP_BUF_TS_MSB 0x501944UL | |
| 1601 | #define NIG_REG_TX_LLH_PTP_BUF_SEQID 0x501948UL | |
| 1602 | #define NIG_REG_TX_LLH_PTP_BUF_TS_LSB 0x50194cUL | |
| 1603 | #define NIG_REG_TX_LLH_PTP_BUF_TS_MSB 0x501950UL | |
| 1604 | #define NIG_REG_RX_PTP_TS_MSB_ERR 0x501954UL | |
| 1605 | #define NIG_REG_TX_PTP_TS_MSB_ERR 0x501958UL | |
| 1606 | #define NIG_REG_TSGEN_SYNC_TIME_LSB 0x5088c0UL | |
| 1607 | #define NIG_REG_TSGEN_SYNC_TIME_MSB 0x5088c4UL | |
| 1608 | #define NIG_REG_TSGEN_RST_DRIFT_CNTR 0x5088d8UL | |
| 1609 | #define NIG_REG_TSGEN_DRIFT_CNTR_CONF 0x5088dcUL | |
| 1610 | #define NIG_REG_TS_OUTPUT_ENABLE_PDA 0x508870UL | |
| 1611 | #define NIG_REG_TIMESYNC_GEN_REG_BB 0x500d00UL | |
| 1612 | #define NIG_REG_TSGEN_FREE_CNT_VALUE_LSB 0x5088a8UL | |
| 1613 | #define NIG_REG_TSGEN_FREE_CNT_VALUE_MSB 0x5088acUL | |
| 9c79ddaa | 1614 | #define NIG_REG_PTP_LATCH_OSTS_PKT_TIME 0x509040UL |
| 60afed72 | 1615 | #define PSWRQ2_REG_WR_MBS0 0x240400UL |
| 9c79ddaa MY |
1616 | |
| 1617 | #define PGLUE_B_REG_PGL_ADDR_E8_F0_K2 0x2aaf98UL | |
| 1618 | #define PGLUE_B_REG_PGL_ADDR_EC_F0_K2 0x2aaf9cUL | |
| 1619 | #define PGLUE_B_REG_PGL_ADDR_F0_F0_K2 0x2aafa0UL | |
| 1620 | #define PGLUE_B_REG_PGL_ADDR_F4_F0_K2 0x2aafa4UL | |
| fc6575bc | 1621 | #define PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE 0x2aae30UL |
| 9c79ddaa MY |
1622 | #define NIG_REG_TSGEN_FREECNT_UPDATE_K2 0x509008UL |
| 1623 | #define CNIG_REG_NIG_PORT0_CONF_K2 0x218200UL | |
| 1624 | ||
| 26462ad9 MY |
1625 | #define NIG_REG_TX_EDPM_CTRL 0x501f0cUL |
| 1626 | #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN (0x1 << 0) | |
| 1627 | #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN_SHIFT 0 | |
| 1628 | #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN (0xff << 1) | |
| 1629 | #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN_SHIFT 1 | |
| 1630 | ||
| d51e4af5 | 1631 | #define PRS_REG_SEARCH_GFT 0x1f11bcUL |
| d52c89f1 | 1632 | #define PRS_REG_SEARCH_NON_IP_AS_GFT 0x1f11c0UL |
| d51e4af5 CM |
1633 | #define PRS_REG_CM_HDR_GFT 0x1f11c8UL |
| 1634 | #define PRS_REG_GFT_CAM 0x1f1100UL | |
| 1635 | #define PRS_REG_GFT_PROFILE_MASK_RAM 0x1f1000UL | |
| 1636 | #define PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT 0 | |
| 1637 | #define PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT 8 | |
| 1638 | #define PRS_REG_LOAD_L2_FILTER 0x1f0198UL | |
| 1639 | ||
| fe56b9e6 | 1640 | #endif |