[linux.git] / arch / riscv / include / uapi / asm / syscalls.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2017-2018 SiFive
 */

/*
 * There is explicitly no include guard here because this file is expected to
 * be included multiple times in order to define the syscall macros via
 * __SYSCALL.
 */

/*
 * Allows the instruction cache to be flushed from userspace.  Despite RISC-V
 * having a direct 'fence.i' instruction available to userspace (which we
 * can't trap!), that's not actually viable when running on Linux because the
 * kernel might schedule a process on another hart.  There is no way for
 * userspace to handle this without invoking the kernel (as it doesn't know the
 * thread->hart mappings), so we've defined a RISC-V specific system call to
 * flush the instruction cache.
 *
 * __NR_riscv_flush_icache is defined to flush the instruction cache over an
 * address range, with the flush applying to either all threads or just the
 * caller.  We don't currently do anything with the address range, that's just
 * in there for forwards compatibility.
 */
#ifndef __NR_riscv_flush_icache
#define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)
#endif
__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)
Commit	Line	Data
9e49a4ed PD	1	/* SPDX-License-Identifier: GPL-2.0 */
9e49a4ed PD	2	/*
e45c7aca	3	* Copyright (C) 2017-2018 SiFive
9e49a4ed PD	4	*/
9e49a4ed PD	5
e45c7aca PD	6	/*
	7	* There is explicitly no include guard here because this file is expected to
	8	* be included multiple times in order to define the syscall macros via
	9	* __SYSCALL.
	10	*/
9e49a4ed PD	11
	12	/*
	13	* Allows the instruction cache to be flushed from userspace. Despite RISC-V
	14	* having a direct 'fence.i' instruction available to userspace (which we
	15	* can't trap!), that's not actually viable when running on Linux because the
	16	* kernel might schedule a process on another hart. There is no way for
	17	* userspace to handle this without invoking the kernel (as it doesn't know the
	18	* thread->hart mappings), so we've defined a RISC-V specific system call to
	19	* flush the instruction cache.
	20	*
	21	* __NR_riscv_flush_icache is defined to flush the instruction cache over an
	22	* address range, with the flush applying to either all threads or just the
	23	* caller. We don't currently do anything with the address range, that's just
	24	* in there for forwards compatibility.
	25	*/
e45c7aca	26	#ifndef __NR_riscv_flush_icache
9e49a4ed	27	#define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)
9e49a4ed	28	#endif
e45c7aca	29	__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)