[linux.git] / drivers / media / platform / verisilicon / rockchip_vpu2_hw_mpeg2_dec.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Hantro VPU codec driver
 *
 * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
 */

#include <linux/unaligned.h>
#include <linux/bitfield.h>
#include <media/v4l2-mem2mem.h>
#include "hantro.h"
#include "hantro_hw.h"

#define VDPU_SWREG(nr)			((nr) * 4)

#define VDPU_REG_DEC_OUT_BASE		VDPU_SWREG(63)
#define VDPU_REG_RLC_VLC_BASE		VDPU_SWREG(64)
#define VDPU_REG_QTABLE_BASE		VDPU_SWREG(61)
#define VDPU_REG_REFER0_BASE		VDPU_SWREG(131)
#define VDPU_REG_REFER2_BASE		VDPU_SWREG(134)
#define VDPU_REG_REFER3_BASE		VDPU_SWREG(135)
#define VDPU_REG_REFER1_BASE		VDPU_SWREG(148)
#define VDPU_REG_DEC_E(v)		((v) ? BIT(0) : 0)

#define VDPU_REG_DEC_ADV_PRE_DIS(v)	((v) ? BIT(11) : 0)
#define VDPU_REG_DEC_SCMD_DIS(v)	((v) ? BIT(10) : 0)
#define VDPU_REG_FILTERING_DIS(v)	((v) ? BIT(8) : 0)
#define VDPU_REG_DEC_LATENCY(v)		(((v) << 1) & GENMASK(6, 1))

#define VDPU_REG_INIT_QP(v)		(((v) << 25) & GENMASK(30, 25))
#define VDPU_REG_STREAM_LEN(v)		(((v) << 0) & GENMASK(23, 0))

#define VDPU_REG_APF_THRESHOLD(v)	(((v) << 17) & GENMASK(30, 17))
#define VDPU_REG_STARTMB_X(v)		(((v) << 8) & GENMASK(16, 8))
#define VDPU_REG_STARTMB_Y(v)		(((v) << 0) & GENMASK(7, 0))

#define VDPU_REG_DEC_MODE(v)		(((v) << 0) & GENMASK(3, 0))

#define VDPU_REG_DEC_STRENDIAN_E(v)	((v) ? BIT(5) : 0)
#define VDPU_REG_DEC_STRSWAP32_E(v)	((v) ? BIT(4) : 0)
#define VDPU_REG_DEC_OUTSWAP32_E(v)	((v) ? BIT(3) : 0)
#define VDPU_REG_DEC_INSWAP32_E(v)	((v) ? BIT(2) : 0)
#define VDPU_REG_DEC_OUT_ENDIAN(v)	((v) ? BIT(1) : 0)
#define VDPU_REG_DEC_IN_ENDIAN(v)	((v) ? BIT(0) : 0)

#define VDPU_REG_DEC_DATA_DISC_E(v)	((v) ? BIT(22) : 0)
#define VDPU_REG_DEC_MAX_BURST(v)	(((v) << 16) & GENMASK(20, 16))
#define VDPU_REG_DEC_AXI_WR_ID(v)	(((v) << 8) & GENMASK(15, 8))
#define VDPU_REG_DEC_AXI_RD_ID(v)	(((v) << 0) & GENMASK(7, 0))

#define VDPU_REG_RLC_MODE_E(v)		((v) ? BIT(20) : 0)
#define VDPU_REG_PIC_INTERLACE_E(v)	((v) ? BIT(17) : 0)
#define VDPU_REG_PIC_FIELDMODE_E(v)	((v) ? BIT(16) : 0)
#define VDPU_REG_PIC_B_E(v)		((v) ? BIT(15) : 0)
#define VDPU_REG_PIC_INTER_E(v)		((v) ? BIT(14) : 0)
#define VDPU_REG_PIC_TOPFIELD_E(v)	((v) ? BIT(13) : 0)
#define VDPU_REG_FWD_INTERLACE_E(v)	((v) ? BIT(12) : 0)
#define VDPU_REG_WRITE_MVS_E(v)		((v) ? BIT(10) : 0)
#define VDPU_REG_DEC_TIMEOUT_E(v)	((v) ? BIT(5) : 0)
#define VDPU_REG_DEC_CLK_GATE_E(v)	((v) ? BIT(4) : 0)

#define VDPU_REG_PIC_MB_WIDTH(v)	(((v) << 23) & GENMASK(31, 23))
#define VDPU_REG_PIC_MB_HEIGHT_P(v)	(((v) << 11) & GENMASK(18, 11))
#define VDPU_REG_ALT_SCAN_E(v)		((v) ? BIT(6) : 0)
#define VDPU_REG_TOPFIELDFIRST_E(v)	((v) ? BIT(5) : 0)

#define VDPU_REG_STRM_START_BIT(v)	(((v) << 26) & GENMASK(31, 26))
#define VDPU_REG_QSCALE_TYPE(v)		((v) ? BIT(24) : 0)
#define VDPU_REG_CON_MV_E(v)		((v) ? BIT(4) : 0)
#define VDPU_REG_INTRA_DC_PREC(v)	(((v) << 2) & GENMASK(3, 2))
#define VDPU_REG_INTRA_VLC_TAB(v)	((v) ? BIT(1) : 0)
#define VDPU_REG_FRAME_PRED_DCT(v)	((v) ? BIT(0) : 0)

#define VDPU_REG_ALT_SCAN_FLAG_E(v)	((v) ? BIT(19) : 0)
#define VDPU_REG_FCODE_FWD_HOR(v)	(((v) << 15) & GENMASK(18, 15))
#define VDPU_REG_FCODE_FWD_VER(v)	(((v) << 11) & GENMASK(14, 11))
#define VDPU_REG_FCODE_BWD_HOR(v)	(((v) << 7) & GENMASK(10, 7))
#define VDPU_REG_FCODE_BWD_VER(v)	(((v) << 3) & GENMASK(6, 3))
#define VDPU_REG_MV_ACCURACY_FWD(v)	((v) ? BIT(2) : 0)
#define VDPU_REG_MV_ACCURACY_BWD(v)	((v) ? BIT(1) : 0)

static void
rockchip_vpu2_mpeg2_dec_set_quantisation(struct hantro_dev *vpu,
					 struct hantro_ctx *ctx)
{
	struct v4l2_ctrl_mpeg2_quantisation *q;

	q = hantro_get_ctrl(ctx, V4L2_CID_STATELESS_MPEG2_QUANTISATION);
	hantro_mpeg2_dec_copy_qtable(ctx->mpeg2_dec.qtable.cpu, q);
	vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, VDPU_REG_QTABLE_BASE);
}

static void
rockchip_vpu2_mpeg2_dec_set_buffers(struct hantro_dev *vpu,
				    struct hantro_ctx *ctx,
				    struct vb2_buffer *src_buf,
				    struct vb2_buffer *dst_buf,
				    const struct v4l2_ctrl_mpeg2_sequence *seq,
				    const struct v4l2_ctrl_mpeg2_picture *pic)
{
	dma_addr_t forward_addr = 0, backward_addr = 0;
	dma_addr_t current_addr, addr;

	switch (pic->picture_coding_type) {
	case V4L2_MPEG2_PIC_CODING_TYPE_B:
		backward_addr = hantro_get_ref(ctx, pic->backward_ref_ts);
		fallthrough;
	case V4L2_MPEG2_PIC_CODING_TYPE_P:
		forward_addr = hantro_get_ref(ctx, pic->forward_ref_ts);
	}

	/* Source bitstream buffer */
	addr = vb2_dma_contig_plane_dma_addr(src_buf, 0);
	vdpu_write_relaxed(vpu, addr, VDPU_REG_RLC_VLC_BASE);

	/* Destination frame buffer */
	addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
	current_addr = addr;

	if (pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD)
		addr += ALIGN(ctx->dst_fmt.width, 16);
	vdpu_write_relaxed(vpu, addr, VDPU_REG_DEC_OUT_BASE);

	if (!forward_addr)
		forward_addr = current_addr;
	if (!backward_addr)
		backward_addr = current_addr;

	/* Set forward ref frame (top/bottom field) */
	if (pic->picture_structure == V4L2_MPEG2_PIC_FRAME ||
	    pic->picture_coding_type == V4L2_MPEG2_PIC_CODING_TYPE_B ||
	    (pic->picture_structure == V4L2_MPEG2_PIC_TOP_FIELD &&
	     pic->flags & V4L2_MPEG2_PIC_TOP_FIELD) ||
	    (pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD &&
	     !(pic->flags & V4L2_MPEG2_PIC_TOP_FIELD))) {
		vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE);
		vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE);
	} else if (pic->picture_structure == V4L2_MPEG2_PIC_TOP_FIELD) {
		vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE);
		vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER1_BASE);
	} else if (pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD) {
		vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER0_BASE);
		vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE);
	}

	/* Set backward ref frame (top/bottom field) */
	vdpu_write_relaxed(vpu, backward_addr, VDPU_REG_REFER2_BASE);
	vdpu_write_relaxed(vpu, backward_addr, VDPU_REG_REFER3_BASE);
}

int rockchip_vpu2_mpeg2_dec_run(struct hantro_ctx *ctx)
{
	struct hantro_dev *vpu = ctx->dev;
	struct vb2_v4l2_buffer *src_buf, *dst_buf;
	const struct v4l2_ctrl_mpeg2_sequence *seq;
	const struct v4l2_ctrl_mpeg2_picture *pic;
	u32 reg;

	src_buf = hantro_get_src_buf(ctx);
	dst_buf = hantro_get_dst_buf(ctx);

	hantro_start_prepare_run(ctx);

	seq = hantro_get_ctrl(ctx,
			      V4L2_CID_STATELESS_MPEG2_SEQUENCE);
	pic = hantro_get_ctrl(ctx,
			      V4L2_CID_STATELESS_MPEG2_PICTURE);

	reg = VDPU_REG_DEC_ADV_PRE_DIS(0) |
	      VDPU_REG_DEC_SCMD_DIS(0) |
	      VDPU_REG_FILTERING_DIS(1) |
	      VDPU_REG_DEC_LATENCY(0);
	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50));

	reg = VDPU_REG_INIT_QP(1) |
	      VDPU_REG_STREAM_LEN(vb2_get_plane_payload(&src_buf->vb2_buf, 0));
	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51));

	reg = VDPU_REG_APF_THRESHOLD(8) |
	      VDPU_REG_STARTMB_X(0) |
	      VDPU_REG_STARTMB_Y(0);
	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52));

	reg = VDPU_REG_DEC_MODE(5);
	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53));

	reg = VDPU_REG_DEC_STRENDIAN_E(1) |
	      VDPU_REG_DEC_STRSWAP32_E(1) |
	      VDPU_REG_DEC_OUTSWAP32_E(1) |
	      VDPU_REG_DEC_INSWAP32_E(1) |
	      VDPU_REG_DEC_OUT_ENDIAN(1) |
	      VDPU_REG_DEC_IN_ENDIAN(1);
	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54));

	reg = VDPU_REG_DEC_DATA_DISC_E(0) |
	      VDPU_REG_DEC_MAX_BURST(16) |
	      VDPU_REG_DEC_AXI_WR_ID(0) |
	      VDPU_REG_DEC_AXI_RD_ID(0);
	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56));

	reg = VDPU_REG_RLC_MODE_E(0) |
	      VDPU_REG_PIC_INTERLACE_E(!(seq->flags & V4L2_MPEG2_SEQ_FLAG_PROGRESSIVE)) |
	      VDPU_REG_PIC_FIELDMODE_E(pic->picture_structure != V4L2_MPEG2_PIC_FRAME) |
	      VDPU_REG_PIC_B_E(pic->picture_coding_type == V4L2_MPEG2_PIC_CODING_TYPE_B) |
	      VDPU_REG_PIC_INTER_E(pic->picture_coding_type != V4L2_MPEG2_PIC_CODING_TYPE_I) |
	      VDPU_REG_PIC_TOPFIELD_E(pic->picture_structure == V4L2_MPEG2_PIC_TOP_FIELD) |
	      VDPU_REG_FWD_INTERLACE_E(0) |
	      VDPU_REG_WRITE_MVS_E(0) |
	      VDPU_REG_DEC_TIMEOUT_E(1) |
	      VDPU_REG_DEC_CLK_GATE_E(1);
	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57));

	reg = VDPU_REG_PIC_MB_WIDTH(MB_WIDTH(ctx->dst_fmt.width)) |
	      VDPU_REG_PIC_MB_HEIGHT_P(MB_HEIGHT(ctx->dst_fmt.height)) |
	      VDPU_REG_ALT_SCAN_E(pic->flags & V4L2_MPEG2_PIC_FLAG_ALT_SCAN) |
	      VDPU_REG_TOPFIELDFIRST_E(pic->flags & V4L2_MPEG2_PIC_FLAG_TOP_FIELD_FIRST);
	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(120));

	reg = VDPU_REG_STRM_START_BIT(0) |
	      VDPU_REG_QSCALE_TYPE(pic->flags & V4L2_MPEG2_PIC_FLAG_Q_SCALE_TYPE) |
	      VDPU_REG_CON_MV_E(pic->flags & V4L2_MPEG2_PIC_FLAG_CONCEALMENT_MV) |
	      VDPU_REG_INTRA_DC_PREC(pic->intra_dc_precision) |
	      VDPU_REG_INTRA_VLC_TAB(pic->flags & V4L2_MPEG2_PIC_FLAG_INTRA_VLC) |
	      VDPU_REG_FRAME_PRED_DCT(pic->flags & V4L2_MPEG2_PIC_FLAG_FRAME_PRED_DCT);
	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(122));

	reg = VDPU_REG_ALT_SCAN_FLAG_E(pic->flags & V4L2_MPEG2_PIC_FLAG_ALT_SCAN) |
	      VDPU_REG_FCODE_FWD_HOR(pic->f_code[0][0]) |
	      VDPU_REG_FCODE_FWD_VER(pic->f_code[0][1]) |
	      VDPU_REG_FCODE_BWD_HOR(pic->f_code[1][0]) |
	      VDPU_REG_FCODE_BWD_VER(pic->f_code[1][1]) |
	      VDPU_REG_MV_ACCURACY_FWD(1) |
	      VDPU_REG_MV_ACCURACY_BWD(1);
	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(136));

	rockchip_vpu2_mpeg2_dec_set_quantisation(vpu, ctx);

	rockchip_vpu2_mpeg2_dec_set_buffers(vpu, ctx, &src_buf->vb2_buf,
					    &dst_buf->vb2_buf, seq, pic);

	/* Kick the watchdog and start decoding */
	hantro_end_prepare_run(ctx);

	reg = vdpu_read(vpu, VDPU_SWREG(57)) | VDPU_REG_DEC_E(1);
	vdpu_write(vpu, reg, VDPU_SWREG(57));

	return 0;
}
Commit	Line	Data
879dee56 JK	1	// SPDX-License-Identifier: GPL-2.0
879dee56 JK	2	/*
a29add8c	3	* Hantro VPU codec driver
879dee56 JK	4	*
	5	* Copyright (C) 2018 Rockchip Electronics Co., Ltd.
	6	*/
	7
5f60d5f6	8	#include <linux/unaligned.h>
879dee56 JK	9	#include <linux/bitfield.h>
879dee56 JK	10	#include <media/v4l2-mem2mem.h>
a29add8c PZ	11	#include "hantro.h"
a29add8c PZ	12	#include "hantro_hw.h"
879dee56 JK	13
	14	#define VDPU_SWREG(nr) ((nr) * 4)
	15
	16	#define VDPU_REG_DEC_OUT_BASE VDPU_SWREG(63)
	17	#define VDPU_REG_RLC_VLC_BASE VDPU_SWREG(64)
	18	#define VDPU_REG_QTABLE_BASE VDPU_SWREG(61)
	19	#define VDPU_REG_REFER0_BASE VDPU_SWREG(131)
	20	#define VDPU_REG_REFER2_BASE VDPU_SWREG(134)
	21	#define VDPU_REG_REFER3_BASE VDPU_SWREG(135)
	22	#define VDPU_REG_REFER1_BASE VDPU_SWREG(148)
	23	#define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0)
	24
	25	#define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0)
	26	#define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0)
	27	#define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0)
	28	#define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1))
	29
	30	#define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25))
	31	#define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0))
	32
	33	#define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17))
	34	#define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8))
	35	#define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0))
	36
	37	#define VDPU_REG_DEC_MODE(v) (((v) << 0) & GENMASK(3, 0))
	38
	39	#define VDPU_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(5) : 0)
	40	#define VDPU_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(4) : 0)
	41	#define VDPU_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(3) : 0)
	42	#define VDPU_REG_DEC_INSWAP32_E(v) ((v) ? BIT(2) : 0)
	43	#define VDPU_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(1) : 0)
	44	#define VDPU_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(0) : 0)
	45
	46	#define VDPU_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(22) : 0)
	47	#define VDPU_REG_DEC_MAX_BURST(v) (((v) << 16) & GENMASK(20, 16))
	48	#define VDPU_REG_DEC_AXI_WR_ID(v) (((v) << 8) & GENMASK(15, 8))
	49	#define VDPU_REG_DEC_AXI_RD_ID(v) (((v) << 0) & GENMASK(7, 0))
	50
	51	#define VDPU_REG_RLC_MODE_E(v) ((v) ? BIT(20) : 0)
	52	#define VDPU_REG_PIC_INTERLACE_E(v) ((v) ? BIT(17) : 0)
	53	#define VDPU_REG_PIC_FIELDMODE_E(v) ((v) ? BIT(16) : 0)
	54	#define VDPU_REG_PIC_B_E(v) ((v) ? BIT(15) : 0)
	55	#define VDPU_REG_PIC_INTER_E(v) ((v) ? BIT(14) : 0)
	56	#define VDPU_REG_PIC_TOPFIELD_E(v) ((v) ? BIT(13) : 0)
	57	#define VDPU_REG_FWD_INTERLACE_E(v) ((v) ? BIT(12) : 0)
	58	#define VDPU_REG_WRITE_MVS_E(v) ((v) ? BIT(10) : 0)
	59	#define VDPU_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(5) : 0)
	60	#define VDPU_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(4) : 0)
	61
	62	#define VDPU_REG_PIC_MB_WIDTH(v) (((v) << 23) & GENMASK(31, 23))
	63	#define VDPU_REG_PIC_MB_HEIGHT_P(v) (((v) << 11) & GENMASK(18, 11))
	64	#define VDPU_REG_ALT_SCAN_E(v) ((v) ? BIT(6) : 0)
	65	#define VDPU_REG_TOPFIELDFIRST_E(v) ((v) ? BIT(5) : 0)
	66
	67	#define VDPU_REG_STRM_START_BIT(v) (((v) << 26) & GENMASK(31, 26))
	68	#define VDPU_REG_QSCALE_TYPE(v) ((v) ? BIT(24) : 0)
	69	#define VDPU_REG_CON_MV_E(v) ((v) ? BIT(4) : 0)
	70	#define VDPU_REG_INTRA_DC_PREC(v) (((v) << 2) & GENMASK(3, 2))
	71	#define VDPU_REG_INTRA_VLC_TAB(v) ((v) ? BIT(1) : 0)
	72	#define VDPU_REG_FRAME_PRED_DCT(v) ((v) ? BIT(0) : 0)
	73
	74	#define VDPU_REG_ALT_SCAN_FLAG_E(v) ((v) ? BIT(19) : 0)
	75	#define VDPU_REG_FCODE_FWD_HOR(v) (((v) << 15) & GENMASK(18, 15))
	76	#define VDPU_REG_FCODE_FWD_VER(v) (((v) << 11) & GENMASK(14, 11))
77	#define VDPU_REG_FCODE_BWD_HOR(v) (((v) << 7) & GENMASK(10, 7))
78	#define VDPU_REG_FCODE_BWD_VER(v) (((v) << 3) & GENMASK(6, 3))
79	#define VDPU_REG_MV_ACCURACY_FWD(v) ((v) ? BIT(2) : 0)
80	#define VDPU_REG_MV_ACCURACY_BWD(v) ((v) ? BIT(1) : 0)
81
879dee56	82	static void
c9caebd5 AB	83	rockchip_vpu2_mpeg2_dec_set_quantisation(struct hantro_dev *vpu,
c9caebd5 AB	84	struct hantro_ctx *ctx)
879dee56	85	{
118f3e15	86	struct v4l2_ctrl_mpeg2_quantisation *q;
879dee56	87
f4815b39	88	q = hantro_get_ctrl(ctx, V4L2_CID_STATELESS_MPEG2_QUANTISATION);
118f3e15 EG	89	hantro_mpeg2_dec_copy_qtable(ctx->mpeg2_dec.qtable.cpu, q);
118f3e15 EG	90	vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, VDPU_REG_QTABLE_BASE);
879dee56 JK	91	}
	92
	93	static void
c9caebd5 AB	94	rockchip_vpu2_mpeg2_dec_set_buffers(struct hantro_dev *vpu,
	95	struct hantro_ctx *ctx,
	96	struct vb2_buffer *src_buf,
	97	struct vb2_buffer *dst_buf,
	98	const struct v4l2_ctrl_mpeg2_sequence *seq,
	99	const struct v4l2_ctrl_mpeg2_picture *pic)
879dee56 JK	100	{
	101	dma_addr_t forward_addr = 0, backward_addr = 0;
	102	dma_addr_t current_addr, addr;
879dee56	103
88e78409 EG	104	switch (pic->picture_coding_type) {
88e78409 EG	105	case V4L2_MPEG2_PIC_CODING_TYPE_B:
b6d7e803	106	backward_addr = hantro_get_ref(ctx, pic->backward_ref_ts);
df561f66	107	fallthrough;
88e78409	108	case V4L2_MPEG2_PIC_CODING_TYPE_P:
b6d7e803	109	forward_addr = hantro_get_ref(ctx, pic->forward_ref_ts);
879dee56 JK	110	}
	111
	112	/* Source bitstream buffer */
	113	addr = vb2_dma_contig_plane_dma_addr(src_buf, 0);
	114	vdpu_write_relaxed(vpu, addr, VDPU_REG_RLC_VLC_BASE);
	115
	116	/* Destination frame buffer */
	117	addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
	118	current_addr = addr;
	119
88e78409	120	if (pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD)
879dee56 JK	121	addr += ALIGN(ctx->dst_fmt.width, 16);
	122	vdpu_write_relaxed(vpu, addr, VDPU_REG_DEC_OUT_BASE);
	123
	124	if (!forward_addr)
	125	forward_addr = current_addr;
	126	if (!backward_addr)
	127	backward_addr = current_addr;
	128
	129	/* Set forward ref frame (top/bottom field) */
88e78409 EG	130	if (pic->picture_structure == V4L2_MPEG2_PIC_FRAME \|\|
	131	pic->picture_coding_type == V4L2_MPEG2_PIC_CODING_TYPE_B \|\|
	132	(pic->picture_structure == V4L2_MPEG2_PIC_TOP_FIELD &&
	133	pic->flags & V4L2_MPEG2_PIC_TOP_FIELD) \|\|
	134	(pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD &&
	135	!(pic->flags & V4L2_MPEG2_PIC_TOP_FIELD))) {
879dee56 JK	136	vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE);
879dee56 JK	137	vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE);
88e78409	138	} else if (pic->picture_structure == V4L2_MPEG2_PIC_TOP_FIELD) {
879dee56 JK	139	vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE);
879dee56 JK	140	vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER1_BASE);
88e78409	141	} else if (pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD) {
879dee56 JK	142	vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER0_BASE);
	143	vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE);
	144	}
	145
	146	/* Set backward ref frame (top/bottom field) */
	147	vdpu_write_relaxed(vpu, backward_addr, VDPU_REG_REFER2_BASE);
	148	vdpu_write_relaxed(vpu, backward_addr, VDPU_REG_REFER3_BASE);
	149	}
	150
c9caebd5	151	int rockchip_vpu2_mpeg2_dec_run(struct hantro_ctx *ctx)
879dee56	152	{
a29add8c	153	struct hantro_dev *vpu = ctx->dev;
879dee56	154	struct vb2_v4l2_buffer src_buf, dst_buf;
f329e21e EG	155	const struct v4l2_ctrl_mpeg2_sequence *seq;
f329e21e EG	156	const struct v4l2_ctrl_mpeg2_picture *pic;
879dee56 JK	157	u32 reg;
879dee56 JK	158
deff5c37 BB	159	src_buf = hantro_get_src_buf(ctx);
deff5c37 BB	160	dst_buf = hantro_get_dst_buf(ctx);
879dee56	161
3143f8a1	162	hantro_start_prepare_run(ctx);
879dee56	163
f329e21e	164	seq = hantro_get_ctrl(ctx,
f4815b39	165	V4L2_CID_STATELESS_MPEG2_SEQUENCE);
f329e21e	166	pic = hantro_get_ctrl(ctx,
f4815b39	167	V4L2_CID_STATELESS_MPEG2_PICTURE);
879dee56 JK	168
	169	reg = VDPU_REG_DEC_ADV_PRE_DIS(0) \|
	170	VDPU_REG_DEC_SCMD_DIS(0) \|
	171	VDPU_REG_FILTERING_DIS(1) \|
	172	VDPU_REG_DEC_LATENCY(0);
	173	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50));
	174
	175	reg = VDPU_REG_INIT_QP(1) \|
701a6a41	176	VDPU_REG_STREAM_LEN(vb2_get_plane_payload(&src_buf->vb2_buf, 0));
879dee56 JK	177	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51));
	178
	179	reg = VDPU_REG_APF_THRESHOLD(8) \|
	180	VDPU_REG_STARTMB_X(0) \|
	181	VDPU_REG_STARTMB_Y(0);
	182	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52));
	183
	184	reg = VDPU_REG_DEC_MODE(5);
	185	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53));
	186
	187	reg = VDPU_REG_DEC_STRENDIAN_E(1) \|
	188	VDPU_REG_DEC_STRSWAP32_E(1) \|
	189	VDPU_REG_DEC_OUTSWAP32_E(1) \|
	190	VDPU_REG_DEC_INSWAP32_E(1) \|
	191	VDPU_REG_DEC_OUT_ENDIAN(1) \|
	192	VDPU_REG_DEC_IN_ENDIAN(1);
	193	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54));
	194
	195	reg = VDPU_REG_DEC_DATA_DISC_E(0) \|
	196	VDPU_REG_DEC_MAX_BURST(16) \|
	197	VDPU_REG_DEC_AXI_WR_ID(0) \|
	198	VDPU_REG_DEC_AXI_RD_ID(0);
	199	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56));
	200
	201	reg = VDPU_REG_RLC_MODE_E(0) \|
88e78409 EG	202	VDPU_REG_PIC_INTERLACE_E(!(seq->flags & V4L2_MPEG2_SEQ_FLAG_PROGRESSIVE)) \|
	203	VDPU_REG_PIC_FIELDMODE_E(pic->picture_structure != V4L2_MPEG2_PIC_FRAME) \|
	204	VDPU_REG_PIC_B_E(pic->picture_coding_type == V4L2_MPEG2_PIC_CODING_TYPE_B) \|
	205	VDPU_REG_PIC_INTER_E(pic->picture_coding_type != V4L2_MPEG2_PIC_CODING_TYPE_I) \|
	206	VDPU_REG_PIC_TOPFIELD_E(pic->picture_structure == V4L2_MPEG2_PIC_TOP_FIELD) \|
879dee56 JK	207	VDPU_REG_FWD_INTERLACE_E(0) \|
	208	VDPU_REG_WRITE_MVS_E(0) \|
	209	VDPU_REG_DEC_TIMEOUT_E(1) \|
	210	VDPU_REG_DEC_CLK_GATE_E(1);
	211	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57));
	212
05e58c83 EG	213	reg = VDPU_REG_PIC_MB_WIDTH(MB_WIDTH(ctx->dst_fmt.width)) \|
05e58c83 EG	214	VDPU_REG_PIC_MB_HEIGHT_P(MB_HEIGHT(ctx->dst_fmt.height)) \|
88e78409 EG	215	VDPU_REG_ALT_SCAN_E(pic->flags & V4L2_MPEG2_PIC_FLAG_ALT_SCAN) \|
88e78409 EG	216	VDPU_REG_TOPFIELDFIRST_E(pic->flags & V4L2_MPEG2_PIC_FLAG_TOP_FIELD_FIRST);
879dee56 JK	217	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(120));
879dee56 JK	218
701a6a41	219	reg = VDPU_REG_STRM_START_BIT(0) \|
88e78409 EG	220	VDPU_REG_QSCALE_TYPE(pic->flags & V4L2_MPEG2_PIC_FLAG_Q_SCALE_TYPE) \|
	221	VDPU_REG_CON_MV_E(pic->flags & V4L2_MPEG2_PIC_FLAG_CONCEALMENT_MV) \|
	222	VDPU_REG_INTRA_DC_PREC(pic->intra_dc_precision) \|
	223	VDPU_REG_INTRA_VLC_TAB(pic->flags & V4L2_MPEG2_PIC_FLAG_INTRA_VLC) \|
	224	VDPU_REG_FRAME_PRED_DCT(pic->flags & V4L2_MPEG2_PIC_FLAG_FRAME_PRED_DCT);
879dee56 JK	225	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(122));
879dee56 JK	226
88e78409 EG	227	reg = VDPU_REG_ALT_SCAN_FLAG_E(pic->flags & V4L2_MPEG2_PIC_FLAG_ALT_SCAN) \|
	228	VDPU_REG_FCODE_FWD_HOR(pic->f_code[0][0]) \|
	229	VDPU_REG_FCODE_FWD_VER(pic->f_code[0][1]) \|
	230	VDPU_REG_FCODE_BWD_HOR(pic->f_code[1][0]) \|
	231	VDPU_REG_FCODE_BWD_VER(pic->f_code[1][1]) \|
879dee56 JK	232	VDPU_REG_MV_ACCURACY_FWD(1) \|
	233	VDPU_REG_MV_ACCURACY_BWD(1);
	234	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(136));
	235
c9caebd5	236	rockchip_vpu2_mpeg2_dec_set_quantisation(vpu, ctx);
879dee56	237
c9caebd5 AB	238	rockchip_vpu2_mpeg2_dec_set_buffers(vpu, ctx, &src_buf->vb2_buf,
c9caebd5 AB	239	&dst_buf->vb2_buf, seq, pic);
879dee56	240
879dee56	241	/* Kick the watchdog and start decoding */
3143f8a1	242	hantro_end_prepare_run(ctx);
879dee56 JK	243
	244	reg = vdpu_read(vpu, VDPU_SWREG(57)) \| VDPU_REG_DEC_E(1);
	245	vdpu_write(vpu, reg, VDPU_SWREG(57));
42cb2a8f BG	246
42cb2a8f BG	247	return 0;
879dee56	248	}