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ASoC: wm_adsp: Add initialisation function for ADSP1
[linux.git] / sound / soc / codecs / wm_adsp.c
CommitLineData
2159ad93
MB		 1/*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/firmware.h>
18#include <linux/pm.h>
19#include <linux/pm_runtime.h>
20#include <linux/regmap.h>
973838a0 21#include <linux/regulator/consumer.h>
2159ad93
MB		 22#include <linux/slab.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/jack.h>
28#include <sound/initval.h>
29#include <sound/tlv.h>
30
31#include <linux/mfd/arizona/registers.h>
32
33#include "wm_adsp.h"
34
35#define adsp_crit(_dsp, fmt, ...) \
36 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
37#define adsp_err(_dsp, fmt, ...) \
38 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
39#define adsp_warn(_dsp, fmt, ...) \
40 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
41#define adsp_info(_dsp, fmt, ...) \
42 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
43#define adsp_dbg(_dsp, fmt, ...) \
44 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
45
46#define ADSP1_CONTROL_1 0x00
47#define ADSP1_CONTROL_2 0x02
48#define ADSP1_CONTROL_3 0x03
49#define ADSP1_CONTROL_4 0x04
50#define ADSP1_CONTROL_5 0x06
51#define ADSP1_CONTROL_6 0x07
52#define ADSP1_CONTROL_7 0x08
53#define ADSP1_CONTROL_8 0x09
54#define ADSP1_CONTROL_9 0x0A
55#define ADSP1_CONTROL_10 0x0B
56#define ADSP1_CONTROL_11 0x0C
57#define ADSP1_CONTROL_12 0x0D
58#define ADSP1_CONTROL_13 0x0F
59#define ADSP1_CONTROL_14 0x10
60#define ADSP1_CONTROL_15 0x11
61#define ADSP1_CONTROL_16 0x12
62#define ADSP1_CONTROL_17 0x13
63#define ADSP1_CONTROL_18 0x14
64#define ADSP1_CONTROL_19 0x16
65#define ADSP1_CONTROL_20 0x17
66#define ADSP1_CONTROL_21 0x18
67#define ADSP1_CONTROL_22 0x1A
68#define ADSP1_CONTROL_23 0x1B
69#define ADSP1_CONTROL_24 0x1C
70#define ADSP1_CONTROL_25 0x1E
71#define ADSP1_CONTROL_26 0x20
72#define ADSP1_CONTROL_27 0x21
73#define ADSP1_CONTROL_28 0x22
74#define ADSP1_CONTROL_29 0x23
75#define ADSP1_CONTROL_30 0x24
76#define ADSP1_CONTROL_31 0x26
77
78/*
79 * ADSP1 Control 19
80 */
81#define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
82#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
83#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
84
85
86/*
87 * ADSP1 Control 30
88 */
89#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
90#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
91#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
92#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
93#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
94#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
95#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
96#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
97#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
98#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
99#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
100#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
101#define ADSP1_START 0x0001 /* DSP1_START */
102#define ADSP1_START_MASK 0x0001 /* DSP1_START */
103#define ADSP1_START_SHIFT 0 /* DSP1_START */
104#define ADSP1_START_WIDTH 1 /* DSP1_START */
105
973838a0
MB		 106#define ADSP2_CONTROL 0
107#define ADSP2_CLOCKING 1
108#define ADSP2_STATUS1 4
2159ad93
MB		 109
110/*
111 * ADSP2 Control
112 */
113
114#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
115#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
116#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
117#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
118#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
119#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
120#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
121#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
122#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
123#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
124#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
125#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
126#define ADSP2_START 0x0001 /* DSP1_START */
127#define ADSP2_START_MASK 0x0001 /* DSP1_START */
128#define ADSP2_START_SHIFT 0 /* DSP1_START */
129#define ADSP2_START_WIDTH 1 /* DSP1_START */
130
973838a0
MB		 131/*
132 * ADSP2 clocking
133 */
134#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
135#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
136#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
137
2159ad93
MB		 138/*
139 * ADSP2 Status 1
140 */
141#define ADSP2_RAM_RDY 0x0001
142#define ADSP2_RAM_RDY_MASK 0x0001
143#define ADSP2_RAM_RDY_SHIFT 0
144#define ADSP2_RAM_RDY_WIDTH 1
145
1023dbd9
MB		 146#define WM_ADSP_NUM_FW 3
147
148static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
149 "MBC/VSS", "Tx", "Rx ANC"
150};
151
152static struct {
153 const char *file;
154} wm_adsp_fw[WM_ADSP_NUM_FW] = {
155 { .file = "mbc-vss" },
156 { .file = "tx" },
157 { .file = "rx-anc" },
158};
159
160static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
161 struct snd_ctl_elem_value *ucontrol)
162{
163 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
164 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
165 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
166
167 ucontrol->value.integer.value[0] = adsp[e->shift_l].fw;
168
169 return 0;
170}
171
172static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
173 struct snd_ctl_elem_value *ucontrol)
174{
175 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
176 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
177 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
178
179 if (ucontrol->value.integer.value[0] == adsp[e->shift_l].fw)
180 return 0;
181
182 if (ucontrol->value.integer.value[0] >= WM_ADSP_NUM_FW)
183 return -EINVAL;
184
185 if (adsp[e->shift_l].running)
186 return -EBUSY;
187
188 adsp->fw = ucontrol->value.integer.value[0];
189
190 return 0;
191}
192
193static const struct soc_enum wm_adsp_fw_enum[] = {
194 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
195 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
196 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
197 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
198};
199
200const struct snd_kcontrol_new wm_adsp_fw_controls[] = {
201 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
202 wm_adsp_fw_get, wm_adsp_fw_put),
203 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
204 wm_adsp_fw_get, wm_adsp_fw_put),
205 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
206 wm_adsp_fw_get, wm_adsp_fw_put),
207 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
208 wm_adsp_fw_get, wm_adsp_fw_put),
209};
210EXPORT_SYMBOL_GPL(wm_adsp_fw_controls);
2159ad93
MB		 211
212static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
213 int type)
214{
215 int i;
216
217 for (i = 0; i < dsp->num_mems; i++)
218 if (dsp->mem[i].type == type)
219 return &dsp->mem[i];
220
221 return NULL;
222}
223
45b9ee72
MB		 224static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *region,
225 unsigned int offset)
226{
227 switch (region->type) {
228 case WMFW_ADSP1_PM:
229 return region->base + (offset * 3);
230 case WMFW_ADSP1_DM:
231 return region->base + (offset * 2);
232 case WMFW_ADSP2_XM:
233 return region->base + (offset * 2);
234 case WMFW_ADSP2_YM:
235 return region->base + (offset * 2);
236 case WMFW_ADSP1_ZM:
237 return region->base + (offset * 2);
238 default:
239 WARN_ON(NULL != "Unknown memory region type");
240 return offset;
241 }
242}
243
2159ad93
MB		 244static int wm_adsp_load(struct wm_adsp *dsp)
245{
246 const struct firmware *firmware;
247 struct regmap *regmap = dsp->regmap;
248 unsigned int pos = 0;
249 const struct wmfw_header *header;
250 const struct wmfw_adsp1_sizes *adsp1_sizes;
251 const struct wmfw_adsp2_sizes *adsp2_sizes;
252 const struct wmfw_footer *footer;
253 const struct wmfw_region *region;
254 const struct wm_adsp_region *mem;
255 const char *region_name;
256 char *file, *text;
257 unsigned int reg;
258 int regions = 0;
259 int ret, offset, type, sizes;
260
261 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
262 if (file == NULL)
263 return -ENOMEM;
264
1023dbd9
MB		 265 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
266 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 267 file[PAGE_SIZE - 1] = '\0';
268
269 ret = request_firmware(&firmware, file, dsp->dev);
270 if (ret != 0) {
271 adsp_err(dsp, "Failed to request '%s'\n", file);
272 goto out;
273 }
274 ret = -EINVAL;
275
276 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
277 if (pos >= firmware->size) {
278 adsp_err(dsp, "%s: file too short, %zu bytes\n",
279 file, firmware->size);
280 goto out_fw;
281 }
282
283 header = (void*)&firmware->data[0];
284
285 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
286 adsp_err(dsp, "%s: invalid magic\n", file);
287 goto out_fw;
288 }
289
290 if (header->ver != 0) {
291 adsp_err(dsp, "%s: unknown file format %d\n",
292 file, header->ver);
293 goto out_fw;
294 }
295
296 if (header->core != dsp->type) {
297 adsp_err(dsp, "%s: invalid core %d != %d\n",
298 file, header->core, dsp->type);
299 goto out_fw;
300 }
301
302 switch (dsp->type) {
303 case WMFW_ADSP1:
304 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
305 adsp1_sizes = (void *)&(header[1]);
306 footer = (void *)&(adsp1_sizes[1]);
307 sizes = sizeof(*adsp1_sizes);
308
309 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
310 file, le32_to_cpu(adsp1_sizes->dm),
311 le32_to_cpu(adsp1_sizes->pm),
312 le32_to_cpu(adsp1_sizes->zm));
313 break;
314
315 case WMFW_ADSP2:
316 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
317 adsp2_sizes = (void *)&(header[1]);
318 footer = (void *)&(adsp2_sizes[1]);
319 sizes = sizeof(*adsp2_sizes);
320
321 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
322 file, le32_to_cpu(adsp2_sizes->xm),
323 le32_to_cpu(adsp2_sizes->ym),
324 le32_to_cpu(adsp2_sizes->pm),
325 le32_to_cpu(adsp2_sizes->zm));
326 break;
327
328 default:
329 BUG_ON(NULL == "Unknown DSP type");
330 goto out_fw;
331 }
332
333 if (le32_to_cpu(header->len) != sizeof(*header) +
334 sizes + sizeof(*footer)) {
335 adsp_err(dsp, "%s: unexpected header length %d\n",
336 file, le32_to_cpu(header->len));
337 goto out_fw;
338 }
339
340 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
341 le64_to_cpu(footer->timestamp));
342
343 while (pos < firmware->size &&
344 pos - firmware->size > sizeof(*region)) {
345 region = (void *)&(firmware->data[pos]);
346 region_name = "Unknown";
347 reg = 0;
348 text = NULL;
349 offset = le32_to_cpu(region->offset) & 0xffffff;
350 type = be32_to_cpu(region->type) & 0xff;
351 mem = wm_adsp_find_region(dsp, type);
352
353 switch (type) {
354 case WMFW_NAME_TEXT:
355 region_name = "Firmware name";
356 text = kzalloc(le32_to_cpu(region->len) + 1,
357 GFP_KERNEL);
358 break;
359 case WMFW_INFO_TEXT:
360 region_name = "Information";
361 text = kzalloc(le32_to_cpu(region->len) + 1,
362 GFP_KERNEL);
363 break;
364 case WMFW_ABSOLUTE:
365 region_name = "Absolute";
366 reg = offset;
367 break;
368 case WMFW_ADSP1_PM:
369 BUG_ON(!mem);
370 region_name = "PM";
45b9ee72 371 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 372 break;
373 case WMFW_ADSP1_DM:
374 BUG_ON(!mem);
375 region_name = "DM";
45b9ee72 376 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 377 break;
378 case WMFW_ADSP2_XM:
379 BUG_ON(!mem);
380 region_name = "XM";
45b9ee72 381 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 382 break;
383 case WMFW_ADSP2_YM:
384 BUG_ON(!mem);
385 region_name = "YM";
45b9ee72 386 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 387 break;
388 case WMFW_ADSP1_ZM:
389 BUG_ON(!mem);
390 region_name = "ZM";
45b9ee72 391 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 392 break;
393 default:
394 adsp_warn(dsp,
395 "%s.%d: Unknown region type %x at %d(%x)\n",
396 file, regions, type, pos, pos);
397 break;
398 }
399
400 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
401 regions, le32_to_cpu(region->len), offset,
402 region_name);
403
404 if (text) {
405 memcpy(text, region->data, le32_to_cpu(region->len));
406 adsp_info(dsp, "%s: %s\n", file, text);
407 kfree(text);
408 }
409
410 if (reg) {
411 ret = regmap_raw_write(regmap, reg, region->data,
412 le32_to_cpu(region->len));
413 if (ret != 0) {
414 adsp_err(dsp,
415 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
416 file, regions,
417 le32_to_cpu(region->len), offset,
418 region_name, ret);
419 goto out_fw;
420 }
421 }
422
423 pos += le32_to_cpu(region->len) + sizeof(*region);
424 regions++;
425 }
426
427 if (pos > firmware->size)
428 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
429 file, regions, pos - firmware->size);
430
431out_fw:
432 release_firmware(firmware);
433out:
434 kfree(file);
435
436 return ret;
437}
438
db40517c
MB		 439static int wm_adsp_setup_algs(struct wm_adsp *dsp)
440{
441 struct regmap *regmap = dsp->regmap;
442 struct wmfw_adsp1_id_hdr adsp1_id;
443 struct wmfw_adsp2_id_hdr adsp2_id;
444 struct wmfw_adsp1_alg_hdr *adsp1_alg;
445 struct wmfw_adsp2_alg_hdr *adsp2_alg;
d62f4bc6 446 void *alg, *buf;
471f4885 447 struct wm_adsp_alg_region *region;
db40517c
MB		 448 const struct wm_adsp_region *mem;
449 unsigned int pos, term;
d62f4bc6 450 size_t algs, buf_size;
db40517c
MB		 451 __be32 val;
452 int i, ret;
453
454 switch (dsp->type) {
455 case WMFW_ADSP1:
456 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
457 break;
458 case WMFW_ADSP2:
459 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
460 break;
461 default:
462 mem = NULL;
463 break;
464 }
465
466 if (mem == NULL) {
467 BUG_ON(mem != NULL);
468 return -EINVAL;
469 }
470
471 switch (dsp->type) {
472 case WMFW_ADSP1:
473 ret = regmap_raw_read(regmap, mem->base, &adsp1_id,
474 sizeof(adsp1_id));
475 if (ret != 0) {
476 adsp_err(dsp, "Failed to read algorithm info: %d\n",
477 ret);
478 return ret;
479 }
480
d62f4bc6
MB		 481 buf = &adsp1_id;
482 buf_size = sizeof(adsp1_id);
483
db40517c
MB		 484 algs = be32_to_cpu(adsp1_id.algs);
485 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
486 be32_to_cpu(adsp1_id.fw.id),
487 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
488 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
489 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
490 algs);
491
492 pos = sizeof(adsp1_id) / 2;
493 term = pos + ((sizeof(*adsp1_alg) * algs) / 2);
494 break;
495
496 case WMFW_ADSP2:
497 ret = regmap_raw_read(regmap, mem->base, &adsp2_id,
498 sizeof(adsp2_id));
499 if (ret != 0) {
500 adsp_err(dsp, "Failed to read algorithm info: %d\n",
501 ret);
502 return ret;
503 }
504
d62f4bc6
MB		 505 buf = &adsp2_id;
506 buf_size = sizeof(adsp2_id);
507
db40517c
MB		 508 algs = be32_to_cpu(adsp2_id.algs);
509 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
510 be32_to_cpu(adsp2_id.fw.id),
511 (be32_to_cpu(adsp2_id.fw.ver) & 0xff0000) >> 16,
512 (be32_to_cpu(adsp2_id.fw.ver) & 0xff00) >> 8,
513 be32_to_cpu(adsp2_id.fw.ver) & 0xff,
514 algs);
515
516 pos = sizeof(adsp2_id) / 2;
517 term = pos + ((sizeof(*adsp2_alg) * algs) / 2);
518 break;
519
520 default:
521 BUG_ON(NULL == "Unknown DSP type");
522 return -EINVAL;
523 }
524
525 if (algs == 0) {
526 adsp_err(dsp, "No algorithms\n");
527 return -EINVAL;
528 }
529
d62f4bc6
MB		 530 if (algs > 1024) {
531 adsp_err(dsp, "Algorithm count %zx excessive\n", algs);
532 print_hex_dump_bytes(dev_name(dsp->dev), DUMP_PREFIX_OFFSET,
533 buf, buf_size);
534 return -EINVAL;
535 }
536
db40517c
MB		 537 /* Read the terminator first to validate the length */
538 ret = regmap_raw_read(regmap, mem->base + term, &val, sizeof(val));
539 if (ret != 0) {
540 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
541 ret);
542 return ret;
543 }
544
545 if (be32_to_cpu(val) != 0xbedead)
546 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
547 term, be32_to_cpu(val));
548
549 alg = kzalloc((term - pos) * 2, GFP_KERNEL);
550 if (!alg)
551 return -ENOMEM;
552
553 ret = regmap_raw_read(regmap, mem->base + pos, alg, (term - pos) * 2);
554 if (ret != 0) {
555 adsp_err(dsp, "Failed to read algorithm list: %d\n",
556 ret);
557 goto out;
558 }
559
560 adsp1_alg = alg;
561 adsp2_alg = alg;
562
563 for (i = 0; i < algs; i++) {
564 switch (dsp->type) {
565 case WMFW_ADSP1:
471f4885 566 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
db40517c
MB		 567 i, be32_to_cpu(adsp1_alg[i].alg.id),
568 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
569 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
471f4885
MB		 570 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
571 be32_to_cpu(adsp1_alg[i].dm),
572 be32_to_cpu(adsp1_alg[i].zm));
573
574 if (adsp1_alg[i].dm) {
575 region = kzalloc(sizeof(*region), GFP_KERNEL);
576 if (!region)
577 return -ENOMEM;
578 region->type = WMFW_ADSP1_DM;
579 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
580 region->base = be32_to_cpu(adsp1_alg[i].dm);
581 list_add_tail(&region->list,
582 &dsp->alg_regions);
583 }
584
585 if (adsp1_alg[i].zm) {
586 region = kzalloc(sizeof(*region), GFP_KERNEL);
587 if (!region)
588 return -ENOMEM;
589 region->type = WMFW_ADSP1_ZM;
590 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
591 region->base = be32_to_cpu(adsp1_alg[i].zm);
592 list_add_tail(&region->list,
593 &dsp->alg_regions);
594 }
db40517c
MB		 595 break;
596
597 case WMFW_ADSP2:
471f4885
MB		 598 adsp_info(dsp,
599 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
db40517c
MB		 600 i, be32_to_cpu(adsp2_alg[i].alg.id),
601 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
602 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
471f4885
MB		 603 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
604 be32_to_cpu(adsp2_alg[i].xm),
605 be32_to_cpu(adsp2_alg[i].ym),
606 be32_to_cpu(adsp2_alg[i].zm));
607
608 if (adsp2_alg[i].xm) {
609 region = kzalloc(sizeof(*region), GFP_KERNEL);
610 if (!region)
611 return -ENOMEM;
612 region->type = WMFW_ADSP2_XM;
613 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
614 region->base = be32_to_cpu(adsp2_alg[i].xm);
615 list_add_tail(&region->list,
616 &dsp->alg_regions);
617 }
618
619 if (adsp2_alg[i].ym) {
620 region = kzalloc(sizeof(*region), GFP_KERNEL);
621 if (!region)
622 return -ENOMEM;
623 region->type = WMFW_ADSP2_YM;
624 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
625 region->base = be32_to_cpu(adsp2_alg[i].ym);
626 list_add_tail(&region->list,
627 &dsp->alg_regions);
628 }
629
630 if (adsp2_alg[i].zm) {
631 region = kzalloc(sizeof(*region), GFP_KERNEL);
632 if (!region)
633 return -ENOMEM;
634 region->type = WMFW_ADSP2_ZM;
635 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
636 region->base = be32_to_cpu(adsp2_alg[i].zm);
637 list_add_tail(&region->list,
638 &dsp->alg_regions);
639 }
db40517c
MB		 640 break;
641 }
642 }
643
644out:
645 kfree(alg);
646 return ret;
647}
648
2159ad93
MB		 649static int wm_adsp_load_coeff(struct wm_adsp *dsp)
650{
651 struct regmap *regmap = dsp->regmap;
652 struct wmfw_coeff_hdr *hdr;
653 struct wmfw_coeff_item *blk;
654 const struct firmware *firmware;
471f4885
MB		 655 const struct wm_adsp_region *mem;
656 struct wm_adsp_alg_region *alg_region;
2159ad93
MB		 657 const char *region_name;
658 int ret, pos, blocks, type, offset, reg;
659 char *file;
660
661 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
662 if (file == NULL)
663 return -ENOMEM;
664
1023dbd9
MB		 665 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
666 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 667 file[PAGE_SIZE - 1] = '\0';
668
669 ret = request_firmware(&firmware, file, dsp->dev);
670 if (ret != 0) {
671 adsp_warn(dsp, "Failed to request '%s'\n", file);
672 ret = 0;
673 goto out;
674 }
675 ret = -EINVAL;
676
677 if (sizeof(*hdr) >= firmware->size) {
678 adsp_err(dsp, "%s: file too short, %zu bytes\n",
679 file, firmware->size);
680 goto out_fw;
681 }
682
683 hdr = (void*)&firmware->data[0];
684 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
685 adsp_err(dsp, "%s: invalid magic\n", file);
686 return -EINVAL;
687 }
688
689 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
690 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
691 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
692 le32_to_cpu(hdr->ver) & 0xff);
693
694 pos = le32_to_cpu(hdr->len);
695
696 blocks = 0;
697 while (pos < firmware->size &&
698 pos - firmware->size > sizeof(*blk)) {
699 blk = (void*)(&firmware->data[pos]);
700
701 type = be32_to_cpu(blk->type) & 0xff;
702 offset = le32_to_cpu(blk->offset) & 0xffffff;
703
704 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
705 file, blocks, le32_to_cpu(blk->id),
706 (le32_to_cpu(blk->ver) >> 16) & 0xff,
707 (le32_to_cpu(blk->ver) >> 8) & 0xff,
708 le32_to_cpu(blk->ver) & 0xff);
709 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
710 file, blocks, le32_to_cpu(blk->len), offset, type);
711
712 reg = 0;
713 region_name = "Unknown";
714 switch (type) {
715 case WMFW_NAME_TEXT:
716 case WMFW_INFO_TEXT:
717 break;
718 case WMFW_ABSOLUTE:
719 region_name = "register";
720 reg = offset;
721 break;
471f4885
MB		 722
723 case WMFW_ADSP1_DM:
724 case WMFW_ADSP1_ZM:
725 case WMFW_ADSP2_XM:
726 case WMFW_ADSP2_YM:
727 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
728 file, blocks, le32_to_cpu(blk->len),
729 type, le32_to_cpu(blk->id));
730
731 mem = wm_adsp_find_region(dsp, type);
732 if (!mem) {
733 adsp_err(dsp, "No base for region %x\n", type);
734 break;
735 }
736
737 reg = 0;
738 list_for_each_entry(alg_region,
739 &dsp->alg_regions, list) {
740 if (le32_to_cpu(blk->id) == alg_region->alg &&
741 type == alg_region->type) {
742 reg = alg_region->base + offset;
743 reg = wm_adsp_region_to_reg(mem,
744 reg);
745 }
746 }
747
748 if (reg == 0)
749 adsp_err(dsp, "No %x for algorithm %x\n",
750 type, le32_to_cpu(blk->id));
751 break;
752
2159ad93
MB		 753 default:
754 adsp_err(dsp, "Unknown region type %x\n", type);
755 break;
756 }
757
758 if (reg) {
759 ret = regmap_raw_write(regmap, reg, blk->data,
760 le32_to_cpu(blk->len));
761 if (ret != 0) {
762 adsp_err(dsp,
763 "%s.%d: Failed to write to %x in %s\n",
764 file, blocks, reg, region_name);
765 }
766 }
767
768 pos += le32_to_cpu(blk->len) + sizeof(*blk);
769 blocks++;
770 }
771
772 if (pos > firmware->size)
773 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
774 file, blocks, pos - firmware->size);
775
776out_fw:
777 release_firmware(firmware);
778out:
779 kfree(file);
780 return 0;
781}
782
5e7a7a22
MB		 783int wm_adsp1_init(struct wm_adsp *adsp)
784{
785 INIT_LIST_HEAD(&adsp->alg_regions);
786
787 return 0;
788}
789EXPORT_SYMBOL_GPL(wm_adsp1_init);
790
2159ad93
MB		 791int wm_adsp1_event(struct snd_soc_dapm_widget *w,
792 struct snd_kcontrol *kcontrol,
793 int event)
794{
795 struct snd_soc_codec *codec = w->codec;
796 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
797 struct wm_adsp *dsp = &dsps[w->shift];
798 int ret;
799
800 switch (event) {
801 case SND_SOC_DAPM_POST_PMU:
802 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
803 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
804
805 ret = wm_adsp_load(dsp);
806 if (ret != 0)
807 goto err;
808
db40517c
MB		 809 ret = wm_adsp_setup_algs(dsp);
810 if (ret != 0)
811 goto err;
812
2159ad93
MB		 813 ret = wm_adsp_load_coeff(dsp);
814 if (ret != 0)
815 goto err;
816
817 /* Start the core running */
818 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
819 ADSP1_CORE_ENA | ADSP1_START,
820 ADSP1_CORE_ENA | ADSP1_START);
821 break;
822
823 case SND_SOC_DAPM_PRE_PMD:
824 /* Halt the core */
825 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
826 ADSP1_CORE_ENA | ADSP1_START, 0);
827
828 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
829 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
830
831 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
832 ADSP1_SYS_ENA, 0);
833 break;
834
835 default:
836 break;
837 }
838
839 return 0;
840
841err:
842 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
843 ADSP1_SYS_ENA, 0);
844 return ret;
845}
846EXPORT_SYMBOL_GPL(wm_adsp1_event);
847
848static int wm_adsp2_ena(struct wm_adsp *dsp)
849{
850 unsigned int val;
851 int ret, count;
852
853 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
854 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
855 if (ret != 0)
856 return ret;
857
858 /* Wait for the RAM to start, should be near instantaneous */
859 count = 0;
860 do {
861 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1,
862 &val);
863 if (ret != 0)
864 return ret;
865 } while (!(val & ADSP2_RAM_RDY) && ++count < 10);
866
867 if (!(val & ADSP2_RAM_RDY)) {
868 adsp_err(dsp, "Failed to start DSP RAM\n");
869 return -EBUSY;
870 }
871
872 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
873 adsp_info(dsp, "RAM ready after %d polls\n", count);
874
875 return 0;
876}
877
878int wm_adsp2_event(struct snd_soc_dapm_widget *w,
879 struct snd_kcontrol *kcontrol, int event)
880{
881 struct snd_soc_codec *codec = w->codec;
882 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
883 struct wm_adsp *dsp = &dsps[w->shift];
471f4885 884 struct wm_adsp_alg_region *alg_region;
973838a0 885 unsigned int val;
2159ad93
MB		 886 int ret;
887
888 switch (event) {
889 case SND_SOC_DAPM_POST_PMU:
dd49e2c8
MB		 890 /*
891 * For simplicity set the DSP clock rate to be the
892 * SYSCLK rate rather than making it configurable.
893 */
894 ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
895 if (ret != 0) {
896 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
897 ret);
898 return ret;
899 }
900 val = (val & ARIZONA_SYSCLK_FREQ_MASK)
901 >> ARIZONA_SYSCLK_FREQ_SHIFT;
902
903 ret = regmap_update_bits(dsp->regmap,
904 dsp->base + ADSP2_CLOCKING,
905 ADSP2_CLK_SEL_MASK, val);
906 if (ret != 0) {
907 adsp_err(dsp, "Failed to set clock rate: %d\n",
908 ret);
909 return ret;
910 }
911
973838a0
MB		 912 if (dsp->dvfs) {
913 ret = regmap_read(dsp->regmap,
914 dsp->base + ADSP2_CLOCKING, &val);
915 if (ret != 0) {
916 dev_err(dsp->dev,
917 "Failed to read clocking: %d\n", ret);
918 return ret;
919 }
920
25c6fdb0 921 if ((val & ADSP2_CLK_SEL_MASK) >= 3) {
973838a0
MB		 922 ret = regulator_enable(dsp->dvfs);
923 if (ret != 0) {
924 dev_err(dsp->dev,
925 "Failed to enable supply: %d\n",
926 ret);
927 return ret;
928 }
929
930 ret = regulator_set_voltage(dsp->dvfs,
931 1800000,
932 1800000);
933 if (ret != 0) {
934 dev_err(dsp->dev,
935 "Failed to raise supply: %d\n",
936 ret);
937 return ret;
938 }
939 }
940 }
941
2159ad93
MB		 942 ret = wm_adsp2_ena(dsp);
943 if (ret != 0)
944 return ret;
945
946 ret = wm_adsp_load(dsp);
947 if (ret != 0)
948 goto err;
949
db40517c
MB		 950 ret = wm_adsp_setup_algs(dsp);
951 if (ret != 0)
952 goto err;
953
2159ad93
MB		 954 ret = wm_adsp_load_coeff(dsp);
955 if (ret != 0)
956 goto err;
957
958 ret = regmap_update_bits(dsp->regmap,
959 dsp->base + ADSP2_CONTROL,
a7f9be7e
MB		 960 ADSP2_CORE_ENA | ADSP2_START,
961 ADSP2_CORE_ENA | ADSP2_START);
2159ad93
MB		 962 if (ret != 0)
963 goto err;
1023dbd9
MB		 964
965 dsp->running = true;
2159ad93
MB		 966 break;
967
968 case SND_SOC_DAPM_PRE_PMD:
1023dbd9
MB		 969 dsp->running = false;
970
2159ad93 971 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e
MB		 972 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
973 ADSP2_START, 0);
973838a0
MB		 974
975 if (dsp->dvfs) {
976 ret = regulator_set_voltage(dsp->dvfs, 1200000,
977 1800000);
978 if (ret != 0)
979 dev_warn(dsp->dev,
980 "Failed to lower supply: %d\n",
981 ret);
982
983 ret = regulator_disable(dsp->dvfs);
984 if (ret != 0)
985 dev_err(dsp->dev,
986 "Failed to enable supply: %d\n",
987 ret);
988 }
471f4885
MB		 989
990 while (!list_empty(&dsp->alg_regions)) {
991 alg_region = list_first_entry(&dsp->alg_regions,
992 struct wm_adsp_alg_region,
993 list);
994 list_del(&alg_region->list);
995 kfree(alg_region);
996 }
2159ad93
MB		 997 break;
998
999 default:
1000 break;
1001 }
1002
1003 return 0;
1004err:
1005 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e 1006 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2159ad93
MB		 1007 return ret;
1008}
1009EXPORT_SYMBOL_GPL(wm_adsp2_event);
973838a0
MB		 1010
1011int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs)
1012{
1013 int ret;
1014
10a2b662
MB		 1015 /*
1016 * Disable the DSP memory by default when in reset for a small
1017 * power saving.
1018 */
1019 ret = regmap_update_bits(adsp->regmap, adsp->base + ADSP2_CONTROL,
1020 ADSP2_MEM_ENA, 0);
1021 if (ret != 0) {
1022 adsp_err(adsp, "Failed to clear memory retention: %d\n", ret);
1023 return ret;
1024 }
1025
471f4885
MB		 1026 INIT_LIST_HEAD(&adsp->alg_regions);
1027
973838a0
MB		 1028 if (dvfs) {
1029 adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD");
1030 if (IS_ERR(adsp->dvfs)) {
1031 ret = PTR_ERR(adsp->dvfs);
1032 dev_err(adsp->dev, "Failed to get DCVDD: %d\n", ret);
1033 return ret;
1034 }
1035
1036 ret = regulator_enable(adsp->dvfs);
1037 if (ret != 0) {
1038 dev_err(adsp->dev, "Failed to enable DCVDD: %d\n",
1039 ret);
1040 return ret;
1041 }
1042
1043 ret = regulator_set_voltage(adsp->dvfs, 1200000, 1800000);
1044 if (ret != 0) {
1045 dev_err(adsp->dev, "Failed to initialise DVFS: %d\n",
1046 ret);
1047 return ret;
1048 }
1049
1050 ret = regulator_disable(adsp->dvfs);
1051 if (ret != 0) {
1052 dev_err(adsp->dev, "Failed to disable DCVDD: %d\n",
1053 ret);
1054 return ret;
1055 }
1056 }
1057
1058 return 0;
1059}
1060EXPORT_SYMBOL_GPL(wm_adsp2_init);
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