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edac: Don't initialize csrow's first_page & friends when not needed
[linux.git] / drivers / edac / sb_edac.c
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eebf11a0
MCC		 1/* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
2 *
3 * This driver supports the memory controllers found on the Intel
4 * processor family Sandy Bridge.
5 *
6 * This file may be distributed under the terms of the
7 * GNU General Public License version 2 only.
8 *
9 * Copyright (c) 2011 by:
10 * Mauro Carvalho Chehab <[email protected]>
11 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16#include <linux/pci_ids.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/edac.h>
20#include <linux/mmzone.h>
eebf11a0
MCC		 21#include <linux/smp.h>
22#include <linux/bitmap.h>
5b889e37 23#include <linux/math64.h>
eebf11a0 24#include <asm/processor.h>
3d78c9af 25#include <asm/mce.h>
eebf11a0
MCC		 26
27#include "edac_core.h"
28
29/* Static vars */
30static LIST_HEAD(sbridge_edac_list);
31static DEFINE_MUTEX(sbridge_edac_lock);
32static int probed;
33
34/*
35 * Alter this version for the module when modifications are made
36 */
37#define SBRIDGE_REVISION " Ver: 1.0.0 "
38#define EDAC_MOD_STR "sbridge_edac"
39
40/*
41 * Debug macros
42 */
43#define sbridge_printk(level, fmt, arg...) \
44 edac_printk(level, "sbridge", fmt, ##arg)
45
46#define sbridge_mc_printk(mci, level, fmt, arg...) \
47 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
48
49/*
50 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
51 */
52#define GET_BITFIELD(v, lo, hi) \
53 (((v) & ((1ULL << ((hi) - (lo) + 1)) - 1) << (lo)) >> (lo))
54
55/*
56 * sbridge Memory Controller Registers
57 */
58
59/*
60 * FIXME: For now, let's order by device function, as it makes
61 * easier for driver's development proccess. This table should be
62 * moved to pci_id.h when submitted upstream
63 */
64#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */
65#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */
66#define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */
67#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */
68#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */
69#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */
70#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */
71#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */
72#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */
73#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */
74#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */
75
76 /*
77 * Currently, unused, but will be needed in the future
78 * implementations, as they hold the error counters
79 */
80#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */
81#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */
82#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */
83#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */
84
85/* Devices 12 Function 6, Offsets 0x80 to 0xcc */
86static const u32 dram_rule[] = {
87 0x80, 0x88, 0x90, 0x98, 0xa0,
88 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
89};
90#define MAX_SAD ARRAY_SIZE(dram_rule)
91
92#define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff)
93#define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3)
94#define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1)
95#define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
96
97static char *get_dram_attr(u32 reg)
98{
99 switch(DRAM_ATTR(reg)) {
100 case 0:
101 return "DRAM";
102 case 1:
103 return "MMCFG";
104 case 2:
105 return "NXM";
106 default:
107 return "unknown";
108 }
109}
110
111static const u32 interleave_list[] = {
112 0x84, 0x8c, 0x94, 0x9c, 0xa4,
113 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
114};
115#define MAX_INTERLEAVE ARRAY_SIZE(interleave_list)
116
117#define SAD_PKG0(reg) GET_BITFIELD(reg, 0, 2)
118#define SAD_PKG1(reg) GET_BITFIELD(reg, 3, 5)
119#define SAD_PKG2(reg) GET_BITFIELD(reg, 8, 10)
120#define SAD_PKG3(reg) GET_BITFIELD(reg, 11, 13)
121#define SAD_PKG4(reg) GET_BITFIELD(reg, 16, 18)
122#define SAD_PKG5(reg) GET_BITFIELD(reg, 19, 21)
123#define SAD_PKG6(reg) GET_BITFIELD(reg, 24, 26)
124#define SAD_PKG7(reg) GET_BITFIELD(reg, 27, 29)
125
126static inline int sad_pkg(u32 reg, int interleave)
127{
128 switch (interleave) {
129 case 0:
130 return SAD_PKG0(reg);
131 case 1:
132 return SAD_PKG1(reg);
133 case 2:
134 return SAD_PKG2(reg);
135 case 3:
136 return SAD_PKG3(reg);
137 case 4:
138 return SAD_PKG4(reg);
139 case 5:
140 return SAD_PKG5(reg);
141 case 6:
142 return SAD_PKG6(reg);
143 case 7:
144 return SAD_PKG7(reg);
145 default:
146 return -EINVAL;
147 }
148}
149
150/* Devices 12 Function 7 */
151
152#define TOLM 0x80
153#define TOHM 0x84
154
155#define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
156#define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
157
158/* Device 13 Function 6 */
159
160#define SAD_TARGET 0xf0
161
162#define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
163
164#define SAD_CONTROL 0xf4
165
166#define NODE_ID(reg) GET_BITFIELD(reg, 0, 2)
167
168/* Device 14 function 0 */
169
170static const u32 tad_dram_rule[] = {
171 0x40, 0x44, 0x48, 0x4c,
172 0x50, 0x54, 0x58, 0x5c,
173 0x60, 0x64, 0x68, 0x6c,
174};
175#define MAX_TAD ARRAY_SIZE(tad_dram_rule)
176
177#define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
178#define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
179#define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
180#define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
181#define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
182#define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
183#define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
184
185/* Device 15, function 0 */
186
187#define MCMTR 0x7c
188
189#define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
190#define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
191#define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
192
193/* Device 15, function 1 */
194
195#define RASENABLES 0xac
196#define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
197
198/* Device 15, functions 2-5 */
199
200static const int mtr_regs[] = {
201 0x80, 0x84, 0x88,
202};
203
204#define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
205#define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
206#define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
207#define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
208#define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
209
210static const u32 tad_ch_nilv_offset[] = {
211 0x90, 0x94, 0x98, 0x9c,
212 0xa0, 0xa4, 0xa8, 0xac,
213 0xb0, 0xb4, 0xb8, 0xbc,
214};
215#define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
216#define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
217
218static const u32 rir_way_limit[] = {
219 0x108, 0x10c, 0x110, 0x114, 0x118,
220};
221#define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
222
223#define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
224#define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
225#define RIR_LIMIT(reg) ((GET_BITFIELD(reg, 1, 10) << 29)| 0x1fffffff)
226
227#define MAX_RIR_WAY 8
228
229static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
230 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
231 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
232 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
233 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
234 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
235};
236
237#define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19)
238#define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14)
239
240/* Device 16, functions 2-7 */
241
242/*
243 * FIXME: Implement the error count reads directly
244 */
245
246static const u32 correrrcnt[] = {
247 0x104, 0x108, 0x10c, 0x110,
248};
249
250#define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
251#define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
252#define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
253#define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
254
255static const u32 correrrthrsld[] = {
256 0x11c, 0x120, 0x124, 0x128,
257};
258
259#define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
260#define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
261
262
263/* Device 17, function 0 */
264
265#define RANK_CFG_A 0x0328
266
267#define IS_RDIMM_ENABLED(reg) GET_BITFIELD(reg, 11, 11)
268
269/*
270 * sbridge structs
271 */
272
273#define NUM_CHANNELS 4
274#define MAX_DIMMS 3 /* Max DIMMS per channel */
275
276struct sbridge_info {
277 u32 mcmtr;
278};
279
280struct sbridge_channel {
281 u32 ranks;
282 u32 dimms;
283};
284
285struct pci_id_descr {
286 int dev;
287 int func;
288 int dev_id;
289 int optional;
290};
291
292struct pci_id_table {
293 const struct pci_id_descr *descr;
294 int n_devs;
295};
296
297struct sbridge_dev {
298 struct list_head list;
299 u8 bus, mc;
300 u8 node_id, source_id;
301 struct pci_dev **pdev;
302 int n_devs;
303 struct mem_ctl_info *mci;
304};
305
306struct sbridge_pvt {
307 struct pci_dev *pci_ta, *pci_ddrio, *pci_ras;
308 struct pci_dev *pci_sad0, *pci_sad1, *pci_ha0;
309 struct pci_dev *pci_br;
310 struct pci_dev *pci_tad[NUM_CHANNELS];
311
312 struct sbridge_dev *sbridge_dev;
313
314 struct sbridge_info info;
315 struct sbridge_channel channel[NUM_CHANNELS];
316
317 int csrow_map[NUM_CHANNELS][MAX_DIMMS];
318
319 /* Memory type detection */
320 bool is_mirrored, is_lockstep, is_close_pg;
321
eebf11a0
MCC		 322 /* Fifo double buffers */
323 struct mce mce_entry[MCE_LOG_LEN];
324 struct mce mce_outentry[MCE_LOG_LEN];
325
326 /* Fifo in/out counters */
327 unsigned mce_in, mce_out;
328
329 /* Count indicator to show errors not got */
330 unsigned mce_overrun;
331
332 /* Memory description */
333 u64 tolm, tohm;
334};
335
336#define PCI_DESCR(device, function, device_id) \
337 .dev = (device), \
338 .func = (function), \
339 .dev_id = (device_id)
340
341static const struct pci_id_descr pci_dev_descr_sbridge[] = {
342 /* Processor Home Agent */
343 { PCI_DESCR(14, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0) },
344
345 /* Memory controller */
346 { PCI_DESCR(15, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA) },
347 { PCI_DESCR(15, 1, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS) },
348 { PCI_DESCR(15, 2, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0) },
349 { PCI_DESCR(15, 3, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1) },
350 { PCI_DESCR(15, 4, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2) },
351 { PCI_DESCR(15, 5, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3) },
352 { PCI_DESCR(17, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO) },
353
354 /* System Address Decoder */
355 { PCI_DESCR(12, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0) },
356 { PCI_DESCR(12, 7, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1) },
357
358 /* Broadcast Registers */
359 { PCI_DESCR(13, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_BR) },
360};
361
362#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
363static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
364 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
365 {0,} /* 0 terminated list. */
366};
367
368/*
369 * pci_device_id table for which devices we are looking for
370 */
36c46f31 371static DEFINE_PCI_DEVICE_TABLE(sbridge_pci_tbl) = {
eebf11a0
MCC		 372 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)},
373 {0,} /* 0 terminated list. */
374};
375
376
377/****************************************************************************
378 Anciliary status routines
379 ****************************************************************************/
380
381static inline int numrank(u32 mtr)
382{
383 int ranks = (1 << RANK_CNT_BITS(mtr));
384
385 if (ranks > 4) {
386 debugf0("Invalid number of ranks: %d (max = 4) raw value = %x (%04x)",
387 ranks, (unsigned int)RANK_CNT_BITS(mtr), mtr);
388 return -EINVAL;
389 }
390
391 return ranks;
392}
393
394static inline int numrow(u32 mtr)
395{
396 int rows = (RANK_WIDTH_BITS(mtr) + 12);
397
398 if (rows < 13 || rows > 18) {
399 debugf0("Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)",
400 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
401 return -EINVAL;
402 }
403
404 return 1 << rows;
405}
406
407static inline int numcol(u32 mtr)
408{
409 int cols = (COL_WIDTH_BITS(mtr) + 10);
410
411 if (cols > 12) {
412 debugf0("Invalid number of cols: %d (max = 4) raw value = %x (%04x)",
413 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
414 return -EINVAL;
415 }
416
417 return 1 << cols;
418}
419
420static struct sbridge_dev *get_sbridge_dev(u8 bus)
421{
422 struct sbridge_dev *sbridge_dev;
423
424 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
425 if (sbridge_dev->bus == bus)
426 return sbridge_dev;
427 }
428
429 return NULL;
430}
431
432static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
433 const struct pci_id_table *table)
434{
435 struct sbridge_dev *sbridge_dev;
436
437 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
438 if (!sbridge_dev)
439 return NULL;
440
441 sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
442 GFP_KERNEL);
443 if (!sbridge_dev->pdev) {
444 kfree(sbridge_dev);
445 return NULL;
446 }
447
448 sbridge_dev->bus = bus;
449 sbridge_dev->n_devs = table->n_devs;
450 list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
451
452 return sbridge_dev;
453}
454
455static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
456{
457 list_del(&sbridge_dev->list);
458 kfree(sbridge_dev->pdev);
459 kfree(sbridge_dev);
460}
461
462/****************************************************************************
463 Memory check routines
464 ****************************************************************************/
465static struct pci_dev *get_pdev_slot_func(u8 bus, unsigned slot,
466 unsigned func)
467{
468 struct sbridge_dev *sbridge_dev = get_sbridge_dev(bus);
469 int i;
470
471 if (!sbridge_dev)
472 return NULL;
473
474 for (i = 0; i < sbridge_dev->n_devs; i++) {
475 if (!sbridge_dev->pdev[i])
476 continue;
477
478 if (PCI_SLOT(sbridge_dev->pdev[i]->devfn) == slot &&
479 PCI_FUNC(sbridge_dev->pdev[i]->devfn) == func) {
480 debugf1("Associated %02x.%02x.%d with %p\n",
481 bus, slot, func, sbridge_dev->pdev[i]);
482 return sbridge_dev->pdev[i];
483 }
484 }
485
486 return NULL;
487}
488
489/**
490 * sbridge_get_active_channels() - gets the number of channels and csrows
491 * bus: Device bus
492 * @channels: Number of channels that will be returned
493 * @csrows: Number of csrows found
494 *
495 * Since EDAC core needs to know in advance the number of available channels
496 * and csrows, in order to allocate memory for csrows/channels, it is needed
497 * to run two similar steps. At the first step, implemented on this function,
498 * it checks the number of csrows/channels present at one socket, identified
499 * by the associated PCI bus.
500 * this is used in order to properly allocate the size of mci components.
501 * Note: one csrow is one dimm.
502 */
503static int sbridge_get_active_channels(const u8 bus, unsigned *channels,
504 unsigned *csrows)
505{
506 struct pci_dev *pdev = NULL;
507 int i, j;
508 u32 mcmtr;
509
510 *channels = 0;
511 *csrows = 0;
512
513 pdev = get_pdev_slot_func(bus, 15, 0);
514 if (!pdev) {
515 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
516 "%2x.%02d.%d!!!\n",
517 bus, 15, 0);
518 return -ENODEV;
519 }
520
521 pci_read_config_dword(pdev, MCMTR, &mcmtr);
522 if (!IS_ECC_ENABLED(mcmtr)) {
523 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
524 return -ENODEV;
525 }
526
527 for (i = 0; i < NUM_CHANNELS; i++) {
528 u32 mtr;
529
530 /* Device 15 functions 2 - 5 */
531 pdev = get_pdev_slot_func(bus, 15, 2 + i);
532 if (!pdev) {
533 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
534 "%2x.%02d.%d!!!\n",
535 bus, 15, 2 + i);
536 return -ENODEV;
537 }
538 (*channels)++;
539
540 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
541 pci_read_config_dword(pdev, mtr_regs[j], &mtr);
542 debugf1("Bus#%02x channel #%d MTR%d = %x\n", bus, i, j, mtr);
543 if (IS_DIMM_PRESENT(mtr))
544 (*csrows)++;
545 }
546 }
547
548 debugf0("Number of active channels: %d, number of active dimms: %d\n",
549 *channels, *csrows);
550
551 return 0;
552}
553
084a4fcc 554static int get_dimm_config(struct mem_ctl_info *mci)
eebf11a0
MCC		 555{
556 struct sbridge_pvt *pvt = mci->pvt_info;
557 struct csrow_info *csr;
558 int i, j, banks, ranks, rows, cols, size, npages;
559 int csrow = 0;
560 unsigned long last_page = 0;
561 u32 reg;
562 enum edac_type mode;
c6e13b52 563 enum mem_type mtype;
084a4fcc 564 struct dimm_info *dimm;
eebf11a0
MCC		 565
566 pci_read_config_dword(pvt->pci_br, SAD_TARGET, &reg);
567 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
568
569 pci_read_config_dword(pvt->pci_br, SAD_CONTROL, &reg);
570 pvt->sbridge_dev->node_id = NODE_ID(reg);
571 debugf0("mc#%d: Node ID: %d, source ID: %d\n",
572 pvt->sbridge_dev->mc,
573 pvt->sbridge_dev->node_id,
574 pvt->sbridge_dev->source_id);
575
576 pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg);
577 if (IS_MIRROR_ENABLED(reg)) {
578 debugf0("Memory mirror is enabled\n");
579 pvt->is_mirrored = true;
580 } else {
581 debugf0("Memory mirror is disabled\n");
582 pvt->is_mirrored = false;
583 }
584
585 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
586 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
587 debugf0("Lockstep is enabled\n");
588 mode = EDAC_S8ECD8ED;
589 pvt->is_lockstep = true;
590 } else {
591 debugf0("Lockstep is disabled\n");
592 mode = EDAC_S4ECD4ED;
593 pvt->is_lockstep = false;
594 }
595 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
596 debugf0("address map is on closed page mode\n");
597 pvt->is_close_pg = true;
598 } else {
599 debugf0("address map is on open page mode\n");
600 pvt->is_close_pg = false;
601 }
602
603 pci_read_config_dword(pvt->pci_ta, RANK_CFG_A, &reg);
604 if (IS_RDIMM_ENABLED(reg)) {
605 /* FIXME: Can also be LRDIMM */
606 debugf0("Memory is registered\n");
c6e13b52 607 mtype = MEM_RDDR3;
eebf11a0
MCC		 608 } else {
609 debugf0("Memory is unregistered\n");
c6e13b52 610 mtype = MEM_DDR3;
eebf11a0
MCC		 611 }
612
613 /* On all supported DDR3 DIMM types, there are 8 banks available */
614 banks = 8;
615
084a4fcc 616 dimm = mci->dimms;
eebf11a0
MCC		 617 for (i = 0; i < NUM_CHANNELS; i++) {
618 u32 mtr;
619
620 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
621 pci_read_config_dword(pvt->pci_tad[i],
622 mtr_regs[j], &mtr);
623 debugf4("Channel #%d MTR%d = %x\n", i, j, mtr);
624 if (IS_DIMM_PRESENT(mtr)) {
625 pvt->channel[i].dimms++;
626
627 ranks = numrank(mtr);
628 rows = numrow(mtr);
629 cols = numcol(mtr);
630
631 /* DDR3 has 8 I/O banks */
632 size = (rows * cols * banks * ranks) >> (20 - 3);
633 npages = MiB_TO_PAGES(size);
634
635 debugf0("mc#%d: channel %d, dimm %d, %d Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
636 pvt->sbridge_dev->mc, i, j,
637 size, npages,
638 banks, ranks, rows, cols);
eebf11a0 639
084a4fcc
MCC		 640 /*
641 * Fake stuff. This controller doesn't see
642 * csrows.
643 */
644 csr = &mci->csrows[csrow];
eebf11a0 645 csr->nr_pages = npages;
eebf11a0 646 csr->csrow_idx = csrow;
eebf11a0
MCC		 647 csr->nr_channels = 1;
648 csr->channels[0].chan_idx = i;
eebf11a0 649 pvt->csrow_map[i][j] = csrow;
eebf11a0
MCC		 650 last_page += npages;
651 csrow++;
084a4fcc
MCC		 652
653 csr->channels[0].dimm = dimm;
654 dimm->grain = 32;
655 dimm->dtype = (banks == 8) ? DEV_X8 : DEV_X4;
656 dimm->mtype = mtype;
657 dimm->edac_mode = mode;
658 snprintf(dimm->label, sizeof(dimm->label),
659 "CPU_SrcID#%u_Channel#%u_DIMM#%u",
660 pvt->sbridge_dev->source_id, i, j);
eebf11a0
MCC		 661 }
662 }
663 }
664
665 return 0;
666}
667
668static void get_memory_layout(const struct mem_ctl_info *mci)
669{
670 struct sbridge_pvt *pvt = mci->pvt_info;
671 int i, j, k, n_sads, n_tads, sad_interl;
672 u32 reg;
673 u64 limit, prv = 0;
674 u64 tmp_mb;
5b889e37 675 u32 mb, kb;
eebf11a0
MCC		 676 u32 rir_way;
677
678 /*
679 * Step 1) Get TOLM/TOHM ranges
680 */
681
682 /* Address range is 32:28 */
683 pci_read_config_dword(pvt->pci_sad1, TOLM,
684 &reg);
685 pvt->tolm = GET_TOLM(reg);
686 tmp_mb = (1 + pvt->tolm) >> 20;
687
5b889e37
MCC		 688 mb = div_u64_rem(tmp_mb, 1000, &kb);
689 debugf0("TOLM: %u.%03u GB (0x%016Lx)\n",
690 mb, kb, (u64)pvt->tolm);
eebf11a0
MCC		 691
692 /* Address range is already 45:25 */
693 pci_read_config_dword(pvt->pci_sad1, TOHM,
694 &reg);
695 pvt->tohm = GET_TOHM(reg);
696 tmp_mb = (1 + pvt->tohm) >> 20;
697
5b889e37
MCC		 698 mb = div_u64_rem(tmp_mb, 1000, &kb);
699 debugf0("TOHM: %u.%03u GB (0x%016Lx)",
700 mb, kb, (u64)pvt->tohm);
eebf11a0
MCC		 701
702 /*
703 * Step 2) Get SAD range and SAD Interleave list
704 * TAD registers contain the interleave wayness. However, it
705 * seems simpler to just discover it indirectly, with the
706 * algorithm bellow.
707 */
708 prv = 0;
709 for (n_sads = 0; n_sads < MAX_SAD; n_sads++) {
710 /* SAD_LIMIT Address range is 45:26 */
711 pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads],
712 &reg);
713 limit = SAD_LIMIT(reg);
714
715 if (!DRAM_RULE_ENABLE(reg))
716 continue;
717
718 if (limit <= prv)
719 break;
720
721 tmp_mb = (limit + 1) >> 20;
5b889e37
MCC		 722 mb = div_u64_rem(tmp_mb, 1000, &kb);
723 debugf0("SAD#%d %s up to %u.%03u GB (0x%016Lx) %s reg=0x%08x\n",
eebf11a0
MCC		 724 n_sads,
725 get_dram_attr(reg),
5b889e37 726 mb, kb,
eebf11a0
MCC		 727 ((u64)tmp_mb) << 20L,
728 INTERLEAVE_MODE(reg) ? "Interleave: 8:6" : "Interleave: [8:6]XOR[18:16]",
729 reg);
730 prv = limit;
731
732 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads],
733 &reg);
734 sad_interl = sad_pkg(reg, 0);
735 for (j = 0; j < 8; j++) {
736 if (j > 0 && sad_interl == sad_pkg(reg, j))
737 break;
738
739 debugf0("SAD#%d, interleave #%d: %d\n",
740 n_sads, j, sad_pkg(reg, j));
741 }
742 }
743
744 /*
745 * Step 3) Get TAD range
746 */
747 prv = 0;
748 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
749 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
750 &reg);
751 limit = TAD_LIMIT(reg);
752 if (limit <= prv)
753 break;
754 tmp_mb = (limit + 1) >> 20;
755
5b889e37
MCC		 756 mb = div_u64_rem(tmp_mb, 1000, &kb);
757 debugf0("TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
758 n_tads, mb, kb,
eebf11a0
MCC		 759 ((u64)tmp_mb) << 20L,
760 (u32)TAD_SOCK(reg),
761 (u32)TAD_CH(reg),
762 (u32)TAD_TGT0(reg),
763 (u32)TAD_TGT1(reg),
764 (u32)TAD_TGT2(reg),
765 (u32)TAD_TGT3(reg),
766 reg);
7fae0db4 767 prv = limit;
eebf11a0
MCC		 768 }
769
770 /*
771 * Step 4) Get TAD offsets, per each channel
772 */
773 for (i = 0; i < NUM_CHANNELS; i++) {
774 if (!pvt->channel[i].dimms)
775 continue;
776 for (j = 0; j < n_tads; j++) {
777 pci_read_config_dword(pvt->pci_tad[i],
778 tad_ch_nilv_offset[j],
779 &reg);
780 tmp_mb = TAD_OFFSET(reg) >> 20;
5b889e37
MCC		 781 mb = div_u64_rem(tmp_mb, 1000, &kb);
782 debugf0("TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
eebf11a0 783 i, j,
5b889e37 784 mb, kb,
eebf11a0
MCC		 785 ((u64)tmp_mb) << 20L,
786 reg);
787 }
788 }
789
790 /*
791 * Step 6) Get RIR Wayness/Limit, per each channel
792 */
793 for (i = 0; i < NUM_CHANNELS; i++) {
794 if (!pvt->channel[i].dimms)
795 continue;
796 for (j = 0; j < MAX_RIR_RANGES; j++) {
797 pci_read_config_dword(pvt->pci_tad[i],
798 rir_way_limit[j],
799 &reg);
800
801 if (!IS_RIR_VALID(reg))
802 continue;
803
804 tmp_mb = RIR_LIMIT(reg) >> 20;
805 rir_way = 1 << RIR_WAY(reg);
5b889e37
MCC		 806 mb = div_u64_rem(tmp_mb, 1000, &kb);
807 debugf0("CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
eebf11a0 808 i, j,
5b889e37 809 mb, kb,
eebf11a0
MCC		 810 ((u64)tmp_mb) << 20L,
811 rir_way,
812 reg);
813
814 for (k = 0; k < rir_way; k++) {
815 pci_read_config_dword(pvt->pci_tad[i],
816 rir_offset[j][k],
817 &reg);
818 tmp_mb = RIR_OFFSET(reg) << 6;
819
5b889e37
MCC		 820 mb = div_u64_rem(tmp_mb, 1000, &kb);
821 debugf0("CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
eebf11a0 822 i, j, k,
5b889e37 823 mb, kb,
eebf11a0
MCC		 824 ((u64)tmp_mb) << 20L,
825 (u32)RIR_RNK_TGT(reg),
826 reg);
827 }
828 }
829 }
830}
831
832struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
833{
834 struct sbridge_dev *sbridge_dev;
835
836 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
837 if (sbridge_dev->node_id == node_id)
838 return sbridge_dev->mci;
839 }
840 return NULL;
841}
842
843static int get_memory_error_data(struct mem_ctl_info *mci,
844 u64 addr,
845 u8 *socket,
846 long *channel_mask,
847 u8 *rank,
848 char *area_type)
849{
850 struct mem_ctl_info *new_mci;
851 struct sbridge_pvt *pvt = mci->pvt_info;
852 char msg[256];
853 int n_rir, n_sads, n_tads, sad_way, sck_xch;
854 int sad_interl, idx, base_ch;
855 int interleave_mode;
856 unsigned sad_interleave[MAX_INTERLEAVE];
857 u32 reg;
858 u8 ch_way,sck_way;
859 u32 tad_offset;
860 u32 rir_way;
5b889e37 861 u32 mb, kb;
eebf11a0
MCC		 862 u64 ch_addr, offset, limit, prv = 0;
863
864
865 /*
866 * Step 0) Check if the address is at special memory ranges
867 * The check bellow is probably enough to fill all cases where
868 * the error is not inside a memory, except for the legacy
869 * range (e. g. VGA addresses). It is unlikely, however, that the
870 * memory controller would generate an error on that range.
871 */
5b889e37 872 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
eebf11a0
MCC		 873 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
874 edac_mc_handle_ce_no_info(mci, msg);
875 return -EINVAL;
876 }
877 if (addr >= (u64)pvt->tohm) {
878 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
879 edac_mc_handle_ce_no_info(mci, msg);
880 return -EINVAL;
881 }
882
883 /*
884 * Step 1) Get socket
885 */
886 for (n_sads = 0; n_sads < MAX_SAD; n_sads++) {
887 pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads],
888 &reg);
889
890 if (!DRAM_RULE_ENABLE(reg))
891 continue;
892
893 limit = SAD_LIMIT(reg);
894 if (limit <= prv) {
895 sprintf(msg, "Can't discover the memory socket");
896 edac_mc_handle_ce_no_info(mci, msg);
897 return -EINVAL;
898 }
899 if (addr <= limit)
900 break;
901 prv = limit;
902 }
903 if (n_sads == MAX_SAD) {
904 sprintf(msg, "Can't discover the memory socket");
905 edac_mc_handle_ce_no_info(mci, msg);
906 return -EINVAL;
907 }
908 area_type = get_dram_attr(reg);
909 interleave_mode = INTERLEAVE_MODE(reg);
910
911 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads],
912 &reg);
913 sad_interl = sad_pkg(reg, 0);
914 for (sad_way = 0; sad_way < 8; sad_way++) {
915 if (sad_way > 0 && sad_interl == sad_pkg(reg, sad_way))
916 break;
917 sad_interleave[sad_way] = sad_pkg(reg, sad_way);
918 debugf0("SAD interleave #%d: %d\n",
919 sad_way, sad_interleave[sad_way]);
920 }
921 debugf0("mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
922 pvt->sbridge_dev->mc,
923 n_sads,
924 addr,
925 limit,
926 sad_way + 7,
ad9c40b7 927 interleave_mode ? "" : "XOR[18:16]");
eebf11a0
MCC		 928 if (interleave_mode)
929 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
930 else
931 idx = (addr >> 6) & 7;
932 switch (sad_way) {
933 case 1:
934 idx = 0;
935 break;
936 case 2:
937 idx = idx & 1;
938 break;
939 case 4:
940 idx = idx & 3;
941 break;
942 case 8:
943 break;
944 default:
945 sprintf(msg, "Can't discover socket interleave");
946 edac_mc_handle_ce_no_info(mci, msg);
947 return -EINVAL;
948 }
949 *socket = sad_interleave[idx];
950 debugf0("SAD interleave index: %d (wayness %d) = CPU socket %d\n",
951 idx, sad_way, *socket);
952
953 /*
954 * Move to the proper node structure, in order to access the
955 * right PCI registers
956 */
957 new_mci = get_mci_for_node_id(*socket);
958 if (!new_mci) {
959 sprintf(msg, "Struct for socket #%u wasn't initialized",
960 *socket);
961 edac_mc_handle_ce_no_info(mci, msg);
962 return -EINVAL;
963 }
964 mci = new_mci;
965 pvt = mci->pvt_info;
966
967 /*
968 * Step 2) Get memory channel
969 */
970 prv = 0;
971 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
972 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
973 &reg);
974 limit = TAD_LIMIT(reg);
975 if (limit <= prv) {
976 sprintf(msg, "Can't discover the memory channel");
977 edac_mc_handle_ce_no_info(mci, msg);
978 return -EINVAL;
979 }
980 if (addr <= limit)
981 break;
982 prv = limit;
983 }
984 ch_way = TAD_CH(reg) + 1;
985 sck_way = TAD_SOCK(reg) + 1;
986 /*
987 * FIXME: Is it right to always use channel 0 for offsets?
988 */
989 pci_read_config_dword(pvt->pci_tad[0],
990 tad_ch_nilv_offset[n_tads],
991 &tad_offset);
992
993 if (ch_way == 3)
994 idx = addr >> 6;
995 else
996 idx = addr >> (6 + sck_way);
997 idx = idx % ch_way;
998
999 /*
1000 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
1001 */
1002 switch (idx) {
1003 case 0:
1004 base_ch = TAD_TGT0(reg);
1005 break;
1006 case 1:
1007 base_ch = TAD_TGT1(reg);
1008 break;
1009 case 2:
1010 base_ch = TAD_TGT2(reg);
1011 break;
1012 case 3:
1013 base_ch = TAD_TGT3(reg);
1014 break;
1015 default:
1016 sprintf(msg, "Can't discover the TAD target");
1017 edac_mc_handle_ce_no_info(mci, msg);
1018 return -EINVAL;
1019 }
1020 *channel_mask = 1 << base_ch;
1021
1022 if (pvt->is_mirrored) {
1023 *channel_mask |= 1 << ((base_ch + 2) % 4);
1024 switch(ch_way) {
1025 case 2:
1026 case 4:
1027 sck_xch = 1 << sck_way * (ch_way >> 1);
1028 break;
1029 default:
1030 sprintf(msg, "Invalid mirror set. Can't decode addr");
1031 edac_mc_handle_ce_no_info(mci, msg);
1032 return -EINVAL;
1033 }
1034 } else
1035 sck_xch = (1 << sck_way) * ch_way;
1036
1037 if (pvt->is_lockstep)
1038 *channel_mask |= 1 << ((base_ch + 1) % 4);
1039
1040 offset = TAD_OFFSET(tad_offset);
1041
1042 debugf0("TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
1043 n_tads,
1044 addr,
1045 limit,
1046 (u32)TAD_SOCK(reg),
1047 ch_way,
1048 offset,
1049 idx,
1050 base_ch,
1051 *channel_mask);
1052
1053 /* Calculate channel address */
1054 /* Remove the TAD offset */
1055
1056 if (offset > addr) {
1057 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
1058 offset, addr);
1059 edac_mc_handle_ce_no_info(mci, msg);
1060 return -EINVAL;
1061 }
1062 addr -= offset;
1063 /* Store the low bits [0:6] of the addr */
1064 ch_addr = addr & 0x7f;
1065 /* Remove socket wayness and remove 6 bits */
1066 addr >>= 6;
5b889e37 1067 addr = div_u64(addr, sck_xch);
eebf11a0
MCC		 1068#if 0
1069 /* Divide by channel way */
1070 addr = addr / ch_way;
1071#endif
1072 /* Recover the last 6 bits */
1073 ch_addr |= addr << 6;
1074
1075 /*
1076 * Step 3) Decode rank
1077 */
1078 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
1079 pci_read_config_dword(pvt->pci_tad[base_ch],
1080 rir_way_limit[n_rir],
1081 &reg);
1082
1083 if (!IS_RIR_VALID(reg))
1084 continue;
1085
1086 limit = RIR_LIMIT(reg);
5b889e37
MCC		 1087 mb = div_u64_rem(limit >> 20, 1000, &kb);
1088 debugf0("RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
eebf11a0 1089 n_rir,
5b889e37 1090 mb, kb,
eebf11a0
MCC		 1091 limit,
1092 1 << RIR_WAY(reg));
1093 if (ch_addr <= limit)
1094 break;
1095 }
1096 if (n_rir == MAX_RIR_RANGES) {
1097 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
1098 ch_addr);
1099 edac_mc_handle_ce_no_info(mci, msg);
1100 return -EINVAL;
1101 }
1102 rir_way = RIR_WAY(reg);
1103 if (pvt->is_close_pg)
1104 idx = (ch_addr >> 6);
1105 else
1106 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */
1107 idx %= 1 << rir_way;
1108
1109 pci_read_config_dword(pvt->pci_tad[base_ch],
1110 rir_offset[n_rir][idx],
1111 &reg);
1112 *rank = RIR_RNK_TGT(reg);
1113
1114 debugf0("RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
1115 n_rir,
1116 ch_addr,
1117 limit,
1118 rir_way,
1119 idx);
1120
1121 return 0;
1122}
1123
1124/****************************************************************************
1125 Device initialization routines: put/get, init/exit
1126 ****************************************************************************/
1127
1128/*
1129 * sbridge_put_all_devices 'put' all the devices that we have
1130 * reserved via 'get'
1131 */
1132static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
1133{
1134 int i;
1135
1136 debugf0(__FILE__ ": %s()\n", __func__);
1137 for (i = 0; i < sbridge_dev->n_devs; i++) {
1138 struct pci_dev *pdev = sbridge_dev->pdev[i];
1139 if (!pdev)
1140 continue;
1141 debugf0("Removing dev %02x:%02x.%d\n",
1142 pdev->bus->number,
1143 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1144 pci_dev_put(pdev);
1145 }
1146}
1147
1148static void sbridge_put_all_devices(void)
1149{
1150 struct sbridge_dev *sbridge_dev, *tmp;
1151
1152 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
1153 sbridge_put_devices(sbridge_dev);
1154 free_sbridge_dev(sbridge_dev);
1155 }
1156}
1157
1158/*
1159 * sbridge_get_all_devices Find and perform 'get' operation on the MCH's
1160 * device/functions we want to reference for this driver
1161 *
1162 * Need to 'get' device 16 func 1 and func 2
1163 */
1164static int sbridge_get_onedevice(struct pci_dev **prev,
1165 u8 *num_mc,
1166 const struct pci_id_table *table,
1167 const unsigned devno)
1168{
1169 struct sbridge_dev *sbridge_dev;
1170 const struct pci_id_descr *dev_descr = &table->descr[devno];
1171
1172 struct pci_dev *pdev = NULL;
1173 u8 bus = 0;
1174
1175 sbridge_printk(KERN_INFO,
1176 "Seeking for: dev %02x.%d PCI ID %04x:%04x\n",
1177 dev_descr->dev, dev_descr->func,
1178 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1179
1180 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1181 dev_descr->dev_id, *prev);
1182
1183 if (!pdev) {
1184 if (*prev) {
1185 *prev = pdev;
1186 return 0;
1187 }
1188
1189 if (dev_descr->optional)
1190 return 0;
1191
1192 if (devno == 0)
1193 return -ENODEV;
1194
1195 sbridge_printk(KERN_INFO,
1196 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
1197 dev_descr->dev, dev_descr->func,
1198 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1199
1200 /* End of list, leave */
1201 return -ENODEV;
1202 }
1203 bus = pdev->bus->number;
1204
1205 sbridge_dev = get_sbridge_dev(bus);
1206 if (!sbridge_dev) {
1207 sbridge_dev = alloc_sbridge_dev(bus, table);
1208 if (!sbridge_dev) {
1209 pci_dev_put(pdev);
1210 return -ENOMEM;
1211 }
1212 (*num_mc)++;
1213 }
1214
1215 if (sbridge_dev->pdev[devno]) {
1216 sbridge_printk(KERN_ERR,
1217 "Duplicated device for "
1218 "dev %02x:%d.%d PCI ID %04x:%04x\n",
1219 bus, dev_descr->dev, dev_descr->func,
1220 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1221 pci_dev_put(pdev);
1222 return -ENODEV;
1223 }
1224
1225 sbridge_dev->pdev[devno] = pdev;
1226
1227 /* Sanity check */
1228 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
1229 PCI_FUNC(pdev->devfn) != dev_descr->func)) {
1230 sbridge_printk(KERN_ERR,
1231 "Device PCI ID %04x:%04x "
1232 "has dev %02x:%d.%d instead of dev %02x:%02x.%d\n",
1233 PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
1234 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1235 bus, dev_descr->dev, dev_descr->func);
1236 return -ENODEV;
1237 }
1238
1239 /* Be sure that the device is enabled */
1240 if (unlikely(pci_enable_device(pdev) < 0)) {
1241 sbridge_printk(KERN_ERR,
1242 "Couldn't enable "
1243 "dev %02x:%d.%d PCI ID %04x:%04x\n",
1244 bus, dev_descr->dev, dev_descr->func,
1245 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1246 return -ENODEV;
1247 }
1248
1249 debugf0("Detected dev %02x:%d.%d PCI ID %04x:%04x\n",
1250 bus, dev_descr->dev,
1251 dev_descr->func,
1252 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1253
1254 /*
1255 * As stated on drivers/pci/search.c, the reference count for
1256 * @from is always decremented if it is not %NULL. So, as we need
1257 * to get all devices up to null, we need to do a get for the device
1258 */
1259 pci_dev_get(pdev);
1260
1261 *prev = pdev;
1262
1263 return 0;
1264}
1265
1266static int sbridge_get_all_devices(u8 *num_mc)
1267{
1268 int i, rc;
1269 struct pci_dev *pdev = NULL;
1270 const struct pci_id_table *table = pci_dev_descr_sbridge_table;
1271
1272 while (table && table->descr) {
1273 for (i = 0; i < table->n_devs; i++) {
1274 pdev = NULL;
1275 do {
1276 rc = sbridge_get_onedevice(&pdev, num_mc,
1277 table, i);
1278 if (rc < 0) {
1279 if (i == 0) {
1280 i = table->n_devs;
1281 break;
1282 }
1283 sbridge_put_all_devices();
1284 return -ENODEV;
1285 }
1286 } while (pdev);
1287 }
1288 table++;
1289 }
1290
1291 return 0;
1292}
1293
1294static int mci_bind_devs(struct mem_ctl_info *mci,
1295 struct sbridge_dev *sbridge_dev)
1296{
1297 struct sbridge_pvt *pvt = mci->pvt_info;
1298 struct pci_dev *pdev;
1299 int i, func, slot;
1300
1301 for (i = 0; i < sbridge_dev->n_devs; i++) {
1302 pdev = sbridge_dev->pdev[i];
1303 if (!pdev)
1304 continue;
1305 slot = PCI_SLOT(pdev->devfn);
1306 func = PCI_FUNC(pdev->devfn);
1307 switch (slot) {
1308 case 12:
1309 switch (func) {
1310 case 6:
1311 pvt->pci_sad0 = pdev;
1312 break;
1313 case 7:
1314 pvt->pci_sad1 = pdev;
1315 break;
1316 default:
1317 goto error;
1318 }
1319 break;
1320 case 13:
1321 switch (func) {
1322 case 6:
1323 pvt->pci_br = pdev;
1324 break;
1325 default:
1326 goto error;
1327 }
1328 break;
1329 case 14:
1330 switch (func) {
1331 case 0:
1332 pvt->pci_ha0 = pdev;
1333 break;
1334 default:
1335 goto error;
1336 }
1337 break;
1338 case 15:
1339 switch (func) {
1340 case 0:
1341 pvt->pci_ta = pdev;
1342 break;
1343 case 1:
1344 pvt->pci_ras = pdev;
1345 break;
1346 case 2:
1347 case 3:
1348 case 4:
1349 case 5:
1350 pvt->pci_tad[func - 2] = pdev;
1351 break;
1352 default:
1353 goto error;
1354 }
1355 break;
1356 case 17:
1357 switch (func) {
1358 case 0:
1359 pvt->pci_ddrio = pdev;
1360 break;
1361 default:
1362 goto error;
1363 }
1364 break;
1365 default:
1366 goto error;
1367 }
1368
1369 debugf0("Associated PCI %02x.%02d.%d with dev = %p\n",
1370 sbridge_dev->bus,
1371 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1372 pdev);
1373 }
1374
1375 /* Check if everything were registered */
1376 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
1377 !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta ||
1378 !pvt->pci_ddrio)
1379 goto enodev;
1380
1381 for (i = 0; i < NUM_CHANNELS; i++) {
1382 if (!pvt->pci_tad[i])
1383 goto enodev;
1384 }
1385 return 0;
1386
1387enodev:
1388 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1389 return -ENODEV;
1390
1391error:
1392 sbridge_printk(KERN_ERR, "Device %d, function %d "
1393 "is out of the expected range\n",
1394 slot, func);
1395 return -EINVAL;
1396}
1397
1398/****************************************************************************
1399 Error check routines
1400 ****************************************************************************/
1401
1402/*
1403 * While Sandy Bridge has error count registers, SMI BIOS read values from
1404 * and resets the counters. So, they are not reliable for the OS to read
1405 * from them. So, we have no option but to just trust on whatever MCE is
1406 * telling us about the errors.
1407 */
1408static void sbridge_mce_output_error(struct mem_ctl_info *mci,
1409 const struct mce *m)
1410{
1411 struct mem_ctl_info *new_mci;
1412 struct sbridge_pvt *pvt = mci->pvt_info;
1413 char *type, *optype, *msg, *recoverable_msg;
1414 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
1415 bool overflow = GET_BITFIELD(m->status, 62, 62);
1416 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
1417 bool recoverable = GET_BITFIELD(m->status, 56, 56);
1418 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
1419 u32 mscod = GET_BITFIELD(m->status, 16, 31);
1420 u32 errcode = GET_BITFIELD(m->status, 0, 15);
1421 u32 channel = GET_BITFIELD(m->status, 0, 3);
1422 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
1423 long channel_mask, first_channel;
1424 u8 rank, socket;
1425 int csrow, rc, dimm;
1426 char *area_type = "Unknown";
1427
1428 if (ripv)
1429 type = "NON_FATAL";
1430 else
1431 type = "FATAL";
1432
1433 /*
1434 * According with Table 15-9 of the Intel Archictecture spec vol 3A,
1435 * memory errors should fit in this mask:
1436 * 000f 0000 1mmm cccc (binary)
1437 * where:
1438 * f = Correction Report Filtering Bit. If 1, subsequent errors
1439 * won't be shown
1440 * mmm = error type
1441 * cccc = channel
1442 * If the mask doesn't match, report an error to the parsing logic
1443 */
1444 if (! ((errcode & 0xef80) == 0x80)) {
1445 optype = "Can't parse: it is not a mem";
1446 } else {
1447 switch (optypenum) {
1448 case 0:
1449 optype = "generic undef request";
1450 break;
1451 case 1:
1452 optype = "memory read";
1453 break;
1454 case 2:
1455 optype = "memory write";
1456 break;
1457 case 3:
1458 optype = "addr/cmd";
1459 break;
1460 case 4:
1461 optype = "memory scrubbing";
1462 break;
1463 default:
1464 optype = "reserved";
1465 break;
1466 }
1467 }
1468
1469 rc = get_memory_error_data(mci, m->addr, &socket,
1470 &channel_mask, &rank, area_type);
1471 if (rc < 0)
1472 return;
1473 new_mci = get_mci_for_node_id(socket);
1474 if (!new_mci) {
1475 edac_mc_handle_ce_no_info(mci, "Error: socket got corrupted!");
1476 return;
1477 }
1478 mci = new_mci;
1479 pvt = mci->pvt_info;
1480
1481 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
1482
1483 if (rank < 4)
1484 dimm = 0;
1485 else if (rank < 8)
1486 dimm = 1;
1487 else
1488 dimm = 2;
1489
1490 csrow = pvt->csrow_map[first_channel][dimm];
1491
1492 if (uncorrected_error && recoverable)
1493 recoverable_msg = " recoverable";
1494 else
1495 recoverable_msg = "";
1496
1497 /*
1498 * FIXME: What should we do with "channel" information on mcelog?
1499 * Probably, we can just discard it, as the channel information
1500 * comes from the get_memory_error_data() address decoding
1501 */
1502 msg = kasprintf(GFP_ATOMIC,
1503 "%d %s error(s): %s on %s area %s%s: cpu=%d Err=%04x:%04x (ch=%d), "
1504 "addr = 0x%08llx => socket=%d, Channel=%ld(mask=%ld), rank=%d\n",
1505 core_err_cnt,
1506 area_type,
1507 optype,
1508 type,
1509 recoverable_msg,
1510 overflow ? "OVERFLOW" : "",
1511 m->cpu,
1512 mscod, errcode,
1513 channel, /* 1111b means not specified */
1514 (long long) m->addr,
1515 socket,
1516 first_channel, /* This is the real channel on SB */
1517 channel_mask,
1518 rank);
1519
1520 debugf0("%s", msg);
1521
1522 /* Call the helper to output message */
1523 if (uncorrected_error)
1524 edac_mc_handle_fbd_ue(mci, csrow, 0, 0, msg);
1525 else
1526 edac_mc_handle_fbd_ce(mci, csrow, 0, msg);
1527
1528 kfree(msg);
1529}
1530
1531/*
1532 * sbridge_check_error Retrieve and process errors reported by the
1533 * hardware. Called by the Core module.
1534 */
1535static void sbridge_check_error(struct mem_ctl_info *mci)
1536{
1537 struct sbridge_pvt *pvt = mci->pvt_info;
1538 int i;
1539 unsigned count = 0;
1540 struct mce *m;
1541
1542 /*
1543 * MCE first step: Copy all mce errors into a temporary buffer
1544 * We use a double buffering here, to reduce the risk of
1545 * loosing an error.
1546 */
1547 smp_rmb();
1548 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1549 % MCE_LOG_LEN;
1550 if (!count)
1551 return;
1552
1553 m = pvt->mce_outentry;
1554 if (pvt->mce_in + count > MCE_LOG_LEN) {
1555 unsigned l = MCE_LOG_LEN - pvt->mce_in;
1556
1557 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1558 smp_wmb();
1559 pvt->mce_in = 0;
1560 count -= l;
1561 m += l;
1562 }
1563 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1564 smp_wmb();
1565 pvt->mce_in += count;
1566
1567 smp_rmb();
1568 if (pvt->mce_overrun) {
1569 sbridge_printk(KERN_ERR, "Lost %d memory errors\n",
1570 pvt->mce_overrun);
1571 smp_wmb();
1572 pvt->mce_overrun = 0;
1573 }
1574
1575 /*
1576 * MCE second step: parse errors and display
1577 */
1578 for (i = 0; i < count; i++)
1579 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]);
1580}
1581
1582/*
1583 * sbridge_mce_check_error Replicates mcelog routine to get errors
1584 * This routine simply queues mcelog errors, and
1585 * return. The error itself should be handled later
1586 * by sbridge_check_error.
1587 * WARNING: As this routine should be called at NMI time, extra care should
1588 * be taken to avoid deadlocks, and to be as fast as possible.
1589 */
3d78c9af
MCC		 1590static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
1591 void *data)
eebf11a0 1592{
3d78c9af
MCC		 1593 struct mce *mce = (struct mce *)data;
1594 struct mem_ctl_info *mci;
1595 struct sbridge_pvt *pvt;
1596
1597 mci = get_mci_for_node_id(mce->socketid);
1598 if (!mci)
1599 return NOTIFY_BAD;
1600 pvt = mci->pvt_info;
eebf11a0
MCC		 1601
1602 /*
1603 * Just let mcelog handle it if the error is
1604 * outside the memory controller. A memory error
1605 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
1606 * bit 12 has an special meaning.
1607 */
1608 if ((mce->status & 0xefff) >> 7 != 1)
3d78c9af 1609 return NOTIFY_DONE;
eebf11a0
MCC		 1610
1611 printk("sbridge: HANDLING MCE MEMORY ERROR\n");
1612
1613 printk("CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
1614 mce->extcpu, mce->mcgstatus, mce->bank, mce->status);
1615 printk("TSC %llx ", mce->tsc);
1616 printk("ADDR %llx ", mce->addr);
1617 printk("MISC %llx ", mce->misc);
1618
1619 printk("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
1620 mce->cpuvendor, mce->cpuid, mce->time,
1621 mce->socketid, mce->apicid);
1622
eebf11a0
MCC		 1623 /* Only handle if it is the right mc controller */
1624 if (cpu_data(mce->cpu).phys_proc_id != pvt->sbridge_dev->mc)
3d78c9af 1625 return NOTIFY_DONE;
eebf11a0
MCC		 1626
1627 smp_rmb();
1628 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
1629 smp_wmb();
1630 pvt->mce_overrun++;
3d78c9af 1631 return NOTIFY_DONE;
eebf11a0
MCC		 1632 }
1633
1634 /* Copy memory error at the ringbuffer */
1635 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
1636 smp_wmb();
1637 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
1638
1639 /* Handle fatal errors immediately */
1640 if (mce->mcgstatus & 1)
1641 sbridge_check_error(mci);
1642
1643 /* Advice mcelog that the error were handled */
3d78c9af 1644 return NOTIFY_STOP;
eebf11a0
MCC		 1645}
1646
3d78c9af
MCC		 1647static struct notifier_block sbridge_mce_dec = {
1648 .notifier_call = sbridge_mce_check_error,
1649};
1650
eebf11a0
MCC		 1651/****************************************************************************
1652 EDAC register/unregister logic
1653 ****************************************************************************/
1654
1655static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
1656{
1657 struct mem_ctl_info *mci = sbridge_dev->mci;
1658 struct sbridge_pvt *pvt;
1659
1660 if (unlikely(!mci || !mci->pvt_info)) {
1661 debugf0("MC: " __FILE__ ": %s(): dev = %p\n",
1662 __func__, &sbridge_dev->pdev[0]->dev);
1663
1664 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
1665 return;
1666 }
1667
1668 pvt = mci->pvt_info;
1669
1670 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
1671 __func__, mci, &sbridge_dev->pdev[0]->dev);
1672
3653ada5 1673 mce_unregister_decode_chain(&sbridge_mce_dec);
eebf11a0
MCC		 1674
1675 /* Remove MC sysfs nodes */
1676 edac_mc_del_mc(mci->dev);
1677
1678 debugf1("%s: free mci struct\n", mci->ctl_name);
1679 kfree(mci->ctl_name);
1680 edac_mc_free(mci);
1681 sbridge_dev->mci = NULL;
1682}
1683
1684static int sbridge_register_mci(struct sbridge_dev *sbridge_dev)
1685{
1686 struct mem_ctl_info *mci;
1687 struct sbridge_pvt *pvt;
1688 int rc, channels, csrows;
1689
1690 /* Check the number of active and not disabled channels */
1691 rc = sbridge_get_active_channels(sbridge_dev->bus, &channels, &csrows);
1692 if (unlikely(rc < 0))
1693 return rc;
1694
1695 /* allocate a new MC control structure */
1696 mci = edac_mc_alloc(sizeof(*pvt), csrows, channels, sbridge_dev->mc);
1697 if (unlikely(!mci))
1698 return -ENOMEM;
1699
1700 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
1701 __func__, mci, &sbridge_dev->pdev[0]->dev);
1702
1703 pvt = mci->pvt_info;
1704 memset(pvt, 0, sizeof(*pvt));
1705
1706 /* Associate sbridge_dev and mci for future usage */
1707 pvt->sbridge_dev = sbridge_dev;
1708 sbridge_dev->mci = mci;
1709
1710 mci->mtype_cap = MEM_FLAG_DDR3;
1711 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1712 mci->edac_cap = EDAC_FLAG_NONE;
1713 mci->mod_name = "sbridge_edac.c";
1714 mci->mod_ver = SBRIDGE_REVISION;
1715 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
1716 mci->dev_name = pci_name(sbridge_dev->pdev[0]);
1717 mci->ctl_page_to_phys = NULL;
1718
1719 /* Set the function pointer to an actual operation function */
1720 mci->edac_check = sbridge_check_error;
1721
1722 /* Store pci devices at mci for faster access */
1723 rc = mci_bind_devs(mci, sbridge_dev);
1724 if (unlikely(rc < 0))
1725 goto fail0;
1726
1727 /* Get dimm basic config and the memory layout */
1728 get_dimm_config(mci);
1729 get_memory_layout(mci);
1730
1731 /* record ptr to the generic device */
1732 mci->dev = &sbridge_dev->pdev[0]->dev;
1733
1734 /* add this new MC control structure to EDAC's list of MCs */
1735 if (unlikely(edac_mc_add_mc(mci))) {
1736 debugf0("MC: " __FILE__
1737 ": %s(): failed edac_mc_add_mc()\n", __func__);
1738 rc = -EINVAL;
1739 goto fail0;
1740 }
1741
3653ada5 1742 mce_register_decode_chain(&sbridge_mce_dec);
eebf11a0 1743 return 0;
eebf11a0
MCC		 1744
1745fail0:
1746 kfree(mci->ctl_name);
1747 edac_mc_free(mci);
1748 sbridge_dev->mci = NULL;
1749 return rc;
1750}
1751
1752/*
1753 * sbridge_probe Probe for ONE instance of device to see if it is
1754 * present.
1755 * return:
1756 * 0 for FOUND a device
1757 * < 0 for error code
1758 */
1759
1760static int __devinit sbridge_probe(struct pci_dev *pdev,
1761 const struct pci_device_id *id)
1762{
1763 int rc;
1764 u8 mc, num_mc = 0;
1765 struct sbridge_dev *sbridge_dev;
1766
1767 /* get the pci devices we want to reserve for our use */
1768 mutex_lock(&sbridge_edac_lock);
1769
1770 /*
1771 * All memory controllers are allocated at the first pass.
1772 */
1773 if (unlikely(probed >= 1)) {
1774 mutex_unlock(&sbridge_edac_lock);
1775 return -ENODEV;
1776 }
1777 probed++;
1778
1779 rc = sbridge_get_all_devices(&num_mc);
1780 if (unlikely(rc < 0))
1781 goto fail0;
1782 mc = 0;
1783
1784 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1785 debugf0("Registering MC#%d (%d of %d)\n", mc, mc + 1, num_mc);
1786 sbridge_dev->mc = mc++;
1787 rc = sbridge_register_mci(sbridge_dev);
1788 if (unlikely(rc < 0))
1789 goto fail1;
1790 }
1791
1792 sbridge_printk(KERN_INFO, "Driver loaded.\n");
1793
1794 mutex_unlock(&sbridge_edac_lock);
1795 return 0;
1796
1797fail1:
1798 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
1799 sbridge_unregister_mci(sbridge_dev);
1800
1801 sbridge_put_all_devices();
1802fail0:
1803 mutex_unlock(&sbridge_edac_lock);
1804 return rc;
1805}
1806
1807/*
1808 * sbridge_remove destructor for one instance of device
1809 *
1810 */
1811static void __devexit sbridge_remove(struct pci_dev *pdev)
1812{
1813 struct sbridge_dev *sbridge_dev;
1814
1815 debugf0(__FILE__ ": %s()\n", __func__);
1816
1817 /*
1818 * we have a trouble here: pdev value for removal will be wrong, since
1819 * it will point to the X58 register used to detect that the machine
1820 * is a Nehalem or upper design. However, due to the way several PCI
1821 * devices are grouped together to provide MC functionality, we need
1822 * to use a different method for releasing the devices
1823 */
1824
1825 mutex_lock(&sbridge_edac_lock);
1826
1827 if (unlikely(!probed)) {
1828 mutex_unlock(&sbridge_edac_lock);
1829 return;
1830 }
1831
1832 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
1833 sbridge_unregister_mci(sbridge_dev);
1834
1835 /* Release PCI resources */
1836 sbridge_put_all_devices();
1837
1838 probed--;
1839
1840 mutex_unlock(&sbridge_edac_lock);
1841}
1842
1843MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl);
1844
1845/*
1846 * sbridge_driver pci_driver structure for this module
1847 *
1848 */
1849static struct pci_driver sbridge_driver = {
1850 .name = "sbridge_edac",
1851 .probe = sbridge_probe,
1852 .remove = __devexit_p(sbridge_remove),
1853 .id_table = sbridge_pci_tbl,
1854};
1855
1856/*
1857 * sbridge_init Module entry function
1858 * Try to initialize this module for its devices
1859 */
1860static int __init sbridge_init(void)
1861{
1862 int pci_rc;
1863
1864 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1865
1866 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1867 opstate_init();
1868
1869 pci_rc = pci_register_driver(&sbridge_driver);
1870
1871 if (pci_rc >= 0)
1872 return 0;
1873
1874 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
1875 pci_rc);
1876
1877 return pci_rc;
1878}
1879
1880/*
1881 * sbridge_exit() Module exit function
1882 * Unregister the driver
1883 */
1884static void __exit sbridge_exit(void)
1885{
1886 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1887 pci_unregister_driver(&sbridge_driver);
1888}
1889
1890module_init(sbridge_init);
1891module_exit(sbridge_exit);
1892
1893module_param(edac_op_state, int, 0444);
1894MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1895
1896MODULE_LICENSE("GPL");
1897MODULE_AUTHOR("Mauro Carvalho Chehab <[email protected]>");
1898MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1899MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge memory controllers - "
1900 SBRIDGE_REVISION);
Empty description
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