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ebc915ad | 1 | /* |
c49a7f18 | 2 | * omap-rng.c - RNG driver for TI OMAP CPU family |
ebc915ad MB |
3 | * |
4 | * Author: Deepak Saxena <[email protected]> | |
5 | * | |
6 | * Copyright 2005 (c) MontaVista Software, Inc. | |
7 | * | |
8 | * Mostly based on original driver: | |
9 | * | |
10 | * Copyright (C) 2005 Nokia Corporation | |
96de0e25 | 11 | * Author: Juha Yrjölä <[email protected]> |
ebc915ad MB |
12 | * |
13 | * This file is licensed under the terms of the GNU General Public | |
14 | * License version 2. This program is licensed "as is" without any | |
15 | * warranty of any kind, whether express or implied. | |
ebc915ad MB |
16 | */ |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/random.h> | |
af2bc7d2 | 21 | #include <linux/clk.h> |
ebc915ad | 22 | #include <linux/err.h> |
af2bc7d2 | 23 | #include <linux/platform_device.h> |
ebc915ad | 24 | #include <linux/hw_random.h> |
984e976f | 25 | #include <linux/delay.h> |
ebc915ad MB |
26 | |
27 | #include <asm/io.h> | |
ebc915ad MB |
28 | |
29 | #define RNG_OUT_REG 0x00 /* Output register */ | |
30 | #define RNG_STAT_REG 0x04 /* Status register | |
31 | [0] = STAT_BUSY */ | |
32 | #define RNG_ALARM_REG 0x24 /* Alarm register | |
33 | [7:0] = ALARM_COUNTER */ | |
34 | #define RNG_CONFIG_REG 0x28 /* Configuration register | |
35 | [11:6] = RESET_COUNT | |
36 | [5:3] = RING2_DELAY | |
37 | [2:0] = RING1_DELAY */ | |
38 | #define RNG_REV_REG 0x3c /* Revision register | |
39 | [7:0] = REV_NB */ | |
40 | #define RNG_MASK_REG 0x40 /* Mask and reset register | |
41 | [2] = IT_EN | |
42 | [1] = SOFTRESET | |
43 | [0] = AUTOIDLE */ | |
44 | #define RNG_SYSSTATUS 0x44 /* System status | |
45 | [0] = RESETDONE */ | |
46 | ||
47 | static void __iomem *rng_base; | |
48 | static struct clk *rng_ick; | |
af2bc7d2 | 49 | static struct platform_device *rng_dev; |
ebc915ad | 50 | |
c49a7f18 | 51 | static inline u32 omap_rng_read_reg(int reg) |
ebc915ad MB |
52 | { |
53 | return __raw_readl(rng_base + reg); | |
54 | } | |
55 | ||
c49a7f18 | 56 | static inline void omap_rng_write_reg(int reg, u32 val) |
ebc915ad MB |
57 | { |
58 | __raw_writel(val, rng_base + reg); | |
59 | } | |
60 | ||
984e976f | 61 | static int omap_rng_data_present(struct hwrng *rng, int wait) |
ebc915ad | 62 | { |
984e976f PM |
63 | int data, i; |
64 | ||
65 | for (i = 0; i < 20; i++) { | |
66 | data = omap_rng_read_reg(RNG_STAT_REG) ? 0 : 1; | |
67 | if (data || !wait) | |
68 | break; | |
c49a7f18 DB |
69 | /* RNG produces data fast enough (2+ MBit/sec, even |
70 | * during "rngtest" loads, that these delays don't | |
71 | * seem to trigger. We *could* use the RNG IRQ, but | |
72 | * that'd be higher overhead ... so why bother? | |
73 | */ | |
984e976f PM |
74 | udelay(10); |
75 | } | |
76 | return data; | |
ebc915ad MB |
77 | } |
78 | ||
79 | static int omap_rng_data_read(struct hwrng *rng, u32 *data) | |
80 | { | |
81 | *data = omap_rng_read_reg(RNG_OUT_REG); | |
82 | ||
83 | return 4; | |
84 | } | |
85 | ||
86 | static struct hwrng omap_rng_ops = { | |
87 | .name = "omap", | |
88 | .data_present = omap_rng_data_present, | |
89 | .data_read = omap_rng_data_read, | |
90 | }; | |
91 | ||
9f171adc | 92 | static int __devinit omap_rng_probe(struct platform_device *pdev) |
ebc915ad | 93 | { |
c652759b | 94 | struct resource *res; |
ebc915ad MB |
95 | int ret; |
96 | ||
97 | /* | |
98 | * A bit ugly, and it will never actually happen but there can | |
99 | * be only one RNG and this catches any bork | |
100 | */ | |
c49a7f18 DB |
101 | if (rng_dev) |
102 | return -EBUSY; | |
ebc915ad | 103 | |
af2bc7d2 | 104 | if (cpu_is_omap24xx()) { |
eeec7c8d | 105 | rng_ick = clk_get(&pdev->dev, "ick"); |
ebc915ad | 106 | if (IS_ERR(rng_ick)) { |
af2bc7d2 | 107 | dev_err(&pdev->dev, "Could not get rng_ick\n"); |
ebc915ad MB |
108 | ret = PTR_ERR(rng_ick); |
109 | return ret; | |
af2bc7d2 DB |
110 | } else |
111 | clk_enable(rng_ick); | |
ebc915ad MB |
112 | } |
113 | ||
114 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
115 | ||
6ba1a31e JL |
116 | if (!res) { |
117 | ret = -ENOENT; | |
118 | goto err_region; | |
119 | } | |
ebc915ad | 120 | |
c652759b | 121 | if (!request_mem_region(res->start, resource_size(res), pdev->name)) { |
55c381e4 RK |
122 | ret = -EBUSY; |
123 | goto err_region; | |
124 | } | |
ebc915ad | 125 | |
c652759b | 126 | dev_set_drvdata(&pdev->dev, res); |
0fd92a15 | 127 | rng_base = ioremap(res->start, resource_size(res)); |
55c381e4 RK |
128 | if (!rng_base) { |
129 | ret = -ENOMEM; | |
130 | goto err_ioremap; | |
131 | } | |
ebc915ad MB |
132 | |
133 | ret = hwrng_register(&omap_rng_ops); | |
55c381e4 RK |
134 | if (ret) |
135 | goto err_register; | |
ebc915ad | 136 | |
af2bc7d2 | 137 | dev_info(&pdev->dev, "OMAP Random Number Generator ver. %02x\n", |
ebc915ad MB |
138 | omap_rng_read_reg(RNG_REV_REG)); |
139 | omap_rng_write_reg(RNG_MASK_REG, 0x1); | |
140 | ||
af2bc7d2 | 141 | rng_dev = pdev; |
ebc915ad MB |
142 | |
143 | return 0; | |
55c381e4 RK |
144 | |
145 | err_register: | |
146 | iounmap(rng_base); | |
147 | rng_base = NULL; | |
148 | err_ioremap: | |
c652759b | 149 | release_mem_region(res->start, resource_size(res)); |
55c381e4 RK |
150 | err_region: |
151 | if (cpu_is_omap24xx()) { | |
152 | clk_disable(rng_ick); | |
153 | clk_put(rng_ick); | |
154 | } | |
155 | return ret; | |
ebc915ad MB |
156 | } |
157 | ||
af2bc7d2 | 158 | static int __exit omap_rng_remove(struct platform_device *pdev) |
ebc915ad | 159 | { |
c652759b | 160 | struct resource *res = dev_get_drvdata(&pdev->dev); |
ebc915ad MB |
161 | |
162 | hwrng_unregister(&omap_rng_ops); | |
163 | ||
164 | omap_rng_write_reg(RNG_MASK_REG, 0x0); | |
165 | ||
55c381e4 RK |
166 | iounmap(rng_base); |
167 | ||
ebc915ad | 168 | if (cpu_is_omap24xx()) { |
af2bc7d2 | 169 | clk_disable(rng_ick); |
ebc915ad MB |
170 | clk_put(rng_ick); |
171 | } | |
172 | ||
c652759b | 173 | release_mem_region(res->start, resource_size(res)); |
ebc915ad MB |
174 | rng_base = NULL; |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
179 | #ifdef CONFIG_PM | |
180 | ||
af2bc7d2 | 181 | static int omap_rng_suspend(struct platform_device *pdev, pm_message_t message) |
ebc915ad MB |
182 | { |
183 | omap_rng_write_reg(RNG_MASK_REG, 0x0); | |
ebc915ad MB |
184 | return 0; |
185 | } | |
186 | ||
af2bc7d2 | 187 | static int omap_rng_resume(struct platform_device *pdev) |
ebc915ad MB |
188 | { |
189 | omap_rng_write_reg(RNG_MASK_REG, 0x1); | |
af2bc7d2 | 190 | return 0; |
ebc915ad MB |
191 | } |
192 | ||
193 | #else | |
194 | ||
195 | #define omap_rng_suspend NULL | |
196 | #define omap_rng_resume NULL | |
197 | ||
198 | #endif | |
199 | ||
c49a7f18 DB |
200 | /* work with hotplug and coldplug */ |
201 | MODULE_ALIAS("platform:omap_rng"); | |
ebc915ad | 202 | |
af2bc7d2 DB |
203 | static struct platform_driver omap_rng_driver = { |
204 | .driver = { | |
205 | .name = "omap_rng", | |
206 | .owner = THIS_MODULE, | |
207 | }, | |
ebc915ad MB |
208 | .probe = omap_rng_probe, |
209 | .remove = __exit_p(omap_rng_remove), | |
210 | .suspend = omap_rng_suspend, | |
211 | .resume = omap_rng_resume | |
212 | }; | |
213 | ||
214 | static int __init omap_rng_init(void) | |
215 | { | |
216 | if (!cpu_is_omap16xx() && !cpu_is_omap24xx()) | |
217 | return -ENODEV; | |
218 | ||
af2bc7d2 | 219 | return platform_driver_register(&omap_rng_driver); |
ebc915ad MB |
220 | } |
221 | ||
222 | static void __exit omap_rng_exit(void) | |
223 | { | |
af2bc7d2 | 224 | platform_driver_unregister(&omap_rng_driver); |
ebc915ad MB |
225 | } |
226 | ||
227 | module_init(omap_rng_init); | |
228 | module_exit(omap_rng_exit); | |
229 | ||
230 | MODULE_AUTHOR("Deepak Saxena (and others)"); | |
231 | MODULE_LICENSE("GPL"); |