[linux.git] / drivers / mfd / lpc_sch.c

/*
 *  lpc_sch.c - LPC interface for Intel Poulsbo SCH
 *
 *  LPC bridge function of the Intel SCH contains many other
 *  functional units, such as Interrupt controllers, Timers,
 *  Power Management, System Management, GPIO, RTC, and LPC
 *  Configuration Registers.
 *
 *  Copyright (c) 2010 CompuLab Ltd
 *  Copyright (c) 2014 Intel Corp.
 *  Author: Denis Turischev <[email protected]>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License 2 as published
 *  by the Free Software Foundation.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/acpi.h>
#include <linux/pci.h>
#include <linux/mfd/core.h>

#define SMBASE		0x40
#define SMBUS_IO_SIZE	64

#define GPIOBASE	0x44
#define GPIO_IO_SIZE	64
#define GPIO_IO_SIZE_CENTERTON	128

/* Intel Quark X1000 GPIO IRQ Number */
#define GPIO_IRQ_QUARK_X1000	9

#define WDTBASE		0x84
#define WDT_IO_SIZE	64

enum sch_chipsets {
	LPC_SCH = 0,		/* Intel Poulsbo SCH */
	LPC_ITC,		/* Intel Tunnel Creek */
	LPC_CENTERTON,		/* Intel Centerton */
	LPC_QUARK_X1000,	/* Intel Quark X1000 */
};

struct lpc_sch_info {
	unsigned int io_size_smbus;
	unsigned int io_size_gpio;
	unsigned int io_size_wdt;
	int irq_gpio;
};

static struct lpc_sch_info sch_chipset_info[] = {
	[LPC_SCH] = {
		.io_size_smbus = SMBUS_IO_SIZE,
		.io_size_gpio = GPIO_IO_SIZE,
		.irq_gpio = -1,
	},
	[LPC_ITC] = {
		.io_size_smbus = SMBUS_IO_SIZE,
		.io_size_gpio = GPIO_IO_SIZE,
		.io_size_wdt = WDT_IO_SIZE,
		.irq_gpio = -1,
	},
	[LPC_CENTERTON] = {
		.io_size_smbus = SMBUS_IO_SIZE,
		.io_size_gpio = GPIO_IO_SIZE_CENTERTON,
		.io_size_wdt = WDT_IO_SIZE,
		.irq_gpio = -1,
	},
	[LPC_QUARK_X1000] = {
		.io_size_gpio = GPIO_IO_SIZE,
		.irq_gpio = GPIO_IRQ_QUARK_X1000,
		.io_size_wdt = WDT_IO_SIZE,
	},
};

static const struct pci_device_id lpc_sch_ids[] = {
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SCH_LPC), LPC_SCH },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ITC_LPC), LPC_ITC },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CENTERTON_ILB), LPC_CENTERTON },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB), LPC_QUARK_X1000 },
	{ 0, }
};
MODULE_DEVICE_TABLE(pci, lpc_sch_ids);

#define LPC_NO_RESOURCE		1
#define LPC_SKIP_RESOURCE	2

static int lpc_sch_get_io(struct pci_dev *pdev, int where, const char *name,
			  struct resource *res, int size)
{
	unsigned int base_addr_cfg;
	unsigned short base_addr;

	if (size == 0)
		return LPC_NO_RESOURCE;

	pci_read_config_dword(pdev, where, &base_addr_cfg);
	base_addr = 0;
	if (!(base_addr_cfg & (1 << 31)))
		dev_warn(&pdev->dev, "Decode of the %s I/O range disabled\n",
			 name);
	else
		base_addr = (unsigned short)base_addr_cfg;

	if (base_addr == 0) {
		dev_warn(&pdev->dev, "I/O space for %s uninitialized\n", name);
		return LPC_SKIP_RESOURCE;
	}

	res->start = base_addr;
	res->end = base_addr + size - 1;
	res->flags = IORESOURCE_IO;

	return 0;
}

static int lpc_sch_populate_cell(struct pci_dev *pdev, int where,
				 const char *name, int size, int irq,
				 int id, struct mfd_cell *cell)
{
	struct resource *res;
	int ret;

	res = devm_kcalloc(&pdev->dev, 2, sizeof(*res), GFP_KERNEL);
	if (!res)
		return -ENOMEM;

	ret = lpc_sch_get_io(pdev, where, name, res, size);
	if (ret)
		return ret;

	memset(cell, 0, sizeof(*cell));

	cell->name = name;
	cell->resources = res;
	cell->num_resources = 1;
	cell->ignore_resource_conflicts = true;
	cell->id = id;

	/* Check if we need to add an IRQ resource */
	if (irq < 0)
		return 0;

	res++;

	res->start = irq;
	res->end = irq;
	res->flags = IORESOURCE_IRQ;

	cell->num_resources++;

	return 0;
}

static int lpc_sch_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct mfd_cell lpc_sch_cells[3];
	struct lpc_sch_info *info = &sch_chipset_info[id->driver_data];
	unsigned int cells = 0;
	int ret;

	ret = lpc_sch_populate_cell(dev, SMBASE, "isch_smbus",
				    info->io_size_smbus, -1,
				    id->device, &lpc_sch_cells[cells]);
	if (ret < 0)
		return ret;
	if (ret == 0)
		cells++;

	ret = lpc_sch_populate_cell(dev, GPIOBASE, "sch_gpio",
				    info->io_size_gpio, info->irq_gpio,
				    id->device, &lpc_sch_cells[cells]);
	if (ret < 0)
		return ret;
	if (ret == 0)
		cells++;

	ret = lpc_sch_populate_cell(dev, WDTBASE, "ie6xx_wdt",
				    info->io_size_wdt, -1,
				    id->device, &lpc_sch_cells[cells]);
	if (ret < 0)
		return ret;
	if (ret == 0)
		cells++;

	if (cells == 0) {
		dev_err(&dev->dev, "All decode registers disabled.\n");
		return -ENODEV;
	}

	return mfd_add_devices(&dev->dev, 0, lpc_sch_cells, cells, NULL, 0, NULL);
}

static void lpc_sch_remove(struct pci_dev *dev)
{
	mfd_remove_devices(&dev->dev);
}

static struct pci_driver lpc_sch_driver = {
	.name		= "lpc_sch",
	.id_table	= lpc_sch_ids,
	.probe		= lpc_sch_probe,
	.remove		= lpc_sch_remove,
};

module_pci_driver(lpc_sch_driver);

MODULE_AUTHOR("Denis Turischev <[email protected]>");
MODULE_DESCRIPTION("LPC interface for Intel Poulsbo SCH");
MODULE_LICENSE("GPL");
Commit	Line	Data
e82c60ae DT	1	/*
	2	* lpc_sch.c - LPC interface for Intel Poulsbo SCH
	3	*
	4	* LPC bridge function of the Intel SCH contains many other
	5	* functional units, such as Interrupt controllers, Timers,
	6	* Power Management, System Management, GPIO, RTC, and LPC
	7	* Configuration Registers.
	8	*
	9	* Copyright (c) 2010 CompuLab Ltd
85de80e8	10	* Copyright (c) 2014 Intel Corp.
e82c60ae DT	11	* Author: Denis Turischev <[email protected]>
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License 2 as published
	15	* by the Free Software Foundation.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
e82c60ae DT	21	*/
e82c60ae DT	22
e82c60ae DT	23	#include <linux/kernel.h>
	24	#include <linux/module.h>
	25	#include <linux/errno.h>
	26	#include <linux/acpi.h>
	27	#include <linux/pci.h>
	28	#include <linux/mfd/core.h>
	29
	30	#define SMBASE 0x40
	31	#define SMBUS_IO_SIZE 64
	32
	33	#define GPIOBASE 0x44
	34	#define GPIO_IO_SIZE 64
8ee3c2a7	35	#define GPIO_IO_SIZE_CENTERTON 128
e82c60ae	36
ec689a8a AS	37	/* Intel Quark X1000 GPIO IRQ Number */
	38	#define GPIO_IRQ_QUARK_X1000 9
	39
19921ef6 AS	40	#define WDTBASE 0x84
	41	#define WDT_IO_SIZE 64
	42
b24512c8 AS	43	enum sch_chipsets {
	44	LPC_SCH = 0, /* Intel Poulsbo SCH */
	45	LPC_ITC, /* Intel Tunnel Creek */
	46	LPC_CENTERTON, /* Intel Centerton */
ec689a8a	47	LPC_QUARK_X1000, /* Intel Quark X1000 */
e82c60ae DT	48	};
e82c60ae DT	49
b24512c8 AS	50	struct lpc_sch_info {
	51	unsigned int io_size_smbus;
	52	unsigned int io_size_gpio;
	53	unsigned int io_size_wdt;
ec689a8a	54	int irq_gpio;
e82c60ae DT	55	};
e82c60ae DT	56
b24512c8 AS	57	static struct lpc_sch_info sch_chipset_info[] = {
	58	[LPC_SCH] = {
	59	.io_size_smbus = SMBUS_IO_SIZE,
	60	.io_size_gpio = GPIO_IO_SIZE,
ec689a8a	61	.irq_gpio = -1,
b24512c8 AS	62	},
	63	[LPC_ITC] = {
	64	.io_size_smbus = SMBUS_IO_SIZE,
	65	.io_size_gpio = GPIO_IO_SIZE,
	66	.io_size_wdt = WDT_IO_SIZE,
ec689a8a	67	.irq_gpio = -1,
b24512c8 AS	68	},
	69	[LPC_CENTERTON] = {
	70	.io_size_smbus = SMBUS_IO_SIZE,
	71	.io_size_gpio = GPIO_IO_SIZE_CENTERTON,
	72	.io_size_wdt = WDT_IO_SIZE,
ec689a8a AS	73	.irq_gpio = -1,
	74	},
	75	[LPC_QUARK_X1000] = {
	76	.io_size_gpio = GPIO_IO_SIZE,
	77	.irq_gpio = GPIO_IRQ_QUARK_X1000,
c68a8658	78	.io_size_wdt = WDT_IO_SIZE,
b24512c8	79	},
19921ef6 AS	80	};
19921ef6 AS	81
36fcd06c	82	static const struct pci_device_id lpc_sch_ids[] = {
b24512c8 AS	83	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SCH_LPC), LPC_SCH },
	84	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ITC_LPC), LPC_ITC },
	85	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CENTERTON_ILB), LPC_CENTERTON },
ec689a8a	86	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB), LPC_QUARK_X1000 },
e82c60ae DT	87	{ 0, }
	88	};
	89	MODULE_DEVICE_TABLE(pci, lpc_sch_ids);
	90
b24512c8 AS	91	#define LPC_NO_RESOURCE 1
	92	#define LPC_SKIP_RESOURCE 2
	93
	94	static int lpc_sch_get_io(struct pci_dev pdev, int where, const char name,
	95	struct resource *res, int size)
e82c60ae DT	96	{
	97	unsigned int base_addr_cfg;
	98	unsigned short base_addr;
	99
b24512c8 AS	100	if (size == 0)
	101	return LPC_NO_RESOURCE;
	102
	103	pci_read_config_dword(pdev, where, &base_addr_cfg);
5829e9b6 DH	104	base_addr = 0;
5829e9b6 DH	105	if (!(base_addr_cfg & (1 << 31)))
b24512c8 AS	106	dev_warn(&pdev->dev, "Decode of the %s I/O range disabled\n",
b24512c8 AS	107	name);
5829e9b6 DH	108	else
5829e9b6 DH	109	base_addr = (unsigned short)base_addr_cfg;
e82c60ae	110
e82c60ae	111	if (base_addr == 0) {
b24512c8 AS	112	dev_warn(&pdev->dev, "I/O space for %s uninitialized\n", name);
b24512c8 AS	113	return LPC_SKIP_RESOURCE;
e82c60ae DT	114	}
e82c60ae DT	115
b24512c8 AS	116	res->start = base_addr;
	117	res->end = base_addr + size - 1;
	118	res->flags = IORESOURCE_IO;
e967f77d	119
b24512c8 AS	120	return 0;
b24512c8 AS	121	}
19921ef6	122
b24512c8	123	static int lpc_sch_populate_cell(struct pci_dev *pdev, int where,
ec689a8a AS	124	const char *name, int size, int irq,
ec689a8a AS	125	int id, struct mfd_cell *cell)
b24512c8 AS	126	{
	127	struct resource *res;
	128	int ret;
19921ef6	129
ec689a8a	130	res = devm_kcalloc(&pdev->dev, 2, sizeof(*res), GFP_KERNEL);
b24512c8 AS	131	if (!res)
	132	return -ENOMEM;
	133
	134	ret = lpc_sch_get_io(pdev, where, name, res, size);
	135	if (ret)
	136	return ret;
	137
	138	memset(cell, 0, sizeof(*cell));
	139
	140	cell->name = name;
	141	cell->resources = res;
	142	cell->num_resources = 1;
	143	cell->ignore_resource_conflicts = true;
	144	cell->id = id;
	145
ec689a8a AS	146	/* Check if we need to add an IRQ resource */
	147	if (irq < 0)
	148	return 0;
	149
	150	res++;
	151
	152	res->start = irq;
	153	res->end = irq;
	154	res->flags = IORESOURCE_IRQ;
	155
	156	cell->num_resources++;
	157
b24512c8 AS	158	return 0;
	159	}
	160
	161	static int lpc_sch_probe(struct pci_dev dev, const struct pci_device_id id)
	162	{
	163	struct mfd_cell lpc_sch_cells[3];
	164	struct lpc_sch_info *info = &sch_chipset_info[id->driver_data];
	165	unsigned int cells = 0;
	166	int ret;
	167
	168	ret = lpc_sch_populate_cell(dev, SMBASE, "isch_smbus",
ec689a8a	169	info->io_size_smbus, -1,
b24512c8 AS	170	id->device, &lpc_sch_cells[cells]);
	171	if (ret < 0)
	172	return ret;
	173	if (ret == 0)
	174	cells++;
	175
	176	ret = lpc_sch_populate_cell(dev, GPIOBASE, "sch_gpio",
ec689a8a	177	info->io_size_gpio, info->irq_gpio,
b24512c8 AS	178	id->device, &lpc_sch_cells[cells]);
	179	if (ret < 0)
	180	return ret;
	181	if (ret == 0)
	182	cells++;
	183
	184	ret = lpc_sch_populate_cell(dev, WDTBASE, "ie6xx_wdt",
ec689a8a	185	info->io_size_wdt, -1,
b24512c8 AS	186	id->device, &lpc_sch_cells[cells]);
	187	if (ret < 0)
	188	return ret;
	189	if (ret == 0)
	190	cells++;
19921ef6	191
5829e9b6 DH	192	if (cells == 0) {
	193	dev_err(&dev->dev, "All decode registers disabled.\n");
	194	return -ENODEV;
19921ef6 AS	195	}
19921ef6 AS	196
bde3e706	197	return mfd_add_devices(&dev->dev, 0, lpc_sch_cells, cells, NULL, 0, NULL);
e82c60ae DT	198	}
e82c60ae DT	199
4740f73f	200	static void lpc_sch_remove(struct pci_dev *dev)
e82c60ae DT	201	{
	202	mfd_remove_devices(&dev->dev);
	203	}
	204
	205	static struct pci_driver lpc_sch_driver = {
	206	.name = "lpc_sch",
	207	.id_table = lpc_sch_ids,
	208	.probe = lpc_sch_probe,
84449216	209	.remove = lpc_sch_remove,
e82c60ae DT	210	};
e82c60ae DT	211
38a36f5a	212	module_pci_driver(lpc_sch_driver);
e82c60ae DT	213
	214	MODULE_AUTHOR("Denis Turischev <[email protected]>");
	215	MODULE_DESCRIPTION("LPC interface for Intel Poulsbo SCH");
	216	MODULE_LICENSE("GPL");