[linux.git] / drivers / mfd / mt6397-core.c

/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Flora Fu, MediaTek
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/regmap.h>
#include <linux/mfd/core.h>
#include <linux/mfd/mt6397/core.h>
#include <linux/mfd/mt6323/core.h>
#include <linux/mfd/mt6397/registers.h>
#include <linux/mfd/mt6323/registers.h>

#define MT6397_RTC_BASE		0xe000
#define MT6397_RTC_SIZE		0x3e

#define MT6323_CID_CODE		0x23
#define MT6391_CID_CODE		0x91
#define MT6397_CID_CODE		0x97

static const struct resource mt6397_rtc_resources[] = {
	{
		.start = MT6397_RTC_BASE,
		.end   = MT6397_RTC_BASE + MT6397_RTC_SIZE,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = MT6397_IRQ_RTC,
		.end   = MT6397_IRQ_RTC,
		.flags = IORESOURCE_IRQ,
	},
};

static const struct resource mt6323_keys_resources[] = {
	DEFINE_RES_IRQ(MT6323_IRQ_STATUS_PWRKEY),
	DEFINE_RES_IRQ(MT6323_IRQ_STATUS_FCHRKEY),
};

static const struct resource mt6397_keys_resources[] = {
	DEFINE_RES_IRQ(MT6397_IRQ_PWRKEY),
	DEFINE_RES_IRQ(MT6397_IRQ_HOMEKEY),
};

static const struct mfd_cell mt6323_devs[] = {
	{
		.name = "mt6323-regulator",
		.of_compatible = "mediatek,mt6323-regulator"
	}, {
		.name = "mt6323-led",
		.of_compatible = "mediatek,mt6323-led"
	}, {
		.name = "mtk-pmic-keys",
		.num_resources = ARRAY_SIZE(mt6323_keys_resources),
		.resources = mt6323_keys_resources,
		.of_compatible = "mediatek,mt6323-keys"
	},
};

static const struct mfd_cell mt6397_devs[] = {
	{
		.name = "mt6397-rtc",
		.num_resources = ARRAY_SIZE(mt6397_rtc_resources),
		.resources = mt6397_rtc_resources,
		.of_compatible = "mediatek,mt6397-rtc",
	}, {
		.name = "mt6397-regulator",
		.of_compatible = "mediatek,mt6397-regulator",
	}, {
		.name = "mt6397-codec",
		.of_compatible = "mediatek,mt6397-codec",
	}, {
		.name = "mt6397-clk",
		.of_compatible = "mediatek,mt6397-clk",
	}, {
		.name = "mt6397-pinctrl",
		.of_compatible = "mediatek,mt6397-pinctrl",
	}, {
		.name = "mtk-pmic-keys",
		.num_resources = ARRAY_SIZE(mt6397_keys_resources),
		.resources = mt6397_keys_resources,
		.of_compatible = "mediatek,mt6397-keys"
	}
};

static void mt6397_irq_lock(struct irq_data *data)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);

	mutex_lock(&mt6397->irqlock);
}

static void mt6397_irq_sync_unlock(struct irq_data *data)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);

	regmap_write(mt6397->regmap, mt6397->int_con[0],
		     mt6397->irq_masks_cur[0]);
	regmap_write(mt6397->regmap, mt6397->int_con[1],
		     mt6397->irq_masks_cur[1]);

	mutex_unlock(&mt6397->irqlock);
}

static void mt6397_irq_disable(struct irq_data *data)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
	int shift = data->hwirq & 0xf;
	int reg = data->hwirq >> 4;

	mt6397->irq_masks_cur[reg] &= ~BIT(shift);
}

static void mt6397_irq_enable(struct irq_data *data)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
	int shift = data->hwirq & 0xf;
	int reg = data->hwirq >> 4;

	mt6397->irq_masks_cur[reg] |= BIT(shift);
}

#ifdef CONFIG_PM_SLEEP
static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
	int shift = irq_data->hwirq & 0xf;
	int reg = irq_data->hwirq >> 4;

	if (on)
		mt6397->wake_mask[reg] |= BIT(shift);
	else
		mt6397->wake_mask[reg] &= ~BIT(shift);

	return 0;
}
#else
#define mt6397_irq_set_wake NULL
#endif

static struct irq_chip mt6397_irq_chip = {
	.name = "mt6397-irq",
	.irq_bus_lock = mt6397_irq_lock,
	.irq_bus_sync_unlock = mt6397_irq_sync_unlock,
	.irq_enable = mt6397_irq_enable,
	.irq_disable = mt6397_irq_disable,
	.irq_set_wake = mt6397_irq_set_wake,
};

static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
		int irqbase)
{
	unsigned int status;
	int i, irq, ret;

	ret = regmap_read(mt6397->regmap, reg, &status);
	if (ret) {
		dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
		return;
	}

	for (i = 0; i < 16; i++) {
		if (status & BIT(i)) {
			irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
			if (irq)
				handle_nested_irq(irq);
		}
	}

	regmap_write(mt6397->regmap, reg, status);
}

static irqreturn_t mt6397_irq_thread(int irq, void *data)
{
	struct mt6397_chip *mt6397 = data;

	mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
	mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);

	return IRQ_HANDLED;
}

static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
					irq_hw_number_t hw)
{
	struct mt6397_chip *mt6397 = d->host_data;

	irq_set_chip_data(irq, mt6397);
	irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
	irq_set_nested_thread(irq, 1);
	irq_set_noprobe(irq);

	return 0;
}

static const struct irq_domain_ops mt6397_irq_domain_ops = {
	.map = mt6397_irq_domain_map,
};

static int mt6397_irq_init(struct mt6397_chip *mt6397)
{
	int ret;

	mutex_init(&mt6397->irqlock);

	/* Mask all interrupt sources */
	regmap_write(mt6397->regmap, mt6397->int_con[0], 0x0);
	regmap_write(mt6397->regmap, mt6397->int_con[1], 0x0);

	mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
		MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
	if (!mt6397->irq_domain) {
		dev_err(mt6397->dev, "could not create irq domain\n");
		return -ENOMEM;
	}

	ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL,
		mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397);
	if (ret) {
		dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n",
			mt6397->irq, ret);
		return ret;
	}

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int mt6397_irq_suspend(struct device *dev)
{
	struct mt6397_chip *chip = dev_get_drvdata(dev);

	regmap_write(chip->regmap, chip->int_con[0], chip->wake_mask[0]);
	regmap_write(chip->regmap, chip->int_con[1], chip->wake_mask[1]);

	enable_irq_wake(chip->irq);

	return 0;
}

static int mt6397_irq_resume(struct device *dev)
{
	struct mt6397_chip *chip = dev_get_drvdata(dev);

	regmap_write(chip->regmap, chip->int_con[0], chip->irq_masks_cur[0]);
	regmap_write(chip->regmap, chip->int_con[1], chip->irq_masks_cur[1]);

	disable_irq_wake(chip->irq);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_irq_suspend,
			mt6397_irq_resume);

static int mt6397_probe(struct platform_device *pdev)
{
	int ret;
	unsigned int id;
	struct mt6397_chip *pmic;

	pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
	if (!pmic)
		return -ENOMEM;

	pmic->dev = &pdev->dev;

	/*
	 * mt6397 MFD is child device of soc pmic wrapper.
	 * Regmap is set from its parent.
	 */
	pmic->regmap = dev_get_regmap(pdev->dev.parent, NULL);
	if (!pmic->regmap)
		return -ENODEV;

	platform_set_drvdata(pdev, pmic);

	ret = regmap_read(pmic->regmap, MT6397_CID, &id);
	if (ret) {
		dev_err(pmic->dev, "Failed to read chip id: %d\n", ret);
		return ret;
	}

	pmic->irq = platform_get_irq(pdev, 0);
	if (pmic->irq <= 0)
		return pmic->irq;

	switch (id & 0xff) {
	case MT6323_CID_CODE:
		pmic->int_con[0] = MT6323_INT_CON0;
		pmic->int_con[1] = MT6323_INT_CON1;
		pmic->int_status[0] = MT6323_INT_STATUS0;
		pmic->int_status[1] = MT6323_INT_STATUS1;
		ret = mt6397_irq_init(pmic);
		if (ret)
			return ret;

		ret = devm_mfd_add_devices(&pdev->dev, -1, mt6323_devs,
					   ARRAY_SIZE(mt6323_devs), NULL,
					   0, pmic->irq_domain);
		break;

	case MT6397_CID_CODE:
	case MT6391_CID_CODE:
		pmic->int_con[0] = MT6397_INT_CON0;
		pmic->int_con[1] = MT6397_INT_CON1;
		pmic->int_status[0] = MT6397_INT_STATUS0;
		pmic->int_status[1] = MT6397_INT_STATUS1;
		ret = mt6397_irq_init(pmic);
		if (ret)
			return ret;

		ret = devm_mfd_add_devices(&pdev->dev, -1, mt6397_devs,
					   ARRAY_SIZE(mt6397_devs), NULL,
					   0, pmic->irq_domain);
		break;

	default:
		dev_err(&pdev->dev, "unsupported chip: %d\n", id);
		ret = -ENODEV;
		break;
	}

	if (ret) {
		irq_domain_remove(pmic->irq_domain);
		dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
	}

	return ret;
}

static const struct of_device_id mt6397_of_match[] = {
	{ .compatible = "mediatek,mt6397" },
	{ .compatible = "mediatek,mt6323" },
	{ }
};
MODULE_DEVICE_TABLE(of, mt6397_of_match);

static const struct platform_device_id mt6397_id[] = {
	{ "mt6397", 0 },
	{ },
};
MODULE_DEVICE_TABLE(platform, mt6397_id);

static struct platform_driver mt6397_driver = {
	.probe = mt6397_probe,
	.driver = {
		.name = "mt6397",
		.of_match_table = of_match_ptr(mt6397_of_match),
		.pm = &mt6397_pm_ops,
	},
	.id_table = mt6397_id,
};

module_platform_driver(mt6397_driver);

MODULE_AUTHOR("Flora Fu, MediaTek");
MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
MODULE_LICENSE("GPL");
Commit	Line	Data
6df8dd5c FF	1	/*
	2	* Copyright (c) 2014 MediaTek Inc.
	3	* Author: Flora Fu, MediaTek
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#include <linux/interrupt.h>
	16	#include <linux/module.h>
	17	#include <linux/of_device.h>
	18	#include <linux/of_irq.h>
	19	#include <linux/regmap.h>
	20	#include <linux/mfd/core.h>
	21	#include <linux/mfd/mt6397/core.h>
44760cf3	22	#include <linux/mfd/mt6323/core.h>
6df8dd5c	23	#include <linux/mfd/mt6397/registers.h>
44760cf3	24	#include <linux/mfd/mt6323/registers.h>
6df8dd5c	25
a5d7ea09 EH	26	#define MT6397_RTC_BASE 0xe000
	27	#define MT6397_RTC_SIZE 0x3e
	28
44760cf3	29	#define MT6323_CID_CODE 0x23
1d2c25ed JC	30	#define MT6391_CID_CODE 0x91
	31	#define MT6397_CID_CODE 0x97
	32
a5d7ea09 EH	33	static const struct resource mt6397_rtc_resources[] = {
	34	{
	35	.start = MT6397_RTC_BASE,
	36	.end = MT6397_RTC_BASE + MT6397_RTC_SIZE,
	37	.flags = IORESOURCE_MEM,
	38	},
	39	{
	40	.start = MT6397_IRQ_RTC,
	41	.end = MT6397_IRQ_RTC,
	42	.flags = IORESOURCE_IRQ,
	43	},
	44	};
	45
55d1d154 CZ	46	static const struct resource mt6323_keys_resources[] = {
	47	DEFINE_RES_IRQ(MT6323_IRQ_STATUS_PWRKEY),
	48	DEFINE_RES_IRQ(MT6323_IRQ_STATUS_FCHRKEY),
	49	};
	50
	51	static const struct resource mt6397_keys_resources[] = {
	52	DEFINE_RES_IRQ(MT6397_IRQ_PWRKEY),
	53	DEFINE_RES_IRQ(MT6397_IRQ_HOMEKEY),
	54	};
	55
44760cf3 JC	56	static const struct mfd_cell mt6323_devs[] = {
	57	{
	58	.name = "mt6323-regulator",
	59	.of_compatible = "mediatek,mt6323-regulator"
040fc9b1	60	}, {
1cb8af8d SW	61	.name = "mt6323-led",
1cb8af8d SW	62	.of_compatible = "mediatek,mt6323-led"
55d1d154 CZ	63	}, {
	64	.name = "mtk-pmic-keys",
	65	.num_resources = ARRAY_SIZE(mt6323_keys_resources),
	66	.resources = mt6323_keys_resources,
	67	.of_compatible = "mediatek,mt6323-keys"
1cb8af8d	68	},
44760cf3 JC	69	};
44760cf3 JC	70
6df8dd5c FF	71	static const struct mfd_cell mt6397_devs[] = {
	72	{
	73	.name = "mt6397-rtc",
a5d7ea09 EH	74	.num_resources = ARRAY_SIZE(mt6397_rtc_resources),
a5d7ea09 EH	75	.resources = mt6397_rtc_resources,
6df8dd5c FF	76	.of_compatible = "mediatek,mt6397-rtc",
	77	}, {
	78	.name = "mt6397-regulator",
	79	.of_compatible = "mediatek,mt6397-regulator",
	80	}, {
	81	.name = "mt6397-codec",
	82	.of_compatible = "mediatek,mt6397-codec",
	83	}, {
	84	.name = "mt6397-clk",
	85	.of_compatible = "mediatek,mt6397-clk",
cf55078b HY	86	}, {
	87	.name = "mt6397-pinctrl",
	88	.of_compatible = "mediatek,mt6397-pinctrl",
55d1d154 CZ	89	}, {
	90	.name = "mtk-pmic-keys",
	91	.num_resources = ARRAY_SIZE(mt6397_keys_resources),
	92	.resources = mt6397_keys_resources,
	93	.of_compatible = "mediatek,mt6397-keys"
	94	}
6df8dd5c FF	95	};
	96
	97	static void mt6397_irq_lock(struct irq_data *data)
	98	{
1e84aa44	99	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
6df8dd5c FF	100
	101	mutex_lock(&mt6397->irqlock);
	102	}
	103
	104	static void mt6397_irq_sync_unlock(struct irq_data *data)
	105	{
1e84aa44	106	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
6df8dd5c	107
feec4799 JC	108	regmap_write(mt6397->regmap, mt6397->int_con[0],
	109	mt6397->irq_masks_cur[0]);
	110	regmap_write(mt6397->regmap, mt6397->int_con[1],
	111	mt6397->irq_masks_cur[1]);
6df8dd5c FF	112
	113	mutex_unlock(&mt6397->irqlock);
	114	}
	115
	116	static void mt6397_irq_disable(struct irq_data *data)
	117	{
1e84aa44	118	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
6df8dd5c FF	119	int shift = data->hwirq & 0xf;
	120	int reg = data->hwirq >> 4;
	121
	122	mt6397->irq_masks_cur[reg] &= ~BIT(shift);
	123	}
	124
	125	static void mt6397_irq_enable(struct irq_data *data)
	126	{
1e84aa44	127	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
6df8dd5c FF	128	int shift = data->hwirq & 0xf;
	129	int reg = data->hwirq >> 4;
	130
	131	mt6397->irq_masks_cur[reg] \|= BIT(shift);
	132	}
	133
f3151ab4 HC	134	#ifdef CONFIG_PM_SLEEP
	135	static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
	136	{
	137	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
	138	int shift = irq_data->hwirq & 0xf;
	139	int reg = irq_data->hwirq >> 4;
	140
	141	if (on)
	142	mt6397->wake_mask[reg] \|= BIT(shift);
	143	else
	144	mt6397->wake_mask[reg] &= ~BIT(shift);
	145
	146	return 0;
	147	}
	148	#else
	149	#define mt6397_irq_set_wake NULL
	150	#endif
	151
6df8dd5c FF	152	static struct irq_chip mt6397_irq_chip = {
	153	.name = "mt6397-irq",
	154	.irq_bus_lock = mt6397_irq_lock,
	155	.irq_bus_sync_unlock = mt6397_irq_sync_unlock,
	156	.irq_enable = mt6397_irq_enable,
	157	.irq_disable = mt6397_irq_disable,
f3151ab4	158	.irq_set_wake = mt6397_irq_set_wake,
6df8dd5c FF	159	};
	160
	161	static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
	162	int irqbase)
	163	{
	164	unsigned int status;
	165	int i, irq, ret;
	166
	167	ret = regmap_read(mt6397->regmap, reg, &status);
	168	if (ret) {
	169	dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
	170	return;
	171	}
	172
	173	for (i = 0; i < 16; i++) {
	174	if (status & BIT(i)) {
	175	irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
	176	if (irq)
	177	handle_nested_irq(irq);
	178	}
	179	}
	180
	181	regmap_write(mt6397->regmap, reg, status);
	182	}
	183
	184	static irqreturn_t mt6397_irq_thread(int irq, void *data)
	185	{
	186	struct mt6397_chip *mt6397 = data;
	187
feec4799 JC	188	mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
feec4799 JC	189	mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
6df8dd5c FF	190
	191	return IRQ_HANDLED;
	192	}
	193
	194	static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
	195	irq_hw_number_t hw)
	196	{
	197	struct mt6397_chip *mt6397 = d->host_data;
	198
	199	irq_set_chip_data(irq, mt6397);
	200	irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
	201	irq_set_nested_thread(irq, 1);
6df8dd5c	202	irq_set_noprobe(irq);
6df8dd5c FF	203
	204	return 0;
	205	}
	206
7ce7b26f	207	static const struct irq_domain_ops mt6397_irq_domain_ops = {
6df8dd5c FF	208	.map = mt6397_irq_domain_map,
	209	};
	210
	211	static int mt6397_irq_init(struct mt6397_chip *mt6397)
	212	{
	213	int ret;
	214
	215	mutex_init(&mt6397->irqlock);
	216
	217	/* Mask all interrupt sources */
feec4799 JC	218	regmap_write(mt6397->regmap, mt6397->int_con[0], 0x0);
feec4799 JC	219	regmap_write(mt6397->regmap, mt6397->int_con[1], 0x0);
6df8dd5c FF	220
	221	mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
	222	MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
	223	if (!mt6397->irq_domain) {
	224	dev_err(mt6397->dev, "could not create irq domain\n");
	225	return -ENOMEM;
	226	}
	227
	228	ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL,
	229	mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397);
	230	if (ret) {
	231	dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n",
	232	mt6397->irq, ret);
	233	return ret;
	234	}
	235
	236	return 0;
	237	}
	238
f3151ab4 HC	239	#ifdef CONFIG_PM_SLEEP
	240	static int mt6397_irq_suspend(struct device *dev)
	241	{
	242	struct mt6397_chip *chip = dev_get_drvdata(dev);
	243
feec4799 JC	244	regmap_write(chip->regmap, chip->int_con[0], chip->wake_mask[0]);
feec4799 JC	245	regmap_write(chip->regmap, chip->int_con[1], chip->wake_mask[1]);
f3151ab4 HC	246
	247	enable_irq_wake(chip->irq);
	248
	249	return 0;
	250	}
	251
	252	static int mt6397_irq_resume(struct device *dev)
	253	{
	254	struct mt6397_chip *chip = dev_get_drvdata(dev);
	255
feec4799 JC	256	regmap_write(chip->regmap, chip->int_con[0], chip->irq_masks_cur[0]);
feec4799 JC	257	regmap_write(chip->regmap, chip->int_con[1], chip->irq_masks_cur[1]);
f3151ab4 HC	258
	259	disable_irq_wake(chip->irq);
	260
	261	return 0;
	262	}
	263	#endif
	264
	265	static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_irq_suspend,
	266	mt6397_irq_resume);
	267
6df8dd5c FF	268	static int mt6397_probe(struct platform_device *pdev)
	269	{
	270	int ret;
1d2c25ed JC	271	unsigned int id;
1d2c25ed JC	272	struct mt6397_chip *pmic;
6df8dd5c	273
1d2c25ed JC	274	pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
1d2c25ed JC	275	if (!pmic)
6df8dd5c FF	276	return -ENOMEM;
6df8dd5c FF	277
1d2c25ed	278	pmic->dev = &pdev->dev;
feec4799	279
6df8dd5c FF	280	/*
	281	* mt6397 MFD is child device of soc pmic wrapper.
	282	* Regmap is set from its parent.
	283	*/
1d2c25ed JC	284	pmic->regmap = dev_get_regmap(pdev->dev.parent, NULL);
1d2c25ed JC	285	if (!pmic->regmap)
6df8dd5c FF	286	return -ENODEV;
6df8dd5c FF	287
1d2c25ed JC	288	platform_set_drvdata(pdev, pmic);
	289
	290	ret = regmap_read(pmic->regmap, MT6397_CID, &id);
	291	if (ret) {
	292	dev_err(pmic->dev, "Failed to read chip id: %d\n", ret);
1387ff53	293	return ret;
1d2c25ed JC	294	}
1d2c25ed JC	295
1387ff53 HC	296	pmic->irq = platform_get_irq(pdev, 0);
	297	if (pmic->irq <= 0)
	298	return pmic->irq;
	299
1d2c25ed	300	switch (id & 0xff) {
44760cf3 JC	301	case MT6323_CID_CODE:
	302	pmic->int_con[0] = MT6323_INT_CON0;
	303	pmic->int_con[1] = MT6323_INT_CON1;
	304	pmic->int_status[0] = MT6323_INT_STATUS0;
	305	pmic->int_status[1] = MT6323_INT_STATUS1;
1387ff53 HC	306	ret = mt6397_irq_init(pmic);
	307	if (ret)
	308	return ret;
	309
08e380a5 LD	310	ret = devm_mfd_add_devices(&pdev->dev, -1, mt6323_devs,
08e380a5 LD	311	ARRAY_SIZE(mt6323_devs), NULL,
e695d3a0	312	0, pmic->irq_domain);
44760cf3 JC	313	break;
44760cf3 JC	314
1d2c25ed JC	315	case MT6397_CID_CODE:
	316	case MT6391_CID_CODE:
	317	pmic->int_con[0] = MT6397_INT_CON0;
	318	pmic->int_con[1] = MT6397_INT_CON1;
	319	pmic->int_status[0] = MT6397_INT_STATUS0;
	320	pmic->int_status[1] = MT6397_INT_STATUS1;
1387ff53 HC	321	ret = mt6397_irq_init(pmic);
	322	if (ret)
	323	return ret;
	324
08e380a5 LD	325	ret = devm_mfd_add_devices(&pdev->dev, -1, mt6397_devs,
08e380a5 LD	326	ARRAY_SIZE(mt6397_devs), NULL,
e695d3a0	327	0, pmic->irq_domain);
1d2c25ed JC	328	break;
	329
	330	default:
	331	dev_err(&pdev->dev, "unsupported chip: %d\n", id);
	332	ret = -ENODEV;
	333	break;
	334	}
6df8dd5c	335
1d2c25ed JC	336	if (ret) {
1d2c25ed JC	337	irq_domain_remove(pmic->irq_domain);
6df8dd5c	338	dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
1d2c25ed	339	}
6df8dd5c FF	340
	341	return ret;
	342	}
	343
6df8dd5c FF	344	static const struct of_device_id mt6397_of_match[] = {
6df8dd5c FF	345	{ .compatible = "mediatek,mt6397" },
44760cf3	346	{ .compatible = "mediatek,mt6323" },
6df8dd5c FF	347	{ }
	348	};
	349	MODULE_DEVICE_TABLE(of, mt6397_of_match);
	350
e1d9a109 JMC	351	static const struct platform_device_id mt6397_id[] = {
	352	{ "mt6397", 0 },
	353	{ },
	354	};
	355	MODULE_DEVICE_TABLE(platform, mt6397_id);
	356
6df8dd5c FF	357	static struct platform_driver mt6397_driver = {
6df8dd5c FF	358	.probe = mt6397_probe,
6df8dd5c FF	359	.driver = {
	360	.name = "mt6397",
	361	.of_match_table = of_match_ptr(mt6397_of_match),
f3151ab4	362	.pm = &mt6397_pm_ops,
6df8dd5c	363	},
e1d9a109	364	.id_table = mt6397_id,
6df8dd5c FF	365	};
	366
	367	module_platform_driver(mt6397_driver);
	368
	369	MODULE_AUTHOR("Flora Fu, MediaTek");
	370	MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
	371	MODULE_LICENSE("GPL");