[linux.git] / drivers / edac / amd76x_edac.c

/*
 * AMD 76x Memory Controller kernel module
 * (C) 2003 Linux Networx (http://lnxi.com)
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * Written by Thayne Harbaugh
 * Based on work by Dan Hollis <goemon at anime dot net> and others.
 *	http://www.anime.net/~goemon/linux-ecc/
 *
 * $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $
 *
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/edac.h>
#include "edac_module.h"

#define EDAC_MOD_STR	"amd76x_edac"

#define amd76x_printk(level, fmt, arg...) \
	edac_printk(level, "amd76x", fmt, ##arg)

#define amd76x_mc_printk(mci, level, fmt, arg...) \
	edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg)

#define AMD76X_NR_CSROWS 8
#define AMD76X_NR_DIMMS  4

/* AMD 76x register addresses - device 0 function 0 - PCI bridge */

#define AMD76X_ECC_MODE_STATUS	0x48	/* Mode and status of ECC (32b)
					 *
					 * 31:16 reserved
					 * 15:14 SERR enabled: x1=ue 1x=ce
					 * 13    reserved
					 * 12    diag: disabled, enabled
					 * 11:10 mode: dis, EC, ECC, ECC+scrub
					 *  9:8  status: x1=ue 1x=ce
					 *  7:4  UE cs row
					 *  3:0  CE cs row
					 */

#define AMD76X_DRAM_MODE_STATUS	0x58	/* DRAM Mode and status (32b)
					 *
					 * 31:26 clock disable 5 - 0
					 * 25    SDRAM init
					 * 24    reserved
					 * 23    mode register service
					 * 22:21 suspend to RAM
					 * 20    burst refresh enable
					 * 19    refresh disable
					 * 18    reserved
					 * 17:16 cycles-per-refresh
					 * 15:8  reserved
					 *  7:0  x4 mode enable 7 - 0
					 */

#define AMD76X_MEM_BASE_ADDR	0xC0	/* Memory base address (8 x 32b)
					 *
					 * 31:23 chip-select base
					 * 22:16 reserved
					 * 15:7  chip-select mask
					 *  6:3  reserved
					 *  2:1  address mode
					 *  0    chip-select enable
					 */

struct amd76x_error_info {
	u32 ecc_mode_status;
};

enum amd76x_chips {
	AMD761 = 0,
	AMD762
};

struct amd76x_dev_info {
	const char *ctl_name;
};

static const struct amd76x_dev_info amd76x_devs[] = {
	[AMD761] = {
		.ctl_name = "AMD761"},
	[AMD762] = {
		.ctl_name = "AMD762"},
};

static struct edac_pci_ctl_info *amd76x_pci;

/**
 *	amd76x_get_error_info	-	fetch error information
 *	@mci: Memory controller
 *	@info: Info to fill in
 *
 *	Fetch and store the AMD76x ECC status. Clear pending status
 *	on the chip so that further errors will be reported
 */
static void amd76x_get_error_info(struct mem_ctl_info *mci,
				struct amd76x_error_info *info)
{
	struct pci_dev *pdev;

	pdev = to_pci_dev(mci->pdev);
	pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS,
			&info->ecc_mode_status);

	if (info->ecc_mode_status & BIT(8))
		pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
				 (u32) BIT(8), (u32) BIT(8));

	if (info->ecc_mode_status & BIT(9))
		pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
				 (u32) BIT(9), (u32) BIT(9));
}

/**
 *	amd76x_process_error_info	-	Error check
 *	@mci: Memory controller
 *	@info: Previously fetched information from chip
 *	@handle_errors: 1 if we should do recovery
 *
 *	Process the chip state and decide if an error has occurred.
 *	A return of 1 indicates an error. Also if handle_errors is true
 *	then attempt to handle and clean up after the error
 */
static int amd76x_process_error_info(struct mem_ctl_info *mci,
				struct amd76x_error_info *info,
				int handle_errors)
{
	int error_found;
	u32 row;

	error_found = 0;

	/*
	 *      Check for an uncorrectable error
	 */
	if (info->ecc_mode_status & BIT(8)) {
		error_found = 1;

		if (handle_errors) {
			row = (info->ecc_mode_status >> 4) & 0xf;
			edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
					     mci->csrows[row]->first_page, 0, 0,
					     row, 0, -1,
					     mci->ctl_name, "");
		}
	}

	/*
	 *      Check for a correctable error
	 */
	if (info->ecc_mode_status & BIT(9)) {
		error_found = 1;

		if (handle_errors) {
			row = info->ecc_mode_status & 0xf;
			edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
					     mci->csrows[row]->first_page, 0, 0,
					     row, 0, -1,
					     mci->ctl_name, "");
		}
	}

	return error_found;
}

/**
 *	amd76x_check	-	Poll the controller
 *	@mci: Memory controller
 *
 *	Called by the poll handlers this function reads the status
 *	from the controller and checks for errors.
 */
static void amd76x_check(struct mem_ctl_info *mci)
{
	struct amd76x_error_info info;
	edac_dbg(3, "\n");
	amd76x_get_error_info(mci, &info);
	amd76x_process_error_info(mci, &info, 1);
}

static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
			enum edac_type edac_mode)
{
	struct csrow_info *csrow;
	struct dimm_info *dimm;
	u32 mba, mba_base, mba_mask, dms;
	int index;

	for (index = 0; index < mci->nr_csrows; index++) {
		csrow = mci->csrows[index];
		dimm = csrow->channels[0]->dimm;

		/* find the DRAM Chip Select Base address and mask */
		pci_read_config_dword(pdev,
				AMD76X_MEM_BASE_ADDR + (index * 4), &mba);

		if (!(mba & BIT(0)))
			continue;

		mba_base = mba & 0xff800000UL;
		mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
		pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms);
		csrow->first_page = mba_base >> PAGE_SHIFT;
		dimm->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
		csrow->last_page = csrow->first_page + dimm->nr_pages - 1;
		csrow->page_mask = mba_mask >> PAGE_SHIFT;
		dimm->grain = dimm->nr_pages << PAGE_SHIFT;
		dimm->mtype = MEM_RDDR;
		dimm->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
		dimm->edac_mode = edac_mode;
	}
}

/**
 *	amd76x_probe1	-	Perform set up for detected device
 *	@pdev; PCI device detected
 *	@dev_idx: Device type index
 *
 *	We have found an AMD76x and now need to set up the memory
 *	controller status reporting. We configure and set up the
 *	memory controller reporting and claim the device.
 */
static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
{
	static const enum edac_type ems_modes[] = {
		EDAC_NONE,
		EDAC_EC,
		EDAC_SECDED,
		EDAC_SECDED
	};
	struct mem_ctl_info *mci;
	struct edac_mc_layer layers[2];
	u32 ems;
	u32 ems_mode;
	struct amd76x_error_info discard;

	edac_dbg(0, "\n");
	pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
	ems_mode = (ems >> 10) & 0x3;

	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = AMD76X_NR_CSROWS;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	layers[1].size = 1;
	layers[1].is_virt_csrow = false;
	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);

	if (mci == NULL)
		return -ENOMEM;

	edac_dbg(0, "mci = %p\n", mci);
	mci->pdev = &pdev->dev;
	mci->mtype_cap = MEM_FLAG_RDDR;
	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
	mci->edac_cap = ems_mode ?
		(EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
	mci->mod_name = EDAC_MOD_STR;
	mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
	mci->dev_name = pci_name(pdev);
	mci->edac_check = amd76x_check;
	mci->ctl_page_to_phys = NULL;

	amd76x_init_csrows(mci, pdev, ems_modes[ems_mode]);
	amd76x_get_error_info(mci, &discard);	/* clear counters */

	/* Here we assume that we will never see multiple instances of this
	 * type of memory controller.  The ID is therefore hardcoded to 0.
	 */
	if (edac_mc_add_mc(mci)) {
		edac_dbg(3, "failed edac_mc_add_mc()\n");
		goto fail;
	}

	/* allocating generic PCI control info */
	amd76x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	if (!amd76x_pci) {
		printk(KERN_WARNING
			"%s(): Unable to create PCI control\n",
			__func__);
		printk(KERN_WARNING
			"%s(): PCI error report via EDAC not setup\n",
			__func__);
	}

	/* get this far and it's successful */
	edac_dbg(3, "success\n");
	return 0;

fail:
	edac_mc_free(mci);
	return -ENODEV;
}

/* returns count (>= 0), or negative on error */
static int amd76x_init_one(struct pci_dev *pdev,
			   const struct pci_device_id *ent)
{
	edac_dbg(0, "\n");

	/* don't need to call pci_enable_device() */
	return amd76x_probe1(pdev, ent->driver_data);
}

/**
 *	amd76x_remove_one	-	driver shutdown
 *	@pdev: PCI device being handed back
 *
 *	Called when the driver is unloaded. Find the matching mci
 *	structure for the device then delete the mci and free the
 *	resources.
 */
static void amd76x_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;

	edac_dbg(0, "\n");

	if (amd76x_pci)
		edac_pci_release_generic_ctl(amd76x_pci);

	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
		return;

	edac_mc_free(mci);
}

static const struct pci_device_id amd76x_pci_tbl[] = {
	{
	 PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 AMD762},
	{
	 PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 AMD761},
	{
	 0,
	 }			/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl);

static struct pci_driver amd76x_driver = {
	.name = EDAC_MOD_STR,
	.probe = amd76x_init_one,
	.remove = amd76x_remove_one,
	.id_table = amd76x_pci_tbl,
};

static int __init amd76x_init(void)
{
       /* Ensure that the OPSTATE is set correctly for POLL or NMI */
       opstate_init();

	return pci_register_driver(&amd76x_driver);
}

static void __exit amd76x_exit(void)
{
	pci_unregister_driver(&amd76x_driver);
}

module_init(amd76x_init);
module_exit(amd76x_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
MODULE_DESCRIPTION("MC support for AMD 76x memory controllers");

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Commit	Line	Data
806c35f5 AC	1	/*
	2	* AMD 76x Memory Controller kernel module
	3	* (C) 2003 Linux Networx (http://lnxi.com)
	4	* This file may be distributed under the terms of the
	5	* GNU General Public License.
	6	*
	7	* Written by Thayne Harbaugh
	8	* Based on work by Dan Hollis <goemon at anime dot net> and others.
	9	* http://www.anime.net/~goemon/linux-ecc/
	10	*
	11	* $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $
	12	*
	13	*/
	14
806c35f5 AC	15	#include <linux/module.h>
806c35f5 AC	16	#include <linux/init.h>
806c35f5 AC	17	#include <linux/pci.h>
806c35f5 AC	18	#include <linux/pci_ids.h>
c3c52bce	19	#include <linux/edac.h>
78d88e8a	20	#include "edac_module.h"
806c35f5	21
929a40ec	22	#define EDAC_MOD_STR "amd76x_edac"
37f04581	23
537fba28	24	#define amd76x_printk(level, fmt, arg...) \
e7ecd891	25	edac_printk(level, "amd76x", fmt, ##arg)
537fba28 DP	26
537fba28 DP	27	#define amd76x_mc_printk(mci, level, fmt, arg...) \
e7ecd891	28	edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg)
537fba28	29
806c35f5	30	#define AMD76X_NR_CSROWS 8
806c35f5 AC	31	#define AMD76X_NR_DIMMS 4
806c35f5 AC	32
806c35f5	33	/* AMD 76x register addresses - device 0 function 0 - PCI bridge */
e7ecd891	34
806c35f5 AC	35	#define AMD76X_ECC_MODE_STATUS 0x48 /* Mode and status of ECC (32b)
	36	*
	37	* 31:16 reserved
	38	* 15:14 SERR enabled: x1=ue 1x=ce
	39	* 13 reserved
	40	* 12 diag: disabled, enabled
	41	* 11:10 mode: dis, EC, ECC, ECC+scrub
	42	* 9:8 status: x1=ue 1x=ce
	43	* 7:4 UE cs row
	44	* 3:0 CE cs row
	45	*/
e7ecd891	46
806c35f5 AC	47	#define AMD76X_DRAM_MODE_STATUS 0x58 /* DRAM Mode and status (32b)
	48	*
	49	* 31:26 clock disable 5 - 0
	50	* 25 SDRAM init
	51	* 24 reserved
	52	* 23 mode register service
	53	* 22:21 suspend to RAM
	54	* 20 burst refresh enable
	55	* 19 refresh disable
	56	* 18 reserved
	57	* 17:16 cycles-per-refresh
	58	* 15:8 reserved
	59	* 7:0 x4 mode enable 7 - 0
	60	*/
e7ecd891	61
806c35f5 AC	62	#define AMD76X_MEM_BASE_ADDR 0xC0 /* Memory base address (8 x 32b)
	63	*
	64	* 31:23 chip-select base
	65	* 22:16 reserved
	66	* 15:7 chip-select mask
	67	* 6:3 reserved
	68	* 2:1 address mode
	69	* 0 chip-select enable
	70	*/
	71
806c35f5 AC	72	struct amd76x_error_info {
	73	u32 ecc_mode_status;
	74	};
	75
806c35f5 AC	76	enum amd76x_chips {
	77	AMD761 = 0,
	78	AMD762
	79	};
	80
806c35f5 AC	81	struct amd76x_dev_info {
	82	const char *ctl_name;
	83	};
	84
806c35f5	85	static const struct amd76x_dev_info amd76x_devs[] = {
e7ecd891	86	[AMD761] = {
052dfb45	87	.ctl_name = "AMD761"},
e7ecd891	88	[AMD762] = {
052dfb45	89	.ctl_name = "AMD762"},
806c35f5 AC	90	};
806c35f5 AC	91
456a2f95 DJ	92	static struct edac_pci_ctl_info *amd76x_pci;
456a2f95 DJ	93
806c35f5 AC	94	/**
	95	* amd76x_get_error_info - fetch error information
	96	* @mci: Memory controller
	97	* @info: Info to fill in
	98	*
	99	* Fetch and store the AMD76x ECC status. Clear pending status
	100	* on the chip so that further errors will be reported
	101	*/
e7ecd891	102	static void amd76x_get_error_info(struct mem_ctl_info *mci,
052dfb45	103	struct amd76x_error_info *info)
806c35f5	104	{
37f04581 DT	105	struct pci_dev *pdev;
37f04581 DT	106
fd687502	107	pdev = to_pci_dev(mci->pdev);
37f04581	108	pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS,
052dfb45	109	&info->ecc_mode_status);
806c35f5 AC	110
806c35f5 AC	111	if (info->ecc_mode_status & BIT(8))
37f04581	112	pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
67cb2b61	113	(u32) BIT(8), (u32) BIT(8));
806c35f5 AC	114
806c35f5 AC	115	if (info->ecc_mode_status & BIT(9))
37f04581	116	pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
67cb2b61	117	(u32) BIT(9), (u32) BIT(9));
806c35f5 AC	118	}
806c35f5 AC	119
806c35f5 AC	120	/**
	121	* amd76x_process_error_info - Error check
	122	* @mci: Memory controller
	123	* @info: Previously fetched information from chip
	124	* @handle_errors: 1 if we should do recovery
	125	*
	126	* Process the chip state and decide if an error has occurred.
	127	* A return of 1 indicates an error. Also if handle_errors is true
	128	* then attempt to handle and clean up after the error
	129	*/
e7ecd891	130	static int amd76x_process_error_info(struct mem_ctl_info *mci,
052dfb45 DT	131	struct amd76x_error_info *info,
052dfb45 DT	132	int handle_errors)
806c35f5 AC	133	{
	134	int error_found;
	135	u32 row;
	136
	137	error_found = 0;
	138
	139	/*
67cb2b61	140	* Check for an uncorrectable error
806c35f5 AC	141	*/
	142	if (info->ecc_mode_status & BIT(8)) {
	143	error_found = 1;
	144
	145	if (handle_errors) {
	146	row = (info->ecc_mode_status >> 4) & 0xf;
9eb07a7f	147	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
de3910eb	148	mci->csrows[row]->first_page, 0, 0,
d8c34af4	149	row, 0, -1,
03f7eae8	150	mci->ctl_name, "");
806c35f5 AC	151	}
	152	}
	153
	154	/*
67cb2b61	155	* Check for a correctable error
806c35f5 AC	156	*/
	157	if (info->ecc_mode_status & BIT(9)) {
	158	error_found = 1;
	159
	160	if (handle_errors) {
	161	row = info->ecc_mode_status & 0xf;
9eb07a7f	162	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
de3910eb	163	mci->csrows[row]->first_page, 0, 0,
d8c34af4	164	row, 0, -1,
03f7eae8	165	mci->ctl_name, "");
806c35f5 AC	166	}
806c35f5 AC	167	}
e7ecd891	168
806c35f5 AC	169	return error_found;
	170	}
	171
	172	/**
	173	* amd76x_check - Poll the controller
	174	* @mci: Memory controller
	175	*
	176	* Called by the poll handlers this function reads the status
	177	* from the controller and checks for errors.
	178	*/
806c35f5 AC	179	static void amd76x_check(struct mem_ctl_info *mci)
	180	{
	181	struct amd76x_error_info info;
956b9ba1	182	edac_dbg(3, "\n");
806c35f5 AC	183	amd76x_get_error_info(mci, &info);
	184	amd76x_process_error_info(mci, &info, 1);
	185	}
	186
13189525	187	static void amd76x_init_csrows(struct mem_ctl_info mci, struct pci_dev pdev,
052dfb45	188	enum edac_type edac_mode)
13189525 DT	189	{
13189525 DT	190	struct csrow_info *csrow;
084a4fcc	191	struct dimm_info *dimm;
13189525 DT	192	u32 mba, mba_base, mba_mask, dms;
	193	int index;
	194
	195	for (index = 0; index < mci->nr_csrows; index++) {
de3910eb MCC	196	csrow = mci->csrows[index];
de3910eb MCC	197	dimm = csrow->channels[0]->dimm;
13189525 DT	198
	199	/* find the DRAM Chip Select Base address and mask */
	200	pci_read_config_dword(pdev,
052dfb45	201	AMD76X_MEM_BASE_ADDR + (index * 4), &mba);
13189525 DT	202
	203	if (!(mba & BIT(0)))
	204	continue;
	205
	206	mba_base = mba & 0xff800000UL;
	207	mba_mask = ((mba & 0xff80) << 16) \| 0x7fffffUL;
	208	pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms);
	209	csrow->first_page = mba_base >> PAGE_SHIFT;
a895bf8b MCC	210	dimm->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
a895bf8b MCC	211	csrow->last_page = csrow->first_page + dimm->nr_pages - 1;
13189525	212	csrow->page_mask = mba_mask >> PAGE_SHIFT;
a895bf8b	213	dimm->grain = dimm->nr_pages << PAGE_SHIFT;
084a4fcc MCC	214	dimm->mtype = MEM_RDDR;
	215	dimm->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
	216	dimm->edac_mode = edac_mode;
13189525 DT	217	}
	218	}
	219
806c35f5 AC	220	/**
	221	* amd76x_probe1 - Perform set up for detected device
	222	* @pdev; PCI device detected
	223	* @dev_idx: Device type index
	224	*
	225	* We have found an AMD76x and now need to set up the memory
	226	* controller status reporting. We configure and set up the
	227	* memory controller reporting and claim the device.
	228	*/
806c35f5 AC	229	static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
806c35f5 AC	230	{
13189525	231	static const enum edac_type ems_modes[] = {
806c35f5 AC	232	EDAC_NONE,
	233	EDAC_EC,
	234	EDAC_SECDED,
	235	EDAC_SECDED
	236	};
d8c34af4 MCC	237	struct mem_ctl_info *mci;
d8c34af4 MCC	238	struct edac_mc_layer layers[2];
806c35f5 AC	239	u32 ems;
806c35f5 AC	240	u32 ems_mode;
749ede57	241	struct amd76x_error_info discard;
806c35f5	242
956b9ba1	243	edac_dbg(0, "\n");
806c35f5 AC	244	pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
806c35f5 AC	245	ems_mode = (ems >> 10) & 0x3;
806c35f5	246
d8c34af4 MCC	247	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	248	layers[0].size = AMD76X_NR_CSROWS;
	249	layers[0].is_virt_csrow = true;
	250	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	251	layers[1].size = 1;
	252	layers[1].is_virt_csrow = false;
ca0907b9	253	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
d8c34af4 MCC	254
d8c34af4 MCC	255	if (mci == NULL)
13189525	256	return -ENOMEM;
806c35f5	257
956b9ba1	258	edac_dbg(0, "mci = %p\n", mci);
fd687502	259	mci->pdev = &pdev->dev;
806c35f5	260	mci->mtype_cap = MEM_FLAG_RDDR;
806c35f5 AC	261	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_EC \| EDAC_FLAG_SECDED;
806c35f5 AC	262	mci->edac_cap = ems_mode ?
052dfb45	263	(EDAC_FLAG_EC \| EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
680cbbbb	264	mci->mod_name = EDAC_MOD_STR;
806c35f5	265	mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
c4192705	266	mci->dev_name = pci_name(pdev);
806c35f5 AC	267	mci->edac_check = amd76x_check;
	268	mci->ctl_page_to_phys = NULL;
	269
13189525	270	amd76x_init_csrows(mci, pdev, ems_modes[ems_mode]);
67cb2b61	271	amd76x_get_error_info(mci, &discard); /* clear counters */
806c35f5	272
2d7bbb91 DT	273	/* Here we assume that we will never see multiple instances of this
	274	* type of memory controller. The ID is therefore hardcoded to 0.
	275	*/
b8f6f975	276	if (edac_mc_add_mc(mci)) {
956b9ba1	277	edac_dbg(3, "failed edac_mc_add_mc()\n");
806c35f5 AC	278	goto fail;
	279	}
	280
456a2f95 DJ	281	/* allocating generic PCI control info */
	282	amd76x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	283	if (!amd76x_pci) {
	284	printk(KERN_WARNING
	285	"%s(): Unable to create PCI control\n",
	286	__func__);
	287	printk(KERN_WARNING
	288	"%s(): PCI error report via EDAC not setup\n",
	289	__func__);
	290	}
	291
806c35f5	292	/* get this far and it's successful */
956b9ba1	293	edac_dbg(3, "success\n");
806c35f5 AC	294	return 0;
806c35f5 AC	295
052dfb45	296	fail:
13189525 DT	297	edac_mc_free(mci);
13189525 DT	298	return -ENODEV;
806c35f5 AC	299	}
	300
	301	/* returns count (>= 0), or negative on error */
9b3c6e85 GKH	302	static int amd76x_init_one(struct pci_dev *pdev,
9b3c6e85 GKH	303	const struct pci_device_id *ent)
806c35f5	304	{
956b9ba1	305	edac_dbg(0, "\n");
806c35f5	306
ee6583f6	307	/* don't need to call pci_enable_device() */
806c35f5 AC	308	return amd76x_probe1(pdev, ent->driver_data);
	309	}
	310
806c35f5 AC	311	/**
	312	* amd76x_remove_one - driver shutdown
	313	* @pdev: PCI device being handed back
	314	*
	315	* Called when the driver is unloaded. Find the matching mci
	316	* structure for the device then delete the mci and free the
	317	* resources.
	318	*/
9b3c6e85	319	static void amd76x_remove_one(struct pci_dev *pdev)
806c35f5 AC	320	{
	321	struct mem_ctl_info *mci;
	322
956b9ba1	323	edac_dbg(0, "\n");
806c35f5	324
456a2f95 DJ	325	if (amd76x_pci)
	326	edac_pci_release_generic_ctl(amd76x_pci);
	327
37f04581	328	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
806c35f5	329	return;
18dbc337	330
806c35f5 AC	331	edac_mc_free(mci);
	332	}
	333
ba935f40	334	static const struct pci_device_id amd76x_pci_tbl[] = {
e7ecd891	335	{
67cb2b61 DT	336	PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
67cb2b61 DT	337	AMD762},
e7ecd891	338	{
67cb2b61 DT	339	PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
67cb2b61 DT	340	AMD761},
e7ecd891	341	{
67cb2b61 DT	342	0,
67cb2b61 DT	343	} /* 0 terminated list. */
806c35f5 AC	344	};
	345
	346	MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl);
	347
806c35f5	348	static struct pci_driver amd76x_driver = {
680cbbbb	349	.name = EDAC_MOD_STR,
806c35f5	350	.probe = amd76x_init_one,
9b3c6e85	351	.remove = amd76x_remove_one,
806c35f5 AC	352	.id_table = amd76x_pci_tbl,
	353	};
	354
da9bb1d2	355	static int __init amd76x_init(void)
806c35f5	356	{
c3c52bce HM	357	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	358	opstate_init();
	359
806c35f5 AC	360	return pci_register_driver(&amd76x_driver);
	361	}
	362
	363	static void __exit amd76x_exit(void)
	364	{
	365	pci_unregister_driver(&amd76x_driver);
	366	}
	367
	368	module_init(amd76x_init);
	369	module_exit(amd76x_exit);
	370
	371	MODULE_LICENSE("GPL");
	372	MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
	373	MODULE_DESCRIPTION("MC support for AMD 76x memory controllers");
c3c52bce HM	374
	375	module_param(edac_op_state, int, 0444);
	376	MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");