[linux.git] / arch / arm / mach-kirkwood / pcie.c

/*
 * arch/arm/mach-kirkwood/pcie.c
 *
 * PCIe functions for Marvell Kirkwood SoCs
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/mbus.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
#include <mach/bridge-regs.h>
#include "common.h"


#define PCIE_BASE	((void __iomem *)PCIE_VIRT_BASE)

void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
{
	*dev = orion_pcie_dev_id(PCIE_BASE);
	*rev = orion_pcie_rev(PCIE_BASE);
}

static int pcie_valid_config(int bus, int dev)
{
	/*
	 * Don't go out when trying to access --
	 * 1. nonexisting device on local bus
	 * 2. where there's no device connected (no link)
	 */
	if (bus == 0 && dev == 0)
		return 1;

	if (!orion_pcie_link_up(PCIE_BASE))
		return 0;

	if (bus == 0 && dev != 1)
		return 0;

	return 1;
}


/*
 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
 * and then reading the PCIE_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */
static DEFINE_SPINLOCK(kirkwood_pcie_lock);

static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
			int size, u32 *val)
{
	unsigned long flags;
	int ret;

	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	spin_lock_irqsave(&kirkwood_pcie_lock, flags);
	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);

	return ret;
}

static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
			int where, int size, u32 val)
{
	unsigned long flags;
	int ret;

	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	spin_lock_irqsave(&kirkwood_pcie_lock, flags);
	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);

	return ret;
}

static struct pci_ops pcie_ops = {
	.read = pcie_rd_conf,
	.write = pcie_wr_conf,
};


static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
{
	struct resource *res;
	extern unsigned int kirkwood_clk_ctrl;

	/*
	 * Generic PCIe unit setup.
	 */
	orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);

	/*
	 * Request resources.
	 */
	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	if (!res)
		panic("pcie_setup unable to alloc resources");

	/*
	 * IORESOURCE_IO
	 */
	res[0].name = "PCIe I/O Space";
	res[0].flags = IORESOURCE_IO;
	res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
	res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
	if (request_resource(&ioport_resource, &res[0]))
		panic("Request PCIe IO resource failed\n");
	sys->resource[0] = &res[0];

	/*
	 * IORESOURCE_MEM
	 */
	res[1].name = "PCIe Memory Space";
	res[1].flags = IORESOURCE_MEM;
	res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE;
	res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
	if (request_resource(&iomem_resource, &res[1]))
		panic("Request PCIe Memory resource failed\n");
	sys->resource[1] = &res[1];

	sys->resource[2] = NULL;
	sys->io_offset = 0;

	kirkwood_clk_ctrl |= CGC_PEX0;

	return 1;
}

static void __devinit rc_pci_fixup(struct pci_dev *dev)
{
	/*
	 * Prevent enumeration of root complex.
	 */
	if (dev->bus->parent == NULL && dev->devfn == 0) {
		int i;

		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end   = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);

static struct pci_bus __init *
kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
{
	struct pci_bus *bus;

	if (nr == 0) {
		bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
	} else {
		bus = NULL;
		BUG();
	}

	return bus;
}

static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	return IRQ_KIRKWOOD_PCIE;
}

static struct hw_pci kirkwood_pci __initdata = {
	.nr_controllers	= 1,
	.swizzle	= pci_std_swizzle,
	.setup		= kirkwood_pcie_setup,
	.scan		= kirkwood_pcie_scan_bus,
	.map_irq	= kirkwood_pcie_map_irq,
};

void __init kirkwood_pcie_init(void)
{
	pci_common_init(&kirkwood_pci);
}
Commit	Line	Data
651c74c7 SB	1	/*
	2	* arch/arm/mach-kirkwood/pcie.c
	3	*
	4	* PCIe functions for Marvell Kirkwood SoCs
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/pci.h>
5a0e3ad6	13	#include <linux/slab.h>
651c74c7	14	#include <linux/mbus.h>
6e5c11a1	15	#include <asm/irq.h>
651c74c7	16	#include <asm/mach/pci.h>
6f088f1d	17	#include <plat/pcie.h>
e8b2b7ba	18	#include <mach/bridge-regs.h>
651c74c7 SB	19	#include "common.h"
	20
	21
	22	#define PCIE_BASE ((void __iomem *)PCIE_VIRT_BASE)
	23
b2b3dc2f RS	24	void __init kirkwood_pcie_id(u32 dev, u32 rev)
	25	{
	26	*dev = orion_pcie_dev_id(PCIE_BASE);
	27	*rev = orion_pcie_rev(PCIE_BASE);
	28	}
	29
651c74c7 SB	30	static int pcie_valid_config(int bus, int dev)
	31	{
	32	/*
	33	* Don't go out when trying to access --
	34	* 1. nonexisting device on local bus
	35	* 2. where there's no device connected (no link)
	36	*/
	37	if (bus == 0 && dev == 0)
	38	return 1;
	39
	40	if (!orion_pcie_link_up(PCIE_BASE))
	41	return 0;
	42
	43	if (bus == 0 && dev != 1)
	44	return 0;
	45
	46	return 1;
	47	}
	48
	49
	50	/*
	51	* PCIe config cycles are done by programming the PCIE_CONF_ADDR register
	52	* and then reading the PCIE_CONF_DATA register. Need to make sure these
	53	* transactions are atomic.
	54	*/
	55	static DEFINE_SPINLOCK(kirkwood_pcie_lock);
	56
	57	static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
	58	int size, u32 *val)
	59	{
	60	unsigned long flags;
	61	int ret;
	62
	63	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
	64	*val = 0xffffffff;
	65	return PCIBIOS_DEVICE_NOT_FOUND;
	66	}
	67
	68	spin_lock_irqsave(&kirkwood_pcie_lock, flags);
	69	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
	70	spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
	71
	72	return ret;
	73	}
	74
	75	static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
	76	int where, int size, u32 val)
	77	{
	78	unsigned long flags;
	79	int ret;
	80
	81	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
	82	return PCIBIOS_DEVICE_NOT_FOUND;
	83
	84	spin_lock_irqsave(&kirkwood_pcie_lock, flags);
	85	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
	86	spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
	87
	88	return ret;
	89	}
	90
	91	static struct pci_ops pcie_ops = {
	92	.read = pcie_rd_conf,
	93	.write = pcie_wr_conf,
94	};
95
96
6de95c19	97	static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
651c74c7 SB	98	{
651c74c7 SB	99	struct resource *res;
e8b2b7ba	100	extern unsigned int kirkwood_clk_ctrl;
651c74c7 SB	101
	102	/*
	103	* Generic PCIe unit setup.
	104	*/
	105	orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
	106
	107	/*
	108	* Request resources.
	109	*/
	110	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	111	if (!res)
	112	panic("pcie_setup unable to alloc resources");
	113
	114	/*
	115	* IORESOURCE_IO
	116	*/
	117	res[0].name = "PCIe I/O Space";
	118	res[0].flags = IORESOURCE_IO;
35f029e2	119	res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
651c74c7 SB	120	res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
	121	if (request_resource(&ioport_resource, &res[0]))
	122	panic("Request PCIe IO resource failed\n");
	123	sys->resource[0] = &res[0];
	124
	125	/*
	126	* IORESOURCE_MEM
	127	*/
	128	res[1].name = "PCIe Memory Space";
	129	res[1].flags = IORESOURCE_MEM;
a1897fa6	130	res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE;
651c74c7 SB	131	res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
	132	if (request_resource(&iomem_resource, &res[1]))
	133	panic("Request PCIe Memory resource failed\n");
	134	sys->resource[1] = &res[1];
	135
	136	sys->resource[2] = NULL;
	137	sys->io_offset = 0;
	138
e8b2b7ba RK	139	kirkwood_clk_ctrl \|= CGC_PEX0;
e8b2b7ba RK	140
651c74c7 SB	141	return 1;
	142	}
	143
	144	static void __devinit rc_pci_fixup(struct pci_dev *dev)
	145	{
	146	/*
	147	* Prevent enumeration of root complex.
	148	*/
	149	if (dev->bus->parent == NULL && dev->devfn == 0) {
	150	int i;
	151
	152	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
	153	dev->resource[i].start = 0;
	154	dev->resource[i].end = 0;
	155	dev->resource[i].flags = 0;
	156	}
	157	}
	158	}
	159	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
	160
	161	static struct pci_bus __init *
	162	kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
	163	{
	164	struct pci_bus *bus;
	165
	166	if (nr == 0) {
	167	bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
	168	} else {
	169	bus = NULL;
	170	BUG();
	171	}
	172
	173	return bus;
	174	}
	175
	176	static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	177	{
	178	return IRQ_KIRKWOOD_PCIE;
	179	}
	180
	181	static struct hw_pci kirkwood_pci __initdata = {
	182	.nr_controllers = 1,
	183	.swizzle = pci_std_swizzle,
	184	.setup = kirkwood_pcie_setup,
	185	.scan = kirkwood_pcie_scan_bus,
	186	.map_irq = kirkwood_pcie_map_irq,
	187	};
	188
	189	void __init kirkwood_pcie_init(void)
	190	{
	191	pci_common_init(&kirkwood_pci);
	192	}