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Linux 3.0-rc2
[linux.git] / drivers / gpio / gpio-omap.c
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5e1c5ff4 1/*
5e1c5ff4
TL		 2 * Support functions for OMAP GPIO
3 *
92105bb7 4 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 5 * Written by Juha Yrjölä <[email protected]>
5e1c5ff4 6 *
44169075
SS		 7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <[email protected]>
9 *
5e1c5ff4
TL		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
5e1c5ff4
TL		 15#include <linux/init.h>
16#include <linux/module.h>
5e1c5ff4 17#include <linux/interrupt.h>
3c437ffd 18#include <linux/syscore_ops.h>
92105bb7 19#include <linux/err.h>
f8ce2547 20#include <linux/clk.h>
fced80c7 21#include <linux/io.h>
77640aab
VC		 22#include <linux/slab.h>
23#include <linux/pm_runtime.h>
5e1c5ff4 24
a09e64fb 25#include <mach/hardware.h>
5e1c5ff4 26#include <asm/irq.h>
a09e64fb
RK		 27#include <mach/irqs.h>
28#include <mach/gpio.h>
5e1c5ff4
TL		 29#include <asm/mach/irq.h>
30
5e1c5ff4 31struct gpio_bank {
9f7065da 32 unsigned long pbase;
92105bb7 33 void __iomem *base;
5e1c5ff4
TL		 34 u16 irq;
35 u16 virtual_irq_start;
92105bb7 36 int method;
140455fa 37#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
92105bb7
TL		 38 u32 suspend_wakeup;
39 u32 saved_wakeup;
3ac4fa99 40#endif
3ac4fa99
JY		 41 u32 non_wakeup_gpios;
42 u32 enabled_non_wakeup_gpios;
43
44 u32 saved_datain;
45 u32 saved_fallingdetect;
46 u32 saved_risingdetect;
b144ff6f 47 u32 level_mask;
4318f36b 48 u32 toggle_mask;
5e1c5ff4 49 spinlock_t lock;
52e31344 50 struct gpio_chip chip;
89db9482 51 struct clk *dbck;
058af1ea 52 u32 mod_usage;
8865b9b6 53 u32 dbck_enable_mask;
77640aab
VC		 54 struct device *dev;
55 bool dbck_flag;
5de62b86 56 int stride;
5e1c5ff4
TL		 57};
58
a8eb7ca0 59#ifdef CONFIG_ARCH_OMAP3
40c670f0 60struct omap3_gpio_regs {
40c670f0
RN		 61 u32 irqenable1;
62 u32 irqenable2;
63 u32 wake_en;
64 u32 ctrl;
65 u32 oe;
66 u32 leveldetect0;
67 u32 leveldetect1;
68 u32 risingdetect;
69 u32 fallingdetect;
70 u32 dataout;
5492fb1a
SMK		 71};
72
40c670f0 73static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
5492fb1a
SMK		 74#endif
75
77640aab
VC		 76/*
77 * TODO: Cleanup gpio_bank usage as it is having information
78 * related to all instances of the device
79 */
80static struct gpio_bank *gpio_bank;
44169075 81
77640aab 82static int bank_width;
44169075 83
c95d10bc
VC		 84/* TODO: Analyze removing gpio_bank_count usage from driver code */
85int gpio_bank_count;
5e1c5ff4
TL		 86
87static inline struct gpio_bank *get_gpio_bank(int gpio)
88{
6e60e79a 89 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 90 if (OMAP_GPIO_IS_MPUIO(gpio))
91 return &gpio_bank[0];
92 return &gpio_bank[1];
93 }
5e1c5ff4
TL		 94 if (cpu_is_omap16xx()) {
95 if (OMAP_GPIO_IS_MPUIO(gpio))
96 return &gpio_bank[0];
97 return &gpio_bank[1 + (gpio >> 4)];
98 }
56739a69 99 if (cpu_is_omap7xx()) {
5e1c5ff4
TL		 100 if (OMAP_GPIO_IS_MPUIO(gpio))
101 return &gpio_bank[0];
102 return &gpio_bank[1 + (gpio >> 5)];
103 }
92105bb7
TL		 104 if (cpu_is_omap24xx())
105 return &gpio_bank[gpio >> 5];
44169075 106 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 107 return &gpio_bank[gpio >> 5];
e031ab23
DB		 108 BUG();
109 return NULL;
5e1c5ff4
TL		 110}
111
112static inline int get_gpio_index(int gpio)
113{
56739a69 114 if (cpu_is_omap7xx())
5e1c5ff4 115 return gpio & 0x1f;
92105bb7
TL		 116 if (cpu_is_omap24xx())
117 return gpio & 0x1f;
44169075 118 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 119 return gpio & 0x1f;
92105bb7 120 return gpio & 0x0f;
5e1c5ff4
TL		 121}
122
123static inline int gpio_valid(int gpio)
124{
125 if (gpio < 0)
126 return -1;
d11ac979 127 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 128 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 129 return -1;
130 return 0;
131 }
6e60e79a 132 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 133 return 0;
5e1c5ff4
TL		 134 if ((cpu_is_omap16xx()) && gpio < 64)
135 return 0;
56739a69 136 if (cpu_is_omap7xx() && gpio < 192)
5e1c5ff4 137 return 0;
25d6f630
TL		 138 if (cpu_is_omap2420() && gpio < 128)
139 return 0;
140 if (cpu_is_omap2430() && gpio < 160)
92105bb7 141 return 0;
44169075 142 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
5492fb1a 143 return 0;
5e1c5ff4
TL		 144 return -1;
145}
146
147static int check_gpio(int gpio)
148{
d32b20fc 149 if (unlikely(gpio_valid(gpio) < 0)) {
5e1c5ff4
TL		 150 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
151 dump_stack();
152 return -1;
153 }
154 return 0;
155}
156
157static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
158{
92105bb7 159 void __iomem *reg = bank->base;
5e1c5ff4
TL		 160 u32 l;
161
162 switch (bank->method) {
e5c56ed3 163#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 164 case METHOD_MPUIO:
5de62b86 165 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
5e1c5ff4 166 break;
e5c56ed3
DB		 167#endif
168#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 169 case METHOD_GPIO_1510:
170 reg += OMAP1510_GPIO_DIR_CONTROL;
171 break;
e5c56ed3
DB		 172#endif
173#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 174 case METHOD_GPIO_1610:
175 reg += OMAP1610_GPIO_DIRECTION;
176 break;
e5c56ed3 177#endif
b718aa81 178#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 179 case METHOD_GPIO_7XX:
180 reg += OMAP7XX_GPIO_DIR_CONTROL;
56739a69
ZM		 181 break;
182#endif
a8eb7ca0 183#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 184 case METHOD_GPIO_24XX:
185 reg += OMAP24XX_GPIO_OE;
186 break;
78a1a6d3
SR		 187#endif
188#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 189 case METHOD_GPIO_44XX:
78a1a6d3
SR		 190 reg += OMAP4_GPIO_OE;
191 break;
e5c56ed3
DB		 192#endif
193 default:
194 WARN_ON(1);
195 return;
5e1c5ff4
TL		 196 }
197 l = __raw_readl(reg);
198 if (is_input)
199 l |= 1 << gpio;
200 else
201 l &= ~(1 << gpio);
202 __raw_writel(l, reg);
203}
204
5e1c5ff4
TL		 205static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
206{
92105bb7 207 void __iomem *reg = bank->base;
5e1c5ff4
TL		 208 u32 l = 0;
209
210 switch (bank->method) {
e5c56ed3 211#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 212 case METHOD_MPUIO:
5de62b86 213 reg += OMAP_MPUIO_OUTPUT / bank->stride;
5e1c5ff4
TL		 214 l = __raw_readl(reg);
215 if (enable)
216 l |= 1 << gpio;
217 else
218 l &= ~(1 << gpio);
219 break;
e5c56ed3
DB		 220#endif
221#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 222 case METHOD_GPIO_1510:
223 reg += OMAP1510_GPIO_DATA_OUTPUT;
224 l = __raw_readl(reg);
225 if (enable)
226 l |= 1 << gpio;
227 else
228 l &= ~(1 << gpio);
229 break;
e5c56ed3
DB		 230#endif
231#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 232 case METHOD_GPIO_1610:
233 if (enable)
234 reg += OMAP1610_GPIO_SET_DATAOUT;
235 else
236 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
237 l = 1 << gpio;
238 break;
e5c56ed3 239#endif
b718aa81 240#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 241 case METHOD_GPIO_7XX:
242 reg += OMAP7XX_GPIO_DATA_OUTPUT;
56739a69
ZM		 243 l = __raw_readl(reg);
244 if (enable)
245 l |= 1 << gpio;
246 else
247 l &= ~(1 << gpio);
248 break;
249#endif
a8eb7ca0 250#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 251 case METHOD_GPIO_24XX:
252 if (enable)
253 reg += OMAP24XX_GPIO_SETDATAOUT;
254 else
255 reg += OMAP24XX_GPIO_CLEARDATAOUT;
256 l = 1 << gpio;
257 break;
78a1a6d3
SR		 258#endif
259#ifdef CONFIG_ARCH_OMAP4
3f1686a9 260 case METHOD_GPIO_44XX:
78a1a6d3
SR		 261 if (enable)
262 reg += OMAP4_GPIO_SETDATAOUT;
263 else
264 reg += OMAP4_GPIO_CLEARDATAOUT;
265 l = 1 << gpio;
266 break;
e5c56ed3 267#endif
5e1c5ff4 268 default:
e5c56ed3 269 WARN_ON(1);
5e1c5ff4
TL		 270 return;
271 }
272 __raw_writel(l, reg);
273}
274
b37c45b8 275static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
5e1c5ff4 276{
92105bb7 277 void __iomem *reg;
5e1c5ff4
TL		 278
279 if (check_gpio(gpio) < 0)
e5c56ed3 280 return -EINVAL;
5e1c5ff4
TL		 281 reg = bank->base;
282 switch (bank->method) {
e5c56ed3 283#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 284 case METHOD_MPUIO:
5de62b86 285 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
5e1c5ff4 286 break;
e5c56ed3
DB		 287#endif
288#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 289 case METHOD_GPIO_1510:
290 reg += OMAP1510_GPIO_DATA_INPUT;
291 break;
e5c56ed3
DB		 292#endif
293#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 294 case METHOD_GPIO_1610:
295 reg += OMAP1610_GPIO_DATAIN;
296 break;
e5c56ed3 297#endif
b718aa81 298#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 299 case METHOD_GPIO_7XX:
300 reg += OMAP7XX_GPIO_DATA_INPUT;
56739a69
ZM		 301 break;
302#endif
a8eb7ca0 303#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 304 case METHOD_GPIO_24XX:
305 reg += OMAP24XX_GPIO_DATAIN;
306 break;
78a1a6d3
SR		 307#endif
308#ifdef CONFIG_ARCH_OMAP4
3f1686a9 309 case METHOD_GPIO_44XX:
78a1a6d3
SR		 310 reg += OMAP4_GPIO_DATAIN;
311 break;
e5c56ed3 312#endif
5e1c5ff4 313 default:
e5c56ed3 314 return -EINVAL;
5e1c5ff4 315 }
92105bb7
TL		 316 return (__raw_readl(reg)
317 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 318}
319
b37c45b8
RQ		 320static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
321{
322 void __iomem *reg;
323
324 if (check_gpio(gpio) < 0)
325 return -EINVAL;
326 reg = bank->base;
327
328 switch (bank->method) {
329#ifdef CONFIG_ARCH_OMAP1
330 case METHOD_MPUIO:
5de62b86 331 reg += OMAP_MPUIO_OUTPUT / bank->stride;
b37c45b8
RQ		 332 break;
333#endif
334#ifdef CONFIG_ARCH_OMAP15XX
335 case METHOD_GPIO_1510:
336 reg += OMAP1510_GPIO_DATA_OUTPUT;
337 break;
338#endif
339#ifdef CONFIG_ARCH_OMAP16XX
340 case METHOD_GPIO_1610:
341 reg += OMAP1610_GPIO_DATAOUT;
342 break;
343#endif
b718aa81 344#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 345 case METHOD_GPIO_7XX:
346 reg += OMAP7XX_GPIO_DATA_OUTPUT;
b37c45b8
RQ		 347 break;
348#endif
9f096868 349#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
b37c45b8
RQ		 350 case METHOD_GPIO_24XX:
351 reg += OMAP24XX_GPIO_DATAOUT;
352 break;
9f096868
C		 353#endif
354#ifdef CONFIG_ARCH_OMAP4
355 case METHOD_GPIO_44XX:
356 reg += OMAP4_GPIO_DATAOUT;
357 break;
b37c45b8
RQ		 358#endif
359 default:
360 return -EINVAL;
361 }
362
363 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
364}
365
92105bb7
TL		 366#define MOD_REG_BIT(reg, bit_mask, set) \
367do { \
368 int l = __raw_readl(base + reg); \
369 if (set) l |= bit_mask; \
370 else l &= ~bit_mask; \
371 __raw_writel(l, base + reg); \
372} while(0)
373
168ef3d9
FB		 374/**
375 * _set_gpio_debounce - low level gpio debounce time
376 * @bank: the gpio bank we're acting upon
377 * @gpio: the gpio number on this @gpio
378 * @debounce: debounce time to use
379 *
380 * OMAP's debounce time is in 31us steps so we need
381 * to convert and round up to the closest unit.
382 */
383static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
384 unsigned debounce)
385{
386 void __iomem *reg = bank->base;
387 u32 val;
388 u32 l;
389
77640aab
VC		 390 if (!bank->dbck_flag)
391 return;
392
168ef3d9
FB		 393 if (debounce < 32)
394 debounce = 0x01;
395 else if (debounce > 7936)
396 debounce = 0xff;
397 else
398 debounce = (debounce / 0x1f) - 1;
399
400 l = 1 << get_gpio_index(gpio);
401
77640aab 402 if (bank->method == METHOD_GPIO_44XX)
168ef3d9
FB		 403 reg += OMAP4_GPIO_DEBOUNCINGTIME;
404 else
405 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
406
407 __raw_writel(debounce, reg);
408
409 reg = bank->base;
77640aab 410 if (bank->method == METHOD_GPIO_44XX)
168ef3d9
FB		 411 reg += OMAP4_GPIO_DEBOUNCENABLE;
412 else
413 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
414
415 val = __raw_readl(reg);
416
417 if (debounce) {
418 val |= l;
77640aab 419 clk_enable(bank->dbck);
168ef3d9
FB		 420 } else {
421 val &= ~l;
77640aab 422 clk_disable(bank->dbck);
168ef3d9 423 }
f7ec0b0b 424 bank->dbck_enable_mask = val;
168ef3d9
FB		 425
426 __raw_writel(val, reg);
427}
428
140455fa 429#ifdef CONFIG_ARCH_OMAP2PLUS
5eb3bb9c
KH		 430static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
431 int trigger)
5e1c5ff4 432{
3ac4fa99 433 void __iomem *base = bank->base;
92105bb7 434 u32 gpio_bit = 1 << gpio;
78a1a6d3 435 u32 val;
92105bb7 436
78a1a6d3
SR		 437 if (cpu_is_omap44xx()) {
438 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
439 trigger & IRQ_TYPE_LEVEL_LOW);
440 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
441 trigger & IRQ_TYPE_LEVEL_HIGH);
442 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
443 trigger & IRQ_TYPE_EDGE_RISING);
444 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
445 trigger & IRQ_TYPE_EDGE_FALLING);
446 } else {
447 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
448 trigger & IRQ_TYPE_LEVEL_LOW);
449 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
450 trigger & IRQ_TYPE_LEVEL_HIGH);
451 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
452 trigger & IRQ_TYPE_EDGE_RISING);
453 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
454 trigger & IRQ_TYPE_EDGE_FALLING);
455 }
3ac4fa99 456 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
78a1a6d3
SR		 457 if (cpu_is_omap44xx()) {
458 if (trigger != 0)
459 __raw_writel(1 << gpio, bank->base+
460 OMAP4_GPIO_IRQWAKEN0);
461 else {
462 val = __raw_readl(bank->base +
463 OMAP4_GPIO_IRQWAKEN0);
464 __raw_writel(val & (~(1 << gpio)), bank->base +
465 OMAP4_GPIO_IRQWAKEN0);
466 }
467 } else {
699117a6
CW		 468 /*
469 * GPIO wakeup request can only be generated on edge
470 * transitions
471 */
472 if (trigger & IRQ_TYPE_EDGE_BOTH)
78a1a6d3 473 __raw_writel(1 << gpio, bank->base
5eb3bb9c 474 + OMAP24XX_GPIO_SETWKUENA);
78a1a6d3
SR		 475 else
476 __raw_writel(1 << gpio, bank->base
5eb3bb9c 477 + OMAP24XX_GPIO_CLEARWKUENA);
78a1a6d3 478 }
a118b5f3
TK		 479 }
480 /* This part needs to be executed always for OMAP34xx */
481 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
699117a6
CW		 482 /*
483 * Log the edge gpio and manually trigger the IRQ
484 * after resume if the input level changes
485 * to avoid irq lost during PER RET/OFF mode
486 * Applies for omap2 non-wakeup gpio and all omap3 gpios
487 */
488 if (trigger & IRQ_TYPE_EDGE_BOTH)
3ac4fa99
JY		 489 bank->enabled_non_wakeup_gpios |= gpio_bit;
490 else
491 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
492 }
5eb3bb9c 493
78a1a6d3
SR		 494 if (cpu_is_omap44xx()) {
495 bank->level_mask =
496 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
497 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
498 } else {
499 bank->level_mask =
500 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
501 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
502 }
92105bb7 503}
3ac4fa99 504#endif
92105bb7 505
9198bcd3 506#ifdef CONFIG_ARCH_OMAP1
4318f36b
CM		 507/*
508 * This only applies to chips that can't do both rising and falling edge
509 * detection at once. For all other chips, this function is a noop.
510 */
511static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
512{
513 void __iomem *reg = bank->base;
514 u32 l = 0;
515
516 switch (bank->method) {
4318f36b 517 case METHOD_MPUIO:
5de62b86 518 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
4318f36b 519 break;
4318f36b
CM		 520#ifdef CONFIG_ARCH_OMAP15XX
521 case METHOD_GPIO_1510:
522 reg += OMAP1510_GPIO_INT_CONTROL;
523 break;
524#endif
525#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
526 case METHOD_GPIO_7XX:
527 reg += OMAP7XX_GPIO_INT_CONTROL;
528 break;
529#endif
530 default:
531 return;
532 }
533
534 l = __raw_readl(reg);
535 if ((l >> gpio) & 1)
536 l &= ~(1 << gpio);
537 else
538 l |= 1 << gpio;
539
540 __raw_writel(l, reg);
541}
9198bcd3 542#endif
4318f36b 543
92105bb7
TL		 544static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
545{
546 void __iomem *reg = bank->base;
547 u32 l = 0;
5e1c5ff4
TL		 548
549 switch (bank->method) {
e5c56ed3 550#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 551 case METHOD_MPUIO:
5de62b86 552 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
5e1c5ff4 553 l = __raw_readl(reg);
29501577 554 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 555 bank->toggle_mask |= 1 << gpio;
6cab4860 556 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 557 l |= 1 << gpio;
6cab4860 558 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 559 l &= ~(1 << gpio);
92105bb7
TL		 560 else
561 goto bad;
5e1c5ff4 562 break;
e5c56ed3
DB		 563#endif
564#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 565 case METHOD_GPIO_1510:
566 reg += OMAP1510_GPIO_INT_CONTROL;
567 l = __raw_readl(reg);
29501577 568 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 569 bank->toggle_mask |= 1 << gpio;
6cab4860 570 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 571 l |= 1 << gpio;
6cab4860 572 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 573 l &= ~(1 << gpio);
92105bb7
TL		 574 else
575 goto bad;
5e1c5ff4 576 break;
e5c56ed3 577#endif
3ac4fa99 578#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 579 case METHOD_GPIO_1610:
5e1c5ff4
TL		 580 if (gpio & 0x08)
581 reg += OMAP1610_GPIO_EDGE_CTRL2;
582 else
583 reg += OMAP1610_GPIO_EDGE_CTRL1;
584 gpio &= 0x07;
585 l = __raw_readl(reg);
586 l &= ~(3 << (gpio << 1));
6cab4860 587 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 588 l |= 2 << (gpio << 1);
6cab4860 589 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 590 l |= 1 << (gpio << 1);
3ac4fa99
JY		 591 if (trigger)
592 /* Enable wake-up during idle for dynamic tick */
593 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
594 else
595 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 596 break;
3ac4fa99 597#endif
b718aa81 598#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 599 case METHOD_GPIO_7XX:
600 reg += OMAP7XX_GPIO_INT_CONTROL;
56739a69 601 l = __raw_readl(reg);
29501577 602 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 603 bank->toggle_mask |= 1 << gpio;
56739a69
ZM		 604 if (trigger & IRQ_TYPE_EDGE_RISING)
605 l |= 1 << gpio;
606 else if (trigger & IRQ_TYPE_EDGE_FALLING)
607 l &= ~(1 << gpio);
608 else
609 goto bad;
610 break;
611#endif
140455fa 612#ifdef CONFIG_ARCH_OMAP2PLUS
92105bb7 613 case METHOD_GPIO_24XX:
3f1686a9 614 case METHOD_GPIO_44XX:
3ac4fa99 615 set_24xx_gpio_triggering(bank, gpio, trigger);
f7c5cc45 616 return 0;
3ac4fa99 617#endif
5e1c5ff4 618 default:
92105bb7 619 goto bad;
5e1c5ff4 620 }
92105bb7
TL		 621 __raw_writel(l, reg);
622 return 0;
623bad:
624 return -EINVAL;
5e1c5ff4
TL		 625}
626
e9191028 627static int gpio_irq_type(struct irq_data *d, unsigned type)
5e1c5ff4
TL		 628{
629 struct gpio_bank *bank;
92105bb7
TL		 630 unsigned gpio;
631 int retval;
a6472533 632 unsigned long flags;
92105bb7 633
e9191028
LB		 634 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
635 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
92105bb7 636 else
e9191028 637 gpio = d->irq - IH_GPIO_BASE;
5e1c5ff4
TL		 638
639 if (check_gpio(gpio) < 0)
92105bb7
TL		 640 return -EINVAL;
641
e5c56ed3 642 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 643 return -EINVAL;
e5c56ed3
DB		 644
645 /* OMAP1 allows only only edge triggering */
5492fb1a 646 if (!cpu_class_is_omap2()
e5c56ed3 647 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 648 return -EINVAL;
649
e9191028 650 bank = irq_data_get_irq_chip_data(d);
a6472533 651 spin_lock_irqsave(&bank->lock, flags);
92105bb7 652 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
a6472533 653 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 654
655 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
6845664a 656 __irq_set_handler_locked(d->irq, handle_level_irq);
672e302e 657 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
6845664a 658 __irq_set_handler_locked(d->irq, handle_edge_irq);
672e302e 659
92105bb7 660 return retval;
5e1c5ff4
TL		 661}
662
663static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
664{
92105bb7 665 void __iomem *reg = bank->base;
5e1c5ff4
TL		 666
667 switch (bank->method) {
e5c56ed3 668#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 669 case METHOD_MPUIO:
670 /* MPUIO irqstatus is reset by reading the status register,
671 * so do nothing here */
672 return;
e5c56ed3
DB		 673#endif
674#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 675 case METHOD_GPIO_1510:
676 reg += OMAP1510_GPIO_INT_STATUS;
677 break;
e5c56ed3
DB		 678#endif
679#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 680 case METHOD_GPIO_1610:
681 reg += OMAP1610_GPIO_IRQSTATUS1;
682 break;
e5c56ed3 683#endif
b718aa81 684#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 685 case METHOD_GPIO_7XX:
686 reg += OMAP7XX_GPIO_INT_STATUS;
56739a69
ZM		 687 break;
688#endif
a8eb7ca0 689#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 690 case METHOD_GPIO_24XX:
691 reg += OMAP24XX_GPIO_IRQSTATUS1;
692 break;
78a1a6d3
SR		 693#endif
694#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 695 case METHOD_GPIO_44XX:
78a1a6d3
SR		 696 reg += OMAP4_GPIO_IRQSTATUS0;
697 break;
e5c56ed3 698#endif
5e1c5ff4 699 default:
e5c56ed3 700 WARN_ON(1);
5e1c5ff4
TL		 701 return;
702 }
703 __raw_writel(gpio_mask, reg);
bee7930f
HD		 704
705 /* Workaround for clearing DSP GPIO interrupts to allow retention */
3f1686a9
TL		 706 if (cpu_is_omap24xx() || cpu_is_omap34xx())
707 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
708 else if (cpu_is_omap44xx())
709 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
710
78a1a6d3 711 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
bedfd154
RQ		 712 __raw_writel(gpio_mask, reg);
713
714 /* Flush posted write for the irq status to avoid spurious interrupts */
715 __raw_readl(reg);
78a1a6d3 716 }
5e1c5ff4
TL		 717}
718
719static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
720{
721 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
722}
723
ea6dedd7
ID		 724static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
725{
726 void __iomem *reg = bank->base;
99c47707
ID		 727 int inv = 0;
728 u32 l;
729 u32 mask;
ea6dedd7
ID		 730
731 switch (bank->method) {
e5c56ed3 732#ifdef CONFIG_ARCH_OMAP1
ea6dedd7 733 case METHOD_MPUIO:
5de62b86 734 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
99c47707
ID		 735 mask = 0xffff;
736 inv = 1;
ea6dedd7 737 break;
e5c56ed3
DB		 738#endif
739#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 740 case METHOD_GPIO_1510:
741 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 742 mask = 0xffff;
743 inv = 1;
ea6dedd7 744 break;
e5c56ed3
DB		 745#endif
746#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 747 case METHOD_GPIO_1610:
748 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 749 mask = 0xffff;
ea6dedd7 750 break;
e5c56ed3 751#endif
b718aa81 752#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 753 case METHOD_GPIO_7XX:
754 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 755 mask = 0xffffffff;
756 inv = 1;
757 break;
758#endif
a8eb7ca0 759#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
ea6dedd7
ID		 760 case METHOD_GPIO_24XX:
761 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 762 mask = 0xffffffff;
ea6dedd7 763 break;
78a1a6d3
SR		 764#endif
765#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 766 case METHOD_GPIO_44XX:
78a1a6d3
SR		 767 reg += OMAP4_GPIO_IRQSTATUSSET0;
768 mask = 0xffffffff;
769 break;
e5c56ed3 770#endif
ea6dedd7 771 default:
e5c56ed3 772 WARN_ON(1);
ea6dedd7
ID		 773 return 0;
774 }
775
99c47707
ID		 776 l = __raw_readl(reg);
777 if (inv)
778 l = ~l;
779 l &= mask;
780 return l;
ea6dedd7
ID		 781}
782
5e1c5ff4
TL		 783static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
784{
92105bb7 785 void __iomem *reg = bank->base;
5e1c5ff4
TL		 786 u32 l;
787
788 switch (bank->method) {
e5c56ed3 789#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 790 case METHOD_MPUIO:
5de62b86 791 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
5e1c5ff4
TL		 792 l = __raw_readl(reg);
793 if (enable)
794 l &= ~(gpio_mask);
795 else
796 l |= gpio_mask;
797 break;
e5c56ed3
DB		 798#endif
799#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 800 case METHOD_GPIO_1510:
801 reg += OMAP1510_GPIO_INT_MASK;
802 l = __raw_readl(reg);
803 if (enable)
804 l &= ~(gpio_mask);
805 else
806 l |= gpio_mask;
807 break;
e5c56ed3
DB		 808#endif
809#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 810 case METHOD_GPIO_1610:
811 if (enable)
812 reg += OMAP1610_GPIO_SET_IRQENABLE1;
813 else
814 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
815 l = gpio_mask;
816 break;
e5c56ed3 817#endif
b718aa81 818#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 819 case METHOD_GPIO_7XX:
820 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 821 l = __raw_readl(reg);
822 if (enable)
823 l &= ~(gpio_mask);
824 else
825 l |= gpio_mask;
826 break;
827#endif
a8eb7ca0 828#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 829 case METHOD_GPIO_24XX:
830 if (enable)
831 reg += OMAP24XX_GPIO_SETIRQENABLE1;
832 else
833 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
834 l = gpio_mask;
835 break;
78a1a6d3
SR		 836#endif
837#ifdef CONFIG_ARCH_OMAP4
3f1686a9 838 case METHOD_GPIO_44XX:
78a1a6d3
SR		 839 if (enable)
840 reg += OMAP4_GPIO_IRQSTATUSSET0;
841 else
842 reg += OMAP4_GPIO_IRQSTATUSCLR0;
843 l = gpio_mask;
844 break;
e5c56ed3 845#endif
5e1c5ff4 846 default:
e5c56ed3 847 WARN_ON(1);
5e1c5ff4
TL		 848 return;
849 }
850 __raw_writel(l, reg);
851}
852
853static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
854{
855 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
856}
857
92105bb7
TL		 858/*
859 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
860 * 1510 does not seem to have a wake-up register. If JTAG is connected
861 * to the target, system will wake up always on GPIO events. While
862 * system is running all registered GPIO interrupts need to have wake-up
863 * enabled. When system is suspended, only selected GPIO interrupts need
864 * to have wake-up enabled.
865 */
866static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
867{
4cc6420c 868 unsigned long uninitialized_var(flags);
a6472533 869
92105bb7 870 switch (bank->method) {
3ac4fa99 871#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 872 case METHOD_MPUIO:
92105bb7 873 case METHOD_GPIO_1610:
a6472533 874 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 875 if (enable)
92105bb7 876 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 877 else
92105bb7 878 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 879 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 880 return 0;
3ac4fa99 881#endif
140455fa 882#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99 883 case METHOD_GPIO_24XX:
3f1686a9 884 case METHOD_GPIO_44XX:
11a78b79
DB		 885 if (bank->non_wakeup_gpios & (1 << gpio)) {
886 printk(KERN_ERR "Unable to modify wakeup on "
887 "non-wakeup GPIO%d\n",
888 (bank - gpio_bank) * 32 + gpio);
889 return -EINVAL;
890 }
a6472533 891 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 892 if (enable)
3ac4fa99 893 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 894 else
3ac4fa99 895 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 896 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 897 return 0;
898#endif
92105bb7
TL		 899 default:
900 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
901 bank->method);
902 return -EINVAL;
903 }
904}
905
4196dd6b
TL		 906static void _reset_gpio(struct gpio_bank *bank, int gpio)
907{
908 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
909 _set_gpio_irqenable(bank, gpio, 0);
910 _clear_gpio_irqstatus(bank, gpio);
6cab4860 911 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 912}
913
92105bb7 914/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
e9191028 915static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
92105bb7 916{
e9191028 917 unsigned int gpio = d->irq - IH_GPIO_BASE;
92105bb7
TL		 918 struct gpio_bank *bank;
919 int retval;
920
921 if (check_gpio(gpio) < 0)
922 return -ENODEV;
e9191028 923 bank = irq_data_get_irq_chip_data(d);
92105bb7 924 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 925
926 return retval;
927}
928
3ff164e1 929static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 930{
3ff164e1 931 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 932 unsigned long flags;
52e31344 933
a6472533 934 spin_lock_irqsave(&bank->lock, flags);
92105bb7 935
4196dd6b
TL		 936 /* Set trigger to none. You need to enable the desired trigger with
937 * request_irq() or set_irq_type().
938 */
3ff164e1 939 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 940
1a8bfa1e 941#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 942 if (bank->method == METHOD_GPIO_1510) {
92105bb7 943 void __iomem *reg;
5e1c5ff4 944
92105bb7 945 /* Claim the pin for MPU */
5e1c5ff4 946 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
3ff164e1 947 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4
TL		 948 }
949#endif
058af1ea
C		 950 if (!cpu_class_is_omap1()) {
951 if (!bank->mod_usage) {
9f096868 952 void __iomem *reg = bank->base;
058af1ea 953 u32 ctrl;
9f096868
C		 954
955 if (cpu_is_omap24xx() || cpu_is_omap34xx())
956 reg += OMAP24XX_GPIO_CTRL;
957 else if (cpu_is_omap44xx())
958 reg += OMAP4_GPIO_CTRL;
959 ctrl = __raw_readl(reg);
058af1ea 960 /* Module is enabled, clocks are not gated */
9f096868
C		 961 ctrl &= 0xFFFFFFFE;
962 __raw_writel(ctrl, reg);
058af1ea
C		 963 }
964 bank->mod_usage |= 1 << offset;
965 }
a6472533 966 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 967
968 return 0;
969}
970
3ff164e1 971static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 972{
3ff164e1 973 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 974 unsigned long flags;
5e1c5ff4 975
a6472533 976 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 977#ifdef CONFIG_ARCH_OMAP16XX
978 if (bank->method == METHOD_GPIO_1610) {
979 /* Disable wake-up during idle for dynamic tick */
980 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
3ff164e1 981 __raw_writel(1 << offset, reg);
92105bb7
TL		 982 }
983#endif
9f096868
C		 984#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
985 if (bank->method == METHOD_GPIO_24XX) {
92105bb7
TL		 986 /* Disable wake-up during idle for dynamic tick */
987 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
3ff164e1 988 __raw_writel(1 << offset, reg);
92105bb7 989 }
9f096868
C		 990#endif
991#ifdef CONFIG_ARCH_OMAP4
992 if (bank->method == METHOD_GPIO_44XX) {
993 /* Disable wake-up during idle for dynamic tick */
994 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
995 __raw_writel(1 << offset, reg);
996 }
92105bb7 997#endif
058af1ea
C		 998 if (!cpu_class_is_omap1()) {
999 bank->mod_usage &= ~(1 << offset);
1000 if (!bank->mod_usage) {
9f096868 1001 void __iomem *reg = bank->base;
058af1ea 1002 u32 ctrl;
9f096868
C		 1003
1004 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1005 reg += OMAP24XX_GPIO_CTRL;
1006 else if (cpu_is_omap44xx())
1007 reg += OMAP4_GPIO_CTRL;
1008 ctrl = __raw_readl(reg);
058af1ea
C		 1009 /* Module is disabled, clocks are gated */
1010 ctrl |= 1;
9f096868 1011 __raw_writel(ctrl, reg);
058af1ea
C		 1012 }
1013 }
3ff164e1 1014 _reset_gpio(bank, bank->chip.base + offset);
a6472533 1015 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1016}
1017
1018/*
1019 * We need to unmask the GPIO bank interrupt as soon as possible to
1020 * avoid missing GPIO interrupts for other lines in the bank.
1021 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1022 * in the bank to avoid missing nested interrupts for a GPIO line.
1023 * If we wait to unmask individual GPIO lines in the bank after the
1024 * line's interrupt handler has been run, we may miss some nested
1025 * interrupts.
1026 */
10dd5ce2 1027static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 1028{
92105bb7 1029 void __iomem *isr_reg = NULL;
5e1c5ff4 1030 u32 isr;
4318f36b 1031 unsigned int gpio_irq, gpio_index;
5e1c5ff4 1032 struct gpio_bank *bank;
ea6dedd7
ID		 1033 u32 retrigger = 0;
1034 int unmasked = 0;
ee144182 1035 struct irq_chip *chip = irq_desc_get_chip(desc);
5e1c5ff4 1036
ee144182 1037 chained_irq_enter(chip, desc);
5e1c5ff4 1038
6845664a 1039 bank = irq_get_handler_data(irq);
e5c56ed3 1040#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 1041 if (bank->method == METHOD_MPUIO)
5de62b86
TL		 1042 isr_reg = bank->base +
1043 OMAP_MPUIO_GPIO_INT / bank->stride;
e5c56ed3 1044#endif
1a8bfa1e 1045#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 1046 if (bank->method == METHOD_GPIO_1510)
1047 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1048#endif
1049#if defined(CONFIG_ARCH_OMAP16XX)
1050 if (bank->method == METHOD_GPIO_1610)
1051 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1052#endif
b718aa81 1053#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 1054 if (bank->method == METHOD_GPIO_7XX)
1055 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
56739a69 1056#endif
a8eb7ca0 1057#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 1058 if (bank->method == METHOD_GPIO_24XX)
1059 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
78a1a6d3
SR		 1060#endif
1061#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 1062 if (bank->method == METHOD_GPIO_44XX)
78a1a6d3 1063 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
92105bb7 1064#endif
b1cc4c55
EK		 1065
1066 if (WARN_ON(!isr_reg))
1067 goto exit;
1068
92105bb7 1069 while(1) {
6e60e79a 1070 u32 isr_saved, level_mask = 0;
ea6dedd7 1071 u32 enabled;
6e60e79a 1072
ea6dedd7
ID		 1073 enabled = _get_gpio_irqbank_mask(bank);
1074 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 1075
1076 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1077 isr &= 0x0000ffff;
1078
5492fb1a 1079 if (cpu_class_is_omap2()) {
b144ff6f 1080 level_mask = bank->level_mask & enabled;
ea6dedd7 1081 }
6e60e79a
TL		 1082
1083 /* clear edge sensitive interrupts before handler(s) are
1084 called so that we don't miss any interrupt occurred while
1085 executing them */
1086 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1087 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1088 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1089
1090 /* if there is only edge sensitive GPIO pin interrupts
1091 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 1092 if (!level_mask && !unmasked) {
1093 unmasked = 1;
ee144182 1094 chained_irq_exit(chip, desc);
ea6dedd7 1095 }
92105bb7 1096
ea6dedd7
ID		 1097 isr |= retrigger;
1098 retrigger = 0;
92105bb7
TL		 1099 if (!isr)
1100 break;
1101
1102 gpio_irq = bank->virtual_irq_start;
1103 for (; isr != 0; isr >>= 1, gpio_irq++) {
4318f36b
CM		 1104 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1105
92105bb7
TL		 1106 if (!(isr & 1))
1107 continue;
29454dde 1108
4318f36b
CM		 1109#ifdef CONFIG_ARCH_OMAP1
1110 /*
1111 * Some chips can't respond to both rising and falling
1112 * at the same time. If this irq was requested with
1113 * both flags, we need to flip the ICR data for the IRQ
1114 * to respond to the IRQ for the opposite direction.
1115 * This will be indicated in the bank toggle_mask.
1116 */
1117 if (bank->toggle_mask & (1 << gpio_index))
1118 _toggle_gpio_edge_triggering(bank, gpio_index);
1119#endif
1120
d8aa0251 1121 generic_handle_irq(gpio_irq);
92105bb7 1122 }
1a8bfa1e 1123 }
ea6dedd7
ID		 1124 /* if bank has any level sensitive GPIO pin interrupt
1125 configured, we must unmask the bank interrupt only after
1126 handler(s) are executed in order to avoid spurious bank
1127 interrupt */
b1cc4c55 1128exit:
ea6dedd7 1129 if (!unmasked)
ee144182 1130 chained_irq_exit(chip, desc);
5e1c5ff4
TL		 1131}
1132
e9191028 1133static void gpio_irq_shutdown(struct irq_data *d)
4196dd6b 1134{
e9191028
LB		 1135 unsigned int gpio = d->irq - IH_GPIO_BASE;
1136 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
4196dd6b
TL		 1137
1138 _reset_gpio(bank, gpio);
1139}
1140
e9191028 1141static void gpio_ack_irq(struct irq_data *d)
5e1c5ff4 1142{
e9191028
LB		 1143 unsigned int gpio = d->irq - IH_GPIO_BASE;
1144 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 1145
1146 _clear_gpio_irqstatus(bank, gpio);
1147}
1148
e9191028 1149static void gpio_mask_irq(struct irq_data *d)
5e1c5ff4 1150{
e9191028
LB		 1151 unsigned int gpio = d->irq - IH_GPIO_BASE;
1152 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 1153
1154 _set_gpio_irqenable(bank, gpio, 0);
55b6019a 1155 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
5e1c5ff4
TL		 1156}
1157
e9191028 1158static void gpio_unmask_irq(struct irq_data *d)
5e1c5ff4 1159{
e9191028
LB		 1160 unsigned int gpio = d->irq - IH_GPIO_BASE;
1161 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
b144ff6f 1162 unsigned int irq_mask = 1 << get_gpio_index(gpio);
8c04a176 1163 u32 trigger = irqd_get_trigger_type(d);
55b6019a
KH		 1164
1165 if (trigger)
1166 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
b144ff6f
KH		 1167
1168 /* For level-triggered GPIOs, the clearing must be done after
1169 * the HW source is cleared, thus after the handler has run */
1170 if (bank->level_mask & irq_mask) {
1171 _set_gpio_irqenable(bank, gpio, 0);
1172 _clear_gpio_irqstatus(bank, gpio);
1173 }
5e1c5ff4 1174
4de8c75b 1175 _set_gpio_irqenable(bank, gpio, 1);
5e1c5ff4
TL		 1176}
1177
e5c56ed3
DB		 1178static struct irq_chip gpio_irq_chip = {
1179 .name = "GPIO",
e9191028
LB		 1180 .irq_shutdown = gpio_irq_shutdown,
1181 .irq_ack = gpio_ack_irq,
1182 .irq_mask = gpio_mask_irq,
1183 .irq_unmask = gpio_unmask_irq,
1184 .irq_set_type = gpio_irq_type,
1185 .irq_set_wake = gpio_wake_enable,
e5c56ed3
DB		 1186};
1187
1188/*---------------------------------------------------------------------*/
1189
1190#ifdef CONFIG_ARCH_OMAP1
1191
1192/* MPUIO uses the always-on 32k clock */
1193
e9191028 1194static void mpuio_ack_irq(struct irq_data *d)
5e1c5ff4
TL		 1195{
1196 /* The ISR is reset automatically, so do nothing here. */
1197}
1198
e9191028 1199static void mpuio_mask_irq(struct irq_data *d)
5e1c5ff4 1200{
e9191028
LB		 1201 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1202 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 1203
1204 _set_gpio_irqenable(bank, gpio, 0);
1205}
1206
e9191028 1207static void mpuio_unmask_irq(struct irq_data *d)
5e1c5ff4 1208{
e9191028
LB		 1209 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1210 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 1211
1212 _set_gpio_irqenable(bank, gpio, 1);
1213}
1214
e5c56ed3
DB		 1215static struct irq_chip mpuio_irq_chip = {
1216 .name = "MPUIO",
e9191028
LB		 1217 .irq_ack = mpuio_ack_irq,
1218 .irq_mask = mpuio_mask_irq,
1219 .irq_unmask = mpuio_unmask_irq,
1220 .irq_set_type = gpio_irq_type,
11a78b79
DB		 1221#ifdef CONFIG_ARCH_OMAP16XX
1222 /* REVISIT: assuming only 16xx supports MPUIO wake events */
e9191028 1223 .irq_set_wake = gpio_wake_enable,
11a78b79 1224#endif
5e1c5ff4
TL		 1225};
1226
e5c56ed3
DB		 1227
1228#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1229
11a78b79
DB		 1230
1231#ifdef CONFIG_ARCH_OMAP16XX
1232
1233#include <linux/platform_device.h>
1234
79ee031f 1235static int omap_mpuio_suspend_noirq(struct device *dev)
11a78b79 1236{
79ee031f 1237 struct platform_device *pdev = to_platform_device(dev);
11a78b79 1238 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 1239 void __iomem *mask_reg = bank->base +
1240 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 1241 unsigned long flags;
11a78b79 1242
a6472533 1243 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 1244 bank->saved_wakeup = __raw_readl(mask_reg);
1245 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 1246 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1247
1248 return 0;
1249}
1250
79ee031f 1251static int omap_mpuio_resume_noirq(struct device *dev)
11a78b79 1252{
79ee031f 1253 struct platform_device *pdev = to_platform_device(dev);
11a78b79 1254 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 1255 void __iomem *mask_reg = bank->base +
1256 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 1257 unsigned long flags;
11a78b79 1258
a6472533 1259 spin_lock_irqsave(&bank->lock, flags);
11a78b79 1260 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 1261 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1262
1263 return 0;
1264}
1265
47145210 1266static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
79ee031f
MD		 1267 .suspend_noirq = omap_mpuio_suspend_noirq,
1268 .resume_noirq = omap_mpuio_resume_noirq,
1269};
1270
3c437ffd 1271/* use platform_driver for this. */
11a78b79 1272static struct platform_driver omap_mpuio_driver = {
11a78b79
DB		 1273 .driver = {
1274 .name = "mpuio",
79ee031f 1275 .pm = &omap_mpuio_dev_pm_ops,
11a78b79
DB		 1276 },
1277};
1278
1279static struct platform_device omap_mpuio_device = {
1280 .name = "mpuio",
1281 .id = -1,
1282 .dev = {
1283 .driver = &omap_mpuio_driver.driver,
1284 }
1285 /* could list the /proc/iomem resources */
1286};
1287
1288static inline void mpuio_init(void)
1289{
77640aab
VC		 1290 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1291 platform_set_drvdata(&omap_mpuio_device, bank);
fcf126d8 1292
11a78b79
DB		 1293 if (platform_driver_register(&omap_mpuio_driver) == 0)
1294 (void) platform_device_register(&omap_mpuio_device);
1295}
1296
1297#else
1298static inline void mpuio_init(void) {}
1299#endif /* 16xx */
1300
e5c56ed3
DB		 1301#else
1302
1303extern struct irq_chip mpuio_irq_chip;
1304
1305#define bank_is_mpuio(bank) 0
11a78b79 1306static inline void mpuio_init(void) {}
e5c56ed3
DB		 1307
1308#endif
1309
1310/*---------------------------------------------------------------------*/
5e1c5ff4 1311
52e31344
DB		 1312/* REVISIT these are stupid implementations! replace by ones that
1313 * don't switch on METHOD_* and which mostly avoid spinlocks
1314 */
1315
1316static int gpio_input(struct gpio_chip *chip, unsigned offset)
1317{
1318 struct gpio_bank *bank;
1319 unsigned long flags;
1320
1321 bank = container_of(chip, struct gpio_bank, chip);
1322 spin_lock_irqsave(&bank->lock, flags);
1323 _set_gpio_direction(bank, offset, 1);
1324 spin_unlock_irqrestore(&bank->lock, flags);
1325 return 0;
1326}
1327
b37c45b8
RQ		 1328static int gpio_is_input(struct gpio_bank *bank, int mask)
1329{
1330 void __iomem *reg = bank->base;
1331
1332 switch (bank->method) {
1333 case METHOD_MPUIO:
5de62b86 1334 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
b37c45b8
RQ		 1335 break;
1336 case METHOD_GPIO_1510:
1337 reg += OMAP1510_GPIO_DIR_CONTROL;
1338 break;
1339 case METHOD_GPIO_1610:
1340 reg += OMAP1610_GPIO_DIRECTION;
1341 break;
7c006926
AB		 1342 case METHOD_GPIO_7XX:
1343 reg += OMAP7XX_GPIO_DIR_CONTROL;
b37c45b8
RQ		 1344 break;
1345 case METHOD_GPIO_24XX:
1346 reg += OMAP24XX_GPIO_OE;
1347 break;
9f096868
C		 1348 case METHOD_GPIO_44XX:
1349 reg += OMAP4_GPIO_OE;
1350 break;
1351 default:
1352 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1353 return -EINVAL;
b37c45b8
RQ		 1354 }
1355 return __raw_readl(reg) & mask;
1356}
1357
52e31344
DB		 1358static int gpio_get(struct gpio_chip *chip, unsigned offset)
1359{
b37c45b8
RQ		 1360 struct gpio_bank *bank;
1361 void __iomem *reg;
1362 int gpio;
1363 u32 mask;
1364
1365 gpio = chip->base + offset;
1366 bank = get_gpio_bank(gpio);
1367 reg = bank->base;
1368 mask = 1 << get_gpio_index(gpio);
1369
1370 if (gpio_is_input(bank, mask))
1371 return _get_gpio_datain(bank, gpio);
1372 else
1373 return _get_gpio_dataout(bank, gpio);
52e31344
DB		 1374}
1375
1376static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1377{
1378 struct gpio_bank *bank;
1379 unsigned long flags;
1380
1381 bank = container_of(chip, struct gpio_bank, chip);
1382 spin_lock_irqsave(&bank->lock, flags);
1383 _set_gpio_dataout(bank, offset, value);
1384 _set_gpio_direction(bank, offset, 0);
1385 spin_unlock_irqrestore(&bank->lock, flags);
1386 return 0;
1387}
1388
168ef3d9
FB		 1389static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1390 unsigned debounce)
1391{
1392 struct gpio_bank *bank;
1393 unsigned long flags;
1394
1395 bank = container_of(chip, struct gpio_bank, chip);
77640aab
VC		 1396
1397 if (!bank->dbck) {
1398 bank->dbck = clk_get(bank->dev, "dbclk");
1399 if (IS_ERR(bank->dbck))
1400 dev_err(bank->dev, "Could not get gpio dbck\n");
1401 }
1402
168ef3d9
FB		 1403 spin_lock_irqsave(&bank->lock, flags);
1404 _set_gpio_debounce(bank, offset, debounce);
1405 spin_unlock_irqrestore(&bank->lock, flags);
1406
1407 return 0;
1408}
1409
52e31344
DB		 1410static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1411{
1412 struct gpio_bank *bank;
1413 unsigned long flags;
1414
1415 bank = container_of(chip, struct gpio_bank, chip);
1416 spin_lock_irqsave(&bank->lock, flags);
1417 _set_gpio_dataout(bank, offset, value);
1418 spin_unlock_irqrestore(&bank->lock, flags);
1419}
1420
a007b709
DB		 1421static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1422{
1423 struct gpio_bank *bank;
1424
1425 bank = container_of(chip, struct gpio_bank, chip);
1426 return bank->virtual_irq_start + offset;
1427}
1428
52e31344
DB		 1429/*---------------------------------------------------------------------*/
1430
9a748053 1431static void __init omap_gpio_show_rev(struct gpio_bank *bank)
9f7065da
TL		 1432{
1433 u32 rev;
1434
9a748053
TL		 1435 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1436 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
9f7065da 1437 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
9a748053 1438 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
9f7065da 1439 else if (cpu_is_omap44xx())
9a748053 1440 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
9f7065da
TL		 1441 else
1442 return;
1443
1444 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1445 (rev >> 4) & 0x0f, rev & 0x0f);
1446}
1447
8ba55c5c
DB		 1448/* This lock class tells lockdep that GPIO irqs are in a different
1449 * category than their parents, so it won't report false recursion.
1450 */
1451static struct lock_class_key gpio_lock_class;
1452
77640aab
VC		 1453static inline int init_gpio_info(struct platform_device *pdev)
1454{
1455 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1456 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1457 GFP_KERNEL);
1458 if (!gpio_bank) {
1459 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1460 return -ENOMEM;
1461 }
1462 return 0;
1463}
1464
1465/* TODO: Cleanup cpu_is_* checks */
2fae7fbe
VC		 1466static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1467{
1468 if (cpu_class_is_omap2()) {
1469 if (cpu_is_omap44xx()) {
1470 __raw_writel(0xffffffff, bank->base +
1471 OMAP4_GPIO_IRQSTATUSCLR0);
1472 __raw_writel(0x00000000, bank->base +
1473 OMAP4_GPIO_DEBOUNCENABLE);
1474 /* Initialize interface clk ungated, module enabled */
1475 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1476 } else if (cpu_is_omap34xx()) {
1477 __raw_writel(0x00000000, bank->base +
1478 OMAP24XX_GPIO_IRQENABLE1);
1479 __raw_writel(0xffffffff, bank->base +
1480 OMAP24XX_GPIO_IRQSTATUS1);
1481 __raw_writel(0x00000000, bank->base +
1482 OMAP24XX_GPIO_DEBOUNCE_EN);
1483
1484 /* Initialize interface clk ungated, module enabled */
1485 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1486 } else if (cpu_is_omap24xx()) {
1487 static const u32 non_wakeup_gpios[] = {
1488 0xe203ffc0, 0x08700040
1489 };
1490 if (id < ARRAY_SIZE(non_wakeup_gpios))
1491 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1492 }
1493 } else if (cpu_class_is_omap1()) {
1494 if (bank_is_mpuio(bank))
5de62b86
TL		 1495 __raw_writew(0xffff, bank->base +
1496 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
2fae7fbe
VC		 1497 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1498 __raw_writew(0xffff, bank->base
1499 + OMAP1510_GPIO_INT_MASK);
1500 __raw_writew(0x0000, bank->base
1501 + OMAP1510_GPIO_INT_STATUS);
1502 }
1503 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1504 __raw_writew(0x0000, bank->base
1505 + OMAP1610_GPIO_IRQENABLE1);
1506 __raw_writew(0xffff, bank->base
1507 + OMAP1610_GPIO_IRQSTATUS1);
1508 __raw_writew(0x0014, bank->base
1509 + OMAP1610_GPIO_SYSCONFIG);
1510
1511 /*
1512 * Enable system clock for GPIO module.
1513 * The CAM_CLK_CTRL *is* really the right place.
1514 */
1515 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1516 ULPD_CAM_CLK_CTRL);
1517 }
1518 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1519 __raw_writel(0xffffffff, bank->base
1520 + OMAP7XX_GPIO_INT_MASK);
1521 __raw_writel(0x00000000, bank->base
1522 + OMAP7XX_GPIO_INT_STATUS);
1523 }
1524 }
1525}
1526
1527static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1528{
77640aab 1529 int j;
2fae7fbe
VC		 1530 static int gpio;
1531
2fae7fbe
VC		 1532 bank->mod_usage = 0;
1533 /*
1534 * REVISIT eventually switch from OMAP-specific gpio structs
1535 * over to the generic ones
1536 */
1537 bank->chip.request = omap_gpio_request;
1538 bank->chip.free = omap_gpio_free;
1539 bank->chip.direction_input = gpio_input;
1540 bank->chip.get = gpio_get;
1541 bank->chip.direction_output = gpio_output;
1542 bank->chip.set_debounce = gpio_debounce;
1543 bank->chip.set = gpio_set;
1544 bank->chip.to_irq = gpio_2irq;
1545 if (bank_is_mpuio(bank)) {
1546 bank->chip.label = "mpuio";
1547#ifdef CONFIG_ARCH_OMAP16XX
1548 bank->chip.dev = &omap_mpuio_device.dev;
1549#endif
1550 bank->chip.base = OMAP_MPUIO(0);
1551 } else {
1552 bank->chip.label = "gpio";
1553 bank->chip.base = gpio;
1554 gpio += bank_width;
1555 }
1556 bank->chip.ngpio = bank_width;
1557
1558 gpiochip_add(&bank->chip);
1559
1560 for (j = bank->virtual_irq_start;
1561 j < bank->virtual_irq_start + bank_width; j++) {
1475b85d 1562 irq_set_lockdep_class(j, &gpio_lock_class);
6845664a 1563 irq_set_chip_data(j, bank);
2fae7fbe 1564 if (bank_is_mpuio(bank))
6845664a 1565 irq_set_chip(j, &mpuio_irq_chip);
2fae7fbe 1566 else
6845664a
TG		 1567 irq_set_chip(j, &gpio_irq_chip);
1568 irq_set_handler(j, handle_simple_irq);
2fae7fbe
VC		 1569 set_irq_flags(j, IRQF_VALID);
1570 }
6845664a
TG		 1571 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1572 irq_set_handler_data(bank->irq, bank);
2fae7fbe
VC		 1573}
1574
77640aab 1575static int __devinit omap_gpio_probe(struct platform_device *pdev)
5e1c5ff4 1576{
77640aab
VC		 1577 static int gpio_init_done;
1578 struct omap_gpio_platform_data *pdata;
1579 struct resource *res;
1580 int id;
5e1c5ff4
TL		 1581 struct gpio_bank *bank;
1582
77640aab
VC		 1583 if (!pdev->dev.platform_data)
1584 return -EINVAL;
5e1c5ff4 1585
77640aab 1586 pdata = pdev->dev.platform_data;
56a25641 1587
77640aab
VC		 1588 if (!gpio_init_done) {
1589 int ret;
5492fb1a 1590
77640aab
VC		 1591 ret = init_gpio_info(pdev);
1592 if (ret)
1593 return ret;
5492fb1a 1594 }
5492fb1a 1595
77640aab
VC		 1596 id = pdev->id;
1597 bank = &gpio_bank[id];
92105bb7 1598
77640aab
VC		 1599 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1600 if (unlikely(!res)) {
1601 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1602 return -ENODEV;
44169075 1603 }
5e1c5ff4 1604
77640aab
VC		 1605 bank->irq = res->start;
1606 bank->virtual_irq_start = pdata->virtual_irq_start;
1607 bank->method = pdata->bank_type;
1608 bank->dev = &pdev->dev;
1609 bank->dbck_flag = pdata->dbck_flag;
5de62b86 1610 bank->stride = pdata->bank_stride;
77640aab 1611 bank_width = pdata->bank_width;
9f7065da 1612
77640aab 1613 spin_lock_init(&bank->lock);
9f7065da 1614
77640aab
VC		 1615 /* Static mapping, never released */
1616 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1617 if (unlikely(!res)) {
1618 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1619 return -ENODEV;
1620 }
89db9482 1621
77640aab
VC		 1622 bank->base = ioremap(res->start, resource_size(res));
1623 if (!bank->base) {
1624 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1625 return -ENOMEM;
5e1c5ff4
TL		 1626 }
1627
77640aab
VC		 1628 pm_runtime_enable(bank->dev);
1629 pm_runtime_get_sync(bank->dev);
1630
1631 omap_gpio_mod_init(bank, id);
1632 omap_gpio_chip_init(bank);
9a748053 1633 omap_gpio_show_rev(bank);
9f7065da 1634
77640aab
VC		 1635 if (!gpio_init_done)
1636 gpio_init_done = 1;
1637
5e1c5ff4
TL		 1638 return 0;
1639}
1640
140455fa 1641#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
3c437ffd 1642static int omap_gpio_suspend(void)
92105bb7
TL		 1643{
1644 int i;
1645
5492fb1a 1646 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1647 return 0;
1648
1649 for (i = 0; i < gpio_bank_count; i++) {
1650 struct gpio_bank *bank = &gpio_bank[i];
1651 void __iomem *wake_status;
1652 void __iomem *wake_clear;
1653 void __iomem *wake_set;
a6472533 1654 unsigned long flags;
92105bb7
TL		 1655
1656 switch (bank->method) {
e5c56ed3 1657#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1658 case METHOD_GPIO_1610:
1659 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1660 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1661 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1662 break;
e5c56ed3 1663#endif
a8eb7ca0 1664#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1665 case METHOD_GPIO_24XX:
723fdb78 1666 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
92105bb7
TL		 1667 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1668 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1669 break;
78a1a6d3
SR		 1670#endif
1671#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1672 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1673 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1674 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1675 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1676 break;
e5c56ed3 1677#endif
92105bb7
TL		 1678 default:
1679 continue;
1680 }
1681
a6472533 1682 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1683 bank->saved_wakeup = __raw_readl(wake_status);
1684 __raw_writel(0xffffffff, wake_clear);
1685 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1686 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1687 }
1688
1689 return 0;
1690}
1691
3c437ffd 1692static void omap_gpio_resume(void)
92105bb7
TL		 1693{
1694 int i;
1695
723fdb78 1696 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
3c437ffd 1697 return;
92105bb7
TL		 1698
1699 for (i = 0; i < gpio_bank_count; i++) {
1700 struct gpio_bank *bank = &gpio_bank[i];
1701 void __iomem *wake_clear;
1702 void __iomem *wake_set;
a6472533 1703 unsigned long flags;
92105bb7
TL		 1704
1705 switch (bank->method) {
e5c56ed3 1706#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1707 case METHOD_GPIO_1610:
1708 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1709 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1710 break;
e5c56ed3 1711#endif
a8eb7ca0 1712#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1713 case METHOD_GPIO_24XX:
0d9356cb
TL		 1714 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1715 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1716 break;
78a1a6d3
SR		 1717#endif
1718#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1719 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1720 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1721 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1722 break;
e5c56ed3 1723#endif
92105bb7
TL		 1724 default:
1725 continue;
1726 }
1727
a6472533 1728 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1729 __raw_writel(0xffffffff, wake_clear);
1730 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1731 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 1732 }
92105bb7
TL		 1733}
1734
3c437ffd 1735static struct syscore_ops omap_gpio_syscore_ops = {
92105bb7
TL		 1736 .suspend = omap_gpio_suspend,
1737 .resume = omap_gpio_resume,
1738};
1739
3ac4fa99
JY		 1740#endif
1741
140455fa 1742#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99
JY		 1743
1744static int workaround_enabled;
1745
72e06d08 1746void omap2_gpio_prepare_for_idle(int off_mode)
3ac4fa99
JY		 1747{
1748 int i, c = 0;
a118b5f3 1749 int min = 0;
3ac4fa99 1750
a118b5f3
TK		 1751 if (cpu_is_omap34xx())
1752 min = 1;
43ffcd9a 1753
a118b5f3 1754 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1755 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1756 u32 l1 = 0, l2 = 0;
0aed0435 1757 int j;
3ac4fa99 1758
0aed0435 1759 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1760 clk_disable(bank->dbck);
1761
72e06d08 1762 if (!off_mode)
43ffcd9a
KH		 1763 continue;
1764
1765 /* If going to OFF, remove triggering for all
1766 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1767 * generated. See OMAP2420 Errata item 1.101. */
3ac4fa99
JY		 1768 if (!(bank->enabled_non_wakeup_gpios))
1769 continue;
3f1686a9
TL		 1770
1771 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1772 bank->saved_datain = __raw_readl(bank->base +
1773 OMAP24XX_GPIO_DATAIN);
1774 l1 = __raw_readl(bank->base +
1775 OMAP24XX_GPIO_FALLINGDETECT);
1776 l2 = __raw_readl(bank->base +
1777 OMAP24XX_GPIO_RISINGDETECT);
1778 }
1779
1780 if (cpu_is_omap44xx()) {
1781 bank->saved_datain = __raw_readl(bank->base +
1782 OMAP4_GPIO_DATAIN);
1783 l1 = __raw_readl(bank->base +
1784 OMAP4_GPIO_FALLINGDETECT);
1785 l2 = __raw_readl(bank->base +
1786 OMAP4_GPIO_RISINGDETECT);
1787 }
1788
3ac4fa99
JY		 1789 bank->saved_fallingdetect = l1;
1790 bank->saved_risingdetect = l2;
1791 l1 &= ~bank->enabled_non_wakeup_gpios;
1792 l2 &= ~bank->enabled_non_wakeup_gpios;
3f1686a9
TL		 1793
1794 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1795 __raw_writel(l1, bank->base +
1796 OMAP24XX_GPIO_FALLINGDETECT);
1797 __raw_writel(l2, bank->base +
1798 OMAP24XX_GPIO_RISINGDETECT);
1799 }
1800
1801 if (cpu_is_omap44xx()) {
1802 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1803 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1804 }
1805
3ac4fa99
JY		 1806 c++;
1807 }
1808 if (!c) {
1809 workaround_enabled = 0;
1810 return;
1811 }
1812 workaround_enabled = 1;
1813}
1814
43ffcd9a 1815void omap2_gpio_resume_after_idle(void)
3ac4fa99
JY		 1816{
1817 int i;
a118b5f3 1818 int min = 0;
3ac4fa99 1819
a118b5f3
TK		 1820 if (cpu_is_omap34xx())
1821 min = 1;
1822 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1823 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1824 u32 l = 0, gen, gen0, gen1;
0aed0435 1825 int j;
3ac4fa99 1826
0aed0435 1827 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1828 clk_enable(bank->dbck);
1829
43ffcd9a
KH		 1830 if (!workaround_enabled)
1831 continue;
1832
3ac4fa99
JY		 1833 if (!(bank->enabled_non_wakeup_gpios))
1834 continue;
3f1686a9
TL		 1835
1836 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1837 __raw_writel(bank->saved_fallingdetect,
3ac4fa99 1838 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
3f1686a9 1839 __raw_writel(bank->saved_risingdetect,
3ac4fa99 1840 bank->base + OMAP24XX_GPIO_RISINGDETECT);
3f1686a9
TL		 1841 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1842 }
1843
1844 if (cpu_is_omap44xx()) {
1845 __raw_writel(bank->saved_fallingdetect,
78a1a6d3 1846 bank->base + OMAP4_GPIO_FALLINGDETECT);
3f1686a9 1847 __raw_writel(bank->saved_risingdetect,
78a1a6d3 1848 bank->base + OMAP4_GPIO_RISINGDETECT);
3f1686a9
TL		 1849 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1850 }
1851
3ac4fa99
JY		 1852 /* Check if any of the non-wakeup interrupt GPIOs have changed
1853 * state. If so, generate an IRQ by software. This is
1854 * horribly racy, but it's the best we can do to work around
1855 * this silicon bug. */
3ac4fa99 1856 l ^= bank->saved_datain;
a118b5f3 1857 l &= bank->enabled_non_wakeup_gpios;
82dbb9d3
EN		 1858
1859 /*
1860 * No need to generate IRQs for the rising edge for gpio IRQs
1861 * configured with falling edge only; and vice versa.
1862 */
1863 gen0 = l & bank->saved_fallingdetect;
1864 gen0 &= bank->saved_datain;
1865
1866 gen1 = l & bank->saved_risingdetect;
1867 gen1 &= ~(bank->saved_datain);
1868
1869 /* FIXME: Consider GPIO IRQs with level detections properly! */
1870 gen = l & (~(bank->saved_fallingdetect) &
1871 ~(bank->saved_risingdetect));
1872 /* Consider all GPIO IRQs needed to be updated */
1873 gen |= gen0 | gen1;
1874
1875 if (gen) {
3ac4fa99 1876 u32 old0, old1;
3f1686a9 1877
f00d6497 1878 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
3f1686a9
TL		 1879 old0 = __raw_readl(bank->base +
1880 OMAP24XX_GPIO_LEVELDETECT0);
1881 old1 = __raw_readl(bank->base +
1882 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1883 __raw_writel(old0 | gen, bank->base +
82dbb9d3 1884 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1885 __raw_writel(old1 | gen, bank->base +
82dbb9d3 1886 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1887 __raw_writel(old0, bank->base +
3f1686a9 1888 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1889 __raw_writel(old1, bank->base +
3f1686a9
TL		 1890 OMAP24XX_GPIO_LEVELDETECT1);
1891 }
1892
1893 if (cpu_is_omap44xx()) {
1894 old0 = __raw_readl(bank->base +
78a1a6d3 1895 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1896 old1 = __raw_readl(bank->base +
78a1a6d3 1897 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1898 __raw_writel(old0 | l, bank->base +
78a1a6d3 1899 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1900 __raw_writel(old1 | l, bank->base +
78a1a6d3 1901 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1902 __raw_writel(old0, bank->base +
78a1a6d3 1903 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1904 __raw_writel(old1, bank->base +
78a1a6d3 1905 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1906 }
3ac4fa99
JY		 1907 }
1908 }
1909
1910}
1911
92105bb7
TL		 1912#endif
1913
a8eb7ca0 1914#ifdef CONFIG_ARCH_OMAP3
40c670f0
RN		 1915/* save the registers of bank 2-6 */
1916void omap_gpio_save_context(void)
1917{
1918 int i;
1919
1920 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1921 for (i = 1; i < gpio_bank_count; i++) {
1922 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 1923 gpio_context[i].irqenable1 =
1924 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1925 gpio_context[i].irqenable2 =
1926 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1927 gpio_context[i].wake_en =
1928 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1929 gpio_context[i].ctrl =
1930 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1931 gpio_context[i].oe =
1932 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1933 gpio_context[i].leveldetect0 =
1934 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1935 gpio_context[i].leveldetect1 =
1936 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1937 gpio_context[i].risingdetect =
1938 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1939 gpio_context[i].fallingdetect =
1940 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1941 gpio_context[i].dataout =
1942 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 1943 }
1944}
1945
1946/* restore the required registers of bank 2-6 */
1947void omap_gpio_restore_context(void)
1948{
1949 int i;
1950
1951 for (i = 1; i < gpio_bank_count; i++) {
1952 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 1953 __raw_writel(gpio_context[i].irqenable1,
1954 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1955 __raw_writel(gpio_context[i].irqenable2,
1956 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1957 __raw_writel(gpio_context[i].wake_en,
1958 bank->base + OMAP24XX_GPIO_WAKE_EN);
1959 __raw_writel(gpio_context[i].ctrl,
1960 bank->base + OMAP24XX_GPIO_CTRL);
1961 __raw_writel(gpio_context[i].oe,
1962 bank->base + OMAP24XX_GPIO_OE);
1963 __raw_writel(gpio_context[i].leveldetect0,
1964 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1965 __raw_writel(gpio_context[i].leveldetect1,
1966 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1967 __raw_writel(gpio_context[i].risingdetect,
1968 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1969 __raw_writel(gpio_context[i].fallingdetect,
1970 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1971 __raw_writel(gpio_context[i].dataout,
1972 bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 1973 }
1974}
1975#endif
1976
77640aab
VC		 1977static struct platform_driver omap_gpio_driver = {
1978 .probe = omap_gpio_probe,
1979 .driver = {
1980 .name = "omap_gpio",
1981 },
1982};
1983
5e1c5ff4 1984/*
77640aab
VC		 1985 * gpio driver register needs to be done before
1986 * machine_init functions access gpio APIs.
1987 * Hence omap_gpio_drv_reg() is a postcore_initcall.
5e1c5ff4 1988 */
77640aab 1989static int __init omap_gpio_drv_reg(void)
5e1c5ff4 1990{
77640aab 1991 return platform_driver_register(&omap_gpio_driver);
5e1c5ff4 1992}
77640aab 1993postcore_initcall(omap_gpio_drv_reg);
5e1c5ff4 1994
92105bb7
TL		 1995static int __init omap_gpio_sysinit(void)
1996{
11a78b79
DB		 1997 mpuio_init();
1998
140455fa 1999#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
3c437ffd
RW		 2000 if (cpu_is_omap16xx() || cpu_class_is_omap2())
2001 register_syscore_ops(&omap_gpio_syscore_ops);
92105bb7
TL		 2002#endif
2003
3c437ffd 2004 return 0;
92105bb7
TL		 2005}
2006
92105bb7 2007arch_initcall(omap_gpio_sysinit);
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