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[linux.git] / drivers / net / sc92031.c
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bf345707
CEB		 1/* Silan SC92031 PCI Fast Ethernet Adapter driver
2 *
3 * Based on vendor drivers:
4 * Silan Fast Ethernet Netcard Driver:
5 * MODULE_AUTHOR ("gaoyonghong");
6 * MODULE_DESCRIPTION ("SILAN Fast Ethernet driver");
7 * MODULE_LICENSE("GPL");
8 * 8139D Fast Ethernet driver:
9 * (C) 2002 by gaoyonghong
10 * MODULE_AUTHOR ("gaoyonghong");
11 * MODULE_DESCRIPTION ("Rsltek 8139D PCI Fast Ethernet Adapter driver");
12 * MODULE_LICENSE("GPL");
13 * Both are almost identical and seem to be based on pci-skeleton.c
14 *
15 * Rewritten for 2.6 by Cesar Eduardo Barros
16 */
17
18/* Note about set_mac_address: I don't know how to change the hardware
19 * matching, so you need to enable IFF_PROMISC when using it.
20 */
21
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/delay.h>
25#include <linux/pci.h>
26#include <linux/dma-mapping.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/ethtool.h>
30#include <linux/crc32.h>
31
32#include <asm/irq.h>
33
34#define PCI_VENDOR_ID_SILAN 0x1904
35#define PCI_DEVICE_ID_SILAN_SC92031 0x2031
36#define PCI_DEVICE_ID_SILAN_8139D 0x8139
37
38#define SC92031_NAME "sc92031"
39#define SC92031_DESCRIPTION "Silan SC92031 PCI Fast Ethernet Adapter driver"
40#define SC92031_VERSION "2.0c"
41
42/* BAR 0 is MMIO, BAR 1 is PIO */
43#ifndef SC92031_USE_BAR
44#define SC92031_USE_BAR 0
45#endif
46
47/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
48static int multicast_filter_limit = 64;
49module_param(multicast_filter_limit, int, 0);
50MODULE_PARM_DESC(multicast_filter_limit,
51 "Maximum number of filtered multicast addresses");
52
53static int media;
54module_param(media, int, 0);
55MODULE_PARM_DESC(media, "Media type (0x00 = autodetect,"
56 " 0x01 = 10M half, 0x02 = 10M full,"
57 " 0x04 = 100M half, 0x08 = 100M full)");
58
59/* Size of the in-memory receive ring. */
60#define RX_BUF_LEN_IDX 3 /* 0==8K, 1==16K, 2==32K, 3==64K ,4==128K*/
61#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
62
63/* Number of Tx descriptor registers. */
64#define NUM_TX_DESC 4
65
66/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
67#define MAX_ETH_FRAME_SIZE 1536
68
69/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
70#define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
71#define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
72
73/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
74#define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
75
76/* Time in jiffies before concluding the transmitter is hung. */
77#define TX_TIMEOUT (4*HZ)
78
79#define SILAN_STATS_NUM 2 /* number of ETHTOOL_GSTATS */
80
81/* media options */
82#define AUTOSELECT 0x00
83#define M10_HALF 0x01
84#define M10_FULL 0x02
85#define M100_HALF 0x04
86#define M100_FULL 0x08
87
88 /* Symbolic offsets to registers. */
89enum silan_registers {
90 Config0 = 0x00, // Config0
91 Config1 = 0x04, // Config1
92 RxBufWPtr = 0x08, // Rx buffer writer poiter
93 IntrStatus = 0x0C, // Interrupt status
94 IntrMask = 0x10, // Interrupt mask
95 RxbufAddr = 0x14, // Rx buffer start address
96 RxBufRPtr = 0x18, // Rx buffer read pointer
97 Txstatusall = 0x1C, // Transmit status of all descriptors
98 TxStatus0 = 0x20, // Transmit status (Four 32bit registers).
99 TxAddr0 = 0x30, // Tx descriptors (also four 32bit).
100 RxConfig = 0x40, // Rx configuration
101 MAC0 = 0x44, // Ethernet hardware address.
102 MAR0 = 0x4C, // Multicast filter.
103 RxStatus0 = 0x54, // Rx status
104 TxConfig = 0x5C, // Tx configuration
105 PhyCtrl = 0x60, // physical control
106 FlowCtrlConfig = 0x64, // flow control
107 Miicmd0 = 0x68, // Mii command0 register
108 Miicmd1 = 0x6C, // Mii command1 register
109 Miistatus = 0x70, // Mii status register
110 Timercnt = 0x74, // Timer counter register
111 TimerIntr = 0x78, // Timer interrupt register
112 PMConfig = 0x7C, // Power Manager configuration
113 CRC0 = 0x80, // Power Manager CRC ( Two 32bit regisers)
114 Wakeup0 = 0x88, // power Manager wakeup( Eight 64bit regiser)
115 LSBCRC0 = 0xC8, // power Manager LSBCRC(Two 32bit regiser)
116 TestD0 = 0xD0,
117 TestD4 = 0xD4,
118 TestD8 = 0xD8,
119};
120
121#define MII_BMCR 0 // Basic mode control register
122#define MII_BMSR 1 // Basic mode status register
123#define MII_JAB 16
124#define MII_OutputStatus 24
125
126#define BMCR_FULLDPLX 0x0100 // Full duplex
127#define BMCR_ANRESTART 0x0200 // Auto negotiation restart
128#define BMCR_ANENABLE 0x1000 // Enable auto negotiation
129#define BMCR_SPEED100 0x2000 // Select 100Mbps
130#define BMSR_LSTATUS 0x0004 // Link status
131#define PHY_16_JAB_ENB 0x1000
132#define PHY_16_PORT_ENB 0x1
133
134enum IntrStatusBits {
135 LinkFail = 0x80000000,
136 LinkOK = 0x40000000,
137 TimeOut = 0x20000000,
138 RxOverflow = 0x0040,
139 RxOK = 0x0020,
140 TxOK = 0x0001,
141 IntrBits = LinkFail|LinkOK|TimeOut|RxOverflow|RxOK|TxOK,
142};
143
144enum TxStatusBits {
145 TxCarrierLost = 0x20000000,
146 TxAborted = 0x10000000,
147 TxOutOfWindow = 0x08000000,
148 TxNccShift = 22,
149 EarlyTxThresShift = 16,
150 TxStatOK = 0x8000,
151 TxUnderrun = 0x4000,
152 TxOwn = 0x2000,
153};
154
155enum RxStatusBits {
156 RxStatesOK = 0x80000,
157 RxBadAlign = 0x40000,
158 RxHugeFrame = 0x20000,
159 RxSmallFrame = 0x10000,
160 RxCRCOK = 0x8000,
161 RxCrlFrame = 0x4000,
162 Rx_Broadcast = 0x2000,
163 Rx_Multicast = 0x1000,
164 RxAddrMatch = 0x0800,
165 MiiErr = 0x0400,
166};
167
168enum RxConfigBits {
169 RxFullDx = 0x80000000,
170 RxEnb = 0x40000000,
171 RxSmall = 0x20000000,
172 RxHuge = 0x10000000,
173 RxErr = 0x08000000,
174 RxAllphys = 0x04000000,
175 RxMulticast = 0x02000000,
176 RxBroadcast = 0x01000000,
177 RxLoopBack = (1 << 23) | (1 << 22),
178 LowThresholdShift = 12,
179 HighThresholdShift = 2,
180};
181
182enum TxConfigBits {
183 TxFullDx = 0x80000000,
184 TxEnb = 0x40000000,
185 TxEnbPad = 0x20000000,
186 TxEnbHuge = 0x10000000,
187 TxEnbFCS = 0x08000000,
188 TxNoBackOff = 0x04000000,
189 TxEnbPrem = 0x02000000,
190 TxCareLostCrs = 0x1000000,
191 TxExdCollNum = 0xf00000,
192 TxDataRate = 0x80000,
193};
194
195enum PhyCtrlconfigbits {
196 PhyCtrlAne = 0x80000000,
197 PhyCtrlSpd100 = 0x40000000,
198 PhyCtrlSpd10 = 0x20000000,
199 PhyCtrlPhyBaseAddr = 0x1f000000,
200 PhyCtrlDux = 0x800000,
201 PhyCtrlReset = 0x400000,
202};
203
204enum FlowCtrlConfigBits {
205 FlowCtrlFullDX = 0x80000000,
206 FlowCtrlEnb = 0x40000000,
207};
208
209enum Config0Bits {
210 Cfg0_Reset = 0x80000000,
211 Cfg0_Anaoff = 0x40000000,
212 Cfg0_LDPS = 0x20000000,
213};
214
215enum Config1Bits {
216 Cfg1_EarlyRx = 1 << 31,
217 Cfg1_EarlyTx = 1 << 30,
218
219 //rx buffer size
220 Cfg1_Rcv8K = 0x0,
221 Cfg1_Rcv16K = 0x1,
222 Cfg1_Rcv32K = 0x3,
223 Cfg1_Rcv64K = 0x7,
224 Cfg1_Rcv128K = 0xf,
225};
226
227enum MiiCmd0Bits {
228 Mii_Divider = 0x20000000,
229 Mii_WRITE = 0x400000,
230 Mii_READ = 0x200000,
231 Mii_SCAN = 0x100000,
232 Mii_Tamod = 0x80000,
233 Mii_Drvmod = 0x40000,
234 Mii_mdc = 0x20000,
235 Mii_mdoen = 0x10000,
236 Mii_mdo = 0x8000,
237 Mii_mdi = 0x4000,
238};
239
240enum MiiStatusBits {
241 Mii_StatusBusy = 0x80000000,
242};
243
244enum PMConfigBits {
245 PM_Enable = 1 << 31,
246 PM_LongWF = 1 << 30,
247 PM_Magic = 1 << 29,
248 PM_LANWake = 1 << 28,
249 PM_LWPTN = (1 << 27 | 1<< 26),
250 PM_LinkUp = 1 << 25,
251 PM_WakeUp = 1 << 24,
252};
253
254/* Locking rules:
255 * priv->lock protects most of the fields of priv and most of the
256 * hardware registers. It does not have to protect against softirqs
257 * between sc92031_disable_interrupts and sc92031_enable_interrupts;
258 * it also does not need to be used in ->open and ->stop while the
259 * device interrupts are off.
260 * Not having to protect against softirqs is very useful due to heavy
261 * use of mdelay() at _sc92031_reset.
262 * Functions prefixed with _sc92031_ must be called with the lock held;
263 * functions prefixed with sc92031_ must be called without the lock held.
264 * Use mmiowb() before unlocking if the hardware was written to.
265 */
266
267/* Locking rules for the interrupt:
268 * - the interrupt and the tasklet never run at the same time
269 * - neither run between sc92031_disable_interrupts and
270 * sc92031_enable_interrupt
271 */
272
273struct sc92031_priv {
274 spinlock_t lock;
275 /* iomap.h cookie */
276 void __iomem *port_base;
277 /* pci device structure */
278 struct pci_dev *pdev;
279 /* tasklet */
280 struct tasklet_struct tasklet;
281
282 /* CPU address of rx ring */
283 void *rx_ring;
284 /* PCI address of rx ring */
285 dma_addr_t rx_ring_dma_addr;
286 /* PCI address of rx ring read pointer */
287 dma_addr_t rx_ring_tail;
288
289 /* tx ring write index */
290 unsigned tx_head;
291 /* tx ring read index */
292 unsigned tx_tail;
293 /* CPU address of tx bounce buffer */
294 void *tx_bufs;
295 /* PCI address of tx bounce buffer */
296 dma_addr_t tx_bufs_dma_addr;
297
298 /* copies of some hardware registers */
299 u32 intr_status;
300 atomic_t intr_mask;
301 u32 rx_config;
302 u32 tx_config;
303 u32 pm_config;
304
305 /* copy of some flags from dev->flags */
306 unsigned int mc_flags;
307
308 /* for ETHTOOL_GSTATS */
309 u64 tx_timeouts;
310 u64 rx_loss;
311
312 /* for dev->get_stats */
313 long rx_value;
bf345707
CEB		 314};
315
316/* I don't know which registers can be safely read; however, I can guess
317 * MAC0 is one of them. */
318static inline void _sc92031_dummy_read(void __iomem *port_base)
319{
320 ioread32(port_base + MAC0);
321}
322
323static u32 _sc92031_mii_wait(void __iomem *port_base)
324{
325 u32 mii_status;
326
327 do {
328 udelay(10);
329 mii_status = ioread32(port_base + Miistatus);
330 } while (mii_status & Mii_StatusBusy);
331
332 return mii_status;
333}
334
335static u32 _sc92031_mii_cmd(void __iomem *port_base, u32 cmd0, u32 cmd1)
336{
337 iowrite32(Mii_Divider, port_base + Miicmd0);
338
339 _sc92031_mii_wait(port_base);
340
341 iowrite32(cmd1, port_base + Miicmd1);
342 iowrite32(Mii_Divider | cmd0, port_base + Miicmd0);
343
344 return _sc92031_mii_wait(port_base);
345}
346
347static void _sc92031_mii_scan(void __iomem *port_base)
348{
349 _sc92031_mii_cmd(port_base, Mii_SCAN, 0x1 << 6);
350}
351
352static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg)
353{
354 return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13;
355}
356
357static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val)
358{
359 _sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11));
360}
361
362static void sc92031_disable_interrupts(struct net_device *dev)
363{
364 struct sc92031_priv *priv = netdev_priv(dev);
365 void __iomem *port_base = priv->port_base;
366
367 /* tell the tasklet/interrupt not to enable interrupts */
368 atomic_set(&priv->intr_mask, 0);
369 wmb();
370
371 /* stop interrupts */
372 iowrite32(0, port_base + IntrMask);
373 _sc92031_dummy_read(port_base);
374 mmiowb();
375
376 /* wait for any concurrent interrupt/tasklet to finish */
377 synchronize_irq(dev->irq);
378 tasklet_disable(&priv->tasklet);
379}
380
381static void sc92031_enable_interrupts(struct net_device *dev)
382{
383 struct sc92031_priv *priv = netdev_priv(dev);
384 void __iomem *port_base = priv->port_base;
385
386 tasklet_enable(&priv->tasklet);
387
388 atomic_set(&priv->intr_mask, IntrBits);
389 wmb();
390
391 iowrite32(IntrBits, port_base + IntrMask);
392 mmiowb();
393}
394
395static void _sc92031_disable_tx_rx(struct net_device *dev)
396{
397 struct sc92031_priv *priv = netdev_priv(dev);
398 void __iomem *port_base = priv->port_base;
399
400 priv->rx_config &= ~RxEnb;
401 priv->tx_config &= ~TxEnb;
402 iowrite32(priv->rx_config, port_base + RxConfig);
403 iowrite32(priv->tx_config, port_base + TxConfig);
404}
405
406static void _sc92031_enable_tx_rx(struct net_device *dev)
407{
408 struct sc92031_priv *priv = netdev_priv(dev);
409 void __iomem *port_base = priv->port_base;
410
411 priv->rx_config |= RxEnb;
412 priv->tx_config |= TxEnb;
413 iowrite32(priv->rx_config, port_base + RxConfig);
414 iowrite32(priv->tx_config, port_base + TxConfig);
415}
416
417static void _sc92031_tx_clear(struct net_device *dev)
418{
419 struct sc92031_priv *priv = netdev_priv(dev);
420
421 while (priv->tx_head - priv->tx_tail > 0) {
422 priv->tx_tail++;
9c28eaea 423 dev->stats.tx_dropped++;
bf345707
CEB		 424 }
425 priv->tx_head = priv->tx_tail = 0;
426}
427
428static void _sc92031_set_mar(struct net_device *dev)
429{
430 struct sc92031_priv *priv = netdev_priv(dev);
431 void __iomem *port_base = priv->port_base;
432 u32 mar0 = 0, mar1 = 0;
433
434 if ((dev->flags & IFF_PROMISC)
435 || dev->mc_count > multicast_filter_limit
436 || (dev->flags & IFF_ALLMULTI))
437 mar0 = mar1 = 0xffffffff;
438 else if (dev->flags & IFF_MULTICAST) {
439 struct dev_mc_list *mc_list;
440
441 for (mc_list = dev->mc_list; mc_list; mc_list = mc_list->next) {
442 u32 crc;
443 unsigned bit = 0;
444
445 crc = ~ether_crc(ETH_ALEN, mc_list->dmi_addr);
446 crc >>= 24;
447
448 if (crc & 0x01) bit |= 0x02;
449 if (crc & 0x02) bit |= 0x01;
450 if (crc & 0x10) bit |= 0x20;
451 if (crc & 0x20) bit |= 0x10;
452 if (crc & 0x40) bit |= 0x08;
453 if (crc & 0x80) bit |= 0x04;
454
455 if (bit > 31)
456 mar0 |= 0x1 << (bit - 32);
457 else
458 mar1 |= 0x1 << bit;
459 }
460 }
461
462 iowrite32(mar0, port_base + MAR0);
463 iowrite32(mar1, port_base + MAR0 + 4);
464}
465
466static void _sc92031_set_rx_config(struct net_device *dev)
467{
468 struct sc92031_priv *priv = netdev_priv(dev);
469 void __iomem *port_base = priv->port_base;
470 unsigned int old_mc_flags;
471 u32 rx_config_bits = 0;
472
473 old_mc_flags = priv->mc_flags;
474
475 if (dev->flags & IFF_PROMISC)
476 rx_config_bits |= RxSmall | RxHuge | RxErr | RxBroadcast
477 | RxMulticast | RxAllphys;
478
479 if (dev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
480 rx_config_bits |= RxMulticast;
481
482 if (dev->flags & IFF_BROADCAST)
483 rx_config_bits |= RxBroadcast;
484
485 priv->rx_config &= ~(RxSmall | RxHuge | RxErr | RxBroadcast
486 | RxMulticast | RxAllphys);
487 priv->rx_config |= rx_config_bits;
488
489 priv->mc_flags = dev->flags & (IFF_PROMISC | IFF_ALLMULTI
490 | IFF_MULTICAST | IFF_BROADCAST);
491
492 if (netif_carrier_ok(dev) && priv->mc_flags != old_mc_flags)
493 iowrite32(priv->rx_config, port_base + RxConfig);
494}
495
496static bool _sc92031_check_media(struct net_device *dev)
497{
498 struct sc92031_priv *priv = netdev_priv(dev);
499 void __iomem *port_base = priv->port_base;
500 u16 bmsr;
501
502 bmsr = _sc92031_mii_read(port_base, MII_BMSR);
503 rmb();
504 if (bmsr & BMSR_LSTATUS) {
505 bool speed_100, duplex_full;
506 u32 flow_ctrl_config = 0;
507 u16 output_status = _sc92031_mii_read(port_base,
508 MII_OutputStatus);
509 _sc92031_mii_scan(port_base);
510
511 speed_100 = output_status & 0x2;
512 duplex_full = output_status & 0x4;
513
514 /* Initial Tx/Rx configuration */
515 priv->rx_config = (0x40 << LowThresholdShift) | (0x1c0 << HighThresholdShift);
516 priv->tx_config = 0x48800000;
517
518 /* NOTE: vendor driver had dead code here to enable tx padding */
519
520 if (!speed_100)
521 priv->tx_config |= 0x80000;
522
523 // configure rx mode
524 _sc92031_set_rx_config(dev);
525
526 if (duplex_full) {
527 priv->rx_config |= RxFullDx;
528 priv->tx_config |= TxFullDx;
529 flow_ctrl_config = FlowCtrlFullDX | FlowCtrlEnb;
530 } else {
531 priv->rx_config &= ~RxFullDx;
532 priv->tx_config &= ~TxFullDx;
533 }
534
535 _sc92031_set_mar(dev);
536 _sc92031_set_rx_config(dev);
537 _sc92031_enable_tx_rx(dev);
538 iowrite32(flow_ctrl_config, port_base + FlowCtrlConfig);
539
540 netif_carrier_on(dev);
541
542 if (printk_ratelimit())
543 printk(KERN_INFO "%s: link up, %sMbps, %s-duplex\n",
544 dev->name,
545 speed_100 ? "100" : "10",
546 duplex_full ? "full" : "half");
547 return true;
548 } else {
549 _sc92031_mii_scan(port_base);
550
551 netif_carrier_off(dev);
552
553 _sc92031_disable_tx_rx(dev);
554
555 if (printk_ratelimit())
556 printk(KERN_INFO "%s: link down\n", dev->name);
557 return false;
558 }
559}
560
561static void _sc92031_phy_reset(struct net_device *dev)
562{
563 struct sc92031_priv *priv = netdev_priv(dev);
564 void __iomem *port_base = priv->port_base;
565 u32 phy_ctrl;
566
567 phy_ctrl = ioread32(port_base + PhyCtrl);
568 phy_ctrl &= ~(PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10);
569 phy_ctrl |= PhyCtrlAne | PhyCtrlReset;
570
571 switch (media) {
572 default:
573 case AUTOSELECT:
574 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
575 break;
576 case M10_HALF:
577 phy_ctrl |= PhyCtrlSpd10;
578 break;
579 case M10_FULL:
580 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd10;
581 break;
582 case M100_HALF:
583 phy_ctrl |= PhyCtrlSpd100;
584 break;
585 case M100_FULL:
586 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
587 break;
588 }
589
590 iowrite32(phy_ctrl, port_base + PhyCtrl);
591 mdelay(10);
592
593 phy_ctrl &= ~PhyCtrlReset;
594 iowrite32(phy_ctrl, port_base + PhyCtrl);
595 mdelay(1);
596
597 _sc92031_mii_write(port_base, MII_JAB,
598 PHY_16_JAB_ENB | PHY_16_PORT_ENB);
599 _sc92031_mii_scan(port_base);
600
601 netif_carrier_off(dev);
602 netif_stop_queue(dev);
603}
604
605static void _sc92031_reset(struct net_device *dev)
606{
607 struct sc92031_priv *priv = netdev_priv(dev);
608 void __iomem *port_base = priv->port_base;
609
610 /* disable PM */
611 iowrite32(0, port_base + PMConfig);
612
613 /* soft reset the chip */
614 iowrite32(Cfg0_Reset, port_base + Config0);
615 mdelay(200);
616
617 iowrite32(0, port_base + Config0);
618 mdelay(10);
619
620 /* disable interrupts */
621 iowrite32(0, port_base + IntrMask);
622
623 /* clear multicast address */
624 iowrite32(0, port_base + MAR0);
625 iowrite32(0, port_base + MAR0 + 4);
626
627 /* init rx ring */
628 iowrite32(priv->rx_ring_dma_addr, port_base + RxbufAddr);
629 priv->rx_ring_tail = priv->rx_ring_dma_addr;
630
631 /* init tx ring */
632 _sc92031_tx_clear(dev);
633
634 /* clear old register values */
635 priv->intr_status = 0;
636 atomic_set(&priv->intr_mask, 0);
637 priv->rx_config = 0;
638 priv->tx_config = 0;
639 priv->mc_flags = 0;
640
641 /* configure rx buffer size */
642 /* NOTE: vendor driver had dead code here to enable early tx/rx */
643 iowrite32(Cfg1_Rcv64K, port_base + Config1);
644
645 _sc92031_phy_reset(dev);
646 _sc92031_check_media(dev);
647
648 /* calculate rx fifo overflow */
649 priv->rx_value = 0;
650
651 /* enable PM */
652 iowrite32(priv->pm_config, port_base + PMConfig);
653
654 /* clear intr register */
655 ioread32(port_base + IntrStatus);
656}
657
658static void _sc92031_tx_tasklet(struct net_device *dev)
659{
660 struct sc92031_priv *priv = netdev_priv(dev);
661 void __iomem *port_base = priv->port_base;
662
663 unsigned old_tx_tail;
664 unsigned entry;
665 u32 tx_status;
666
667 old_tx_tail = priv->tx_tail;
668 while (priv->tx_head - priv->tx_tail > 0) {
669 entry = priv->tx_tail % NUM_TX_DESC;
670 tx_status = ioread32(port_base + TxStatus0 + entry * 4);
671
672 if (!(tx_status & (TxStatOK | TxUnderrun | TxAborted)))
673 break;
674
675 priv->tx_tail++;
676
677 if (tx_status & TxStatOK) {
9c28eaea
SH		 678 dev->stats.tx_bytes += tx_status & 0x1fff;
679 dev->stats.tx_packets++;
bf345707 680 /* Note: TxCarrierLost is always asserted at 100mbps. */
9c28eaea 681 dev->stats.collisions += (tx_status >> 22) & 0xf;
bf345707
CEB		 682 }
683
684 if (tx_status & (TxOutOfWindow | TxAborted)) {
9c28eaea 685 dev->stats.tx_errors++;
bf345707
CEB		 686
687 if (tx_status & TxAborted)
9c28eaea 688 dev->stats.tx_aborted_errors++;
bf345707
CEB		 689
690 if (tx_status & TxCarrierLost)
9c28eaea 691 dev->stats.tx_carrier_errors++;
bf345707
CEB		 692
693 if (tx_status & TxOutOfWindow)
9c28eaea 694 dev->stats.tx_window_errors++;
bf345707
CEB		 695 }
696
697 if (tx_status & TxUnderrun)
9c28eaea 698 dev->stats.tx_fifo_errors++;
bf345707
CEB		 699 }
700
701 if (priv->tx_tail != old_tx_tail)
702 if (netif_queue_stopped(dev))
703 netif_wake_queue(dev);
704}
705
9c28eaea
SH		 706static void _sc92031_rx_tasklet_error(struct net_device *dev,
707 u32 rx_status, unsigned rx_size)
bf345707
CEB		 708{
709 if(rx_size > (MAX_ETH_FRAME_SIZE + 4) || rx_size < 16) {
9c28eaea
SH		 710 dev->stats.rx_errors++;
711 dev->stats.rx_length_errors++;
bf345707
CEB		 712 }
713
714 if (!(rx_status & RxStatesOK)) {
9c28eaea 715 dev->stats.rx_errors++;
bf345707
CEB		 716
717 if (rx_status & (RxHugeFrame | RxSmallFrame))
9c28eaea 718 dev->stats.rx_length_errors++;
bf345707
CEB		 719
720 if (rx_status & RxBadAlign)
9c28eaea 721 dev->stats.rx_frame_errors++;
bf345707
CEB		 722
723 if (!(rx_status & RxCRCOK))
9c28eaea
SH		 724 dev->stats.rx_crc_errors++;
725 } else {
726 struct sc92031_priv *priv = netdev_priv(dev);
bf345707 727 priv->rx_loss++;
9c28eaea 728 }
bf345707
CEB		 729}
730
731static void _sc92031_rx_tasklet(struct net_device *dev)
732{
733 struct sc92031_priv *priv = netdev_priv(dev);
734 void __iomem *port_base = priv->port_base;
735
736 dma_addr_t rx_ring_head;
737 unsigned rx_len;
738 unsigned rx_ring_offset;
739 void *rx_ring = priv->rx_ring;
740
741 rx_ring_head = ioread32(port_base + RxBufWPtr);
742 rmb();
743
744 /* rx_ring_head is only 17 bits in the RxBufWPtr register.
745 * we need to change it to 32 bits physical address
746 */
747 rx_ring_head &= (dma_addr_t)(RX_BUF_LEN - 1);
748 rx_ring_head |= priv->rx_ring_dma_addr & ~(dma_addr_t)(RX_BUF_LEN - 1);
749 if (rx_ring_head < priv->rx_ring_dma_addr)
750 rx_ring_head += RX_BUF_LEN;
751
752 if (rx_ring_head >= priv->rx_ring_tail)
753 rx_len = rx_ring_head - priv->rx_ring_tail;
754 else
755 rx_len = RX_BUF_LEN - (priv->rx_ring_tail - rx_ring_head);
756
757 if (!rx_len)
758 return;
759
760 if (unlikely(rx_len > RX_BUF_LEN)) {
761 if (printk_ratelimit())
762 printk(KERN_ERR "%s: rx packets length > rx buffer\n",
763 dev->name);
764 return;
765 }
766
767 rx_ring_offset = (priv->rx_ring_tail - priv->rx_ring_dma_addr) % RX_BUF_LEN;
768
769 while (rx_len) {
770 u32 rx_status;
771 unsigned rx_size, rx_size_align, pkt_size;
772 struct sk_buff *skb;
773
774 rx_status = le32_to_cpup((__le32 *)(rx_ring + rx_ring_offset));
775 rmb();
776
777 rx_size = rx_status >> 20;
778 rx_size_align = (rx_size + 3) & ~3; // for 4 bytes aligned
779 pkt_size = rx_size - 4; // Omit the four octet CRC from the length.
780
781 rx_ring_offset = (rx_ring_offset + 4) % RX_BUF_LEN;
782
783 if (unlikely(rx_status == 0
784 || rx_size > (MAX_ETH_FRAME_SIZE + 4)
785 || rx_size < 16
786 || !(rx_status & RxStatesOK))) {
9c28eaea 787 _sc92031_rx_tasklet_error(dev, rx_status, rx_size);
bf345707
CEB		 788 break;
789 }
790
791 if (unlikely(rx_size_align + 4 > rx_len)) {
792 if (printk_ratelimit())
793 printk(KERN_ERR "%s: rx_len is too small\n", dev->name);
794 break;
795 }
796
797 rx_len -= rx_size_align + 4;
798
2723b019 799 skb = netdev_alloc_skb(dev, pkt_size + NET_IP_ALIGN);
bf345707
CEB		 800 if (unlikely(!skb)) {
801 if (printk_ratelimit())
802 printk(KERN_ERR "%s: Couldn't allocate a skb_buff for a packet of size %u\n",
803 dev->name, pkt_size);
804 goto next;
805 }
806
807 skb_reserve(skb, NET_IP_ALIGN);
808
809 if ((rx_ring_offset + pkt_size) > RX_BUF_LEN) {
810 memcpy(skb_put(skb, RX_BUF_LEN - rx_ring_offset),
811 rx_ring + rx_ring_offset, RX_BUF_LEN - rx_ring_offset);
812 memcpy(skb_put(skb, pkt_size - (RX_BUF_LEN - rx_ring_offset)),
813 rx_ring, pkt_size - (RX_BUF_LEN - rx_ring_offset));
814 } else {
815 memcpy(skb_put(skb, pkt_size), rx_ring + rx_ring_offset, pkt_size);
816 }
817
bf345707 818 skb->protocol = eth_type_trans(skb, dev);
bf345707
CEB		 819 netif_rx(skb);
820
9c28eaea
SH		 821 dev->stats.rx_bytes += pkt_size;
822 dev->stats.rx_packets++;
bf345707
CEB		 823
824 if (rx_status & Rx_Multicast)
9c28eaea 825 dev->stats.multicast++;
bf345707
CEB		 826
827 next:
828 rx_ring_offset = (rx_ring_offset + rx_size_align) % RX_BUF_LEN;
829 }
830 mb();
831
832 priv->rx_ring_tail = rx_ring_head;
833 iowrite32(priv->rx_ring_tail, port_base + RxBufRPtr);
834}
835
836static void _sc92031_link_tasklet(struct net_device *dev)
837{
bf345707
CEB		 838 if (_sc92031_check_media(dev))
839 netif_wake_queue(dev);
840 else {
841 netif_stop_queue(dev);
9c28eaea 842 dev->stats.tx_carrier_errors++;
bf345707
CEB		 843 }
844}
845
846static void sc92031_tasklet(unsigned long data)
847{
848 struct net_device *dev = (struct net_device *)data;
849 struct sc92031_priv *priv = netdev_priv(dev);
850 void __iomem *port_base = priv->port_base;
851 u32 intr_status, intr_mask;
852
853 intr_status = priv->intr_status;
854
855 spin_lock(&priv->lock);
856
857 if (unlikely(!netif_running(dev)))
858 goto out;
859
860 if (intr_status & TxOK)
861 _sc92031_tx_tasklet(dev);
862
863 if (intr_status & RxOK)
864 _sc92031_rx_tasklet(dev);
865
866 if (intr_status & RxOverflow)
9c28eaea 867 dev->stats.rx_errors++;
bf345707
CEB		 868
869 if (intr_status & TimeOut) {
9c28eaea
SH		 870 dev->stats.rx_errors++;
871 dev->stats.rx_length_errors++;
bf345707
CEB		 872 }
873
874 if (intr_status & (LinkFail | LinkOK))
875 _sc92031_link_tasklet(dev);
876
877out:
878 intr_mask = atomic_read(&priv->intr_mask);
879 rmb();
880
881 iowrite32(intr_mask, port_base + IntrMask);
882 mmiowb();
883
884 spin_unlock(&priv->lock);
885}
886
887static irqreturn_t sc92031_interrupt(int irq, void *dev_id)
888{
889 struct net_device *dev = dev_id;
890 struct sc92031_priv *priv = netdev_priv(dev);
891 void __iomem *port_base = priv->port_base;
892 u32 intr_status, intr_mask;
893
894 /* mask interrupts before clearing IntrStatus */
895 iowrite32(0, port_base + IntrMask);
896 _sc92031_dummy_read(port_base);
897
898 intr_status = ioread32(port_base + IntrStatus);
899 if (unlikely(intr_status == 0xffffffff))
900 return IRQ_NONE; // hardware has gone missing
901
902 intr_status &= IntrBits;
903 if (!intr_status)
904 goto out_none;
905
906 priv->intr_status = intr_status;
907 tasklet_schedule(&priv->tasklet);
908
909 return IRQ_HANDLED;
910
911out_none:
912 intr_mask = atomic_read(&priv->intr_mask);
913 rmb();
914
915 iowrite32(intr_mask, port_base + IntrMask);
916 mmiowb();
917
918 return IRQ_NONE;
919}
920
921static struct net_device_stats *sc92031_get_stats(struct net_device *dev)
922{
923 struct sc92031_priv *priv = netdev_priv(dev);
924 void __iomem *port_base = priv->port_base;
925
926 // FIXME I do not understand what is this trying to do.
927 if (netif_running(dev)) {
928 int temp;
929
930 spin_lock_bh(&priv->lock);
931
932 /* Update the error count. */
933 temp = (ioread32(port_base + RxStatus0) >> 16) & 0xffff;
934
935 if (temp == 0xffff) {
936 priv->rx_value += temp;
9c28eaea
SH		 937 dev->stats.rx_fifo_errors = priv->rx_value;
938 } else
939 dev->stats.rx_fifo_errors = temp + priv->rx_value;
bf345707
CEB		 940
941 spin_unlock_bh(&priv->lock);
942 }
943
9c28eaea 944 return &dev->stats;
bf345707
CEB		 945}
946
947static int sc92031_start_xmit(struct sk_buff *skb, struct net_device *dev)
948{
bf345707
CEB		 949 struct sc92031_priv *priv = netdev_priv(dev);
950 void __iomem *port_base = priv->port_base;
bf345707
CEB		 951 unsigned len;
952 unsigned entry;
953 u32 tx_status;
954
955 if (unlikely(skb->len > TX_BUF_SIZE)) {
9c28eaea 956 dev->stats.tx_dropped++;
bf345707
CEB		 957 goto out;
958 }
959
699784b7 960 spin_lock(&priv->lock);
bf345707
CEB		 961
962 if (unlikely(!netif_carrier_ok(dev))) {
9c28eaea 963 dev->stats.tx_dropped++;
bf345707
CEB		 964 goto out_unlock;
965 }
966
967 BUG_ON(priv->tx_head - priv->tx_tail >= NUM_TX_DESC);
968
969 entry = priv->tx_head++ % NUM_TX_DESC;
970
971 skb_copy_and_csum_dev(skb, priv->tx_bufs + entry * TX_BUF_SIZE);
972
973 len = skb->len;
6f94f709 974 if (len < ETH_ZLEN) {
5a0a92e6
GR		 975 memset(priv->tx_bufs + entry * TX_BUF_SIZE + len,
976 0, ETH_ZLEN - len);
977 len = ETH_ZLEN;
978 }
bf345707
CEB		 979
980 wmb();
981
982 if (len < 100)
983 tx_status = len;
984 else if (len < 300)
985 tx_status = 0x30000 | len;
986 else
987 tx_status = 0x50000 | len;
988
989 iowrite32(priv->tx_bufs_dma_addr + entry * TX_BUF_SIZE,
990 port_base + TxAddr0 + entry * 4);
991 iowrite32(tx_status, port_base + TxStatus0 + entry * 4);
992 mmiowb();
993
994 dev->trans_start = jiffies;
995
996 if (priv->tx_head - priv->tx_tail >= NUM_TX_DESC)
997 netif_stop_queue(dev);
998
999out_unlock:
699784b7 1000 spin_unlock(&priv->lock);
bf345707
CEB		 1001
1002out:
1003 dev_kfree_skb(skb);
1004
26a17b7b 1005 return NETDEV_TX_OK;
bf345707
CEB		 1006}
1007
1008static int sc92031_open(struct net_device *dev)
1009{
1010 int err;
1011 struct sc92031_priv *priv = netdev_priv(dev);
1012 struct pci_dev *pdev = priv->pdev;
1013
1014 priv->rx_ring = pci_alloc_consistent(pdev, RX_BUF_LEN,
1015 &priv->rx_ring_dma_addr);
1016 if (unlikely(!priv->rx_ring)) {
1017 err = -ENOMEM;
1018 goto out_alloc_rx_ring;
1019 }
1020
1021 priv->tx_bufs = pci_alloc_consistent(pdev, TX_BUF_TOT_LEN,
1022 &priv->tx_bufs_dma_addr);
1023 if (unlikely(!priv->tx_bufs)) {
1024 err = -ENOMEM;
1025 goto out_alloc_tx_bufs;
1026 }
1027 priv->tx_head = priv->tx_tail = 0;
1028
1029 err = request_irq(pdev->irq, sc92031_interrupt,
2db6346f 1030 IRQF_SHARED, dev->name, dev);
bf345707
CEB		 1031 if (unlikely(err < 0))
1032 goto out_request_irq;
1033
1034 priv->pm_config = 0;
1035
1036 /* Interrupts already disabled by sc92031_stop or sc92031_probe */
699784b7 1037 spin_lock_bh(&priv->lock);
bf345707
CEB		 1038
1039 _sc92031_reset(dev);
1040 mmiowb();
1041
699784b7 1042 spin_unlock_bh(&priv->lock);
bf345707
CEB		 1043 sc92031_enable_interrupts(dev);
1044
1045 if (netif_carrier_ok(dev))
1046 netif_start_queue(dev);
1047 else
1048 netif_tx_disable(dev);
1049
1050 return 0;
1051
1052out_request_irq:
1053 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1054 priv->tx_bufs_dma_addr);
1055out_alloc_tx_bufs:
1056 pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1057 priv->rx_ring_dma_addr);
1058out_alloc_rx_ring:
1059 return err;
1060}
1061
1062static int sc92031_stop(struct net_device *dev)
1063{
1064 struct sc92031_priv *priv = netdev_priv(dev);
1065 struct pci_dev *pdev = priv->pdev;
1066
1067 netif_tx_disable(dev);
1068
1069 /* Disable interrupts, stop Tx and Rx. */
1070 sc92031_disable_interrupts(dev);
1071
699784b7 1072 spin_lock_bh(&priv->lock);
bf345707
CEB		 1073
1074 _sc92031_disable_tx_rx(dev);
1075 _sc92031_tx_clear(dev);
1076 mmiowb();
1077
699784b7 1078 spin_unlock_bh(&priv->lock);
bf345707
CEB		 1079
1080 free_irq(pdev->irq, dev);
1081 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1082 priv->tx_bufs_dma_addr);
1083 pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1084 priv->rx_ring_dma_addr);
1085
1086 return 0;
1087}
1088
1089static void sc92031_set_multicast_list(struct net_device *dev)
1090{
1091 struct sc92031_priv *priv = netdev_priv(dev);
1092
1093 spin_lock_bh(&priv->lock);
1094
1095 _sc92031_set_mar(dev);
1096 _sc92031_set_rx_config(dev);
1097 mmiowb();
1098
1099 spin_unlock_bh(&priv->lock);
1100}
1101
1102static void sc92031_tx_timeout(struct net_device *dev)
1103{
1104 struct sc92031_priv *priv = netdev_priv(dev);
1105
1106 /* Disable interrupts by clearing the interrupt mask.*/
1107 sc92031_disable_interrupts(dev);
1108
1109 spin_lock(&priv->lock);
1110
1111 priv->tx_timeouts++;
1112
1113 _sc92031_reset(dev);
1114 mmiowb();
1115
1116 spin_unlock(&priv->lock);
1117
1118 /* enable interrupts */
1119 sc92031_enable_interrupts(dev);
1120
1121 if (netif_carrier_ok(dev))
1122 netif_wake_queue(dev);
1123}
1124
1125#ifdef CONFIG_NET_POLL_CONTROLLER
1126static void sc92031_poll_controller(struct net_device *dev)
1127{
1128 disable_irq(dev->irq);
1129 if (sc92031_interrupt(dev->irq, dev) != IRQ_NONE)
1130 sc92031_tasklet((unsigned long)dev);
1131 enable_irq(dev->irq);
1132}
1133#endif
1134
1135static int sc92031_ethtool_get_settings(struct net_device *dev,
1136 struct ethtool_cmd *cmd)
1137{
1138 struct sc92031_priv *priv = netdev_priv(dev);
1139 void __iomem *port_base = priv->port_base;
1140 u8 phy_address;
1141 u32 phy_ctrl;
1142 u16 output_status;
1143
1144 spin_lock_bh(&priv->lock);
1145
1146 phy_address = ioread32(port_base + Miicmd1) >> 27;
1147 phy_ctrl = ioread32(port_base + PhyCtrl);
1148
1149 output_status = _sc92031_mii_read(port_base, MII_OutputStatus);
1150 _sc92031_mii_scan(port_base);
1151 mmiowb();
1152
1153 spin_unlock_bh(&priv->lock);
1154
1155 cmd->supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
1156 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
1157 | SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII;
1158
1159 cmd->advertising = ADVERTISED_TP | ADVERTISED_MII;
1160
1161 if ((phy_ctrl & (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1162 == (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1163 cmd->advertising |= ADVERTISED_Autoneg;
1164
1165 if ((phy_ctrl & PhyCtrlSpd10) == PhyCtrlSpd10)
1166 cmd->advertising |= ADVERTISED_10baseT_Half;
1167
1168 if ((phy_ctrl & (PhyCtrlSpd10 | PhyCtrlDux))
1169 == (PhyCtrlSpd10 | PhyCtrlDux))
1170 cmd->advertising |= ADVERTISED_10baseT_Full;
1171
1172 if ((phy_ctrl & PhyCtrlSpd100) == PhyCtrlSpd100)
1173 cmd->advertising |= ADVERTISED_100baseT_Half;
1174
1175 if ((phy_ctrl & (PhyCtrlSpd100 | PhyCtrlDux))
1176 == (PhyCtrlSpd100 | PhyCtrlDux))
1177 cmd->advertising |= ADVERTISED_100baseT_Full;
1178
1179 if (phy_ctrl & PhyCtrlAne)
1180 cmd->advertising |= ADVERTISED_Autoneg;
1181
1182 cmd->speed = (output_status & 0x2) ? SPEED_100 : SPEED_10;
1183 cmd->duplex = (output_status & 0x4) ? DUPLEX_FULL : DUPLEX_HALF;
1184 cmd->port = PORT_MII;
1185 cmd->phy_address = phy_address;
1186 cmd->transceiver = XCVR_INTERNAL;
1187 cmd->autoneg = (phy_ctrl & PhyCtrlAne) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
1188
1189 return 0;
1190}
1191
1192static int sc92031_ethtool_set_settings(struct net_device *dev,
1193 struct ethtool_cmd *cmd)
1194{
1195 struct sc92031_priv *priv = netdev_priv(dev);
1196 void __iomem *port_base = priv->port_base;
1197 u32 phy_ctrl;
1198 u32 old_phy_ctrl;
1199
1200 if (!(cmd->speed == SPEED_10 || cmd->speed == SPEED_100))
1201 return -EINVAL;
1202 if (!(cmd->duplex == DUPLEX_HALF || cmd->duplex == DUPLEX_FULL))
1203 return -EINVAL;
1204 if (!(cmd->port == PORT_MII))
1205 return -EINVAL;
1206 if (!(cmd->phy_address == 0x1f))
1207 return -EINVAL;
1208 if (!(cmd->transceiver == XCVR_INTERNAL))
1209 return -EINVAL;
1210 if (!(cmd->autoneg == AUTONEG_DISABLE || cmd->autoneg == AUTONEG_ENABLE))
1211 return -EINVAL;
1212
1213 if (cmd->autoneg == AUTONEG_ENABLE) {
1214 if (!(cmd->advertising & (ADVERTISED_Autoneg
1215 | ADVERTISED_100baseT_Full
1216 | ADVERTISED_100baseT_Half
1217 | ADVERTISED_10baseT_Full
1218 | ADVERTISED_10baseT_Half)))
1219 return -EINVAL;
1220
1221 phy_ctrl = PhyCtrlAne;
1222
1223 // FIXME: I'm not sure what the original code was trying to do
1224 if (cmd->advertising & ADVERTISED_Autoneg)
1225 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
1226 if (cmd->advertising & ADVERTISED_100baseT_Full)
1227 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
1228 if (cmd->advertising & ADVERTISED_100baseT_Half)
1229 phy_ctrl |= PhyCtrlSpd100;
1230 if (cmd->advertising & ADVERTISED_10baseT_Full)
1231 phy_ctrl |= PhyCtrlSpd10 | PhyCtrlDux;
1232 if (cmd->advertising & ADVERTISED_10baseT_Half)
1233 phy_ctrl |= PhyCtrlSpd10;
1234 } else {
1235 // FIXME: Whole branch guessed
1236 phy_ctrl = 0;
1237
1238 if (cmd->speed == SPEED_10)
1239 phy_ctrl |= PhyCtrlSpd10;
1240 else /* cmd->speed == SPEED_100 */
1241 phy_ctrl |= PhyCtrlSpd100;
1242
1243 if (cmd->duplex == DUPLEX_FULL)
1244 phy_ctrl |= PhyCtrlDux;
1245 }
1246
1247 spin_lock_bh(&priv->lock);
1248
1249 old_phy_ctrl = ioread32(port_base + PhyCtrl);
1250 phy_ctrl |= old_phy_ctrl & ~(PhyCtrlAne | PhyCtrlDux
1251 | PhyCtrlSpd100 | PhyCtrlSpd10);
1252 if (phy_ctrl != old_phy_ctrl)
1253 iowrite32(phy_ctrl, port_base + PhyCtrl);
1254
1255 spin_unlock_bh(&priv->lock);
1256
1257 return 0;
1258}
1259
1260static void sc92031_ethtool_get_drvinfo(struct net_device *dev,
1261 struct ethtool_drvinfo *drvinfo)
1262{
1263 struct sc92031_priv *priv = netdev_priv(dev);
1264 struct pci_dev *pdev = priv->pdev;
1265
1266 strcpy(drvinfo->driver, SC92031_NAME);
1267 strcpy(drvinfo->version, SC92031_VERSION);
1268 strcpy(drvinfo->bus_info, pci_name(pdev));
1269}
1270
1271static void sc92031_ethtool_get_wol(struct net_device *dev,
1272 struct ethtool_wolinfo *wolinfo)
1273{
1274 struct sc92031_priv *priv = netdev_priv(dev);
1275 void __iomem *port_base = priv->port_base;
1276 u32 pm_config;
1277
1278 spin_lock_bh(&priv->lock);
1279 pm_config = ioread32(port_base + PMConfig);
1280 spin_unlock_bh(&priv->lock);
1281
1282 // FIXME: Guessed
1283 wolinfo->supported = WAKE_PHY | WAKE_MAGIC
1284 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1285 wolinfo->wolopts = 0;
1286
1287 if (pm_config & PM_LinkUp)
1288 wolinfo->wolopts |= WAKE_PHY;
1289
1290 if (pm_config & PM_Magic)
1291 wolinfo->wolopts |= WAKE_MAGIC;
1292
1293 if (pm_config & PM_WakeUp)
1294 // FIXME: Guessed
1295 wolinfo->wolopts |= WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1296}
1297
1298static int sc92031_ethtool_set_wol(struct net_device *dev,
1299 struct ethtool_wolinfo *wolinfo)
1300{
1301 struct sc92031_priv *priv = netdev_priv(dev);
1302 void __iomem *port_base = priv->port_base;
1303 u32 pm_config;
1304
1305 spin_lock_bh(&priv->lock);
1306
1307 pm_config = ioread32(port_base + PMConfig)
1308 & ~(PM_LinkUp | PM_Magic | PM_WakeUp);
1309
1310 if (wolinfo->wolopts & WAKE_PHY)
1311 pm_config |= PM_LinkUp;
1312
1313 if (wolinfo->wolopts & WAKE_MAGIC)
1314 pm_config |= PM_Magic;
1315
1316 // FIXME: Guessed
1317 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST))
1318 pm_config |= PM_WakeUp;
1319
1320 priv->pm_config = pm_config;
1321 iowrite32(pm_config, port_base + PMConfig);
1322 mmiowb();
1323
1324 spin_unlock_bh(&priv->lock);
1325
1326 return 0;
1327}
1328
1329static int sc92031_ethtool_nway_reset(struct net_device *dev)
1330{
1331 int err = 0;
1332 struct sc92031_priv *priv = netdev_priv(dev);
1333 void __iomem *port_base = priv->port_base;
1334 u16 bmcr;
1335
1336 spin_lock_bh(&priv->lock);
1337
1338 bmcr = _sc92031_mii_read(port_base, MII_BMCR);
1339 if (!(bmcr & BMCR_ANENABLE)) {
1340 err = -EINVAL;
1341 goto out;
1342 }
1343
1344 _sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART);
1345
1346out:
1347 _sc92031_mii_scan(port_base);
1348 mmiowb();
1349
1350 spin_unlock_bh(&priv->lock);
1351
1352 return err;
1353}
1354
1355static const char sc92031_ethtool_stats_strings[SILAN_STATS_NUM][ETH_GSTRING_LEN] = {
1356 "tx_timeout",
1357 "rx_loss",
1358};
1359
1360static void sc92031_ethtool_get_strings(struct net_device *dev,
1361 u32 stringset, u8 *data)
1362{
1363 if (stringset == ETH_SS_STATS)
1364 memcpy(data, sc92031_ethtool_stats_strings,
1365 SILAN_STATS_NUM * ETH_GSTRING_LEN);
1366}
1367
b9f2c044 1368static int sc92031_ethtool_get_sset_count(struct net_device *dev, int sset)
bf345707 1369{
b9f2c044
JG		 1370 switch (sset) {
1371 case ETH_SS_STATS:
1372 return SILAN_STATS_NUM;
1373 default:
1374 return -EOPNOTSUPP;
1375 }
bf345707
CEB		 1376}
1377
1378static void sc92031_ethtool_get_ethtool_stats(struct net_device *dev,
1379 struct ethtool_stats *stats, u64 *data)
1380{
1381 struct sc92031_priv *priv = netdev_priv(dev);
1382
1383 spin_lock_bh(&priv->lock);
1384 data[0] = priv->tx_timeouts;
1385 data[1] = priv->rx_loss;
1386 spin_unlock_bh(&priv->lock);
1387}
1388
974acda0 1389static const struct ethtool_ops sc92031_ethtool_ops = {
bf345707
CEB		 1390 .get_settings = sc92031_ethtool_get_settings,
1391 .set_settings = sc92031_ethtool_set_settings,
1392 .get_drvinfo = sc92031_ethtool_get_drvinfo,
1393 .get_wol = sc92031_ethtool_get_wol,
1394 .set_wol = sc92031_ethtool_set_wol,
1395 .nway_reset = sc92031_ethtool_nway_reset,
1396 .get_link = ethtool_op_get_link,
bf345707 1397 .get_strings = sc92031_ethtool_get_strings,
b9f2c044 1398 .get_sset_count = sc92031_ethtool_get_sset_count,
bf345707 1399 .get_ethtool_stats = sc92031_ethtool_get_ethtool_stats,
bf345707
CEB		 1400};
1401
974acda0
SH		 1402
1403static const struct net_device_ops sc92031_netdev_ops = {
1404 .ndo_get_stats = sc92031_get_stats,
1405 .ndo_start_xmit = sc92031_start_xmit,
1406 .ndo_open = sc92031_open,
1407 .ndo_stop = sc92031_stop,
1408 .ndo_set_multicast_list = sc92031_set_multicast_list,
1409 .ndo_change_mtu = eth_change_mtu,
1410 .ndo_validate_addr = eth_validate_addr,
1411 .ndo_tx_timeout = sc92031_tx_timeout,
1412#ifdef CONFIG_NET_POLL_CONTROLLER
1413 .ndo_poll_controller = sc92031_poll_controller,
1414#endif
1415};
1416
bf345707
CEB		 1417static int __devinit sc92031_probe(struct pci_dev *pdev,
1418 const struct pci_device_id *id)
1419{
1420 int err;
1421 void __iomem* port_base;
1422 struct net_device *dev;
1423 struct sc92031_priv *priv;
1424 u32 mac0, mac1;
1425
1426 err = pci_enable_device(pdev);
1427 if (unlikely(err < 0))
1428 goto out_enable_device;
1429
1430 pci_set_master(pdev);
1431
1432 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1433 if (unlikely(err < 0))
1434 goto out_set_dma_mask;
1435
1436 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1437 if (unlikely(err < 0))
1438 goto out_set_dma_mask;
1439
1440 err = pci_request_regions(pdev, SC92031_NAME);
1441 if (unlikely(err < 0))
1442 goto out_request_regions;
1443
1444 port_base = pci_iomap(pdev, SC92031_USE_BAR, 0);
1445 if (unlikely(!port_base)) {
1446 err = -EIO;
1447 goto out_iomap;
1448 }
1449
1450 dev = alloc_etherdev(sizeof(struct sc92031_priv));
1451 if (unlikely(!dev)) {
1452 err = -ENOMEM;
1453 goto out_alloc_etherdev;
1454 }
1455
1456 pci_set_drvdata(pdev, dev);
5a81f143 1457 SET_NETDEV_DEV(dev, &pdev->dev);
bf345707
CEB		 1458
1459#if SC92031_USE_BAR == 0
1460 dev->mem_start = pci_resource_start(pdev, SC92031_USE_BAR);
1461 dev->mem_end = pci_resource_end(pdev, SC92031_USE_BAR);
1462#elif SC92031_USE_BAR == 1
1463 dev->base_addr = pci_resource_start(pdev, SC92031_USE_BAR);
1464#endif
1465 dev->irq = pdev->irq;
1466
1467 /* faked with skb_copy_and_csum_dev */
1468 dev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1469
974acda0 1470 dev->netdev_ops = &sc92031_netdev_ops;
bf345707 1471 dev->watchdog_timeo = TX_TIMEOUT;
974acda0 1472 dev->ethtool_ops = &sc92031_ethtool_ops;
bf345707
CEB		 1473
1474 priv = netdev_priv(dev);
1475 spin_lock_init(&priv->lock);
1476 priv->port_base = port_base;
1477 priv->pdev = pdev;
1478 tasklet_init(&priv->tasklet, sc92031_tasklet, (unsigned long)dev);
1479 /* Fudge tasklet count so the call to sc92031_enable_interrupts at
1480 * sc92031_open will work correctly */
1481 tasklet_disable_nosync(&priv->tasklet);
1482
1483 /* PCI PM Wakeup */
1484 iowrite32((~PM_LongWF & ~PM_LWPTN) | PM_Enable, port_base + PMConfig);
1485
1486 mac0 = ioread32(port_base + MAC0);
1487 mac1 = ioread32(port_base + MAC0 + 4);
1488 dev->dev_addr[0] = dev->perm_addr[0] = mac0 >> 24;
1489 dev->dev_addr[1] = dev->perm_addr[1] = mac0 >> 16;
1490 dev->dev_addr[2] = dev->perm_addr[2] = mac0 >> 8;
1491 dev->dev_addr[3] = dev->perm_addr[3] = mac0;
1492 dev->dev_addr[4] = dev->perm_addr[4] = mac1 >> 8;
1493 dev->dev_addr[5] = dev->perm_addr[5] = mac1;
1494
1495 err = register_netdev(dev);
1496 if (err < 0)
1497 goto out_register_netdev;
1498
1499 return 0;
1500
1501out_register_netdev:
1502 free_netdev(dev);
1503out_alloc_etherdev:
1504 pci_iounmap(pdev, port_base);
1505out_iomap:
1506 pci_release_regions(pdev);
1507out_request_regions:
1508out_set_dma_mask:
1509 pci_disable_device(pdev);
1510out_enable_device:
1511 return err;
1512}
1513
1514static void __devexit sc92031_remove(struct pci_dev *pdev)
1515{
1516 struct net_device *dev = pci_get_drvdata(pdev);
1517 struct sc92031_priv *priv = netdev_priv(dev);
1518 void __iomem* port_base = priv->port_base;
1519
1520 unregister_netdev(dev);
1521 free_netdev(dev);
1522 pci_iounmap(pdev, port_base);
1523 pci_release_regions(pdev);
1524 pci_disable_device(pdev);
1525}
1526
1527static int sc92031_suspend(struct pci_dev *pdev, pm_message_t state)
1528{
1529 struct net_device *dev = pci_get_drvdata(pdev);
1530 struct sc92031_priv *priv = netdev_priv(dev);
1531
1532 pci_save_state(pdev);
1533
1534 if (!netif_running(dev))
1535 goto out;
1536
1537 netif_device_detach(dev);
1538
1539 /* Disable interrupts, stop Tx and Rx. */
1540 sc92031_disable_interrupts(dev);
1541
699784b7 1542 spin_lock_bh(&priv->lock);
bf345707
CEB		 1543
1544 _sc92031_disable_tx_rx(dev);
1545 _sc92031_tx_clear(dev);
1546 mmiowb();
1547
699784b7 1548 spin_unlock_bh(&priv->lock);
bf345707
CEB		 1549
1550out:
1551 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1552
1553 return 0;
1554}
1555
1556static int sc92031_resume(struct pci_dev *pdev)
1557{
1558 struct net_device *dev = pci_get_drvdata(pdev);
1559 struct sc92031_priv *priv = netdev_priv(dev);
1560
1561 pci_restore_state(pdev);
1562 pci_set_power_state(pdev, PCI_D0);
1563
1564 if (!netif_running(dev))
1565 goto out;
1566
1567 /* Interrupts already disabled by sc92031_suspend */
699784b7 1568 spin_lock_bh(&priv->lock);
bf345707
CEB		 1569
1570 _sc92031_reset(dev);
1571 mmiowb();
1572
699784b7 1573 spin_unlock_bh(&priv->lock);
bf345707
CEB		 1574 sc92031_enable_interrupts(dev);
1575
1576 netif_device_attach(dev);
1577
1578 if (netif_carrier_ok(dev))
1579 netif_wake_queue(dev);
1580 else
1581 netif_tx_disable(dev);
1582
1583out:
1584 return 0;
1585}
1586
1587static struct pci_device_id sc92031_pci_device_id_table[] __devinitdata = {
1588 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, PCI_DEVICE_ID_SILAN_SC92031) },
1589 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, PCI_DEVICE_ID_SILAN_8139D) },
1590 { 0, }
1591};
1592MODULE_DEVICE_TABLE(pci, sc92031_pci_device_id_table);
1593
1594static struct pci_driver sc92031_pci_driver = {
1595 .name = SC92031_NAME,
1596 .id_table = sc92031_pci_device_id_table,
1597 .probe = sc92031_probe,
1598 .remove = __devexit_p(sc92031_remove),
1599 .suspend = sc92031_suspend,
1600 .resume = sc92031_resume,
1601};
1602
1603static int __init sc92031_init(void)
1604{
1605 printk(KERN_INFO SC92031_DESCRIPTION " " SC92031_VERSION "\n");
1606 return pci_register_driver(&sc92031_pci_driver);
1607}
1608
1609static void __exit sc92031_exit(void)
1610{
1611 pci_unregister_driver(&sc92031_pci_driver);
1612}
1613
1614module_init(sc92031_init);
1615module_exit(sc92031_exit);
1616
1617MODULE_LICENSE("GPL");
1618MODULE_AUTHOR("Cesar Eduardo Barros <[email protected]>");
1619MODULE_DESCRIPTION(SC92031_DESCRIPTION);
1620MODULE_VERSION(SC92031_VERSION);
Empty description
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