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c283cf2c MC |
1 | /* |
2 | * drivers/watchdog/ar7_wdt.c | |
3 | * | |
4 | * Copyright (C) 2007 Nicolas Thill <[email protected]> | |
5 | * Copyright (c) 2005 Enrik Berkhan <[email protected]> | |
6 | * | |
7 | * Some code taken from: | |
8 | * National Semiconductor SCx200 Watchdog support | |
9 | * Copyright (c) 2001,2002 Christer Weinigel <[email protected]> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
24 | */ | |
25 | ||
27c766aa JP |
26 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
27 | ||
c283cf2c MC |
28 | #include <linux/module.h> |
29 | #include <linux/moduleparam.h> | |
30 | #include <linux/errno.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/miscdevice.h> | |
64d4062a | 33 | #include <linux/platform_device.h> |
c283cf2c | 34 | #include <linux/watchdog.h> |
c283cf2c MC |
35 | #include <linux/fs.h> |
36 | #include <linux/ioport.h> | |
37 | #include <linux/io.h> | |
38 | #include <linux/uaccess.h> | |
780019dd | 39 | #include <linux/clk.h> |
c283cf2c MC |
40 | |
41 | #include <asm/addrspace.h> | |
c5e7f5a3 | 42 | #include <asm/mach-ar7/ar7.h> |
c283cf2c | 43 | |
c283cf2c MC |
44 | #define LONGNAME "TI AR7 Watchdog Timer" |
45 | ||
46 | MODULE_AUTHOR("Nicolas Thill <[email protected]>"); | |
47 | MODULE_DESCRIPTION(LONGNAME); | |
48 | MODULE_LICENSE("GPL"); | |
49 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | |
50 | ||
51 | static int margin = 60; | |
52 | module_param(margin, int, 0); | |
53 | MODULE_PARM_DESC(margin, "Watchdog margin in seconds"); | |
54 | ||
86a1e189 WVS |
55 | static bool nowayout = WATCHDOG_NOWAYOUT; |
56 | module_param(nowayout, bool, 0); | |
c283cf2c MC |
57 | MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close"); |
58 | ||
59 | #define READ_REG(x) readl((void __iomem *)&(x)) | |
60 | #define WRITE_REG(x, v) writel((v), (void __iomem *)&(x)) | |
61 | ||
62 | struct ar7_wdt { | |
63 | u32 kick_lock; | |
64 | u32 kick; | |
65 | u32 change_lock; | |
66 | u32 change; | |
67 | u32 disable_lock; | |
68 | u32 disable; | |
69 | u32 prescale_lock; | |
70 | u32 prescale; | |
71 | }; | |
72 | ||
670d59c0 | 73 | static unsigned long wdt_is_open; |
c283cf2c | 74 | static unsigned expect_close; |
1334f329 | 75 | static DEFINE_SPINLOCK(wdt_lock); |
c283cf2c MC |
76 | |
77 | /* XXX currently fixed, allows max margin ~68.72 secs */ | |
78 | #define prescale_value 0xffff | |
79 | ||
64d4062a FF |
80 | /* Resource of the WDT registers */ |
81 | static struct resource *ar7_regs_wdt; | |
c283cf2c MC |
82 | /* Pointer to the remapped WDT IO space */ |
83 | static struct ar7_wdt *ar7_wdt; | |
c283cf2c | 84 | |
780019dd FF |
85 | static struct clk *vbus_clk; |
86 | ||
c283cf2c MC |
87 | static void ar7_wdt_kick(u32 value) |
88 | { | |
89 | WRITE_REG(ar7_wdt->kick_lock, 0x5555); | |
90 | if ((READ_REG(ar7_wdt->kick_lock) & 3) == 1) { | |
91 | WRITE_REG(ar7_wdt->kick_lock, 0xaaaa); | |
92 | if ((READ_REG(ar7_wdt->kick_lock) & 3) == 3) { | |
93 | WRITE_REG(ar7_wdt->kick, value); | |
94 | return; | |
95 | } | |
96 | } | |
27c766aa | 97 | pr_err("failed to unlock WDT kick reg\n"); |
c283cf2c MC |
98 | } |
99 | ||
100 | static void ar7_wdt_prescale(u32 value) | |
101 | { | |
102 | WRITE_REG(ar7_wdt->prescale_lock, 0x5a5a); | |
103 | if ((READ_REG(ar7_wdt->prescale_lock) & 3) == 1) { | |
104 | WRITE_REG(ar7_wdt->prescale_lock, 0xa5a5); | |
105 | if ((READ_REG(ar7_wdt->prescale_lock) & 3) == 3) { | |
106 | WRITE_REG(ar7_wdt->prescale, value); | |
107 | return; | |
108 | } | |
109 | } | |
27c766aa | 110 | pr_err("failed to unlock WDT prescale reg\n"); |
c283cf2c MC |
111 | } |
112 | ||
113 | static void ar7_wdt_change(u32 value) | |
114 | { | |
115 | WRITE_REG(ar7_wdt->change_lock, 0x6666); | |
116 | if ((READ_REG(ar7_wdt->change_lock) & 3) == 1) { | |
117 | WRITE_REG(ar7_wdt->change_lock, 0xbbbb); | |
118 | if ((READ_REG(ar7_wdt->change_lock) & 3) == 3) { | |
119 | WRITE_REG(ar7_wdt->change, value); | |
120 | return; | |
121 | } | |
122 | } | |
27c766aa | 123 | pr_err("failed to unlock WDT change reg\n"); |
c283cf2c MC |
124 | } |
125 | ||
126 | static void ar7_wdt_disable(u32 value) | |
127 | { | |
128 | WRITE_REG(ar7_wdt->disable_lock, 0x7777); | |
129 | if ((READ_REG(ar7_wdt->disable_lock) & 3) == 1) { | |
130 | WRITE_REG(ar7_wdt->disable_lock, 0xcccc); | |
131 | if ((READ_REG(ar7_wdt->disable_lock) & 3) == 2) { | |
132 | WRITE_REG(ar7_wdt->disable_lock, 0xdddd); | |
133 | if ((READ_REG(ar7_wdt->disable_lock) & 3) == 3) { | |
134 | WRITE_REG(ar7_wdt->disable, value); | |
135 | return; | |
136 | } | |
137 | } | |
138 | } | |
27c766aa | 139 | pr_err("failed to unlock WDT disable reg\n"); |
c283cf2c MC |
140 | } |
141 | ||
142 | static void ar7_wdt_update_margin(int new_margin) | |
143 | { | |
144 | u32 change; | |
780019dd | 145 | u32 vbus_rate; |
c283cf2c | 146 | |
780019dd FF |
147 | vbus_rate = clk_get_rate(vbus_clk); |
148 | change = new_margin * (vbus_rate / prescale_value); | |
670d59c0 AC |
149 | if (change < 1) |
150 | change = 1; | |
151 | if (change > 0xffff) | |
152 | change = 0xffff; | |
c283cf2c | 153 | ar7_wdt_change(change); |
780019dd | 154 | margin = change * prescale_value / vbus_rate; |
27c766aa JP |
155 | pr_info("timer margin %d seconds (prescale %d, change %d, freq %d)\n", |
156 | margin, prescale_value, change, vbus_rate); | |
c283cf2c MC |
157 | } |
158 | ||
159 | static void ar7_wdt_enable_wdt(void) | |
160 | { | |
27c766aa | 161 | pr_debug("enabling watchdog timer\n"); |
c283cf2c MC |
162 | ar7_wdt_disable(1); |
163 | ar7_wdt_kick(1); | |
164 | } | |
165 | ||
166 | static void ar7_wdt_disable_wdt(void) | |
167 | { | |
27c766aa | 168 | pr_debug("disabling watchdog timer\n"); |
c283cf2c MC |
169 | ar7_wdt_disable(0); |
170 | } | |
171 | ||
172 | static int ar7_wdt_open(struct inode *inode, struct file *file) | |
173 | { | |
174 | /* only allow one at a time */ | |
670d59c0 | 175 | if (test_and_set_bit(0, &wdt_is_open)) |
c283cf2c MC |
176 | return -EBUSY; |
177 | ar7_wdt_enable_wdt(); | |
178 | expect_close = 0; | |
179 | ||
180 | return nonseekable_open(inode, file); | |
181 | } | |
182 | ||
183 | static int ar7_wdt_release(struct inode *inode, struct file *file) | |
184 | { | |
185 | if (!expect_close) | |
27c766aa | 186 | pr_warn("watchdog device closed unexpectedly, will not disable the watchdog timer\n"); |
c283cf2c MC |
187 | else if (!nowayout) |
188 | ar7_wdt_disable_wdt(); | |
670d59c0 | 189 | clear_bit(0, &wdt_is_open); |
c283cf2c MC |
190 | return 0; |
191 | } | |
192 | ||
c283cf2c MC |
193 | static ssize_t ar7_wdt_write(struct file *file, const char *data, |
194 | size_t len, loff_t *ppos) | |
195 | { | |
196 | /* check for a magic close character */ | |
197 | if (len) { | |
198 | size_t i; | |
199 | ||
670d59c0 | 200 | spin_lock(&wdt_lock); |
c283cf2c | 201 | ar7_wdt_kick(1); |
670d59c0 | 202 | spin_unlock(&wdt_lock); |
c283cf2c MC |
203 | |
204 | expect_close = 0; | |
205 | for (i = 0; i < len; ++i) { | |
206 | char c; | |
7944d3a5 | 207 | if (get_user(c, data + i)) |
c283cf2c MC |
208 | return -EFAULT; |
209 | if (c == 'V') | |
210 | expect_close = 1; | |
211 | } | |
212 | ||
213 | } | |
214 | return len; | |
215 | } | |
216 | ||
670d59c0 AC |
217 | static long ar7_wdt_ioctl(struct file *file, |
218 | unsigned int cmd, unsigned long arg) | |
c283cf2c | 219 | { |
42747d71 | 220 | static const struct watchdog_info ident = { |
c283cf2c MC |
221 | .identity = LONGNAME, |
222 | .firmware_version = 1, | |
e73a7802 WVS |
223 | .options = (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | |
224 | WDIOF_MAGICCLOSE), | |
c283cf2c MC |
225 | }; |
226 | int new_margin; | |
227 | ||
228 | switch (cmd) { | |
c283cf2c MC |
229 | case WDIOC_GETSUPPORT: |
230 | if (copy_to_user((struct watchdog_info *)arg, &ident, | |
231 | sizeof(ident))) | |
232 | return -EFAULT; | |
233 | return 0; | |
234 | case WDIOC_GETSTATUS: | |
235 | case WDIOC_GETBOOTSTATUS: | |
236 | if (put_user(0, (int *)arg)) | |
237 | return -EFAULT; | |
238 | return 0; | |
239 | case WDIOC_KEEPALIVE: | |
240 | ar7_wdt_kick(1); | |
241 | return 0; | |
242 | case WDIOC_SETTIMEOUT: | |
243 | if (get_user(new_margin, (int *)arg)) | |
244 | return -EFAULT; | |
245 | if (new_margin < 1) | |
246 | return -EINVAL; | |
247 | ||
670d59c0 | 248 | spin_lock(&wdt_lock); |
c283cf2c MC |
249 | ar7_wdt_update_margin(new_margin); |
250 | ar7_wdt_kick(1); | |
670d59c0 | 251 | spin_unlock(&wdt_lock); |
c283cf2c MC |
252 | |
253 | case WDIOC_GETTIMEOUT: | |
254 | if (put_user(margin, (int *)arg)) | |
255 | return -EFAULT; | |
256 | return 0; | |
0c06090c WVS |
257 | default: |
258 | return -ENOTTY; | |
c283cf2c MC |
259 | } |
260 | } | |
261 | ||
b47a166e | 262 | static const struct file_operations ar7_wdt_fops = { |
c283cf2c MC |
263 | .owner = THIS_MODULE, |
264 | .write = ar7_wdt_write, | |
670d59c0 | 265 | .unlocked_ioctl = ar7_wdt_ioctl, |
c283cf2c MC |
266 | .open = ar7_wdt_open, |
267 | .release = ar7_wdt_release, | |
6038f373 | 268 | .llseek = no_llseek, |
c283cf2c MC |
269 | }; |
270 | ||
271 | static struct miscdevice ar7_wdt_miscdev = { | |
272 | .minor = WATCHDOG_MINOR, | |
273 | .name = "watchdog", | |
274 | .fops = &ar7_wdt_fops, | |
275 | }; | |
276 | ||
2d991a16 | 277 | static int ar7_wdt_probe(struct platform_device *pdev) |
c283cf2c MC |
278 | { |
279 | int rc; | |
280 | ||
64d4062a FF |
281 | ar7_regs_wdt = |
282 | platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); | |
283 | if (!ar7_regs_wdt) { | |
27c766aa | 284 | pr_err("could not get registers resource\n"); |
ae21cc20 | 285 | return -ENODEV; |
c283cf2c MC |
286 | } |
287 | ||
ae21cc20 | 288 | ar7_wdt = devm_request_and_ioremap(&pdev->dev, ar7_regs_wdt); |
64d4062a | 289 | if (!ar7_wdt) { |
27c766aa | 290 | pr_err("could not ioremap registers\n"); |
ae21cc20 | 291 | return -ENXIO; |
64d4062a | 292 | } |
c283cf2c | 293 | |
780019dd FF |
294 | vbus_clk = clk_get(NULL, "vbus"); |
295 | if (IS_ERR(vbus_clk)) { | |
27c766aa | 296 | pr_err("could not get vbus clock\n"); |
ae21cc20 | 297 | return PTR_ERR(vbus_clk); |
780019dd FF |
298 | } |
299 | ||
c283cf2c MC |
300 | ar7_wdt_disable_wdt(); |
301 | ar7_wdt_prescale(prescale_value); | |
302 | ar7_wdt_update_margin(margin); | |
303 | ||
c283cf2c MC |
304 | rc = misc_register(&ar7_wdt_miscdev); |
305 | if (rc) { | |
27c766aa | 306 | pr_err("unable to register misc device\n"); |
ae21cc20 | 307 | goto out; |
c283cf2c | 308 | } |
ae21cc20 | 309 | return 0; |
c283cf2c | 310 | |
c283cf2c | 311 | out: |
ae21cc20 JL |
312 | clk_put(vbus_clk); |
313 | vbus_clk = NULL; | |
c283cf2c MC |
314 | return rc; |
315 | } | |
316 | ||
4b12b896 | 317 | static int ar7_wdt_remove(struct platform_device *pdev) |
c283cf2c MC |
318 | { |
319 | misc_deregister(&ar7_wdt_miscdev); | |
ae21cc20 JL |
320 | clk_put(vbus_clk); |
321 | vbus_clk = NULL; | |
64d4062a FF |
322 | return 0; |
323 | } | |
324 | ||
325 | static void ar7_wdt_shutdown(struct platform_device *pdev) | |
326 | { | |
327 | if (!nowayout) | |
328 | ar7_wdt_disable_wdt(); | |
329 | } | |
330 | ||
331 | static struct platform_driver ar7_wdt_driver = { | |
332 | .probe = ar7_wdt_probe, | |
82268714 | 333 | .remove = ar7_wdt_remove, |
64d4062a FF |
334 | .shutdown = ar7_wdt_shutdown, |
335 | .driver = { | |
336 | .owner = THIS_MODULE, | |
337 | .name = "ar7_wdt", | |
338 | }, | |
339 | }; | |
340 | ||
b8ec6118 | 341 | module_platform_driver(ar7_wdt_driver); |