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[ALSA] sun-cs4231: improved waiting after MCE down
[linux.git] / sound / isa / cs423x / cs4231_lib.c
CommitLineData
1da177e4 1/*
c1017a4c 2 * Copyright (c) by Jaroslav Kysela <[email protected]>
1da177e4
LT		 3 * Routines for control of CS4231(A)/CS4232/InterWave & compatible chips
4 *
5 * Bugs:
6 * - sometimes record brokes playback with WSS portion of
7 * Yamaha OPL3-SA3 chip
8 * - CS4231 (GUS MAX) - still trouble with occasional noises
9 * - broken initialization?
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 */
26
27#include <sound/driver.h>
28#include <linux/delay.h>
29#include <linux/pm.h>
30#include <linux/init.h>
31#include <linux/interrupt.h>
32#include <linux/slab.h>
33#include <linux/ioport.h>
34#include <sound/core.h>
35#include <sound/cs4231.h>
36#include <sound/pcm_params.h>
37
38#include <asm/io.h>
39#include <asm/dma.h>
40#include <asm/irq.h>
41
c1017a4c 42MODULE_AUTHOR("Jaroslav Kysela <[email protected]>");
1da177e4
LT		 43MODULE_DESCRIPTION("Routines for control of CS4231(A)/CS4232/InterWave & compatible chips");
44MODULE_LICENSE("GPL");
45
46#if 0
47#define SNDRV_DEBUG_MCE
48#endif
49
50/*
51 * Some variables
52 */
53
54static unsigned char freq_bits[14] = {
55 /* 5510 */ 0x00 | CS4231_XTAL2,
56 /* 6620 */ 0x0E | CS4231_XTAL2,
57 /* 8000 */ 0x00 | CS4231_XTAL1,
58 /* 9600 */ 0x0E | CS4231_XTAL1,
59 /* 11025 */ 0x02 | CS4231_XTAL2,
60 /* 16000 */ 0x02 | CS4231_XTAL1,
61 /* 18900 */ 0x04 | CS4231_XTAL2,
62 /* 22050 */ 0x06 | CS4231_XTAL2,
63 /* 27042 */ 0x04 | CS4231_XTAL1,
64 /* 32000 */ 0x06 | CS4231_XTAL1,
65 /* 33075 */ 0x0C | CS4231_XTAL2,
66 /* 37800 */ 0x08 | CS4231_XTAL2,
67 /* 44100 */ 0x0A | CS4231_XTAL2,
68 /* 48000 */ 0x0C | CS4231_XTAL1
69};
70
71static unsigned int rates[14] = {
72 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
73 27042, 32000, 33075, 37800, 44100, 48000
74};
75
ba2375a4 76static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
6c041b5e 77 .count = ARRAY_SIZE(rates),
1da177e4
LT		 78 .list = rates,
79 .mask = 0,
80};
81
ba2375a4 82static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime)
1da177e4
LT		 83{
84 return snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
85}
86
87static unsigned char snd_cs4231_original_image[32] =
88{
89 0x00, /* 00/00 - lic */
90 0x00, /* 01/01 - ric */
91 0x9f, /* 02/02 - la1ic */
92 0x9f, /* 03/03 - ra1ic */
93 0x9f, /* 04/04 - la2ic */
94 0x9f, /* 05/05 - ra2ic */
95 0xbf, /* 06/06 - loc */
96 0xbf, /* 07/07 - roc */
97 0x20, /* 08/08 - pdfr */
98 CS4231_AUTOCALIB, /* 09/09 - ic */
99 0x00, /* 0a/10 - pc */
100 0x00, /* 0b/11 - ti */
101 CS4231_MODE2, /* 0c/12 - mi */
102 0xfc, /* 0d/13 - lbc */
103 0x00, /* 0e/14 - pbru */
104 0x00, /* 0f/15 - pbrl */
105 0x80, /* 10/16 - afei */
106 0x01, /* 11/17 - afeii */
107 0x9f, /* 12/18 - llic */
108 0x9f, /* 13/19 - rlic */
109 0x00, /* 14/20 - tlb */
110 0x00, /* 15/21 - thb */
111 0x00, /* 16/22 - la3mic/reserved */
112 0x00, /* 17/23 - ra3mic/reserved */
113 0x00, /* 18/24 - afs */
114 0x00, /* 19/25 - lamoc/version */
115 0xcf, /* 1a/26 - mioc */
116 0x00, /* 1b/27 - ramoc/reserved */
117 0x20, /* 1c/28 - cdfr */
118 0x00, /* 1d/29 - res4 */
119 0x00, /* 1e/30 - cbru */
120 0x00, /* 1f/31 - cbrl */
121};
122
123/*
124 * Basic I/O functions
125 */
126
ba2375a4 127static inline void cs4231_outb(struct snd_cs4231 *chip, u8 offset, u8 val)
1da177e4 128{
1da177e4 129 outb(val, chip->port + offset);
1da177e4
LT		 130}
131
ba2375a4 132static inline u8 cs4231_inb(struct snd_cs4231 *chip, u8 offset)
1da177e4 133{
1da177e4 134 return inb(chip->port + offset);
1da177e4
LT		 135}
136
6c041b5e 137static void snd_cs4231_wait(struct snd_cs4231 *chip)
1da177e4
LT		 138{
139 int timeout;
1da177e4
LT		 140
141 for (timeout = 250;
142 timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
143 timeout--)
144 udelay(100);
6c041b5e
KH		 145}
146
147static void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg,
148 unsigned char mask, unsigned char value)
149{
150 unsigned char tmp = (chip->image[reg] & mask) | value;
151
152 snd_cs4231_wait(chip);
1da177e4
LT		 153#ifdef CONFIG_SND_DEBUG
154 if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
155 snd_printk("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
156#endif
6c041b5e
KH		 157 chip->image[reg] = tmp;
158 if (!chip->calibrate_mute) {
1da177e4 159 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
6c041b5e 160 wmb();
1da177e4 161 cs4231_outb(chip, CS4231P(REG), tmp);
1da177e4
LT		 162 mb();
163 }
164}
165
ba2375a4 166static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg, unsigned char value)
1da177e4
LT		 167{
168 int timeout;
169
170 for (timeout = 250;
171 timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
172 timeout--)
173 udelay(10);
174 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
175 cs4231_outb(chip, CS4231P(REG), value);
176 mb();
177}
178
ba2375a4 179void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char value)
1da177e4 180{
6c041b5e 181 snd_cs4231_wait(chip);
1da177e4
LT		 182#ifdef CONFIG_SND_DEBUG
183 if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
184 snd_printk("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
185#endif
186 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
187 cs4231_outb(chip, CS4231P(REG), value);
188 chip->image[reg] = value;
189 mb();
6c041b5e
KH		 190 snd_printdd("codec out - reg 0x%x = 0x%x\n",
191 chip->mce_bit | reg, value);
1da177e4
LT		 192}
193
ba2375a4 194unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg)
1da177e4 195{
6c041b5e 196 snd_cs4231_wait(chip);
1da177e4
LT		 197#ifdef CONFIG_SND_DEBUG
198 if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
199 snd_printk("in: auto calibration time out - reg = 0x%x\n", reg);
200#endif
201 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
202 mb();
203 return cs4231_inb(chip, CS4231P(REG));
204}
205
ba2375a4 206void snd_cs4236_ext_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char val)
1da177e4
LT		 207{
208 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
209 cs4231_outb(chip, CS4231P(REG), reg | (chip->image[CS4236_EXT_REG] & 0x01));
210 cs4231_outb(chip, CS4231P(REG), val);
211 chip->eimage[CS4236_REG(reg)] = val;
212#if 0
213 printk("ext out : reg = 0x%x, val = 0x%x\n", reg, val);
214#endif
215}
216
ba2375a4 217unsigned char snd_cs4236_ext_in(struct snd_cs4231 *chip, unsigned char reg)
1da177e4
LT		 218{
219 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
220 cs4231_outb(chip, CS4231P(REG), reg | (chip->image[CS4236_EXT_REG] & 0x01));
221#if 1
222 return cs4231_inb(chip, CS4231P(REG));
223#else
224 {
225 unsigned char res;
226 res = cs4231_inb(chip, CS4231P(REG));
227 printk("ext in : reg = 0x%x, val = 0x%x\n", reg, res);
228 return res;
229 }
230#endif
231}
232
233#if 0
234
ba2375a4 235static void snd_cs4231_debug(struct snd_cs4231 *chip)
1da177e4
LT		 236{
237 printk("CS4231 REGS: INDEX = 0x%02x ", cs4231_inb(chip, CS4231P(REGSEL)));
238 printk(" STATUS = 0x%02x\n", cs4231_inb(chip, CS4231P(STATUS)));
239 printk(" 0x00: left input = 0x%02x ", snd_cs4231_in(chip, 0x00));
240 printk(" 0x10: alt 1 (CFIG 2) = 0x%02x\n", snd_cs4231_in(chip, 0x10));
241 printk(" 0x01: right input = 0x%02x ", snd_cs4231_in(chip, 0x01));
242 printk(" 0x11: alt 2 (CFIG 3) = 0x%02x\n", snd_cs4231_in(chip, 0x11));
243 printk(" 0x02: GF1 left input = 0x%02x ", snd_cs4231_in(chip, 0x02));
244 printk(" 0x12: left line in = 0x%02x\n", snd_cs4231_in(chip, 0x12));
245 printk(" 0x03: GF1 right input = 0x%02x ", snd_cs4231_in(chip, 0x03));
246 printk(" 0x13: right line in = 0x%02x\n", snd_cs4231_in(chip, 0x13));
247 printk(" 0x04: CD left input = 0x%02x ", snd_cs4231_in(chip, 0x04));
248 printk(" 0x14: timer low = 0x%02x\n", snd_cs4231_in(chip, 0x14));
249 printk(" 0x05: CD right input = 0x%02x ", snd_cs4231_in(chip, 0x05));
250 printk(" 0x15: timer high = 0x%02x\n", snd_cs4231_in(chip, 0x15));
251 printk(" 0x06: left output = 0x%02x ", snd_cs4231_in(chip, 0x06));
252 printk(" 0x16: left MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x16));
253 printk(" 0x07: right output = 0x%02x ", snd_cs4231_in(chip, 0x07));
254 printk(" 0x17: right MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x17));
255 printk(" 0x08: playback format = 0x%02x ", snd_cs4231_in(chip, 0x08));
256 printk(" 0x18: IRQ status = 0x%02x\n", snd_cs4231_in(chip, 0x18));
257 printk(" 0x09: iface (CFIG 1) = 0x%02x ", snd_cs4231_in(chip, 0x09));
258 printk(" 0x19: left line out = 0x%02x\n", snd_cs4231_in(chip, 0x19));
259 printk(" 0x0a: pin control = 0x%02x ", snd_cs4231_in(chip, 0x0a));
260 printk(" 0x1a: mono control = 0x%02x\n", snd_cs4231_in(chip, 0x1a));
261 printk(" 0x0b: init & status = 0x%02x ", snd_cs4231_in(chip, 0x0b));
262 printk(" 0x1b: right line out = 0x%02x\n", snd_cs4231_in(chip, 0x1b));
263 printk(" 0x0c: revision & mode = 0x%02x ", snd_cs4231_in(chip, 0x0c));
264 printk(" 0x1c: record format = 0x%02x\n", snd_cs4231_in(chip, 0x1c));
265 printk(" 0x0d: loopback = 0x%02x ", snd_cs4231_in(chip, 0x0d));
266 printk(" 0x1d: var freq (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x1d));
267 printk(" 0x0e: ply upr count = 0x%02x ", snd_cs4231_in(chip, 0x0e));
268 printk(" 0x1e: ply lwr count = 0x%02x\n", snd_cs4231_in(chip, 0x1e));
269 printk(" 0x0f: rec upr count = 0x%02x ", snd_cs4231_in(chip, 0x0f));
270 printk(" 0x1f: rec lwr count = 0x%02x\n", snd_cs4231_in(chip, 0x1f));
271}
272
273#endif
274
275/*
276 * CS4231 detection / MCE routines
277 */
278
ba2375a4 279static void snd_cs4231_busy_wait(struct snd_cs4231 *chip)
1da177e4
LT		 280{
281 int timeout;
282
283 /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
284 for (timeout = 5; timeout > 0; timeout--)
285 cs4231_inb(chip, CS4231P(REGSEL));
286 /* end of cleanup sequence */
287 for (timeout = 250;
288 timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
289 timeout--)
290 udelay(10);
291}
292
ba2375a4 293void snd_cs4231_mce_up(struct snd_cs4231 *chip)
1da177e4
LT		 294{
295 unsigned long flags;
296 int timeout;
297
6c041b5e 298 snd_cs4231_wait(chip);
1da177e4
LT		 299#ifdef CONFIG_SND_DEBUG
300 if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
301 snd_printk("mce_up - auto calibration time out (0)\n");
302#endif
303 spin_lock_irqsave(&chip->reg_lock, flags);
304 chip->mce_bit |= CS4231_MCE;
305 timeout = cs4231_inb(chip, CS4231P(REGSEL));
306 if (timeout == 0x80)
307 snd_printk("mce_up [0x%lx]: serious init problem - codec still busy\n", chip->port);
308 if (!(timeout & CS4231_MCE))
309 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
310 spin_unlock_irqrestore(&chip->reg_lock, flags);
311}
312
ba2375a4 313void snd_cs4231_mce_down(struct snd_cs4231 *chip)
1da177e4
LT		 314{
315 unsigned long flags;
316 int timeout;
317
318 snd_cs4231_busy_wait(chip);
d44df2d0 319
1da177e4
LT		 320#ifdef CONFIG_SND_DEBUG
321 if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
322 snd_printk("mce_down [0x%lx] - auto calibration time out (0)\n", (long)CS4231P(REGSEL));
323#endif
324 spin_lock_irqsave(&chip->reg_lock, flags);
325 chip->mce_bit &= ~CS4231_MCE;
326 timeout = cs4231_inb(chip, CS4231P(REGSEL));
327 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
328 spin_unlock_irqrestore(&chip->reg_lock, flags);
329 if (timeout == 0x80)
330 snd_printk("mce_down [0x%lx]: serious init problem - codec still busy\n", chip->port);
331 if ((timeout & CS4231_MCE) == 0 ||
332 !(chip->hardware & (CS4231_HW_CS4231_MASK | CS4231_HW_CS4232_MASK))) {
333 return;
334 }
335 snd_cs4231_busy_wait(chip);
336
90cf9b85
RH		 337 /*
338 * Wait for (possible -- during init auto-calibration may not be set)
339 * calibration process to start. Needs upto 5 sample periods on AD1848
340 * which at the slowest possible rate of 5.5125 kHz means 907 us.
341 */
342 msleep(1);
d44df2d0
RH		 343
344 snd_printdd("(1) jiffies = %lu\n", jiffies);
345
23d4635e
KH		 346 /* check condition up to 250 ms */
347 timeout = msecs_to_jiffies(250);
348 while (snd_cs4231_in(chip, CS4231_TEST_INIT) &
349 CS4231_CALIB_IN_PROGRESS) {
350
351 if (timeout <= 0) {
352 snd_printk(KERN_ERR "mce_down - "
353 "auto calibration time out (2)\n");
1da177e4
LT		 354 return;
355 }
23d4635e 356 timeout = schedule_timeout(timeout);
1da177e4 357 }
d44df2d0
RH		 358
359 snd_printdd("(2) jiffies = %lu\n", jiffies);
360
23d4635e
KH		 361 /* check condition up to 100 ms */
362 timeout = msecs_to_jiffies(100);
1da177e4 363 while (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
23d4635e 364 if (timeout <= 0) {
1da177e4
LT		 365 snd_printk(KERN_ERR "mce_down - auto calibration time out (3)\n");
366 return;
367 }
23d4635e 368 timeout = schedule_timeout(timeout);
1da177e4 369 }
d44df2d0
RH		 370
371 snd_printdd("(3) jiffies = %lu\n", jiffies);
372 snd_printd("mce_down - exit = 0x%x\n", cs4231_inb(chip, CS4231P(REGSEL)));
1da177e4
LT		 373}
374
375static unsigned int snd_cs4231_get_count(unsigned char format, unsigned int size)
376{
377 switch (format & 0xe0) {
378 case CS4231_LINEAR_16:
379 case CS4231_LINEAR_16_BIG:
380 size >>= 1;
381 break;
382 case CS4231_ADPCM_16:
383 return size >> 2;
384 }
385 if (format & CS4231_STEREO)
386 size >>= 1;
387 return size;
388}
389
ba2375a4 390static int snd_cs4231_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 391 int cmd)
392{
ba2375a4 393 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 394 int result = 0;
395 unsigned int what;
ba2375a4 396 struct snd_pcm_substream *s;
1da177e4
LT		 397 int do_start;
398
399#if 0
400 printk("codec trigger!!! - what = %i, enable = %i, status = 0x%x\n", what, enable, cs4231_inb(chip, CS4231P(STATUS)));
401#endif
402
403 switch (cmd) {
404 case SNDRV_PCM_TRIGGER_START:
405 case SNDRV_PCM_TRIGGER_RESUME:
406 do_start = 1; break;
407 case SNDRV_PCM_TRIGGER_STOP:
408 case SNDRV_PCM_TRIGGER_SUSPEND:
409 do_start = 0; break;
410 default:
411 return -EINVAL;
412 }
413
414 what = 0;
ef991b95 415 snd_pcm_group_for_each_entry(s, substream) {
1da177e4
LT		 416 if (s == chip->playback_substream) {
417 what |= CS4231_PLAYBACK_ENABLE;
418 snd_pcm_trigger_done(s, substream);
419 } else if (s == chip->capture_substream) {
420 what |= CS4231_RECORD_ENABLE;
421 snd_pcm_trigger_done(s, substream);
422 }
423 }
424 spin_lock(&chip->reg_lock);
425 if (do_start) {
426 chip->image[CS4231_IFACE_CTRL] |= what;
427 if (chip->trigger)
428 chip->trigger(chip, what, 1);
429 } else {
430 chip->image[CS4231_IFACE_CTRL] &= ~what;
431 if (chip->trigger)
432 chip->trigger(chip, what, 0);
433 }
434 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
435 spin_unlock(&chip->reg_lock);
436#if 0
437 snd_cs4231_debug(chip);
438#endif
439 return result;
440}
441
442/*
443 * CODEC I/O
444 */
445
446static unsigned char snd_cs4231_get_rate(unsigned int rate)
447{
448 int i;
449
6c041b5e 450 for (i = 0; i < ARRAY_SIZE(rates); i++)
1da177e4
LT		 451 if (rate == rates[i])
452 return freq_bits[i];
453 // snd_BUG();
6c041b5e 454 return freq_bits[ARRAY_SIZE(rates) - 1];
1da177e4
LT		 455}
456
ba2375a4 457static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip,
1da177e4
LT		 458 int format,
459 int channels)
460{
461 unsigned char rformat;
462
463 rformat = CS4231_LINEAR_8;
464 switch (format) {
465 case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;
466 case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;
467 case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;
468 case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;
469 case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;
470 }
471 if (channels > 1)
472 rformat |= CS4231_STEREO;
473#if 0
474 snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode);
475#endif
476 return rformat;
477}
478
ba2375a4 479static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute)
1da177e4
LT		 480{
481 unsigned long flags;
482
483 mute = mute ? 1 : 0;
484 spin_lock_irqsave(&chip->reg_lock, flags);
485 if (chip->calibrate_mute == mute) {
486 spin_unlock_irqrestore(&chip->reg_lock, flags);
487 return;
488 }
489 if (!mute) {
490 snd_cs4231_dout(chip, CS4231_LEFT_INPUT, chip->image[CS4231_LEFT_INPUT]);
491 snd_cs4231_dout(chip, CS4231_RIGHT_INPUT, chip->image[CS4231_RIGHT_INPUT]);
492 snd_cs4231_dout(chip, CS4231_LOOPBACK, chip->image[CS4231_LOOPBACK]);
493 }
494 snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
495 snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
496 snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
497 snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
498 snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
499 snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT, mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
500 snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN, mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
501 snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN, mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
502 snd_cs4231_dout(chip, CS4231_MONO_CTRL, mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
503 if (chip->hardware == CS4231_HW_INTERWAVE) {
504 snd_cs4231_dout(chip, CS4231_LEFT_MIC_INPUT, mute ? 0x80 : chip->image[CS4231_LEFT_MIC_INPUT]);
505 snd_cs4231_dout(chip, CS4231_RIGHT_MIC_INPUT, mute ? 0x80 : chip->image[CS4231_RIGHT_MIC_INPUT]);
506 snd_cs4231_dout(chip, CS4231_LINE_LEFT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LINE_LEFT_OUTPUT]);
507 snd_cs4231_dout(chip, CS4231_LINE_RIGHT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LINE_RIGHT_OUTPUT]);
508 }
509 chip->calibrate_mute = mute;
510 spin_unlock_irqrestore(&chip->reg_lock, flags);
511}
512
ba2375a4
TI		 513static void snd_cs4231_playback_format(struct snd_cs4231 *chip,
514 struct snd_pcm_hw_params *params,
1da177e4
LT		 515 unsigned char pdfr)
516{
517 unsigned long flags;
518 int full_calib = 1;
519
8b7547f9 520 mutex_lock(&chip->mce_mutex);
1da177e4
LT		 521 snd_cs4231_calibrate_mute(chip, 1);
522 if (chip->hardware == CS4231_HW_CS4231A ||
523 (chip->hardware & CS4231_HW_CS4232_MASK)) {
524 spin_lock_irqsave(&chip->reg_lock, flags);
525 if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (pdfr & 0x0f)) { /* rate is same? */
526 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | 0x10);
527 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT] = pdfr);
528 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~0x10);
529 udelay(100); /* Fixes audible clicks at least on GUS MAX */
530 full_calib = 0;
531 }
532 spin_unlock_irqrestore(&chip->reg_lock, flags);
533 }
534 if (full_calib) {
535 snd_cs4231_mce_up(chip);
536 spin_lock_irqsave(&chip->reg_lock, flags);
537 if (chip->hardware != CS4231_HW_INTERWAVE && !chip->single_dma) {
538 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
539 (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
540 (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
541 pdfr);
542 } else {
543 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT] = pdfr);
544 }
545 spin_unlock_irqrestore(&chip->reg_lock, flags);
e2340465
PV		 546 if (chip->hardware == CS4231_HW_OPL3SA2)
547 udelay(100); /* this seems to help */
1da177e4
LT		 548 snd_cs4231_mce_down(chip);
549 }
550 snd_cs4231_calibrate_mute(chip, 0);
8b7547f9 551 mutex_unlock(&chip->mce_mutex);
1da177e4
LT		 552}
553
ba2375a4
TI		 554static void snd_cs4231_capture_format(struct snd_cs4231 *chip,
555 struct snd_pcm_hw_params *params,
1da177e4
LT		 556 unsigned char cdfr)
557{
558 unsigned long flags;
559 int full_calib = 1;
560
8b7547f9 561 mutex_lock(&chip->mce_mutex);
1da177e4
LT		 562 snd_cs4231_calibrate_mute(chip, 1);
563 if (chip->hardware == CS4231_HW_CS4231A ||
564 (chip->hardware & CS4231_HW_CS4232_MASK)) {
565 spin_lock_irqsave(&chip->reg_lock, flags);
566 if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (cdfr & 0x0f) || /* rate is same? */
567 (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
568 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | 0x20);
569 snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT] = cdfr);
570 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~0x20);
571 full_calib = 0;
572 }
573 spin_unlock_irqrestore(&chip->reg_lock, flags);
574 }
575 if (full_calib) {
576 snd_cs4231_mce_up(chip);
577 spin_lock_irqsave(&chip->reg_lock, flags);
578 if (chip->hardware != CS4231_HW_INTERWAVE) {
579 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
580 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
581 ((chip->single_dma ? cdfr : chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
582 (cdfr & 0x0f));
583 spin_unlock_irqrestore(&chip->reg_lock, flags);
584 snd_cs4231_mce_down(chip);
585 snd_cs4231_mce_up(chip);
586 spin_lock_irqsave(&chip->reg_lock, flags);
587 }
588 }
589 snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
590 spin_unlock_irqrestore(&chip->reg_lock, flags);
591 snd_cs4231_mce_down(chip);
592 }
593 snd_cs4231_calibrate_mute(chip, 0);
8b7547f9 594 mutex_unlock(&chip->mce_mutex);
1da177e4
LT		 595}
596
597/*
598 * Timer interface
599 */
600
ba2375a4 601static unsigned long snd_cs4231_timer_resolution(struct snd_timer * timer)
1da177e4 602{
ba2375a4 603 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 604 if (chip->hardware & CS4231_HW_CS4236B_MASK)
605 return 14467;
606 else
607 return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
608}
609
ba2375a4 610static int snd_cs4231_timer_start(struct snd_timer * timer)
1da177e4
LT		 611{
612 unsigned long flags;
613 unsigned int ticks;
ba2375a4 614 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 615 spin_lock_irqsave(&chip->reg_lock, flags);
616 ticks = timer->sticks;
617 if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
618 (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
619 (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
620 snd_cs4231_out(chip, CS4231_TIMER_HIGH, chip->image[CS4231_TIMER_HIGH] = (unsigned char) (ticks >> 8));
621 snd_cs4231_out(chip, CS4231_TIMER_LOW, chip->image[CS4231_TIMER_LOW] = (unsigned char) ticks);
622 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | CS4231_TIMER_ENABLE);
623 }
624 spin_unlock_irqrestore(&chip->reg_lock, flags);
625 return 0;
626}
627
ba2375a4 628static int snd_cs4231_timer_stop(struct snd_timer * timer)
1da177e4
LT		 629{
630 unsigned long flags;
ba2375a4 631 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 632 spin_lock_irqsave(&chip->reg_lock, flags);
633 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE);
634 spin_unlock_irqrestore(&chip->reg_lock, flags);
635 return 0;
636}
637
ba2375a4 638static void snd_cs4231_init(struct snd_cs4231 *chip)
1da177e4
LT		 639{
640 unsigned long flags;
641
642 snd_cs4231_mce_down(chip);
643
644#ifdef SNDRV_DEBUG_MCE
645 snd_printk("init: (1)\n");
646#endif
647 snd_cs4231_mce_up(chip);
648 spin_lock_irqsave(&chip->reg_lock, flags);
649 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
650 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO |
651 CS4231_CALIB_MODE);
652 chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
653 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
654 spin_unlock_irqrestore(&chip->reg_lock, flags);
655 snd_cs4231_mce_down(chip);
656
657#ifdef SNDRV_DEBUG_MCE
658 snd_printk("init: (2)\n");
659#endif
660
661 snd_cs4231_mce_up(chip);
662 spin_lock_irqsave(&chip->reg_lock, flags);
663 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
664 spin_unlock_irqrestore(&chip->reg_lock, flags);
665 snd_cs4231_mce_down(chip);
666
667#ifdef SNDRV_DEBUG_MCE
668 snd_printk("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]);
669#endif
670
671 spin_lock_irqsave(&chip->reg_lock, flags);
672 snd_cs4231_out(chip, CS4231_ALT_FEATURE_2, chip->image[CS4231_ALT_FEATURE_2]);
673 spin_unlock_irqrestore(&chip->reg_lock, flags);
674
675 snd_cs4231_mce_up(chip);
676 spin_lock_irqsave(&chip->reg_lock, flags);
677 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT]);
678 spin_unlock_irqrestore(&chip->reg_lock, flags);
679 snd_cs4231_mce_down(chip);
680
681#ifdef SNDRV_DEBUG_MCE
682 snd_printk("init: (4)\n");
683#endif
684
685 snd_cs4231_mce_up(chip);
686 spin_lock_irqsave(&chip->reg_lock, flags);
687 snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
688 spin_unlock_irqrestore(&chip->reg_lock, flags);
689 snd_cs4231_mce_down(chip);
690
691#ifdef SNDRV_DEBUG_MCE
692 snd_printk("init: (5)\n");
693#endif
694}
695
ba2375a4 696static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode)
1da177e4
LT		 697{
698 unsigned long flags;
699
8b7547f9 700 mutex_lock(&chip->open_mutex);
1da177e4
LT		 701 if ((chip->mode & mode) ||
702 ((chip->mode & CS4231_MODE_OPEN) && chip->single_dma)) {
8b7547f9 703 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 704 return -EAGAIN;
705 }
706 if (chip->mode & CS4231_MODE_OPEN) {
707 chip->mode |= mode;
8b7547f9 708 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 709 return 0;
710 }
711 /* ok. now enable and ack CODEC IRQ */
712 spin_lock_irqsave(&chip->reg_lock, flags);
713 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
714 CS4231_RECORD_IRQ |
715 CS4231_TIMER_IRQ);
716 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
717 cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
718 cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
719 chip->image[CS4231_PIN_CTRL] |= CS4231_IRQ_ENABLE;
720 snd_cs4231_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
721 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
722 CS4231_RECORD_IRQ |
723 CS4231_TIMER_IRQ);
724 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
725 spin_unlock_irqrestore(&chip->reg_lock, flags);
726
727 chip->mode = mode;
8b7547f9 728 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 729 return 0;
730}
731
ba2375a4 732static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
1da177e4
LT		 733{
734 unsigned long flags;
735
8b7547f9 736 mutex_lock(&chip->open_mutex);
1da177e4
LT		 737 chip->mode &= ~mode;
738 if (chip->mode & CS4231_MODE_OPEN) {
8b7547f9 739 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 740 return;
741 }
742 snd_cs4231_calibrate_mute(chip, 1);
743
744 /* disable IRQ */
745 spin_lock_irqsave(&chip->reg_lock, flags);
746 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
747 cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
748 cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
749 chip->image[CS4231_PIN_CTRL] &= ~CS4231_IRQ_ENABLE;
750 snd_cs4231_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
751
752 /* now disable record & playback */
753
754 if (chip->image[CS4231_IFACE_CTRL] & (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
755 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
756 spin_unlock_irqrestore(&chip->reg_lock, flags);
757 snd_cs4231_mce_up(chip);
758 spin_lock_irqsave(&chip->reg_lock, flags);
759 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
760 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
761 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
762 spin_unlock_irqrestore(&chip->reg_lock, flags);
763 snd_cs4231_mce_down(chip);
764 spin_lock_irqsave(&chip->reg_lock, flags);
765 }
766
767 /* clear IRQ again */
768 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
769 cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
770 cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
771 spin_unlock_irqrestore(&chip->reg_lock, flags);
772
773 snd_cs4231_calibrate_mute(chip, 0);
774
775 chip->mode = 0;
8b7547f9 776 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 777}
778
779/*
780 * timer open/close
781 */
782
ba2375a4 783static int snd_cs4231_timer_open(struct snd_timer * timer)
1da177e4 784{
ba2375a4 785 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 786 snd_cs4231_open(chip, CS4231_MODE_TIMER);
787 return 0;
788}
789
ba2375a4 790static int snd_cs4231_timer_close(struct snd_timer * timer)
1da177e4 791{
ba2375a4 792 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 793 snd_cs4231_close(chip, CS4231_MODE_TIMER);
794 return 0;
795}
796
ba2375a4 797static struct snd_timer_hardware snd_cs4231_timer_table =
1da177e4
LT		 798{
799 .flags = SNDRV_TIMER_HW_AUTO,
800 .resolution = 9945,
801 .ticks = 65535,
802 .open = snd_cs4231_timer_open,
803 .close = snd_cs4231_timer_close,
804 .c_resolution = snd_cs4231_timer_resolution,
805 .start = snd_cs4231_timer_start,
806 .stop = snd_cs4231_timer_stop,
807};
808
809/*
810 * ok.. exported functions..
811 */
812
ba2375a4
TI		 813static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream,
814 struct snd_pcm_hw_params *hw_params)
1da177e4 815{
ba2375a4 816 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 817 unsigned char new_pdfr;
818 int err;
819
820 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
821 return err;
822 new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params), params_channels(hw_params)) |
823 snd_cs4231_get_rate(params_rate(hw_params));
824 chip->set_playback_format(chip, hw_params, new_pdfr);
825 return 0;
826}
827
ba2375a4 828static int snd_cs4231_playback_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 829{
830 return snd_pcm_lib_free_pages(substream);
831}
832
ba2375a4 833static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 834{
ba2375a4
TI		 835 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
836 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 837 unsigned long flags;
838 unsigned int size = snd_pcm_lib_buffer_bytes(substream);
839 unsigned int count = snd_pcm_lib_period_bytes(substream);
840
841 spin_lock_irqsave(&chip->reg_lock, flags);
842 chip->p_dma_size = size;
843 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO);
844 snd_dma_program(chip->dma1, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
845 count = snd_cs4231_get_count(chip->image[CS4231_PLAYBK_FORMAT], count) - 1;
846 snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
847 snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
848 spin_unlock_irqrestore(&chip->reg_lock, flags);
849#if 0
850 snd_cs4231_debug(chip);
851#endif
852 return 0;
853}
1da177e4 854
ba2375a4
TI		 855static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream,
856 struct snd_pcm_hw_params *hw_params)
1da177e4 857{
ba2375a4 858 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 859 unsigned char new_cdfr;
860 int err;
861
862 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
863 return err;
864 new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params), params_channels(hw_params)) |
865 snd_cs4231_get_rate(params_rate(hw_params));
866 chip->set_capture_format(chip, hw_params, new_cdfr);
867 return 0;
868}
869
ba2375a4 870static int snd_cs4231_capture_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 871{
872 return snd_pcm_lib_free_pages(substream);
873}
874
ba2375a4 875static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 876{
ba2375a4
TI		 877 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
878 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 879 unsigned long flags;
880 unsigned int size = snd_pcm_lib_buffer_bytes(substream);
881 unsigned int count = snd_pcm_lib_period_bytes(substream);
882
883 spin_lock_irqsave(&chip->reg_lock, flags);
884 chip->c_dma_size = size;
885 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
886 snd_dma_program(chip->dma2, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
887 count = snd_cs4231_get_count(chip->image[CS4231_REC_FORMAT], count) - 1;
888 if (chip->single_dma && chip->hardware != CS4231_HW_INTERWAVE) {
889 snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
890 snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
891 } else {
892 snd_cs4231_out(chip, CS4231_REC_LWR_CNT, (unsigned char) count);
893 snd_cs4231_out(chip, CS4231_REC_UPR_CNT, (unsigned char) (count >> 8));
894 }
895 spin_unlock_irqrestore(&chip->reg_lock, flags);
896 return 0;
897}
1da177e4 898
ba2375a4 899static void snd_cs4231_overrange(struct snd_cs4231 *chip)
1da177e4
LT		 900{
901 unsigned long flags;
902 unsigned char res;
903
904 spin_lock_irqsave(&chip->reg_lock, flags);
905 res = snd_cs4231_in(chip, CS4231_TEST_INIT);
906 spin_unlock_irqrestore(&chip->reg_lock, flags);
907 if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
908 chip->capture_substream->runtime->overrange++;
909}
910
7d12e780 911irqreturn_t snd_cs4231_interrupt(int irq, void *dev_id)
1da177e4 912{
ba2375a4 913 struct snd_cs4231 *chip = dev_id;
1da177e4
LT		 914 unsigned char status;
915
916 status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
917 if (status & CS4231_TIMER_IRQ) {
918 if (chip->timer)
919 snd_timer_interrupt(chip->timer, chip->timer->sticks);
920 }
921 if (chip->single_dma && chip->hardware != CS4231_HW_INTERWAVE) {
922 if (status & CS4231_PLAYBACK_IRQ) {
923 if (chip->mode & CS4231_MODE_PLAY) {
924 if (chip->playback_substream)
925 snd_pcm_period_elapsed(chip->playback_substream);
926 }
927 if (chip->mode & CS4231_MODE_RECORD) {
928 if (chip->capture_substream) {
929 snd_cs4231_overrange(chip);
930 snd_pcm_period_elapsed(chip->capture_substream);
931 }
932 }
933 }
934 } else {
935 if (status & CS4231_PLAYBACK_IRQ) {
936 if (chip->playback_substream)
937 snd_pcm_period_elapsed(chip->playback_substream);
938 }
939 if (status & CS4231_RECORD_IRQ) {
940 if (chip->capture_substream) {
941 snd_cs4231_overrange(chip);
942 snd_pcm_period_elapsed(chip->capture_substream);
943 }
944 }
945 }
946
947 spin_lock(&chip->reg_lock);
948 snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
949 spin_unlock(&chip->reg_lock);
950 return IRQ_HANDLED;
951}
952
ba2375a4 953static snd_pcm_uframes_t snd_cs4231_playback_pointer(struct snd_pcm_substream *substream)
1da177e4 954{
ba2375a4 955 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 956 size_t ptr;
957
958 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
959 return 0;
960 ptr = snd_dma_pointer(chip->dma1, chip->p_dma_size);
961 return bytes_to_frames(substream->runtime, ptr);
962}
963
ba2375a4 964static snd_pcm_uframes_t snd_cs4231_capture_pointer(struct snd_pcm_substream *substream)
1da177e4 965{
ba2375a4 966 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 967 size_t ptr;
968
969 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
970 return 0;
971 ptr = snd_dma_pointer(chip->dma2, chip->c_dma_size);
972 return bytes_to_frames(substream->runtime, ptr);
973}
1da177e4
LT		 974
975/*
976
977 */
978
ba2375a4 979static int snd_cs4231_probe(struct snd_cs4231 *chip)
1da177e4
LT		 980{
981 unsigned long flags;
982 int i, id, rev;
983 unsigned char *ptr;
984 unsigned int hw;
985
986#if 0
987 snd_cs4231_debug(chip);
988#endif
989 id = 0;
990 for (i = 0; i < 50; i++) {
991 mb();
992 if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
993 udelay(2000);
994 else {
995 spin_lock_irqsave(&chip->reg_lock, flags);
996 snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
997 id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
998 spin_unlock_irqrestore(&chip->reg_lock, flags);
999 if (id == 0x0a)
1000 break; /* this is valid value */
1001 }
1002 }
1003 snd_printdd("cs4231: port = 0x%lx, id = 0x%x\n", chip->port, id);
1004 if (id != 0x0a)
1005 return -ENODEV; /* no valid device found */
1006
1007 if (((hw = chip->hardware) & CS4231_HW_TYPE_MASK) == CS4231_HW_DETECT) {
1008 rev = snd_cs4231_in(chip, CS4231_VERSION) & 0xe7;
1009 snd_printdd("CS4231: VERSION (I25) = 0x%x\n", rev);
1010 if (rev == 0x80) {
1011 unsigned char tmp = snd_cs4231_in(chip, 23);
1012 snd_cs4231_out(chip, 23, ~tmp);
1013 if (snd_cs4231_in(chip, 23) != tmp)
1014 chip->hardware = CS4231_HW_AD1845;
1015 else
1016 chip->hardware = CS4231_HW_CS4231;
1017 } else if (rev == 0xa0) {
1018 chip->hardware = CS4231_HW_CS4231A;
1019 } else if (rev == 0xa2) {
1020 chip->hardware = CS4231_HW_CS4232;
1021 } else if (rev == 0xb2) {
1022 chip->hardware = CS4231_HW_CS4232A;
1023 } else if (rev == 0x83) {
1024 chip->hardware = CS4231_HW_CS4236;
1025 } else if (rev == 0x03) {
1026 chip->hardware = CS4231_HW_CS4236B;
1027 } else {
1028 snd_printk("unknown CS chip with version 0x%x\n", rev);
1029 return -ENODEV; /* unknown CS4231 chip? */
1030 }
1031 }
1032 spin_lock_irqsave(&chip->reg_lock, flags);
1033 cs4231_inb(chip, CS4231P(STATUS)); /* clear any pendings IRQ */
1034 cs4231_outb(chip, CS4231P(STATUS), 0);
1035 mb();
1036 spin_unlock_irqrestore(&chip->reg_lock, flags);
1037
1038 chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
1039 switch (chip->hardware) {
1040 case CS4231_HW_INTERWAVE:
1041 chip->image[CS4231_MISC_INFO] = CS4231_IW_MODE3;
1042 break;
1043 case CS4231_HW_CS4235:
1044 case CS4231_HW_CS4236B:
1045 case CS4231_HW_CS4237B:
1046 case CS4231_HW_CS4238B:
1047 case CS4231_HW_CS4239:
1048 if (hw == CS4231_HW_DETECT3)
1049 chip->image[CS4231_MISC_INFO] = CS4231_4236_MODE3;
1050 else
1051 chip->hardware = CS4231_HW_CS4236;
1052 break;
1053 }
1054
1055 chip->image[CS4231_IFACE_CTRL] =
1056 (chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA) |
1057 (chip->single_dma ? CS4231_SINGLE_DMA : 0);
1058 chip->image[CS4231_ALT_FEATURE_1] = 0x80;
1059 chip->image[CS4231_ALT_FEATURE_2] = chip->hardware == CS4231_HW_INTERWAVE ? 0xc2 : 0x01;
1060 ptr = (unsigned char *) &chip->image;
1061 snd_cs4231_mce_down(chip);
1062 spin_lock_irqsave(&chip->reg_lock, flags);
1063 for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
1064 snd_cs4231_out(chip, i, *ptr++);
1065 spin_unlock_irqrestore(&chip->reg_lock, flags);
1066 snd_cs4231_mce_up(chip);
1067 snd_cs4231_mce_down(chip);
1068
1069 mdelay(2);
1070
1071 /* ok.. try check hardware version for CS4236+ chips */
1072 if ((hw & CS4231_HW_TYPE_MASK) == CS4231_HW_DETECT) {
1073 if (chip->hardware == CS4231_HW_CS4236B) {
1074 rev = snd_cs4236_ext_in(chip, CS4236_VERSION);
1075 snd_cs4236_ext_out(chip, CS4236_VERSION, 0xff);
1076 id = snd_cs4236_ext_in(chip, CS4236_VERSION);
1077 snd_cs4236_ext_out(chip, CS4236_VERSION, rev);
1078 snd_printdd("CS4231: ext version; rev = 0x%x, id = 0x%x\n", rev, id);
1079 if ((id & 0x1f) == 0x1d) { /* CS4235 */
1080 chip->hardware = CS4231_HW_CS4235;
1081 switch (id >> 5) {
1082 case 4:
1083 case 5:
1084 case 6:
1085 break;
1086 default:
1087 snd_printk("unknown CS4235 chip (enhanced version = 0x%x)\n", id);
1088 }
1089 } else if ((id & 0x1f) == 0x0b) { /* CS4236/B */
1090 switch (id >> 5) {
1091 case 4:
1092 case 5:
1093 case 6:
1094 case 7:
1095 chip->hardware = CS4231_HW_CS4236B;
1096 break;
1097 default:
1098 snd_printk("unknown CS4236 chip (enhanced version = 0x%x)\n", id);
1099 }
1100 } else if ((id & 0x1f) == 0x08) { /* CS4237B */
1101 chip->hardware = CS4231_HW_CS4237B;
1102 switch (id >> 5) {
1103 case 4:
1104 case 5:
1105 case 6:
1106 case 7:
1107 break;
1108 default:
1109 snd_printk("unknown CS4237B chip (enhanced version = 0x%x)\n", id);
1110 }
1111 } else if ((id & 0x1f) == 0x09) { /* CS4238B */
1112 chip->hardware = CS4231_HW_CS4238B;
1113 switch (id >> 5) {
1114 case 5:
1115 case 6:
1116 case 7:
1117 break;
1118 default:
1119 snd_printk("unknown CS4238B chip (enhanced version = 0x%x)\n", id);
1120 }
1121 } else if ((id & 0x1f) == 0x1e) { /* CS4239 */
1122 chip->hardware = CS4231_HW_CS4239;
1123 switch (id >> 5) {
1124 case 4:
1125 case 5:
1126 case 6:
1127 break;
1128 default:
1129 snd_printk("unknown CS4239 chip (enhanced version = 0x%x)\n", id);
1130 }
1131 } else {
1132 snd_printk("unknown CS4236/CS423xB chip (enhanced version = 0x%x)\n", id);
1133 }
1134 }
1135 }
1136 return 0; /* all things are ok.. */
1137}
1138
1139/*
1140
1141 */
1142
ba2375a4 1143static struct snd_pcm_hardware snd_cs4231_playback =
1da177e4
LT		 1144{
1145 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1146 SNDRV_PCM_INFO_MMAP_VALID |
1147 SNDRV_PCM_INFO_RESUME |
1148 SNDRV_PCM_INFO_SYNC_START),
1149 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
1150 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
1151 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1152 .rate_min = 5510,
1153 .rate_max = 48000,
1154 .channels_min = 1,
1155 .channels_max = 2,
1156 .buffer_bytes_max = (128*1024),
1157 .period_bytes_min = 64,
1158 .period_bytes_max = (128*1024),
1159 .periods_min = 1,
1160 .periods_max = 1024,
1161 .fifo_size = 0,
1162};
1163
ba2375a4 1164static struct snd_pcm_hardware snd_cs4231_capture =
1da177e4
LT		 1165{
1166 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1167 SNDRV_PCM_INFO_MMAP_VALID |
1168 SNDRV_PCM_INFO_RESUME |
1169 SNDRV_PCM_INFO_SYNC_START),
1170 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
1171 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
1172 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1173 .rate_min = 5510,
1174 .rate_max = 48000,
1175 .channels_min = 1,
1176 .channels_max = 2,
1177 .buffer_bytes_max = (128*1024),
1178 .period_bytes_min = 64,
1179 .period_bytes_max = (128*1024),
1180 .periods_min = 1,
1181 .periods_max = 1024,
1182 .fifo_size = 0,
1183};
1184
1185/*
1186
1187 */
1188
ba2375a4 1189static int snd_cs4231_playback_open(struct snd_pcm_substream *substream)
1da177e4 1190{
ba2375a4
TI		 1191 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1192 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1193 int err;
1194
1195 runtime->hw = snd_cs4231_playback;
1196
1197 /* hardware bug in InterWave chipset */
1198 if (chip->hardware == CS4231_HW_INTERWAVE && chip->dma1 > 3)
1199 runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_MU_LAW;
1200
1201 /* hardware limitation of cheap chips */
1202 if (chip->hardware == CS4231_HW_CS4235 ||
1203 chip->hardware == CS4231_HW_CS4239)
1204 runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
1205
1da177e4
LT		 1206 snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.buffer_bytes_max);
1207 snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.period_bytes_max);
1208
1209 if (chip->claim_dma) {
1210 if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma1)) < 0)
1211 return err;
1212 }
1da177e4
LT		 1213
1214 if ((err = snd_cs4231_open(chip, CS4231_MODE_PLAY)) < 0) {
1da177e4
LT		 1215 if (chip->release_dma)
1216 chip->release_dma(chip, chip->dma_private_data, chip->dma1);
1da177e4
LT		 1217 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1218 return err;
1219 }
1220 chip->playback_substream = substream;
1da177e4
LT		 1221 snd_pcm_set_sync(substream);
1222 chip->rate_constraint(runtime);
1223 return 0;
1224}
1225
ba2375a4 1226static int snd_cs4231_capture_open(struct snd_pcm_substream *substream)
1da177e4 1227{
ba2375a4
TI		 1228 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1229 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1230 int err;
1231
1232 runtime->hw = snd_cs4231_capture;
1233
1234 /* hardware limitation of cheap chips */
1235 if (chip->hardware == CS4231_HW_CS4235 ||
1236 chip->hardware == CS4231_HW_CS4239)
1237 runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
1238
1da177e4
LT		 1239 snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.buffer_bytes_max);
1240 snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.period_bytes_max);
1241
1242 if (chip->claim_dma) {
1243 if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma2)) < 0)
1244 return err;
1245 }
1da177e4
LT		 1246
1247 if ((err = snd_cs4231_open(chip, CS4231_MODE_RECORD)) < 0) {
1da177e4
LT		 1248 if (chip->release_dma)
1249 chip->release_dma(chip, chip->dma_private_data, chip->dma2);
1da177e4
LT		 1250 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1251 return err;
1252 }
1253 chip->capture_substream = substream;
1da177e4
LT		 1254 snd_pcm_set_sync(substream);
1255 chip->rate_constraint(runtime);
1256 return 0;
1257}
1258
ba2375a4 1259static int snd_cs4231_playback_close(struct snd_pcm_substream *substream)
1da177e4 1260{
ba2375a4 1261 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1262
1263 chip->playback_substream = NULL;
1264 snd_cs4231_close(chip, CS4231_MODE_PLAY);
1265 return 0;
1266}
1267
ba2375a4 1268static int snd_cs4231_capture_close(struct snd_pcm_substream *substream)
1da177e4 1269{
ba2375a4 1270 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1271
1272 chip->capture_substream = NULL;
1273 snd_cs4231_close(chip, CS4231_MODE_RECORD);
1274 return 0;
1275}
1276
1277#ifdef CONFIG_PM
1278
1279/* lowlevel suspend callback for CS4231 */
ba2375a4 1280static void snd_cs4231_suspend(struct snd_cs4231 *chip)
1da177e4
LT		 1281{
1282 int reg;
1283 unsigned long flags;
1284
7bb35e20 1285 snd_pcm_suspend_all(chip->pcm);
1da177e4
LT		 1286 spin_lock_irqsave(&chip->reg_lock, flags);
1287 for (reg = 0; reg < 32; reg++)
1288 chip->image[reg] = snd_cs4231_in(chip, reg);
1289 spin_unlock_irqrestore(&chip->reg_lock, flags);
1290}
1291
1292/* lowlevel resume callback for CS4231 */
ba2375a4 1293static void snd_cs4231_resume(struct snd_cs4231 *chip)
1da177e4
LT		 1294{
1295 int reg;
1296 unsigned long flags;
a2c855bb 1297 /* int timeout; */
1da177e4
LT		 1298
1299 snd_cs4231_mce_up(chip);
1300 spin_lock_irqsave(&chip->reg_lock, flags);
1301 for (reg = 0; reg < 32; reg++) {
1302 switch (reg) {
1303 case CS4231_VERSION:
1304 break;
1305 default:
1306 snd_cs4231_out(chip, reg, chip->image[reg]);
1307 break;
1308 }
1309 }
1310 spin_unlock_irqrestore(&chip->reg_lock, flags);
fa55f837 1311#if 1
1da177e4
LT		 1312 snd_cs4231_mce_down(chip);
1313#else
1314 /* The following is a workaround to avoid freeze after resume on TP600E.
1315 This is the first half of copy of snd_cs4231_mce_down(), but doesn't
1316 include rescheduling. -- iwai
1317 */
1318 snd_cs4231_busy_wait(chip);
1319 spin_lock_irqsave(&chip->reg_lock, flags);
1320 chip->mce_bit &= ~CS4231_MCE;
1321 timeout = cs4231_inb(chip, CS4231P(REGSEL));
1322 cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
1323 spin_unlock_irqrestore(&chip->reg_lock, flags);
1324 if (timeout == 0x80)
1325 snd_printk("down [0x%lx]: serious init problem - codec still busy\n", chip->port);
1326 if ((timeout & CS4231_MCE) == 0 ||
1327 !(chip->hardware & (CS4231_HW_CS4231_MASK | CS4231_HW_CS4232_MASK))) {
1328 return;
1329 }
1330 snd_cs4231_busy_wait(chip);
1331#endif
1332}
1da177e4
LT		 1333#endif /* CONFIG_PM */
1334
ba2375a4 1335static int snd_cs4231_free(struct snd_cs4231 *chip)
1da177e4 1336{
b1d5776d
TI		 1337 release_and_free_resource(chip->res_port);
1338 release_and_free_resource(chip->res_cport);
1da177e4
LT		 1339 if (chip->irq >= 0) {
1340 disable_irq(chip->irq);
1341 if (!(chip->hwshare & CS4231_HWSHARE_IRQ))
1342 free_irq(chip->irq, (void *) chip);
1343 }
1344 if (!(chip->hwshare & CS4231_HWSHARE_DMA1) && chip->dma1 >= 0) {
1345 snd_dma_disable(chip->dma1);
1346 free_dma(chip->dma1);
1347 }
1348 if (!(chip->hwshare & CS4231_HWSHARE_DMA2) && chip->dma2 >= 0 && chip->dma2 != chip->dma1) {
1349 snd_dma_disable(chip->dma2);
1350 free_dma(chip->dma2);
1351 }
1352 if (chip->timer)
1353 snd_device_free(chip->card, chip->timer);
1354 kfree(chip);
1355 return 0;
1356}
1357
ba2375a4 1358static int snd_cs4231_dev_free(struct snd_device *device)
1da177e4 1359{
ba2375a4 1360 struct snd_cs4231 *chip = device->device_data;
1da177e4
LT		 1361 return snd_cs4231_free(chip);
1362}
1363
ba2375a4 1364const char *snd_cs4231_chip_id(struct snd_cs4231 *chip)
1da177e4
LT		 1365{
1366 switch (chip->hardware) {
1367 case CS4231_HW_CS4231: return "CS4231";
1368 case CS4231_HW_CS4231A: return "CS4231A";
1369 case CS4231_HW_CS4232: return "CS4232";
1370 case CS4231_HW_CS4232A: return "CS4232A";
1371 case CS4231_HW_CS4235: return "CS4235";
1372 case CS4231_HW_CS4236: return "CS4236";
1373 case CS4231_HW_CS4236B: return "CS4236B";
1374 case CS4231_HW_CS4237B: return "CS4237B";
1375 case CS4231_HW_CS4238B: return "CS4238B";
1376 case CS4231_HW_CS4239: return "CS4239";
1377 case CS4231_HW_INTERWAVE: return "AMD InterWave";
1378 case CS4231_HW_OPL3SA2: return chip->card->shortname;
1379 case CS4231_HW_AD1845: return "AD1845";
1380 default: return "???";
1381 }
1382}
1383
ba2375a4 1384static int snd_cs4231_new(struct snd_card *card,
1da177e4
LT		 1385 unsigned short hardware,
1386 unsigned short hwshare,
ba2375a4 1387 struct snd_cs4231 ** rchip)
1da177e4 1388{
ba2375a4 1389 struct snd_cs4231 *chip;
1da177e4
LT		 1390
1391 *rchip = NULL;
9e76a76e 1392 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 1393 if (chip == NULL)
1394 return -ENOMEM;
1395 chip->hardware = hardware;
1396 chip->hwshare = hwshare;
1397
1398 spin_lock_init(&chip->reg_lock);
8b7547f9
IM		 1399 mutex_init(&chip->mce_mutex);
1400 mutex_init(&chip->open_mutex);
1da177e4
LT		 1401 chip->card = card;
1402 chip->rate_constraint = snd_cs4231_xrate;
1403 chip->set_playback_format = snd_cs4231_playback_format;
1404 chip->set_capture_format = snd_cs4231_capture_format;
1405 memcpy(&chip->image, &snd_cs4231_original_image, sizeof(snd_cs4231_original_image));
1406
1407 *rchip = chip;
1408 return 0;
1409}
1410
ba2375a4 1411int snd_cs4231_create(struct snd_card *card,
1da177e4
LT		 1412 unsigned long port,
1413 unsigned long cport,
1414 int irq, int dma1, int dma2,
1415 unsigned short hardware,
1416 unsigned short hwshare,
ba2375a4 1417 struct snd_cs4231 ** rchip)
1da177e4 1418{
ba2375a4 1419 static struct snd_device_ops ops = {
1da177e4
LT		 1420 .dev_free = snd_cs4231_dev_free,
1421 };
ba2375a4 1422 struct snd_cs4231 *chip;
1da177e4
LT		 1423 int err;
1424
1425 err = snd_cs4231_new(card, hardware, hwshare, &chip);
1426 if (err < 0)
1427 return err;
1428
1429 chip->irq = -1;
1430 chip->dma1 = -1;
1431 chip->dma2 = -1;
1432
1433 if ((chip->res_port = request_region(port, 4, "CS4231")) == NULL) {
1434 snd_printk(KERN_ERR "cs4231: can't grab port 0x%lx\n", port);
1435 snd_cs4231_free(chip);
1436 return -EBUSY;
1437 }
1438 chip->port = port;
1439 if ((long)cport >= 0 && (chip->res_cport = request_region(cport, 8, "CS4232 Control")) == NULL) {
1440 snd_printk(KERN_ERR "cs4231: can't grab control port 0x%lx\n", cport);
1441 snd_cs4231_free(chip);
1442 return -ENODEV;
1443 }
1444 chip->cport = cport;
65ca68b3 1445 if (!(hwshare & CS4231_HWSHARE_IRQ) && request_irq(irq, snd_cs4231_interrupt, IRQF_DISABLED, "CS4231", (void *) chip)) {
1da177e4
LT		 1446 snd_printk(KERN_ERR "cs4231: can't grab IRQ %d\n", irq);
1447 snd_cs4231_free(chip);
1448 return -EBUSY;
1449 }
1450 chip->irq = irq;
1451 if (!(hwshare & CS4231_HWSHARE_DMA1) && request_dma(dma1, "CS4231 - 1")) {
1452 snd_printk(KERN_ERR "cs4231: can't grab DMA1 %d\n", dma1);
1453 snd_cs4231_free(chip);
1454 return -EBUSY;
1455 }
1456 chip->dma1 = dma1;
1457 if (!(hwshare & CS4231_HWSHARE_DMA2) && dma1 != dma2 && dma2 >= 0 && request_dma(dma2, "CS4231 - 2")) {
1458 snd_printk(KERN_ERR "cs4231: can't grab DMA2 %d\n", dma2);
1459 snd_cs4231_free(chip);
1460 return -EBUSY;
1461 }
1462 if (dma1 == dma2 || dma2 < 0) {
1463 chip->single_dma = 1;
1464 chip->dma2 = chip->dma1;
1465 } else
1466 chip->dma2 = dma2;
1467
1468 /* global setup */
1469 if (snd_cs4231_probe(chip) < 0) {
1470 snd_cs4231_free(chip);
1471 return -ENODEV;
1472 }
1473 snd_cs4231_init(chip);
1474
a9824c86 1475#if 0
1da177e4
LT		 1476 if (chip->hardware & CS4231_HW_CS4232_MASK) {
1477 if (chip->res_cport == NULL)
1478 snd_printk("CS4232 control port features are not accessible\n");
1479 }
a9824c86 1480#endif
1da177e4
LT		 1481
1482 /* Register device */
1483 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1484 snd_cs4231_free(chip);
1485 return err;
1486 }
1487
1488#ifdef CONFIG_PM
1489 /* Power Management */
1490 chip->suspend = snd_cs4231_suspend;
1491 chip->resume = snd_cs4231_resume;
1da177e4
LT		 1492#endif
1493
1494 *rchip = chip;
1495 return 0;
1496}
1497
ba2375a4 1498static struct snd_pcm_ops snd_cs4231_playback_ops = {
1da177e4
LT		 1499 .open = snd_cs4231_playback_open,
1500 .close = snd_cs4231_playback_close,
1501 .ioctl = snd_pcm_lib_ioctl,
1502 .hw_params = snd_cs4231_playback_hw_params,
1503 .hw_free = snd_cs4231_playback_hw_free,
1504 .prepare = snd_cs4231_playback_prepare,
1505 .trigger = snd_cs4231_trigger,
1506 .pointer = snd_cs4231_playback_pointer,
1507};
1508
ba2375a4 1509static struct snd_pcm_ops snd_cs4231_capture_ops = {
1da177e4
LT		 1510 .open = snd_cs4231_capture_open,
1511 .close = snd_cs4231_capture_close,
1512 .ioctl = snd_pcm_lib_ioctl,
1513 .hw_params = snd_cs4231_capture_hw_params,
1514 .hw_free = snd_cs4231_capture_hw_free,
1515 .prepare = snd_cs4231_capture_prepare,
1516 .trigger = snd_cs4231_trigger,
1517 .pointer = snd_cs4231_capture_pointer,
1518};
1519
ba2375a4 1520int snd_cs4231_pcm(struct snd_cs4231 *chip, int device, struct snd_pcm **rpcm)
1da177e4 1521{
ba2375a4 1522 struct snd_pcm *pcm;
1da177e4
LT		 1523 int err;
1524
1525 if ((err = snd_pcm_new(chip->card, "CS4231", device, 1, 1, &pcm)) < 0)
1526 return err;
1527
1528 spin_lock_init(&chip->reg_lock);
8b7547f9
IM		 1529 mutex_init(&chip->mce_mutex);
1530 mutex_init(&chip->open_mutex);
1da177e4
LT		 1531
1532 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4231_playback_ops);
1533 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4231_capture_ops);
1534
1535 /* global setup */
1536 pcm->private_data = chip;
1da177e4
LT		 1537 pcm->info_flags = 0;
1538 if (chip->single_dma)
1539 pcm->info_flags |= SNDRV_PCM_INFO_HALF_DUPLEX;
1540 if (chip->hardware != CS4231_HW_INTERWAVE)
1541 pcm->info_flags |= SNDRV_PCM_INFO_JOINT_DUPLEX;
1542 strcpy(pcm->name, snd_cs4231_chip_id(chip));
1543
1da177e4
LT		 1544 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1545 snd_dma_isa_data(),
1546 64*1024, chip->dma1 > 3 || chip->dma2 > 3 ? 128*1024 : 64*1024);
1da177e4
LT		 1547
1548 chip->pcm = pcm;
1549 if (rpcm)
1550 *rpcm = pcm;
1551 return 0;
1552}
1553
ba2375a4 1554static void snd_cs4231_timer_free(struct snd_timer *timer)
1da177e4 1555{
ba2375a4 1556 struct snd_cs4231 *chip = timer->private_data;
1da177e4
LT		 1557 chip->timer = NULL;
1558}
1559
ba2375a4 1560int snd_cs4231_timer(struct snd_cs4231 *chip, int device, struct snd_timer **rtimer)
1da177e4 1561{
ba2375a4
TI		 1562 struct snd_timer *timer;
1563 struct snd_timer_id tid;
1da177e4
LT		 1564 int err;
1565
1566 /* Timer initialization */
1567 tid.dev_class = SNDRV_TIMER_CLASS_CARD;
1568 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
1569 tid.card = chip->card->number;
1570 tid.device = device;
1571 tid.subdevice = 0;
1572 if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
1573 return err;
1574 strcpy(timer->name, snd_cs4231_chip_id(chip));
1575 timer->private_data = chip;
1576 timer->private_free = snd_cs4231_timer_free;
1577 timer->hw = snd_cs4231_timer_table;
1578 chip->timer = timer;
1579 if (rtimer)
1580 *rtimer = timer;
1581 return 0;
1582}
1583
1584/*
1585 * MIXER part
1586 */
1587
ba2375a4 1588static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1589{
1590 static char *texts[4] = {
1591 "Line", "Aux", "Mic", "Mix"
1592 };
1593 static char *opl3sa_texts[4] = {
1594 "Line", "CD", "Mic", "Mix"
1595 };
1596 static char *gusmax_texts[4] = {
1597 "Line", "Synth", "Mic", "Mix"
1598 };
1599 char **ptexts = texts;
ba2375a4 1600 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1601
1602 snd_assert(chip->card != NULL, return -EINVAL);
1603 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1604 uinfo->count = 2;
1605 uinfo->value.enumerated.items = 4;
1606 if (uinfo->value.enumerated.item > 3)
1607 uinfo->value.enumerated.item = 3;
1608 if (!strcmp(chip->card->driver, "GUS MAX"))
1609 ptexts = gusmax_texts;
1610 switch (chip->hardware) {
1611 case CS4231_HW_INTERWAVE: ptexts = gusmax_texts; break;
1612 case CS4231_HW_OPL3SA2: ptexts = opl3sa_texts; break;
1613 }
1614 strcpy(uinfo->value.enumerated.name, ptexts[uinfo->value.enumerated.item]);
1615 return 0;
1616}
1617
ba2375a4 1618static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1619{
ba2375a4 1620 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1621 unsigned long flags;
1622
1623 spin_lock_irqsave(&chip->reg_lock, flags);
1624 ucontrol->value.enumerated.item[0] = (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
1625 ucontrol->value.enumerated.item[1] = (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
1626 spin_unlock_irqrestore(&chip->reg_lock, flags);
1627 return 0;
1628}
1629
ba2375a4 1630static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1631{
ba2375a4 1632 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1633 unsigned long flags;
1634 unsigned short left, right;
1635 int change;
1636
1637 if (ucontrol->value.enumerated.item[0] > 3 ||
1638 ucontrol->value.enumerated.item[1] > 3)
1639 return -EINVAL;
1640 left = ucontrol->value.enumerated.item[0] << 6;
1641 right = ucontrol->value.enumerated.item[1] << 6;
1642 spin_lock_irqsave(&chip->reg_lock, flags);
1643 left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
1644 right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
1645 change = left != chip->image[CS4231_LEFT_INPUT] ||
1646 right != chip->image[CS4231_RIGHT_INPUT];
1647 snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
1648 snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
1649 spin_unlock_irqrestore(&chip->reg_lock, flags);
1650 return change;
1651}
1652
ba2375a4 1653int snd_cs4231_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1654{
1655 int mask = (kcontrol->private_value >> 16) & 0xff;
1656
1657 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1658 uinfo->count = 1;
1659 uinfo->value.integer.min = 0;
1660 uinfo->value.integer.max = mask;
1661 return 0;
1662}
1663
ba2375a4 1664int snd_cs4231_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1665{
ba2375a4 1666 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1667 unsigned long flags;
1668 int reg = kcontrol->private_value & 0xff;
1669 int shift = (kcontrol->private_value >> 8) & 0xff;
1670 int mask = (kcontrol->private_value >> 16) & 0xff;
1671 int invert = (kcontrol->private_value >> 24) & 0xff;
1672
1673 spin_lock_irqsave(&chip->reg_lock, flags);
1674 ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
1675 spin_unlock_irqrestore(&chip->reg_lock, flags);
1676 if (invert)
1677 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
1678 return 0;
1679}
1680
ba2375a4 1681int snd_cs4231_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1682{
ba2375a4 1683 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1684 unsigned long flags;
1685 int reg = kcontrol->private_value & 0xff;
1686 int shift = (kcontrol->private_value >> 8) & 0xff;
1687 int mask = (kcontrol->private_value >> 16) & 0xff;
1688 int invert = (kcontrol->private_value >> 24) & 0xff;
1689 int change;
1690 unsigned short val;
1691
1692 val = (ucontrol->value.integer.value[0] & mask);
1693 if (invert)
1694 val = mask - val;
1695 val <<= shift;
1696 spin_lock_irqsave(&chip->reg_lock, flags);
1697 val = (chip->image[reg] & ~(mask << shift)) | val;
1698 change = val != chip->image[reg];
1699 snd_cs4231_out(chip, reg, val);
1700 spin_unlock_irqrestore(&chip->reg_lock, flags);
1701 return change;
1702}
1703
ba2375a4 1704int snd_cs4231_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1705{
1706 int mask = (kcontrol->private_value >> 24) & 0xff;
1707
1708 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1709 uinfo->count = 2;
1710 uinfo->value.integer.min = 0;
1711 uinfo->value.integer.max = mask;
1712 return 0;
1713}
1714
ba2375a4 1715int snd_cs4231_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1716{
ba2375a4 1717 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1718 unsigned long flags;
1719 int left_reg = kcontrol->private_value & 0xff;
1720 int right_reg = (kcontrol->private_value >> 8) & 0xff;
1721 int shift_left = (kcontrol->private_value >> 16) & 0x07;
1722 int shift_right = (kcontrol->private_value >> 19) & 0x07;
1723 int mask = (kcontrol->private_value >> 24) & 0xff;
1724 int invert = (kcontrol->private_value >> 22) & 1;
1725
1726 spin_lock_irqsave(&chip->reg_lock, flags);
1727 ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
1728 ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
1729 spin_unlock_irqrestore(&chip->reg_lock, flags);
1730 if (invert) {
1731 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
1732 ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
1733 }
1734 return 0;
1735}
1736
ba2375a4 1737int snd_cs4231_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1738{
ba2375a4 1739 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1740 unsigned long flags;
1741 int left_reg = kcontrol->private_value & 0xff;
1742 int right_reg = (kcontrol->private_value >> 8) & 0xff;
1743 int shift_left = (kcontrol->private_value >> 16) & 0x07;
1744 int shift_right = (kcontrol->private_value >> 19) & 0x07;
1745 int mask = (kcontrol->private_value >> 24) & 0xff;
1746 int invert = (kcontrol->private_value >> 22) & 1;
1747 int change;
1748 unsigned short val1, val2;
1749
1750 val1 = ucontrol->value.integer.value[0] & mask;
1751 val2 = ucontrol->value.integer.value[1] & mask;
1752 if (invert) {
1753 val1 = mask - val1;
1754 val2 = mask - val2;
1755 }
1756 val1 <<= shift_left;
1757 val2 <<= shift_right;
1758 spin_lock_irqsave(&chip->reg_lock, flags);
1759 val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
1760 val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
1761 change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
1762 snd_cs4231_out(chip, left_reg, val1);
1763 snd_cs4231_out(chip, right_reg, val2);
1764 spin_unlock_irqrestore(&chip->reg_lock, flags);
1765 return change;
1766}
1767
ba2375a4 1768static struct snd_kcontrol_new snd_cs4231_controls[] = {
1da177e4
LT		 1769CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
1770CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
1771CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
1772CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
1773CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
1774CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
1775CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
1776CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
1777CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
1778CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
1779CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
1780CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
1781CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
1782{
1783 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1784 .name = "Capture Source",
1785 .info = snd_cs4231_info_mux,
1786 .get = snd_cs4231_get_mux,
1787 .put = snd_cs4231_put_mux,
1788},
1789CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
1790CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
1791CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1)
1792};
1793
ba2375a4 1794int snd_cs4231_mixer(struct snd_cs4231 *chip)
1da177e4 1795{
ba2375a4 1796 struct snd_card *card;
1da177e4
LT		 1797 unsigned int idx;
1798 int err;
1799
1800 snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
1801
1802 card = chip->card;
1803
1804 strcpy(card->mixername, chip->pcm->name);
1805
1806 for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
1807 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4231_controls[idx], chip))) < 0)
1808 return err;
1809 }
1810 return 0;
1811}
1812
1813EXPORT_SYMBOL(snd_cs4231_out);
1814EXPORT_SYMBOL(snd_cs4231_in);
1815EXPORT_SYMBOL(snd_cs4236_ext_out);
1816EXPORT_SYMBOL(snd_cs4236_ext_in);
1817EXPORT_SYMBOL(snd_cs4231_mce_up);
1818EXPORT_SYMBOL(snd_cs4231_mce_down);
1819EXPORT_SYMBOL(snd_cs4231_interrupt);
1820EXPORT_SYMBOL(snd_cs4231_chip_id);
1821EXPORT_SYMBOL(snd_cs4231_create);
1822EXPORT_SYMBOL(snd_cs4231_pcm);
1823EXPORT_SYMBOL(snd_cs4231_mixer);
1824EXPORT_SYMBOL(snd_cs4231_timer);
1825EXPORT_SYMBOL(snd_cs4231_info_single);
1826EXPORT_SYMBOL(snd_cs4231_get_single);
1827EXPORT_SYMBOL(snd_cs4231_put_single);
1828EXPORT_SYMBOL(snd_cs4231_info_double);
1829EXPORT_SYMBOL(snd_cs4231_get_double);
1830EXPORT_SYMBOL(snd_cs4231_put_double);
1831
1832/*
1833 * INIT part
1834 */
1835
1836static int __init alsa_cs4231_init(void)
1837{
1838 return 0;
1839}
1840
1841static void __exit alsa_cs4231_exit(void)
1842{
1843}
1844
1845module_init(alsa_cs4231_init)
1846module_exit(alsa_cs4231_exit)
Empty description
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