]> Git Repo - linux.git/blame - sound/soc/codecs/wm_adsp.c
projects / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: wm_adsp: Add a handler for the compressed IRQ
[linux.git] / sound / soc / codecs / wm_adsp.c
CommitLineData
2159ad93
MB		 1/*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/firmware.h>
cf17c83c 18#include <linux/list.h>
2159ad93
MB		 19#include <linux/pm.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
973838a0 22#include <linux/regulator/consumer.h>
2159ad93 23#include <linux/slab.h>
cdcd7f72 24#include <linux/vmalloc.h>
6ab2b7b4 25#include <linux/workqueue.h>
f9f55e31 26#include <linux/debugfs.h>
2159ad93
MB		 27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/jack.h>
32#include <sound/initval.h>
33#include <sound/tlv.h>
34
35#include <linux/mfd/arizona/registers.h>
36
dc91428a 37#include "arizona.h"
2159ad93
MB		 38#include "wm_adsp.h"
39
40#define adsp_crit(_dsp, fmt, ...) \
41 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
42#define adsp_err(_dsp, fmt, ...) \
43 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
44#define adsp_warn(_dsp, fmt, ...) \
45 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
46#define adsp_info(_dsp, fmt, ...) \
47 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
48#define adsp_dbg(_dsp, fmt, ...) \
49 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
50
51#define ADSP1_CONTROL_1 0x00
52#define ADSP1_CONTROL_2 0x02
53#define ADSP1_CONTROL_3 0x03
54#define ADSP1_CONTROL_4 0x04
55#define ADSP1_CONTROL_5 0x06
56#define ADSP1_CONTROL_6 0x07
57#define ADSP1_CONTROL_7 0x08
58#define ADSP1_CONTROL_8 0x09
59#define ADSP1_CONTROL_9 0x0A
60#define ADSP1_CONTROL_10 0x0B
61#define ADSP1_CONTROL_11 0x0C
62#define ADSP1_CONTROL_12 0x0D
63#define ADSP1_CONTROL_13 0x0F
64#define ADSP1_CONTROL_14 0x10
65#define ADSP1_CONTROL_15 0x11
66#define ADSP1_CONTROL_16 0x12
67#define ADSP1_CONTROL_17 0x13
68#define ADSP1_CONTROL_18 0x14
69#define ADSP1_CONTROL_19 0x16
70#define ADSP1_CONTROL_20 0x17
71#define ADSP1_CONTROL_21 0x18
72#define ADSP1_CONTROL_22 0x1A
73#define ADSP1_CONTROL_23 0x1B
74#define ADSP1_CONTROL_24 0x1C
75#define ADSP1_CONTROL_25 0x1E
76#define ADSP1_CONTROL_26 0x20
77#define ADSP1_CONTROL_27 0x21
78#define ADSP1_CONTROL_28 0x22
79#define ADSP1_CONTROL_29 0x23
80#define ADSP1_CONTROL_30 0x24
81#define ADSP1_CONTROL_31 0x26
82
83/*
84 * ADSP1 Control 19
85 */
86#define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
87#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
88#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
89
90
91/*
92 * ADSP1 Control 30
93 */
94#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
95#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
96#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
97#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
98#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
99#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
100#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
101#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
102#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
103#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
104#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
105#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
106#define ADSP1_START 0x0001 /* DSP1_START */
107#define ADSP1_START_MASK 0x0001 /* DSP1_START */
108#define ADSP1_START_SHIFT 0 /* DSP1_START */
109#define ADSP1_START_WIDTH 1 /* DSP1_START */
110
94e205bf
CR		 111/*
112 * ADSP1 Control 31
113 */
114#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
115#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
116#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
117
2d30b575
MB		 118#define ADSP2_CONTROL 0x0
119#define ADSP2_CLOCKING 0x1
120#define ADSP2_STATUS1 0x4
121#define ADSP2_WDMA_CONFIG_1 0x30
122#define ADSP2_WDMA_CONFIG_2 0x31
123#define ADSP2_RDMA_CONFIG_1 0x34
2159ad93 124
10337b07
RF		 125#define ADSP2_SCRATCH0 0x40
126#define ADSP2_SCRATCH1 0x41
127#define ADSP2_SCRATCH2 0x42
128#define ADSP2_SCRATCH3 0x43
129
2159ad93
MB		 130/*
131 * ADSP2 Control
132 */
133
134#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
135#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
136#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
137#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
138#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
139#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
140#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
141#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
142#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
143#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
144#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
145#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
146#define ADSP2_START 0x0001 /* DSP1_START */
147#define ADSP2_START_MASK 0x0001 /* DSP1_START */
148#define ADSP2_START_SHIFT 0 /* DSP1_START */
149#define ADSP2_START_WIDTH 1 /* DSP1_START */
150
973838a0
MB		 151/*
152 * ADSP2 clocking
153 */
154#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
155#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
156#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
157
2159ad93
MB		 158/*
159 * ADSP2 Status 1
160 */
161#define ADSP2_RAM_RDY 0x0001
162#define ADSP2_RAM_RDY_MASK 0x0001
163#define ADSP2_RAM_RDY_SHIFT 0
164#define ADSP2_RAM_RDY_WIDTH 1
165
cf17c83c
MB		 166struct wm_adsp_buf {
167 struct list_head list;
168 void *buf;
169};
170
171static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
172 struct list_head *list)
173{
174 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
175
176 if (buf == NULL)
177 return NULL;
178
cdcd7f72 179 buf->buf = vmalloc(len);
cf17c83c 180 if (!buf->buf) {
cdcd7f72 181 vfree(buf);
cf17c83c
MB		 182 return NULL;
183 }
cdcd7f72 184 memcpy(buf->buf, src, len);
cf17c83c
MB		 185
186 if (list)
187 list_add_tail(&buf->list, list);
188
189 return buf;
190}
191
192static void wm_adsp_buf_free(struct list_head *list)
193{
194 while (!list_empty(list)) {
195 struct wm_adsp_buf *buf = list_first_entry(list,
196 struct wm_adsp_buf,
197 list);
198 list_del(&buf->list);
cdcd7f72 199 vfree(buf->buf);
cf17c83c
MB		 200 kfree(buf);
201 }
202}
203
04d1300f
CK		 204#define WM_ADSP_FW_MBC_VSS 0
205#define WM_ADSP_FW_HIFI 1
206#define WM_ADSP_FW_TX 2
207#define WM_ADSP_FW_TX_SPK 3
208#define WM_ADSP_FW_RX 4
209#define WM_ADSP_FW_RX_ANC 5
210#define WM_ADSP_FW_CTRL 6
211#define WM_ADSP_FW_ASR 7
212#define WM_ADSP_FW_TRACE 8
213#define WM_ADSP_FW_SPK_PROT 9
214#define WM_ADSP_FW_MISC 10
215
216#define WM_ADSP_NUM_FW 11
dd84f925 217
1023dbd9 218static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
04d1300f
CK		 219 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
220 [WM_ADSP_FW_HIFI] = "MasterHiFi",
221 [WM_ADSP_FW_TX] = "Tx",
222 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
223 [WM_ADSP_FW_RX] = "Rx",
224 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
225 [WM_ADSP_FW_CTRL] = "Voice Ctrl",
226 [WM_ADSP_FW_ASR] = "ASR Assist",
227 [WM_ADSP_FW_TRACE] = "Dbg Trace",
228 [WM_ADSP_FW_SPK_PROT] = "Protection",
229 [WM_ADSP_FW_MISC] = "Misc",
1023dbd9
MB		 230};
231
2cd19bdb
CK		 232struct wm_adsp_system_config_xm_hdr {
233 __be32 sys_enable;
234 __be32 fw_id;
235 __be32 fw_rev;
236 __be32 boot_status;
237 __be32 watchdog;
238 __be32 dma_buffer_size;
239 __be32 rdma[6];
240 __be32 wdma[8];
241 __be32 build_job_name[3];
242 __be32 build_job_number;
243};
244
245struct wm_adsp_alg_xm_struct {
246 __be32 magic;
247 __be32 smoothing;
248 __be32 threshold;
249 __be32 host_buf_ptr;
250 __be32 start_seq;
251 __be32 high_water_mark;
252 __be32 low_water_mark;
253 __be64 smoothed_power;
254};
255
256struct wm_adsp_buffer {
257 __be32 X_buf_base; /* XM base addr of first X area */
258 __be32 X_buf_size; /* Size of 1st X area in words */
259 __be32 X_buf_base2; /* XM base addr of 2nd X area */
260 __be32 X_buf_brk; /* Total X size in words */
261 __be32 Y_buf_base; /* YM base addr of Y area */
262 __be32 wrap; /* Total size X and Y in words */
263 __be32 high_water_mark; /* Point at which IRQ is asserted */
264 __be32 irq_count; /* bits 1-31 count IRQ assertions */
265 __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */
266 __be32 next_write_index; /* word index of next write */
267 __be32 next_read_index; /* word index of next read */
268 __be32 error; /* error if any */
269 __be32 oldest_block_index; /* word index of oldest surviving */
270 __be32 requested_rewind; /* how many blocks rewind was done */
271 __be32 reserved_space; /* internal */
272 __be32 min_free; /* min free space since stream start */
273 __be32 blocks_written[2]; /* total blocks written (64 bit) */
274 __be32 words_written[2]; /* total words written (64 bit) */
275};
276
277struct wm_adsp_compr_buf {
278 struct wm_adsp *dsp;
279
280 struct wm_adsp_buffer_region *regions;
281 u32 host_buf_ptr;
565ace46
CK		 282
283 u32 error;
284 u32 irq_count;
285 int read_index;
286 int avail;
2cd19bdb
CK		 287};
288
406abc95
CK		 289struct wm_adsp_compr {
290 struct wm_adsp *dsp;
95fe9597 291 struct wm_adsp_compr_buf *buf;
406abc95
CK		 292
293 struct snd_compr_stream *stream;
294 struct snd_compressed_buffer size;
565ace46
CK		 295
296 unsigned int copied_total;
406abc95
CK		 297};
298
299#define WM_ADSP_DATA_WORD_SIZE 3
300
301#define WM_ADSP_MIN_FRAGMENTS 1
302#define WM_ADSP_MAX_FRAGMENTS 256
303#define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE)
304#define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE)
305
2cd19bdb
CK		 306#define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7
307
308#define HOST_BUFFER_FIELD(field) \
309 (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
310
311#define ALG_XM_FIELD(field) \
312 (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
313
314static int wm_adsp_buffer_init(struct wm_adsp *dsp);
315static int wm_adsp_buffer_free(struct wm_adsp *dsp);
316
317struct wm_adsp_buffer_region {
318 unsigned int offset;
319 unsigned int cumulative_size;
320 unsigned int mem_type;
321 unsigned int base_addr;
322};
323
324struct wm_adsp_buffer_region_def {
325 unsigned int mem_type;
326 unsigned int base_offset;
327 unsigned int size_offset;
328};
329
330static struct wm_adsp_buffer_region_def ez2control_regions[] = {
331 {
332 .mem_type = WMFW_ADSP2_XM,
333 .base_offset = HOST_BUFFER_FIELD(X_buf_base),
334 .size_offset = HOST_BUFFER_FIELD(X_buf_size),
335 },
336 {
337 .mem_type = WMFW_ADSP2_XM,
338 .base_offset = HOST_BUFFER_FIELD(X_buf_base2),
339 .size_offset = HOST_BUFFER_FIELD(X_buf_brk),
340 },
341 {
342 .mem_type = WMFW_ADSP2_YM,
343 .base_offset = HOST_BUFFER_FIELD(Y_buf_base),
344 .size_offset = HOST_BUFFER_FIELD(wrap),
345 },
346};
347
406abc95
CK		 348struct wm_adsp_fw_caps {
349 u32 id;
350 struct snd_codec_desc desc;
2cd19bdb
CK		 351 int num_regions;
352 struct wm_adsp_buffer_region_def *region_defs;
406abc95
CK		 353};
354
355static const struct wm_adsp_fw_caps ez2control_caps[] = {
356 {
357 .id = SND_AUDIOCODEC_BESPOKE,
358 .desc = {
359 .max_ch = 1,
360 .sample_rates = { 16000 },
361 .num_sample_rates = 1,
362 .formats = SNDRV_PCM_FMTBIT_S16_LE,
363 },
2cd19bdb
CK		 364 .num_regions = ARRAY_SIZE(ez2control_regions),
365 .region_defs = ez2control_regions,
406abc95
CK		 366 },
367};
368
369static const struct {
1023dbd9 370 const char *file;
406abc95
CK		 371 int compr_direction;
372 int num_caps;
373 const struct wm_adsp_fw_caps *caps;
1023dbd9 374} wm_adsp_fw[WM_ADSP_NUM_FW] = {
04d1300f
CK		 375 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
376 [WM_ADSP_FW_HIFI] = { .file = "hifi" },
377 [WM_ADSP_FW_TX] = { .file = "tx" },
378 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
379 [WM_ADSP_FW_RX] = { .file = "rx" },
380 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
406abc95
CK		 381 [WM_ADSP_FW_CTRL] = {
382 .file = "ctrl",
383 .compr_direction = SND_COMPRESS_CAPTURE,
384 .num_caps = ARRAY_SIZE(ez2control_caps),
385 .caps = ez2control_caps,
386 },
04d1300f
CK		 387 [WM_ADSP_FW_ASR] = { .file = "asr" },
388 [WM_ADSP_FW_TRACE] = { .file = "trace" },
389 [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
390 [WM_ADSP_FW_MISC] = { .file = "misc" },
1023dbd9
MB		 391};
392
6ab2b7b4
DP		 393struct wm_coeff_ctl_ops {
394 int (*xget)(struct snd_kcontrol *kcontrol,
395 struct snd_ctl_elem_value *ucontrol);
396 int (*xput)(struct snd_kcontrol *kcontrol,
397 struct snd_ctl_elem_value *ucontrol);
398 int (*xinfo)(struct snd_kcontrol *kcontrol,
399 struct snd_ctl_elem_info *uinfo);
400};
401
6ab2b7b4
DP		 402struct wm_coeff_ctl {
403 const char *name;
2323736d 404 const char *fw_name;
3809f001 405 struct wm_adsp_alg_region alg_region;
6ab2b7b4 406 struct wm_coeff_ctl_ops ops;
3809f001 407 struct wm_adsp *dsp;
6ab2b7b4
DP		 408 unsigned int enabled:1;
409 struct list_head list;
410 void *cache;
2323736d 411 unsigned int offset;
6ab2b7b4 412 size_t len;
0c2e3f34 413 unsigned int set:1;
6ab2b7b4 414 struct snd_kcontrol *kcontrol;
26c22a19 415 unsigned int flags;
6ab2b7b4
DP		 416};
417
f9f55e31
RF		 418#ifdef CONFIG_DEBUG_FS
419static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
420{
421 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
422
f9f55e31
RF		 423 kfree(dsp->wmfw_file_name);
424 dsp->wmfw_file_name = tmp;
f9f55e31
RF		 425}
426
427static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
428{
429 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
430
f9f55e31
RF		 431 kfree(dsp->bin_file_name);
432 dsp->bin_file_name = tmp;
f9f55e31
RF		 433}
434
435static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
436{
f9f55e31
RF		 437 kfree(dsp->wmfw_file_name);
438 kfree(dsp->bin_file_name);
439 dsp->wmfw_file_name = NULL;
440 dsp->bin_file_name = NULL;
f9f55e31
RF		 441}
442
443static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
444 char __user *user_buf,
445 size_t count, loff_t *ppos)
446{
447 struct wm_adsp *dsp = file->private_data;
448 ssize_t ret;
449
078e7183 450 mutex_lock(&dsp->pwr_lock);
f9f55e31
RF		 451
452 if (!dsp->wmfw_file_name || !dsp->running)
453 ret = 0;
454 else
455 ret = simple_read_from_buffer(user_buf, count, ppos,
456 dsp->wmfw_file_name,
457 strlen(dsp->wmfw_file_name));
458
078e7183 459 mutex_unlock(&dsp->pwr_lock);
f9f55e31
RF		 460 return ret;
461}
462
463static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
464 char __user *user_buf,
465 size_t count, loff_t *ppos)
466{
467 struct wm_adsp *dsp = file->private_data;
468 ssize_t ret;
469
078e7183 470 mutex_lock(&dsp->pwr_lock);
f9f55e31
RF		 471
472 if (!dsp->bin_file_name || !dsp->running)
473 ret = 0;
474 else
475 ret = simple_read_from_buffer(user_buf, count, ppos,
476 dsp->bin_file_name,
477 strlen(dsp->bin_file_name));
478
078e7183 479 mutex_unlock(&dsp->pwr_lock);
f9f55e31
RF		 480 return ret;
481}
482
483static const struct {
484 const char *name;
485 const struct file_operations fops;
486} wm_adsp_debugfs_fops[] = {
487 {
488 .name = "wmfw_file_name",
489 .fops = {
490 .open = simple_open,
491 .read = wm_adsp_debugfs_wmfw_read,
492 },
493 },
494 {
495 .name = "bin_file_name",
496 .fops = {
497 .open = simple_open,
498 .read = wm_adsp_debugfs_bin_read,
499 },
500 },
501};
502
503static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
504 struct snd_soc_codec *codec)
505{
506 struct dentry *root = NULL;
507 char *root_name;
508 int i;
509
510 if (!codec->component.debugfs_root) {
511 adsp_err(dsp, "No codec debugfs root\n");
512 goto err;
513 }
514
515 root_name = kmalloc(PAGE_SIZE, GFP_KERNEL);
516 if (!root_name)
517 goto err;
518
519 snprintf(root_name, PAGE_SIZE, "dsp%d", dsp->num);
520 root = debugfs_create_dir(root_name, codec->component.debugfs_root);
521 kfree(root_name);
522
523 if (!root)
524 goto err;
525
526 if (!debugfs_create_bool("running", S_IRUGO, root, &dsp->running))
527 goto err;
528
529 if (!debugfs_create_x32("fw_id", S_IRUGO, root, &dsp->fw_id))
530 goto err;
531
532 if (!debugfs_create_x32("fw_version", S_IRUGO, root,
533 &dsp->fw_id_version))
534 goto err;
535
536 for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) {
537 if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name,
538 S_IRUGO, root, dsp,
539 &wm_adsp_debugfs_fops[i].fops))
540 goto err;
541 }
542
543 dsp->debugfs_root = root;
544 return;
545
546err:
547 debugfs_remove_recursive(root);
548 adsp_err(dsp, "Failed to create debugfs\n");
549}
550
551static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
552{
553 wm_adsp_debugfs_clear(dsp);
554 debugfs_remove_recursive(dsp->debugfs_root);
555}
556#else
557static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
558 struct snd_soc_codec *codec)
559{
560}
561
562static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
563{
564}
565
566static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
567 const char *s)
568{
569}
570
571static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
572 const char *s)
573{
574}
575
576static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
577{
578}
579#endif
580
1023dbd9
MB		 581static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
582 struct snd_ctl_elem_value *ucontrol)
583{
ea53bf77 584 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1023dbd9 585 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3809f001 586 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
1023dbd9 587
3809f001 588 ucontrol->value.integer.value[0] = dsp[e->shift_l].fw;
1023dbd9
MB		 589
590 return 0;
591}
592
593static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
594 struct snd_ctl_elem_value *ucontrol)
595{
ea53bf77 596 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1023dbd9 597 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3809f001 598 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
d27c5e15 599 int ret = 0;
1023dbd9 600
3809f001 601 if (ucontrol->value.integer.value[0] == dsp[e->shift_l].fw)
1023dbd9
MB		 602 return 0;
603
604 if (ucontrol->value.integer.value[0] >= WM_ADSP_NUM_FW)
605 return -EINVAL;
606
d27c5e15
CK		 607 mutex_lock(&dsp[e->shift_l].pwr_lock);
608
406abc95 609 if (dsp[e->shift_l].running || dsp[e->shift_l].compr)
d27c5e15
CK		 610 ret = -EBUSY;
611 else
612 dsp[e->shift_l].fw = ucontrol->value.integer.value[0];
1023dbd9 613
d27c5e15 614 mutex_unlock(&dsp[e->shift_l].pwr_lock);
1023dbd9 615
d27c5e15 616 return ret;
1023dbd9
MB		 617}
618
619static const struct soc_enum wm_adsp_fw_enum[] = {
620 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
621 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
622 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
623 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
624};
625
336d0442 626const struct snd_kcontrol_new wm_adsp_fw_controls[] = {
1023dbd9
MB		 627 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
628 wm_adsp_fw_get, wm_adsp_fw_put),
629 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
630 wm_adsp_fw_get, wm_adsp_fw_put),
631 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
632 wm_adsp_fw_get, wm_adsp_fw_put),
336d0442
RF		 633 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
634 wm_adsp_fw_get, wm_adsp_fw_put),
b6ed61cf 635};
336d0442 636EXPORT_SYMBOL_GPL(wm_adsp_fw_controls);
2159ad93
MB		 637
638static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
639 int type)
640{
641 int i;
642
643 for (i = 0; i < dsp->num_mems; i++)
644 if (dsp->mem[i].type == type)
645 return &dsp->mem[i];
646
647 return NULL;
648}
649
3809f001 650static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
45b9ee72
MB		 651 unsigned int offset)
652{
3809f001 653 if (WARN_ON(!mem))
6c452bda 654 return offset;
3809f001 655 switch (mem->type) {
45b9ee72 656 case WMFW_ADSP1_PM:
3809f001 657 return mem->base + (offset * 3);
45b9ee72 658 case WMFW_ADSP1_DM:
3809f001 659 return mem->base + (offset * 2);
45b9ee72 660 case WMFW_ADSP2_XM:
3809f001 661 return mem->base + (offset * 2);
45b9ee72 662 case WMFW_ADSP2_YM:
3809f001 663 return mem->base + (offset * 2);
45b9ee72 664 case WMFW_ADSP1_ZM:
3809f001 665 return mem->base + (offset * 2);
45b9ee72 666 default:
6c452bda 667 WARN(1, "Unknown memory region type");
45b9ee72
MB		 668 return offset;
669 }
670}
671
10337b07
RF		 672static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
673{
674 u16 scratch[4];
675 int ret;
676
677 ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2_SCRATCH0,
678 scratch, sizeof(scratch));
679 if (ret) {
680 adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret);
681 return;
682 }
683
684 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
685 be16_to_cpu(scratch[0]),
686 be16_to_cpu(scratch[1]),
687 be16_to_cpu(scratch[2]),
688 be16_to_cpu(scratch[3]));
689}
690
7585a5b0 691static int wm_coeff_info(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 692 struct snd_ctl_elem_info *uinfo)
693{
7585a5b0 694 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kctl->private_value;
6ab2b7b4
DP		 695
696 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
697 uinfo->count = ctl->len;
698 return 0;
699}
700
c9f8dd71 701static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
6ab2b7b4
DP		 702 const void *buf, size_t len)
703{
3809f001 704 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
6ab2b7b4 705 const struct wm_adsp_region *mem;
3809f001 706 struct wm_adsp *dsp = ctl->dsp;
6ab2b7b4
DP		 707 void *scratch;
708 int ret;
709 unsigned int reg;
710
3809f001 711 mem = wm_adsp_find_region(dsp, alg_region->type);
6ab2b7b4 712 if (!mem) {
3809f001
CK		 713 adsp_err(dsp, "No base for region %x\n",
714 alg_region->type);
6ab2b7b4
DP		 715 return -EINVAL;
716 }
717
2323736d 718 reg = ctl->alg_region.base + ctl->offset;
6ab2b7b4
DP		 719 reg = wm_adsp_region_to_reg(mem, reg);
720
721 scratch = kmemdup(buf, ctl->len, GFP_KERNEL | GFP_DMA);
722 if (!scratch)
723 return -ENOMEM;
724
3809f001 725 ret = regmap_raw_write(dsp->regmap, reg, scratch,
6ab2b7b4
DP		 726 ctl->len);
727 if (ret) {
3809f001 728 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
43bc3bf6 729 ctl->len, reg, ret);
6ab2b7b4
DP		 730 kfree(scratch);
731 return ret;
732 }
3809f001 733 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", ctl->len, reg);
6ab2b7b4
DP		 734
735 kfree(scratch);
736
737 return 0;
738}
739
7585a5b0 740static int wm_coeff_put(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 741 struct snd_ctl_elem_value *ucontrol)
742{
7585a5b0 743 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kctl->private_value;
6ab2b7b4 744 char *p = ucontrol->value.bytes.data;
168d10e7
CK		 745 int ret = 0;
746
747 mutex_lock(&ctl->dsp->pwr_lock);
6ab2b7b4
DP		 748
749 memcpy(ctl->cache, p, ctl->len);
750
65d17a9c 751 ctl->set = 1;
168d10e7
CK		 752 if (ctl->enabled)
753 ret = wm_coeff_write_control(ctl, p, ctl->len);
6ab2b7b4 754
168d10e7
CK		 755 mutex_unlock(&ctl->dsp->pwr_lock);
756
757 return ret;
6ab2b7b4
DP		 758}
759
c9f8dd71 760static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
6ab2b7b4
DP		 761 void *buf, size_t len)
762{
3809f001 763 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
6ab2b7b4 764 const struct wm_adsp_region *mem;
3809f001 765 struct wm_adsp *dsp = ctl->dsp;
6ab2b7b4
DP		 766 void *scratch;
767 int ret;
768 unsigned int reg;
769
3809f001 770 mem = wm_adsp_find_region(dsp, alg_region->type);
6ab2b7b4 771 if (!mem) {
3809f001
CK		 772 adsp_err(dsp, "No base for region %x\n",
773 alg_region->type);
6ab2b7b4
DP		 774 return -EINVAL;
775 }
776
2323736d 777 reg = ctl->alg_region.base + ctl->offset;
6ab2b7b4
DP		 778 reg = wm_adsp_region_to_reg(mem, reg);
779
780 scratch = kmalloc(ctl->len, GFP_KERNEL | GFP_DMA);
781 if (!scratch)
782 return -ENOMEM;
783
3809f001 784 ret = regmap_raw_read(dsp->regmap, reg, scratch, ctl->len);
6ab2b7b4 785 if (ret) {
3809f001 786 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
43bc3bf6 787 ctl->len, reg, ret);
6ab2b7b4
DP		 788 kfree(scratch);
789 return ret;
790 }
3809f001 791 adsp_dbg(dsp, "Read %zu bytes from %x\n", ctl->len, reg);
6ab2b7b4
DP		 792
793 memcpy(buf, scratch, ctl->len);
794 kfree(scratch);
795
796 return 0;
797}
798
7585a5b0 799static int wm_coeff_get(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 800 struct snd_ctl_elem_value *ucontrol)
801{
7585a5b0 802 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kctl->private_value;
6ab2b7b4 803 char *p = ucontrol->value.bytes.data;
168d10e7
CK		 804 int ret = 0;
805
806 mutex_lock(&ctl->dsp->pwr_lock);
6ab2b7b4 807
26c22a19
CK		 808 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
809 if (ctl->enabled)
168d10e7 810 ret = wm_coeff_read_control(ctl, p, ctl->len);
26c22a19 811 else
168d10e7
CK		 812 ret = -EPERM;
813 } else {
bc1765d6
CK		 814 if (!ctl->flags && ctl->enabled)
815 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
816
168d10e7 817 memcpy(p, ctl->cache, ctl->len);
26c22a19
CK		 818 }
819
168d10e7 820 mutex_unlock(&ctl->dsp->pwr_lock);
26c22a19 821
168d10e7 822 return ret;
6ab2b7b4
DP		 823}
824
6ab2b7b4 825struct wmfw_ctl_work {
3809f001 826 struct wm_adsp *dsp;
6ab2b7b4
DP		 827 struct wm_coeff_ctl *ctl;
828 struct work_struct work;
829};
830
3809f001 831static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
6ab2b7b4
DP		 832{
833 struct snd_kcontrol_new *kcontrol;
834 int ret;
835
92bb4c32 836 if (!ctl || !ctl->name)
6ab2b7b4
DP		 837 return -EINVAL;
838
839 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
840 if (!kcontrol)
841 return -ENOMEM;
842 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
843
844 kcontrol->name = ctl->name;
845 kcontrol->info = wm_coeff_info;
846 kcontrol->get = wm_coeff_get;
847 kcontrol->put = wm_coeff_put;
848 kcontrol->private_value = (unsigned long)ctl;
849
26c22a19
CK		 850 if (ctl->flags) {
851 if (ctl->flags & WMFW_CTL_FLAG_WRITEABLE)
852 kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
853 if (ctl->flags & WMFW_CTL_FLAG_READABLE)
854 kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_READ;
855 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
856 kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_VOLATILE;
857 }
858
3809f001 859 ret = snd_soc_add_card_controls(dsp->card,
81ad93ec 860 kcontrol, 1);
6ab2b7b4
DP		 861 if (ret < 0)
862 goto err_kcontrol;
863
864 kfree(kcontrol);
865
3809f001 866 ctl->kcontrol = snd_soc_card_get_kcontrol(dsp->card,
81ad93ec
DP		 867 ctl->name);
868
6ab2b7b4
DP		 869 return 0;
870
871err_kcontrol:
872 kfree(kcontrol);
873 return ret;
874}
875
b21acc1c
CK		 876static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
877{
878 struct wm_coeff_ctl *ctl;
879 int ret;
880
881 list_for_each_entry(ctl, &dsp->ctl_list, list) {
882 if (!ctl->enabled || ctl->set)
883 continue;
26c22a19
CK		 884 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
885 continue;
886
b21acc1c
CK		 887 ret = wm_coeff_read_control(ctl,
888 ctl->cache,
889 ctl->len);
890 if (ret < 0)
891 return ret;
892 }
893
894 return 0;
895}
896
897static int wm_coeff_sync_controls(struct wm_adsp *dsp)
898{
899 struct wm_coeff_ctl *ctl;
900 int ret;
901
902 list_for_each_entry(ctl, &dsp->ctl_list, list) {
903 if (!ctl->enabled)
904 continue;
26c22a19 905 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
b21acc1c
CK		 906 ret = wm_coeff_write_control(ctl,
907 ctl->cache,
908 ctl->len);
909 if (ret < 0)
910 return ret;
911 }
912 }
913
914 return 0;
915}
916
917static void wm_adsp_ctl_work(struct work_struct *work)
918{
919 struct wmfw_ctl_work *ctl_work = container_of(work,
920 struct wmfw_ctl_work,
921 work);
922
923 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
924 kfree(ctl_work);
925}
926
927static int wm_adsp_create_control(struct wm_adsp *dsp,
928 const struct wm_adsp_alg_region *alg_region,
2323736d 929 unsigned int offset, unsigned int len,
26c22a19
CK		 930 const char *subname, unsigned int subname_len,
931 unsigned int flags)
b21acc1c
CK		 932{
933 struct wm_coeff_ctl *ctl;
934 struct wmfw_ctl_work *ctl_work;
935 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
936 char *region_name;
937 int ret;
938
26c22a19
CK		 939 if (flags & WMFW_CTL_FLAG_SYS)
940 return 0;
941
b21acc1c
CK		 942 switch (alg_region->type) {
943 case WMFW_ADSP1_PM:
944 region_name = "PM";
945 break;
946 case WMFW_ADSP1_DM:
947 region_name = "DM";
948 break;
949 case WMFW_ADSP2_XM:
950 region_name = "XM";
951 break;
952 case WMFW_ADSP2_YM:
953 region_name = "YM";
954 break;
955 case WMFW_ADSP1_ZM:
956 region_name = "ZM";
957 break;
958 default:
2323736d 959 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
b21acc1c
CK		 960 return -EINVAL;
961 }
962
cb5b57a9
CK		 963 switch (dsp->fw_ver) {
964 case 0:
965 case 1:
966 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "DSP%d %s %x",
967 dsp->num, region_name, alg_region->alg);
968 break;
969 default:
970 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
971 "DSP%d%c %.12s %x", dsp->num, *region_name,
972 wm_adsp_fw_text[dsp->fw], alg_region->alg);
973
974 /* Truncate the subname from the start if it is too long */
975 if (subname) {
976 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
977 int skip = 0;
978
979 if (subname_len > avail)
980 skip = subname_len - avail;
981
982 snprintf(name + ret,
983 SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s",
984 subname_len - skip, subname + skip);
985 }
986 break;
987 }
b21acc1c 988
7585a5b0 989 list_for_each_entry(ctl, &dsp->ctl_list, list) {
b21acc1c
CK		 990 if (!strcmp(ctl->name, name)) {
991 if (!ctl->enabled)
992 ctl->enabled = 1;
993 return 0;
994 }
995 }
996
997 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
998 if (!ctl)
999 return -ENOMEM;
2323736d 1000 ctl->fw_name = wm_adsp_fw_text[dsp->fw];
b21acc1c
CK		 1001 ctl->alg_region = *alg_region;
1002 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
1003 if (!ctl->name) {
1004 ret = -ENOMEM;
1005 goto err_ctl;
1006 }
1007 ctl->enabled = 1;
1008 ctl->set = 0;
1009 ctl->ops.xget = wm_coeff_get;
1010 ctl->ops.xput = wm_coeff_put;
1011 ctl->dsp = dsp;
1012
26c22a19 1013 ctl->flags = flags;
2323736d 1014 ctl->offset = offset;
b21acc1c
CK		 1015 if (len > 512) {
1016 adsp_warn(dsp, "Truncating control %s from %d\n",
1017 ctl->name, len);
1018 len = 512;
1019 }
1020 ctl->len = len;
1021 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
1022 if (!ctl->cache) {
1023 ret = -ENOMEM;
1024 goto err_ctl_name;
1025 }
1026
2323736d
CK		 1027 list_add(&ctl->list, &dsp->ctl_list);
1028
b21acc1c
CK		 1029 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
1030 if (!ctl_work) {
1031 ret = -ENOMEM;
1032 goto err_ctl_cache;
1033 }
1034
1035 ctl_work->dsp = dsp;
1036 ctl_work->ctl = ctl;
1037 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
1038 schedule_work(&ctl_work->work);
1039
1040 return 0;
1041
1042err_ctl_cache:
1043 kfree(ctl->cache);
1044err_ctl_name:
1045 kfree(ctl->name);
1046err_ctl:
1047 kfree(ctl);
1048
1049 return ret;
1050}
1051
2323736d
CK		 1052struct wm_coeff_parsed_alg {
1053 int id;
1054 const u8 *name;
1055 int name_len;
1056 int ncoeff;
1057};
1058
1059struct wm_coeff_parsed_coeff {
1060 int offset;
1061 int mem_type;
1062 const u8 *name;
1063 int name_len;
1064 int ctl_type;
1065 int flags;
1066 int len;
1067};
1068
cb5b57a9
CK		 1069static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
1070{
1071 int length;
1072
1073 switch (bytes) {
1074 case 1:
1075 length = **pos;
1076 break;
1077 case 2:
8299ee81 1078 length = le16_to_cpu(*((__le16 *)*pos));
cb5b57a9
CK		 1079 break;
1080 default:
1081 return 0;
1082 }
1083
1084 if (str)
1085 *str = *pos + bytes;
1086
1087 *pos += ((length + bytes) + 3) & ~0x03;
1088
1089 return length;
1090}
1091
1092static int wm_coeff_parse_int(int bytes, const u8 **pos)
1093{
1094 int val = 0;
1095
1096 switch (bytes) {
1097 case 2:
8299ee81 1098 val = le16_to_cpu(*((__le16 *)*pos));
cb5b57a9
CK		 1099 break;
1100 case 4:
8299ee81 1101 val = le32_to_cpu(*((__le32 *)*pos));
cb5b57a9
CK		 1102 break;
1103 default:
1104 break;
1105 }
1106
1107 *pos += bytes;
1108
1109 return val;
1110}
1111
2323736d
CK		 1112static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
1113 struct wm_coeff_parsed_alg *blk)
1114{
1115 const struct wmfw_adsp_alg_data *raw;
1116
cb5b57a9
CK		 1117 switch (dsp->fw_ver) {
1118 case 0:
1119 case 1:
1120 raw = (const struct wmfw_adsp_alg_data *)*data;
1121 *data = raw->data;
2323736d 1122
cb5b57a9
CK		 1123 blk->id = le32_to_cpu(raw->id);
1124 blk->name = raw->name;
1125 blk->name_len = strlen(raw->name);
1126 blk->ncoeff = le32_to_cpu(raw->ncoeff);
1127 break;
1128 default:
1129 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
1130 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
1131 &blk->name);
1132 wm_coeff_parse_string(sizeof(u16), data, NULL);
1133 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
1134 break;
1135 }
2323736d
CK		 1136
1137 adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
1138 adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
1139 adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
1140}
1141
1142static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
1143 struct wm_coeff_parsed_coeff *blk)
1144{
1145 const struct wmfw_adsp_coeff_data *raw;
cb5b57a9
CK		 1146 const u8 *tmp;
1147 int length;
2323736d 1148
cb5b57a9
CK		 1149 switch (dsp->fw_ver) {
1150 case 0:
1151 case 1:
1152 raw = (const struct wmfw_adsp_coeff_data *)*data;
1153 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
1154
1155 blk->offset = le16_to_cpu(raw->hdr.offset);
1156 blk->mem_type = le16_to_cpu(raw->hdr.type);
1157 blk->name = raw->name;
1158 blk->name_len = strlen(raw->name);
1159 blk->ctl_type = le16_to_cpu(raw->ctl_type);
1160 blk->flags = le16_to_cpu(raw->flags);
1161 blk->len = le32_to_cpu(raw->len);
1162 break;
1163 default:
1164 tmp = *data;
1165 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1166 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1167 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1168 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
1169 &blk->name);
1170 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
1171 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
1172 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
1173 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
1174 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
1175
1176 *data = *data + sizeof(raw->hdr) + length;
1177 break;
1178 }
2323736d
CK		 1179
1180 adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1181 adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1182 adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1183 adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1184 adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1185 adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1186}
1187
1188static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
1189 const struct wmfw_region *region)
1190{
1191 struct wm_adsp_alg_region alg_region = {};
1192 struct wm_coeff_parsed_alg alg_blk;
1193 struct wm_coeff_parsed_coeff coeff_blk;
1194 const u8 *data = region->data;
1195 int i, ret;
1196
1197 wm_coeff_parse_alg(dsp, &data, &alg_blk);
1198 for (i = 0; i < alg_blk.ncoeff; i++) {
1199 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
1200
1201 switch (coeff_blk.ctl_type) {
1202 case SNDRV_CTL_ELEM_TYPE_BYTES:
1203 break;
1204 default:
1205 adsp_err(dsp, "Unknown control type: %d\n",
1206 coeff_blk.ctl_type);
1207 return -EINVAL;
1208 }
1209
1210 alg_region.type = coeff_blk.mem_type;
1211 alg_region.alg = alg_blk.id;
1212
1213 ret = wm_adsp_create_control(dsp, &alg_region,
1214 coeff_blk.offset,
1215 coeff_blk.len,
1216 coeff_blk.name,
26c22a19
CK		 1217 coeff_blk.name_len,
1218 coeff_blk.flags);
2323736d
CK		 1219 if (ret < 0)
1220 adsp_err(dsp, "Failed to create control: %.*s, %d\n",
1221 coeff_blk.name_len, coeff_blk.name, ret);
1222 }
1223
1224 return 0;
1225}
1226
2159ad93
MB		 1227static int wm_adsp_load(struct wm_adsp *dsp)
1228{
cf17c83c 1229 LIST_HEAD(buf_list);
2159ad93
MB		 1230 const struct firmware *firmware;
1231 struct regmap *regmap = dsp->regmap;
1232 unsigned int pos = 0;
1233 const struct wmfw_header *header;
1234 const struct wmfw_adsp1_sizes *adsp1_sizes;
1235 const struct wmfw_adsp2_sizes *adsp2_sizes;
1236 const struct wmfw_footer *footer;
1237 const struct wmfw_region *region;
1238 const struct wm_adsp_region *mem;
1239 const char *region_name;
1240 char *file, *text;
cf17c83c 1241 struct wm_adsp_buf *buf;
2159ad93
MB		 1242 unsigned int reg;
1243 int regions = 0;
1244 int ret, offset, type, sizes;
1245
1246 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1247 if (file == NULL)
1248 return -ENOMEM;
1249
1023dbd9
MB		 1250 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
1251 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 1252 file[PAGE_SIZE - 1] = '\0';
1253
1254 ret = request_firmware(&firmware, file, dsp->dev);
1255 if (ret != 0) {
1256 adsp_err(dsp, "Failed to request '%s'\n", file);
1257 goto out;
1258 }
1259 ret = -EINVAL;
1260
1261 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1262 if (pos >= firmware->size) {
1263 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1264 file, firmware->size);
1265 goto out_fw;
1266 }
1267
7585a5b0 1268 header = (void *)&firmware->data[0];
2159ad93
MB		 1269
1270 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1271 adsp_err(dsp, "%s: invalid magic\n", file);
1272 goto out_fw;
1273 }
1274
2323736d
CK		 1275 switch (header->ver) {
1276 case 0:
c61e59fe
CK		 1277 adsp_warn(dsp, "%s: Depreciated file format %d\n",
1278 file, header->ver);
1279 break;
2323736d 1280 case 1:
cb5b57a9 1281 case 2:
2323736d
CK		 1282 break;
1283 default:
2159ad93
MB		 1284 adsp_err(dsp, "%s: unknown file format %d\n",
1285 file, header->ver);
1286 goto out_fw;
1287 }
2323736d 1288
3626992a 1289 adsp_info(dsp, "Firmware version: %d\n", header->ver);
2323736d 1290 dsp->fw_ver = header->ver;
2159ad93
MB		 1291
1292 if (header->core != dsp->type) {
1293 adsp_err(dsp, "%s: invalid core %d != %d\n",
1294 file, header->core, dsp->type);
1295 goto out_fw;
1296 }
1297
1298 switch (dsp->type) {
1299 case WMFW_ADSP1:
1300 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1301 adsp1_sizes = (void *)&(header[1]);
1302 footer = (void *)&(adsp1_sizes[1]);
1303 sizes = sizeof(*adsp1_sizes);
1304
1305 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
1306 file, le32_to_cpu(adsp1_sizes->dm),
1307 le32_to_cpu(adsp1_sizes->pm),
1308 le32_to_cpu(adsp1_sizes->zm));
1309 break;
1310
1311 case WMFW_ADSP2:
1312 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
1313 adsp2_sizes = (void *)&(header[1]);
1314 footer = (void *)&(adsp2_sizes[1]);
1315 sizes = sizeof(*adsp2_sizes);
1316
1317 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
1318 file, le32_to_cpu(adsp2_sizes->xm),
1319 le32_to_cpu(adsp2_sizes->ym),
1320 le32_to_cpu(adsp2_sizes->pm),
1321 le32_to_cpu(adsp2_sizes->zm));
1322 break;
1323
1324 default:
6c452bda 1325 WARN(1, "Unknown DSP type");
2159ad93
MB		 1326 goto out_fw;
1327 }
1328
1329 if (le32_to_cpu(header->len) != sizeof(*header) +
1330 sizes + sizeof(*footer)) {
1331 adsp_err(dsp, "%s: unexpected header length %d\n",
1332 file, le32_to_cpu(header->len));
1333 goto out_fw;
1334 }
1335
1336 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1337 le64_to_cpu(footer->timestamp));
1338
1339 while (pos < firmware->size &&
1340 pos - firmware->size > sizeof(*region)) {
1341 region = (void *)&(firmware->data[pos]);
1342 region_name = "Unknown";
1343 reg = 0;
1344 text = NULL;
1345 offset = le32_to_cpu(region->offset) & 0xffffff;
1346 type = be32_to_cpu(region->type) & 0xff;
1347 mem = wm_adsp_find_region(dsp, type);
7585a5b0 1348
2159ad93
MB		 1349 switch (type) {
1350 case WMFW_NAME_TEXT:
1351 region_name = "Firmware name";
1352 text = kzalloc(le32_to_cpu(region->len) + 1,
1353 GFP_KERNEL);
1354 break;
2323736d
CK		 1355 case WMFW_ALGORITHM_DATA:
1356 region_name = "Algorithm";
1357 ret = wm_adsp_parse_coeff(dsp, region);
1358 if (ret != 0)
1359 goto out_fw;
1360 break;
2159ad93
MB		 1361 case WMFW_INFO_TEXT:
1362 region_name = "Information";
1363 text = kzalloc(le32_to_cpu(region->len) + 1,
1364 GFP_KERNEL);
1365 break;
1366 case WMFW_ABSOLUTE:
1367 region_name = "Absolute";
1368 reg = offset;
1369 break;
1370 case WMFW_ADSP1_PM:
2159ad93 1371 region_name = "PM";
45b9ee72 1372 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1373 break;
1374 case WMFW_ADSP1_DM:
2159ad93 1375 region_name = "DM";
45b9ee72 1376 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1377 break;
1378 case WMFW_ADSP2_XM:
2159ad93 1379 region_name = "XM";
45b9ee72 1380 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1381 break;
1382 case WMFW_ADSP2_YM:
2159ad93 1383 region_name = "YM";
45b9ee72 1384 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1385 break;
1386 case WMFW_ADSP1_ZM:
2159ad93 1387 region_name = "ZM";
45b9ee72 1388 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1389 break;
1390 default:
1391 adsp_warn(dsp,
1392 "%s.%d: Unknown region type %x at %d(%x)\n",
1393 file, regions, type, pos, pos);
1394 break;
1395 }
1396
1397 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1398 regions, le32_to_cpu(region->len), offset,
1399 region_name);
1400
1401 if (text) {
1402 memcpy(text, region->data, le32_to_cpu(region->len));
1403 adsp_info(dsp, "%s: %s\n", file, text);
1404 kfree(text);
1405 }
1406
1407 if (reg) {
cdcd7f72
CK		 1408 buf = wm_adsp_buf_alloc(region->data,
1409 le32_to_cpu(region->len),
1410 &buf_list);
1411 if (!buf) {
1412 adsp_err(dsp, "Out of memory\n");
1413 ret = -ENOMEM;
1414 goto out_fw;
1415 }
c1a7898d 1416
cdcd7f72
CK		 1417 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1418 le32_to_cpu(region->len));
1419 if (ret != 0) {
1420 adsp_err(dsp,
1421 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1422 file, regions,
1423 le32_to_cpu(region->len), offset,
1424 region_name, ret);
1425 goto out_fw;
2159ad93
MB		 1426 }
1427 }
1428
1429 pos += le32_to_cpu(region->len) + sizeof(*region);
1430 regions++;
1431 }
cf17c83c
MB		 1432
1433 ret = regmap_async_complete(regmap);
1434 if (ret != 0) {
1435 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1436 goto out_fw;
1437 }
1438
2159ad93
MB		 1439 if (pos > firmware->size)
1440 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1441 file, regions, pos - firmware->size);
1442
f9f55e31
RF		 1443 wm_adsp_debugfs_save_wmfwname(dsp, file);
1444
2159ad93 1445out_fw:
cf17c83c
MB		 1446 regmap_async_complete(regmap);
1447 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 1448 release_firmware(firmware);
1449out:
1450 kfree(file);
1451
1452 return ret;
1453}
1454
2323736d
CK		 1455static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
1456 const struct wm_adsp_alg_region *alg_region)
1457{
1458 struct wm_coeff_ctl *ctl;
1459
1460 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1461 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
1462 alg_region->alg == ctl->alg_region.alg &&
1463 alg_region->type == ctl->alg_region.type) {
1464 ctl->alg_region.base = alg_region->base;
1465 }
1466 }
1467}
1468
3809f001 1469static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
b618a185 1470 unsigned int pos, unsigned int len)
db40517c 1471{
b618a185
CK		 1472 void *alg;
1473 int ret;
db40517c 1474 __be32 val;
db40517c 1475
3809f001 1476 if (n_algs == 0) {
b618a185
CK		 1477 adsp_err(dsp, "No algorithms\n");
1478 return ERR_PTR(-EINVAL);
db40517c
MB		 1479 }
1480
3809f001
CK		 1481 if (n_algs > 1024) {
1482 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
b618a185
CK		 1483 return ERR_PTR(-EINVAL);
1484 }
db40517c 1485
b618a185
CK		 1486 /* Read the terminator first to validate the length */
1487 ret = regmap_raw_read(dsp->regmap, pos + len, &val, sizeof(val));
1488 if (ret != 0) {
1489 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1490 ret);
1491 return ERR_PTR(ret);
1492 }
db40517c 1493
b618a185
CK		 1494 if (be32_to_cpu(val) != 0xbedead)
1495 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
1496 pos + len, be32_to_cpu(val));
d62f4bc6 1497
b618a185
CK		 1498 alg = kzalloc(len * 2, GFP_KERNEL | GFP_DMA);
1499 if (!alg)
1500 return ERR_PTR(-ENOMEM);
db40517c 1501
b618a185
CK		 1502 ret = regmap_raw_read(dsp->regmap, pos, alg, len * 2);
1503 if (ret != 0) {
1504 adsp_err(dsp, "Failed to read algorithm list: %d\n",
1505 ret);
1506 kfree(alg);
1507 return ERR_PTR(ret);
1508 }
ac50009f 1509
b618a185
CK		 1510 return alg;
1511}
ac50009f 1512
14197095
CK		 1513static struct wm_adsp_alg_region *
1514 wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id)
1515{
1516 struct wm_adsp_alg_region *alg_region;
1517
1518 list_for_each_entry(alg_region, &dsp->alg_regions, list) {
1519 if (id == alg_region->alg && type == alg_region->type)
1520 return alg_region;
1521 }
1522
1523 return NULL;
1524}
1525
d9d20e17
CK		 1526static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
1527 int type, __be32 id,
1528 __be32 base)
1529{
1530 struct wm_adsp_alg_region *alg_region;
1531
1532 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
1533 if (!alg_region)
1534 return ERR_PTR(-ENOMEM);
1535
1536 alg_region->type = type;
1537 alg_region->alg = be32_to_cpu(id);
1538 alg_region->base = be32_to_cpu(base);
1539
1540 list_add_tail(&alg_region->list, &dsp->alg_regions);
1541
2323736d
CK		 1542 if (dsp->fw_ver > 0)
1543 wm_adsp_ctl_fixup_base(dsp, alg_region);
1544
d9d20e17
CK		 1545 return alg_region;
1546}
1547
b618a185
CK		 1548static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
1549{
1550 struct wmfw_adsp1_id_hdr adsp1_id;
1551 struct wmfw_adsp1_alg_hdr *adsp1_alg;
3809f001 1552 struct wm_adsp_alg_region *alg_region;
b618a185
CK		 1553 const struct wm_adsp_region *mem;
1554 unsigned int pos, len;
3809f001 1555 size_t n_algs;
b618a185 1556 int i, ret;
db40517c 1557
b618a185
CK		 1558 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
1559 if (WARN_ON(!mem))
1560 return -EINVAL;
1561
1562 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
1563 sizeof(adsp1_id));
1564 if (ret != 0) {
1565 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1566 ret);
1567 return ret;
1568 }
db40517c 1569
3809f001 1570 n_algs = be32_to_cpu(adsp1_id.n_algs);
b618a185
CK		 1571 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
1572 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1573 dsp->fw_id,
1574 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
1575 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
1576 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
3809f001 1577 n_algs);
b618a185 1578
d9d20e17
CK		 1579 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1580 adsp1_id.fw.id, adsp1_id.zm);
1581 if (IS_ERR(alg_region))
1582 return PTR_ERR(alg_region);
d62f4bc6 1583
d9d20e17
CK		 1584 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1585 adsp1_id.fw.id, adsp1_id.dm);
1586 if (IS_ERR(alg_region))
1587 return PTR_ERR(alg_region);
db40517c 1588
b618a185 1589 pos = sizeof(adsp1_id) / 2;
3809f001 1590 len = (sizeof(*adsp1_alg) * n_algs) / 2;
b618a185 1591
3809f001 1592 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
b618a185
CK		 1593 if (IS_ERR(adsp1_alg))
1594 return PTR_ERR(adsp1_alg);
1595
3809f001 1596 for (i = 0; i < n_algs; i++) {
b618a185
CK		 1597 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
1598 i, be32_to_cpu(adsp1_alg[i].alg.id),
1599 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
1600 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
1601 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
1602 be32_to_cpu(adsp1_alg[i].dm),
1603 be32_to_cpu(adsp1_alg[i].zm));
ac50009f 1604
d9d20e17
CK		 1605 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1606 adsp1_alg[i].alg.id,
1607 adsp1_alg[i].dm);
1608 if (IS_ERR(alg_region)) {
1609 ret = PTR_ERR(alg_region);
b618a185
CK		 1610 goto out;
1611 }
2323736d
CK		 1612 if (dsp->fw_ver == 0) {
1613 if (i + 1 < n_algs) {
1614 len = be32_to_cpu(adsp1_alg[i + 1].dm);
1615 len -= be32_to_cpu(adsp1_alg[i].dm);
1616 len *= 4;
1617 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1618 len, NULL, 0, 0);
2323736d
CK		 1619 } else {
1620 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
1621 be32_to_cpu(adsp1_alg[i].alg.id));
1622 }
b618a185 1623 }
ac50009f 1624
d9d20e17
CK		 1625 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1626 adsp1_alg[i].alg.id,
1627 adsp1_alg[i].zm);
1628 if (IS_ERR(alg_region)) {
1629 ret = PTR_ERR(alg_region);
b618a185
CK		 1630 goto out;
1631 }
2323736d
CK		 1632 if (dsp->fw_ver == 0) {
1633 if (i + 1 < n_algs) {
1634 len = be32_to_cpu(adsp1_alg[i + 1].zm);
1635 len -= be32_to_cpu(adsp1_alg[i].zm);
1636 len *= 4;
1637 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1638 len, NULL, 0, 0);
2323736d
CK		 1639 } else {
1640 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1641 be32_to_cpu(adsp1_alg[i].alg.id));
1642 }
b618a185 1643 }
db40517c
MB		 1644 }
1645
b618a185
CK		 1646out:
1647 kfree(adsp1_alg);
1648 return ret;
1649}
db40517c 1650
b618a185
CK		 1651static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
1652{
1653 struct wmfw_adsp2_id_hdr adsp2_id;
1654 struct wmfw_adsp2_alg_hdr *adsp2_alg;
3809f001 1655 struct wm_adsp_alg_region *alg_region;
b618a185
CK		 1656 const struct wm_adsp_region *mem;
1657 unsigned int pos, len;
3809f001 1658 size_t n_algs;
b618a185
CK		 1659 int i, ret;
1660
1661 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
1662 if (WARN_ON(!mem))
d62f4bc6 1663 return -EINVAL;
d62f4bc6 1664
b618a185
CK		 1665 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
1666 sizeof(adsp2_id));
db40517c 1667 if (ret != 0) {
b618a185
CK		 1668 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1669 ret);
db40517c
MB		 1670 return ret;
1671 }
1672
3809f001 1673 n_algs = be32_to_cpu(adsp2_id.n_algs);
b618a185 1674 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
f9f55e31 1675 dsp->fw_id_version = be32_to_cpu(adsp2_id.fw.ver);
b618a185
CK		 1676 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1677 dsp->fw_id,
f9f55e31
RF		 1678 (dsp->fw_id_version & 0xff0000) >> 16,
1679 (dsp->fw_id_version & 0xff00) >> 8,
1680 dsp->fw_id_version & 0xff,
3809f001 1681 n_algs);
b618a185 1682
d9d20e17
CK		 1683 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1684 adsp2_id.fw.id, adsp2_id.xm);
1685 if (IS_ERR(alg_region))
1686 return PTR_ERR(alg_region);
db40517c 1687
d9d20e17
CK		 1688 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1689 adsp2_id.fw.id, adsp2_id.ym);
1690 if (IS_ERR(alg_region))
1691 return PTR_ERR(alg_region);
db40517c 1692
d9d20e17
CK		 1693 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
1694 adsp2_id.fw.id, adsp2_id.zm);
1695 if (IS_ERR(alg_region))
1696 return PTR_ERR(alg_region);
db40517c 1697
b618a185 1698 pos = sizeof(adsp2_id) / 2;
3809f001 1699 len = (sizeof(*adsp2_alg) * n_algs) / 2;
db40517c 1700
3809f001 1701 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
b618a185
CK		 1702 if (IS_ERR(adsp2_alg))
1703 return PTR_ERR(adsp2_alg);
471f4885 1704
3809f001 1705 for (i = 0; i < n_algs; i++) {
b618a185
CK		 1706 adsp_info(dsp,
1707 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
1708 i, be32_to_cpu(adsp2_alg[i].alg.id),
1709 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
1710 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
1711 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
1712 be32_to_cpu(adsp2_alg[i].xm),
1713 be32_to_cpu(adsp2_alg[i].ym),
1714 be32_to_cpu(adsp2_alg[i].zm));
db40517c 1715
d9d20e17
CK		 1716 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1717 adsp2_alg[i].alg.id,
1718 adsp2_alg[i].xm);
1719 if (IS_ERR(alg_region)) {
1720 ret = PTR_ERR(alg_region);
b618a185
CK		 1721 goto out;
1722 }
2323736d
CK		 1723 if (dsp->fw_ver == 0) {
1724 if (i + 1 < n_algs) {
1725 len = be32_to_cpu(adsp2_alg[i + 1].xm);
1726 len -= be32_to_cpu(adsp2_alg[i].xm);
1727 len *= 4;
1728 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1729 len, NULL, 0, 0);
2323736d
CK		 1730 } else {
1731 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
1732 be32_to_cpu(adsp2_alg[i].alg.id));
1733 }
b618a185 1734 }
471f4885 1735
d9d20e17
CK		 1736 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1737 adsp2_alg[i].alg.id,
1738 adsp2_alg[i].ym);
1739 if (IS_ERR(alg_region)) {
1740 ret = PTR_ERR(alg_region);
b618a185
CK		 1741 goto out;
1742 }
2323736d
CK		 1743 if (dsp->fw_ver == 0) {
1744 if (i + 1 < n_algs) {
1745 len = be32_to_cpu(adsp2_alg[i + 1].ym);
1746 len -= be32_to_cpu(adsp2_alg[i].ym);
1747 len *= 4;
1748 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1749 len, NULL, 0, 0);
2323736d
CK		 1750 } else {
1751 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
1752 be32_to_cpu(adsp2_alg[i].alg.id));
1753 }
b618a185 1754 }
471f4885 1755
d9d20e17
CK		 1756 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
1757 adsp2_alg[i].alg.id,
1758 adsp2_alg[i].zm);
1759 if (IS_ERR(alg_region)) {
1760 ret = PTR_ERR(alg_region);
b618a185
CK		 1761 goto out;
1762 }
2323736d
CK		 1763 if (dsp->fw_ver == 0) {
1764 if (i + 1 < n_algs) {
1765 len = be32_to_cpu(adsp2_alg[i + 1].zm);
1766 len -= be32_to_cpu(adsp2_alg[i].zm);
1767 len *= 4;
1768 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1769 len, NULL, 0, 0);
2323736d
CK		 1770 } else {
1771 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1772 be32_to_cpu(adsp2_alg[i].alg.id));
1773 }
db40517c
MB		 1774 }
1775 }
1776
1777out:
b618a185 1778 kfree(adsp2_alg);
db40517c
MB		 1779 return ret;
1780}
1781
2159ad93
MB		 1782static int wm_adsp_load_coeff(struct wm_adsp *dsp)
1783{
cf17c83c 1784 LIST_HEAD(buf_list);
2159ad93
MB		 1785 struct regmap *regmap = dsp->regmap;
1786 struct wmfw_coeff_hdr *hdr;
1787 struct wmfw_coeff_item *blk;
1788 const struct firmware *firmware;
471f4885
MB		 1789 const struct wm_adsp_region *mem;
1790 struct wm_adsp_alg_region *alg_region;
2159ad93
MB		 1791 const char *region_name;
1792 int ret, pos, blocks, type, offset, reg;
1793 char *file;
cf17c83c 1794 struct wm_adsp_buf *buf;
2159ad93
MB		 1795
1796 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1797 if (file == NULL)
1798 return -ENOMEM;
1799
1023dbd9
MB		 1800 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
1801 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 1802 file[PAGE_SIZE - 1] = '\0';
1803
1804 ret = request_firmware(&firmware, file, dsp->dev);
1805 if (ret != 0) {
1806 adsp_warn(dsp, "Failed to request '%s'\n", file);
1807 ret = 0;
1808 goto out;
1809 }
1810 ret = -EINVAL;
1811
1812 if (sizeof(*hdr) >= firmware->size) {
1813 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1814 file, firmware->size);
1815 goto out_fw;
1816 }
1817
7585a5b0 1818 hdr = (void *)&firmware->data[0];
2159ad93
MB		 1819 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
1820 adsp_err(dsp, "%s: invalid magic\n", file);
a4cdbec7 1821 goto out_fw;
2159ad93
MB		 1822 }
1823
c712326d
MB		 1824 switch (be32_to_cpu(hdr->rev) & 0xff) {
1825 case 1:
1826 break;
1827 default:
1828 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
1829 file, be32_to_cpu(hdr->rev) & 0xff);
1830 ret = -EINVAL;
1831 goto out_fw;
1832 }
1833
2159ad93
MB		 1834 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
1835 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
1836 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
1837 le32_to_cpu(hdr->ver) & 0xff);
1838
1839 pos = le32_to_cpu(hdr->len);
1840
1841 blocks = 0;
1842 while (pos < firmware->size &&
1843 pos - firmware->size > sizeof(*blk)) {
7585a5b0 1844 blk = (void *)(&firmware->data[pos]);
2159ad93 1845
c712326d
MB		 1846 type = le16_to_cpu(blk->type);
1847 offset = le16_to_cpu(blk->offset);
2159ad93
MB		 1848
1849 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
1850 file, blocks, le32_to_cpu(blk->id),
1851 (le32_to_cpu(blk->ver) >> 16) & 0xff,
1852 (le32_to_cpu(blk->ver) >> 8) & 0xff,
1853 le32_to_cpu(blk->ver) & 0xff);
1854 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
1855 file, blocks, le32_to_cpu(blk->len), offset, type);
1856
1857 reg = 0;
1858 region_name = "Unknown";
1859 switch (type) {
c712326d
MB		 1860 case (WMFW_NAME_TEXT << 8):
1861 case (WMFW_INFO_TEXT << 8):
2159ad93 1862 break;
c712326d 1863 case (WMFW_ABSOLUTE << 8):
f395a218
MB		 1864 /*
1865 * Old files may use this for global
1866 * coefficients.
1867 */
1868 if (le32_to_cpu(blk->id) == dsp->fw_id &&
1869 offset == 0) {
1870 region_name = "global coefficients";
1871 mem = wm_adsp_find_region(dsp, type);
1872 if (!mem) {
1873 adsp_err(dsp, "No ZM\n");
1874 break;
1875 }
1876 reg = wm_adsp_region_to_reg(mem, 0);
1877
1878 } else {
1879 region_name = "register";
1880 reg = offset;
1881 }
2159ad93 1882 break;
471f4885
MB		 1883
1884 case WMFW_ADSP1_DM:
1885 case WMFW_ADSP1_ZM:
1886 case WMFW_ADSP2_XM:
1887 case WMFW_ADSP2_YM:
1888 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
1889 file, blocks, le32_to_cpu(blk->len),
1890 type, le32_to_cpu(blk->id));
1891
1892 mem = wm_adsp_find_region(dsp, type);
1893 if (!mem) {
1894 adsp_err(dsp, "No base for region %x\n", type);
1895 break;
1896 }
1897
14197095
CK		 1898 alg_region = wm_adsp_find_alg_region(dsp, type,
1899 le32_to_cpu(blk->id));
1900 if (alg_region) {
1901 reg = alg_region->base;
1902 reg = wm_adsp_region_to_reg(mem, reg);
1903 reg += offset;
1904 } else {
471f4885
MB		 1905 adsp_err(dsp, "No %x for algorithm %x\n",
1906 type, le32_to_cpu(blk->id));
14197095 1907 }
471f4885
MB		 1908 break;
1909
2159ad93 1910 default:
25c62f7e
MB		 1911 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
1912 file, blocks, type, pos);
2159ad93
MB		 1913 break;
1914 }
1915
1916 if (reg) {
cf17c83c
MB		 1917 buf = wm_adsp_buf_alloc(blk->data,
1918 le32_to_cpu(blk->len),
1919 &buf_list);
a76fefab
MB		 1920 if (!buf) {
1921 adsp_err(dsp, "Out of memory\n");
f4b82812
WY		 1922 ret = -ENOMEM;
1923 goto out_fw;
a76fefab
MB		 1924 }
1925
20da6d5a
MB		 1926 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
1927 file, blocks, le32_to_cpu(blk->len),
1928 reg);
cf17c83c
MB		 1929 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1930 le32_to_cpu(blk->len));
2159ad93
MB		 1931 if (ret != 0) {
1932 adsp_err(dsp,
43bc3bf6
DP		 1933 "%s.%d: Failed to write to %x in %s: %d\n",
1934 file, blocks, reg, region_name, ret);
2159ad93
MB		 1935 }
1936 }
1937
be951017 1938 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
2159ad93
MB		 1939 blocks++;
1940 }
1941
cf17c83c
MB		 1942 ret = regmap_async_complete(regmap);
1943 if (ret != 0)
1944 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1945
2159ad93
MB		 1946 if (pos > firmware->size)
1947 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1948 file, blocks, pos - firmware->size);
1949
f9f55e31
RF		 1950 wm_adsp_debugfs_save_binname(dsp, file);
1951
2159ad93 1952out_fw:
9da7a5a9 1953 regmap_async_complete(regmap);
2159ad93 1954 release_firmware(firmware);
cf17c83c 1955 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 1956out:
1957 kfree(file);
f4b82812 1958 return ret;
2159ad93
MB		 1959}
1960
3809f001 1961int wm_adsp1_init(struct wm_adsp *dsp)
5e7a7a22 1962{
3809f001 1963 INIT_LIST_HEAD(&dsp->alg_regions);
5e7a7a22 1964
078e7183
CK		 1965 mutex_init(&dsp->pwr_lock);
1966
5e7a7a22
MB		 1967 return 0;
1968}
1969EXPORT_SYMBOL_GPL(wm_adsp1_init);
1970
2159ad93
MB		 1971int wm_adsp1_event(struct snd_soc_dapm_widget *w,
1972 struct snd_kcontrol *kcontrol,
1973 int event)
1974{
72718517 1975 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2159ad93
MB		 1976 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1977 struct wm_adsp *dsp = &dsps[w->shift];
b0101b4f 1978 struct wm_adsp_alg_region *alg_region;
6ab2b7b4 1979 struct wm_coeff_ctl *ctl;
2159ad93 1980 int ret;
7585a5b0 1981 unsigned int val;
2159ad93 1982
00200107 1983 dsp->card = codec->component.card;
92bb4c32 1984
078e7183
CK		 1985 mutex_lock(&dsp->pwr_lock);
1986
2159ad93
MB		 1987 switch (event) {
1988 case SND_SOC_DAPM_POST_PMU:
1989 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1990 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
1991
94e205bf
CR		 1992 /*
1993 * For simplicity set the DSP clock rate to be the
1994 * SYSCLK rate rather than making it configurable.
1995 */
7585a5b0 1996 if (dsp->sysclk_reg) {
94e205bf
CR		 1997 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
1998 if (ret != 0) {
1999 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
2000 ret);
078e7183 2001 goto err_mutex;
94e205bf
CR		 2002 }
2003
2004 val = (val & dsp->sysclk_mask)
2005 >> dsp->sysclk_shift;
2006
2007 ret = regmap_update_bits(dsp->regmap,
2008 dsp->base + ADSP1_CONTROL_31,
2009 ADSP1_CLK_SEL_MASK, val);
2010 if (ret != 0) {
2011 adsp_err(dsp, "Failed to set clock rate: %d\n",
2012 ret);
078e7183 2013 goto err_mutex;
94e205bf
CR		 2014 }
2015 }
2016
2159ad93
MB		 2017 ret = wm_adsp_load(dsp);
2018 if (ret != 0)
078e7183 2019 goto err_ena;
2159ad93 2020
b618a185 2021 ret = wm_adsp1_setup_algs(dsp);
db40517c 2022 if (ret != 0)
078e7183 2023 goto err_ena;
db40517c 2024
2159ad93
MB		 2025 ret = wm_adsp_load_coeff(dsp);
2026 if (ret != 0)
078e7183 2027 goto err_ena;
2159ad93 2028
0c2e3f34 2029 /* Initialize caches for enabled and unset controls */
81ad93ec 2030 ret = wm_coeff_init_control_caches(dsp);
6ab2b7b4 2031 if (ret != 0)
078e7183 2032 goto err_ena;
6ab2b7b4 2033
0c2e3f34 2034 /* Sync set controls */
81ad93ec 2035 ret = wm_coeff_sync_controls(dsp);
6ab2b7b4 2036 if (ret != 0)
078e7183 2037 goto err_ena;
6ab2b7b4 2038
2159ad93
MB		 2039 /* Start the core running */
2040 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2041 ADSP1_CORE_ENA | ADSP1_START,
2042 ADSP1_CORE_ENA | ADSP1_START);
2043 break;
2044
2045 case SND_SOC_DAPM_PRE_PMD:
2046 /* Halt the core */
2047 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2048 ADSP1_CORE_ENA | ADSP1_START, 0);
2049
2050 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
2051 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
2052
2053 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2054 ADSP1_SYS_ENA, 0);
6ab2b7b4 2055
81ad93ec 2056 list_for_each_entry(ctl, &dsp->ctl_list, list)
6ab2b7b4 2057 ctl->enabled = 0;
b0101b4f
DP		 2058
2059 while (!list_empty(&dsp->alg_regions)) {
2060 alg_region = list_first_entry(&dsp->alg_regions,
2061 struct wm_adsp_alg_region,
2062 list);
2063 list_del(&alg_region->list);
2064 kfree(alg_region);
2065 }
2159ad93
MB		 2066 break;
2067
2068 default:
2069 break;
2070 }
2071
078e7183
CK		 2072 mutex_unlock(&dsp->pwr_lock);
2073
2159ad93
MB		 2074 return 0;
2075
078e7183 2076err_ena:
2159ad93
MB		 2077 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2078 ADSP1_SYS_ENA, 0);
078e7183
CK		 2079err_mutex:
2080 mutex_unlock(&dsp->pwr_lock);
2081
2159ad93
MB		 2082 return ret;
2083}
2084EXPORT_SYMBOL_GPL(wm_adsp1_event);
2085
2086static int wm_adsp2_ena(struct wm_adsp *dsp)
2087{
2088 unsigned int val;
2089 int ret, count;
2090
1552c325
MB		 2091 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
2092 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2159ad93
MB		 2093 if (ret != 0)
2094 return ret;
2095
2096 /* Wait for the RAM to start, should be near instantaneous */
939fd1e8 2097 for (count = 0; count < 10; ++count) {
2159ad93
MB		 2098 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1,
2099 &val);
2100 if (ret != 0)
2101 return ret;
939fd1e8
CK		 2102
2103 if (val & ADSP2_RAM_RDY)
2104 break;
2105
2106 msleep(1);
2107 }
2159ad93
MB		 2108
2109 if (!(val & ADSP2_RAM_RDY)) {
2110 adsp_err(dsp, "Failed to start DSP RAM\n");
2111 return -EBUSY;
2112 }
2113
2114 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
2159ad93
MB		 2115
2116 return 0;
2117}
2118
18b1a902 2119static void wm_adsp2_boot_work(struct work_struct *work)
2159ad93 2120{
d8a64d6a
CK		 2121 struct wm_adsp *dsp = container_of(work,
2122 struct wm_adsp,
2123 boot_work);
2159ad93 2124 int ret;
d8a64d6a 2125 unsigned int val;
2159ad93 2126
078e7183
CK		 2127 mutex_lock(&dsp->pwr_lock);
2128
d8a64d6a
CK		 2129 /*
2130 * For simplicity set the DSP clock rate to be the
2131 * SYSCLK rate rather than making it configurable.
2132 */
2133 ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
2134 if (ret != 0) {
2135 adsp_err(dsp, "Failed to read SYSCLK state: %d\n", ret);
078e7183 2136 goto err_mutex;
d8a64d6a
CK		 2137 }
2138 val = (val & ARIZONA_SYSCLK_FREQ_MASK)
2139 >> ARIZONA_SYSCLK_FREQ_SHIFT;
92bb4c32 2140
d8a64d6a
CK		 2141 ret = regmap_update_bits_async(dsp->regmap,
2142 dsp->base + ADSP2_CLOCKING,
2143 ADSP2_CLK_SEL_MASK, val);
2144 if (ret != 0) {
2145 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
078e7183 2146 goto err_mutex;
d8a64d6a 2147 }
dd49e2c8 2148
d8a64d6a
CK		 2149 ret = wm_adsp2_ena(dsp);
2150 if (ret != 0)
078e7183 2151 goto err_mutex;
2159ad93 2152
d8a64d6a
CK		 2153 ret = wm_adsp_load(dsp);
2154 if (ret != 0)
078e7183 2155 goto err_ena;
2159ad93 2156
b618a185 2157 ret = wm_adsp2_setup_algs(dsp);
d8a64d6a 2158 if (ret != 0)
078e7183 2159 goto err_ena;
db40517c 2160
d8a64d6a
CK		 2161 ret = wm_adsp_load_coeff(dsp);
2162 if (ret != 0)
078e7183 2163 goto err_ena;
2159ad93 2164
d8a64d6a
CK		 2165 /* Initialize caches for enabled and unset controls */
2166 ret = wm_coeff_init_control_caches(dsp);
2167 if (ret != 0)
078e7183 2168 goto err_ena;
6ab2b7b4 2169
d8a64d6a
CK		 2170 /* Sync set controls */
2171 ret = wm_coeff_sync_controls(dsp);
2172 if (ret != 0)
078e7183 2173 goto err_ena;
d8a64d6a 2174
d8a64d6a
CK		 2175 dsp->running = true;
2176
078e7183
CK		 2177 mutex_unlock(&dsp->pwr_lock);
2178
d8a64d6a 2179 return;
6ab2b7b4 2180
078e7183 2181err_ena:
d8a64d6a
CK		 2182 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2183 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
078e7183
CK		 2184err_mutex:
2185 mutex_unlock(&dsp->pwr_lock);
d8a64d6a
CK		 2186}
2187
12db5edd
CK		 2188int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
2189 struct snd_kcontrol *kcontrol, int event)
2190{
72718517 2191 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
12db5edd
CK		 2192 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2193 struct wm_adsp *dsp = &dsps[w->shift];
2194
00200107 2195 dsp->card = codec->component.card;
12db5edd
CK		 2196
2197 switch (event) {
2198 case SND_SOC_DAPM_PRE_PMU:
2199 queue_work(system_unbound_wq, &dsp->boot_work);
2200 break;
2201 default:
2202 break;
cab27258 2203 }
12db5edd
CK		 2204
2205 return 0;
2206}
2207EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
2208
d8a64d6a
CK		 2209int wm_adsp2_event(struct snd_soc_dapm_widget *w,
2210 struct snd_kcontrol *kcontrol, int event)
2211{
72718517 2212 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
d8a64d6a
CK		 2213 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2214 struct wm_adsp *dsp = &dsps[w->shift];
2215 struct wm_adsp_alg_region *alg_region;
2216 struct wm_coeff_ctl *ctl;
2217 int ret;
2218
d8a64d6a
CK		 2219 switch (event) {
2220 case SND_SOC_DAPM_POST_PMU:
d8a64d6a
CK		 2221 flush_work(&dsp->boot_work);
2222
2223 if (!dsp->running)
2224 return -EIO;
6ab2b7b4 2225
d8a64d6a
CK		 2226 ret = regmap_update_bits(dsp->regmap,
2227 dsp->base + ADSP2_CONTROL,
00e4c3b6
CK		 2228 ADSP2_CORE_ENA | ADSP2_START,
2229 ADSP2_CORE_ENA | ADSP2_START);
2159ad93
MB		 2230 if (ret != 0)
2231 goto err;
2cd19bdb
CK		 2232
2233 if (wm_adsp_fw[dsp->fw].num_caps != 0)
2234 ret = wm_adsp_buffer_init(dsp);
2235
2159ad93
MB		 2236 break;
2237
2238 case SND_SOC_DAPM_PRE_PMD:
10337b07
RF		 2239 /* Log firmware state, it can be useful for analysis */
2240 wm_adsp2_show_fw_status(dsp);
2241
078e7183
CK		 2242 mutex_lock(&dsp->pwr_lock);
2243
f9f55e31
RF		 2244 wm_adsp_debugfs_clear(dsp);
2245
2246 dsp->fw_id = 0;
2247 dsp->fw_id_version = 0;
1023dbd9
MB		 2248 dsp->running = false;
2249
2159ad93 2250 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e
MB		 2251 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
2252 ADSP2_START, 0);
973838a0 2253
2d30b575
MB		 2254 /* Make sure DMAs are quiesced */
2255 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2256 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
2257 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2258
81ad93ec 2259 list_for_each_entry(ctl, &dsp->ctl_list, list)
6ab2b7b4 2260 ctl->enabled = 0;
6ab2b7b4 2261
471f4885
MB		 2262 while (!list_empty(&dsp->alg_regions)) {
2263 alg_region = list_first_entry(&dsp->alg_regions,
2264 struct wm_adsp_alg_region,
2265 list);
2266 list_del(&alg_region->list);
2267 kfree(alg_region);
2268 }
ddbc5efe 2269
2cd19bdb
CK		 2270 if (wm_adsp_fw[dsp->fw].num_caps != 0)
2271 wm_adsp_buffer_free(dsp);
2272
078e7183
CK		 2273 mutex_unlock(&dsp->pwr_lock);
2274
ddbc5efe 2275 adsp_dbg(dsp, "Shutdown complete\n");
2159ad93
MB		 2276 break;
2277
2278 default:
2279 break;
2280 }
2281
2282 return 0;
2283err:
2284 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e 2285 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2159ad93
MB		 2286 return ret;
2287}
2288EXPORT_SYMBOL_GPL(wm_adsp2_event);
973838a0 2289
f5e2ce92
RF		 2290int wm_adsp2_codec_probe(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2291{
f9f55e31
RF		 2292 wm_adsp2_init_debugfs(dsp, codec);
2293
218e5087 2294 return snd_soc_add_codec_controls(codec,
336d0442
RF		 2295 &wm_adsp_fw_controls[dsp->num - 1],
2296 1);
f5e2ce92
RF		 2297}
2298EXPORT_SYMBOL_GPL(wm_adsp2_codec_probe);
2299
2300int wm_adsp2_codec_remove(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2301{
f9f55e31
RF		 2302 wm_adsp2_cleanup_debugfs(dsp);
2303
f5e2ce92
RF		 2304 return 0;
2305}
2306EXPORT_SYMBOL_GPL(wm_adsp2_codec_remove);
2307
81ac58b1 2308int wm_adsp2_init(struct wm_adsp *dsp)
973838a0
MB		 2309{
2310 int ret;
2311
10a2b662
MB		 2312 /*
2313 * Disable the DSP memory by default when in reset for a small
2314 * power saving.
2315 */
3809f001 2316 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
10a2b662
MB		 2317 ADSP2_MEM_ENA, 0);
2318 if (ret != 0) {
3809f001 2319 adsp_err(dsp, "Failed to clear memory retention: %d\n", ret);
10a2b662
MB		 2320 return ret;
2321 }
2322
3809f001
CK		 2323 INIT_LIST_HEAD(&dsp->alg_regions);
2324 INIT_LIST_HEAD(&dsp->ctl_list);
2325 INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work);
6ab2b7b4 2326
078e7183
CK		 2327 mutex_init(&dsp->pwr_lock);
2328
973838a0
MB		 2329 return 0;
2330}
2331EXPORT_SYMBOL_GPL(wm_adsp2_init);
0a37c6ef 2332
406abc95
CK		 2333int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream)
2334{
2335 struct wm_adsp_compr *compr;
2336 int ret = 0;
2337
2338 mutex_lock(&dsp->pwr_lock);
2339
2340 if (wm_adsp_fw[dsp->fw].num_caps == 0) {
2341 adsp_err(dsp, "Firmware does not support compressed API\n");
2342 ret = -ENXIO;
2343 goto out;
2344 }
2345
2346 if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) {
2347 adsp_err(dsp, "Firmware does not support stream direction\n");
2348 ret = -EINVAL;
2349 goto out;
2350 }
2351
95fe9597
CK		 2352 if (dsp->compr) {
2353 /* It is expect this limitation will be removed in future */
2354 adsp_err(dsp, "Only a single stream supported per DSP\n");
2355 ret = -EBUSY;
2356 goto out;
2357 }
2358
406abc95
CK		 2359 compr = kzalloc(sizeof(*compr), GFP_KERNEL);
2360 if (!compr) {
2361 ret = -ENOMEM;
2362 goto out;
2363 }
2364
2365 compr->dsp = dsp;
2366 compr->stream = stream;
2367
2368 dsp->compr = compr;
2369
2370 stream->runtime->private_data = compr;
2371
2372out:
2373 mutex_unlock(&dsp->pwr_lock);
2374
2375 return ret;
2376}
2377EXPORT_SYMBOL_GPL(wm_adsp_compr_open);
2378
2379int wm_adsp_compr_free(struct snd_compr_stream *stream)
2380{
2381 struct wm_adsp_compr *compr = stream->runtime->private_data;
2382 struct wm_adsp *dsp = compr->dsp;
2383
2384 mutex_lock(&dsp->pwr_lock);
2385
2386 dsp->compr = NULL;
2387
2388 kfree(compr);
2389
2390 mutex_unlock(&dsp->pwr_lock);
2391
2392 return 0;
2393}
2394EXPORT_SYMBOL_GPL(wm_adsp_compr_free);
2395
2396static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
2397 struct snd_compr_params *params)
2398{
2399 struct wm_adsp_compr *compr = stream->runtime->private_data;
2400 struct wm_adsp *dsp = compr->dsp;
2401 const struct wm_adsp_fw_caps *caps;
2402 const struct snd_codec_desc *desc;
2403 int i, j;
2404
2405 if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE ||
2406 params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE ||
2407 params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS ||
2408 params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS ||
2409 params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) {
2410 adsp_err(dsp, "Invalid buffer fragsize=%d fragments=%d\n",
2411 params->buffer.fragment_size,
2412 params->buffer.fragments);
2413
2414 return -EINVAL;
2415 }
2416
2417 for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) {
2418 caps = &wm_adsp_fw[dsp->fw].caps[i];
2419 desc = &caps->desc;
2420
2421 if (caps->id != params->codec.id)
2422 continue;
2423
2424 if (stream->direction == SND_COMPRESS_PLAYBACK) {
2425 if (desc->max_ch < params->codec.ch_out)
2426 continue;
2427 } else {
2428 if (desc->max_ch < params->codec.ch_in)
2429 continue;
2430 }
2431
2432 if (!(desc->formats & (1 << params->codec.format)))
2433 continue;
2434
2435 for (j = 0; j < desc->num_sample_rates; ++j)
2436 if (desc->sample_rates[j] == params->codec.sample_rate)
2437 return 0;
2438 }
2439
2440 adsp_err(dsp, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
2441 params->codec.id, params->codec.ch_in, params->codec.ch_out,
2442 params->codec.sample_rate, params->codec.format);
2443 return -EINVAL;
2444}
2445
565ace46
CK		 2446static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr)
2447{
2448 return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE;
2449}
2450
406abc95
CK		 2451int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
2452 struct snd_compr_params *params)
2453{
2454 struct wm_adsp_compr *compr = stream->runtime->private_data;
2455 int ret;
2456
2457 ret = wm_adsp_compr_check_params(stream, params);
2458 if (ret)
2459 return ret;
2460
2461 compr->size = params->buffer;
2462
2463 adsp_dbg(compr->dsp, "fragment_size=%d fragments=%d\n",
2464 compr->size.fragment_size, compr->size.fragments);
2465
2466 return 0;
2467}
2468EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
2469
2470int wm_adsp_compr_get_caps(struct snd_compr_stream *stream,
2471 struct snd_compr_caps *caps)
2472{
2473 struct wm_adsp_compr *compr = stream->runtime->private_data;
2474 int fw = compr->dsp->fw;
2475 int i;
2476
2477 if (wm_adsp_fw[fw].caps) {
2478 for (i = 0; i < wm_adsp_fw[fw].num_caps; i++)
2479 caps->codecs[i] = wm_adsp_fw[fw].caps[i].id;
2480
2481 caps->num_codecs = i;
2482 caps->direction = wm_adsp_fw[fw].compr_direction;
2483
2484 caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE;
2485 caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE;
2486 caps->min_fragments = WM_ADSP_MIN_FRAGMENTS;
2487 caps->max_fragments = WM_ADSP_MAX_FRAGMENTS;
2488 }
2489
2490 return 0;
2491}
2492EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps);
2493
2cd19bdb
CK		 2494static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type,
2495 unsigned int mem_addr,
2496 unsigned int num_words, u32 *data)
2497{
2498 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
2499 unsigned int i, reg;
2500 int ret;
2501
2502 if (!mem)
2503 return -EINVAL;
2504
2505 reg = wm_adsp_region_to_reg(mem, mem_addr);
2506
2507 ret = regmap_raw_read(dsp->regmap, reg, data,
2508 sizeof(*data) * num_words);
2509 if (ret < 0)
2510 return ret;
2511
2512 for (i = 0; i < num_words; ++i)
2513 data[i] = be32_to_cpu(data[i]) & 0x00ffffffu;
2514
2515 return 0;
2516}
2517
2518static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type,
2519 unsigned int mem_addr, u32 *data)
2520{
2521 return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data);
2522}
2523
2524static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type,
2525 unsigned int mem_addr, u32 data)
2526{
2527 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
2528 unsigned int reg;
2529
2530 if (!mem)
2531 return -EINVAL;
2532
2533 reg = wm_adsp_region_to_reg(mem, mem_addr);
2534
2535 data = cpu_to_be32(data & 0x00ffffffu);
2536
2537 return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data));
2538}
2539
2540static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf,
2541 unsigned int field_offset, u32 *data)
2542{
2543 return wm_adsp_read_data_word(buf->dsp, WMFW_ADSP2_XM,
2544 buf->host_buf_ptr + field_offset, data);
2545}
2546
2547static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf,
2548 unsigned int field_offset, u32 data)
2549{
2550 return wm_adsp_write_data_word(buf->dsp, WMFW_ADSP2_XM,
2551 buf->host_buf_ptr + field_offset, data);
2552}
2553
2554static int wm_adsp_buffer_locate(struct wm_adsp_compr_buf *buf)
2555{
2556 struct wm_adsp_alg_region *alg_region;
2557 struct wm_adsp *dsp = buf->dsp;
2558 u32 xmalg, addr, magic;
2559 int i, ret;
2560
2561 alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id);
2562 xmalg = sizeof(struct wm_adsp_system_config_xm_hdr) / sizeof(__be32);
2563
2564 addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
2565 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic);
2566 if (ret < 0)
2567 return ret;
2568
2569 if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC)
2570 return -EINVAL;
2571
2572 addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
2573 for (i = 0; i < 5; ++i) {
2574 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr,
2575 &buf->host_buf_ptr);
2576 if (ret < 0)
2577 return ret;
2578
2579 if (buf->host_buf_ptr)
2580 break;
2581
2582 usleep_range(1000, 2000);
2583 }
2584
2585 if (!buf->host_buf_ptr)
2586 return -EIO;
2587
2588 adsp_dbg(dsp, "host_buf_ptr=%x\n", buf->host_buf_ptr);
2589
2590 return 0;
2591}
2592
2593static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf)
2594{
2595 const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps;
2596 struct wm_adsp_buffer_region *region;
2597 u32 offset = 0;
2598 int i, ret;
2599
2600 for (i = 0; i < caps->num_regions; ++i) {
2601 region = &buf->regions[i];
2602
2603 region->offset = offset;
2604 region->mem_type = caps->region_defs[i].mem_type;
2605
2606 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset,
2607 &region->base_addr);
2608 if (ret < 0)
2609 return ret;
2610
2611 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset,
2612 &offset);
2613 if (ret < 0)
2614 return ret;
2615
2616 region->cumulative_size = offset;
2617
2618 adsp_dbg(buf->dsp,
2619 "region=%d type=%d base=%04x off=%04x size=%04x\n",
2620 i, region->mem_type, region->base_addr,
2621 region->offset, region->cumulative_size);
2622 }
2623
2624 return 0;
2625}
2626
2627static int wm_adsp_buffer_init(struct wm_adsp *dsp)
2628{
2629 struct wm_adsp_compr_buf *buf;
2630 int ret;
2631
2632 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
2633 if (!buf)
2634 return -ENOMEM;
2635
2636 buf->dsp = dsp;
565ace46
CK		 2637 buf->read_index = -1;
2638 buf->irq_count = 0xFFFFFFFF;
2cd19bdb
CK		 2639
2640 ret = wm_adsp_buffer_locate(buf);
2641 if (ret < 0) {
2642 adsp_err(dsp, "Failed to acquire host buffer: %d\n", ret);
2643 goto err_buffer;
2644 }
2645
2646 buf->regions = kcalloc(wm_adsp_fw[dsp->fw].caps->num_regions,
2647 sizeof(*buf->regions), GFP_KERNEL);
2648 if (!buf->regions) {
2649 ret = -ENOMEM;
2650 goto err_buffer;
2651 }
2652
2653 ret = wm_adsp_buffer_populate(buf);
2654 if (ret < 0) {
2655 adsp_err(dsp, "Failed to populate host buffer: %d\n", ret);
2656 goto err_regions;
2657 }
2658
2659 dsp->buffer = buf;
2660
2661 return 0;
2662
2663err_regions:
2664 kfree(buf->regions);
2665err_buffer:
2666 kfree(buf);
2667 return ret;
2668}
2669
2670static int wm_adsp_buffer_free(struct wm_adsp *dsp)
2671{
2672 if (dsp->buffer) {
2673 kfree(dsp->buffer->regions);
2674 kfree(dsp->buffer);
2675
2676 dsp->buffer = NULL;
2677 }
2678
2679 return 0;
2680}
2681
95fe9597
CK		 2682static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr)
2683{
2684 return compr->buf != NULL;
2685}
2686
2687static int wm_adsp_compr_attach(struct wm_adsp_compr *compr)
2688{
2689 /*
2690 * Note this will be more complex once each DSP can support multiple
2691 * streams
2692 */
2693 if (!compr->dsp->buffer)
2694 return -EINVAL;
2695
2696 compr->buf = compr->dsp->buffer;
2697
2698 return 0;
2699}
2700
2701int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd)
2702{
2703 struct wm_adsp_compr *compr = stream->runtime->private_data;
2704 struct wm_adsp *dsp = compr->dsp;
2705 int ret = 0;
2706
2707 adsp_dbg(dsp, "Trigger: %d\n", cmd);
2708
2709 mutex_lock(&dsp->pwr_lock);
2710
2711 switch (cmd) {
2712 case SNDRV_PCM_TRIGGER_START:
2713 if (wm_adsp_compr_attached(compr))
2714 break;
2715
2716 ret = wm_adsp_compr_attach(compr);
2717 if (ret < 0) {
2718 adsp_err(dsp, "Failed to link buffer and stream: %d\n",
2719 ret);
2720 break;
2721 }
565ace46
CK		 2722
2723 /* Trigger the IRQ at one fragment of data */
2724 ret = wm_adsp_buffer_write(compr->buf,
2725 HOST_BUFFER_FIELD(high_water_mark),
2726 wm_adsp_compr_frag_words(compr));
2727 if (ret < 0) {
2728 adsp_err(dsp, "Failed to set high water mark: %d\n",
2729 ret);
2730 break;
2731 }
95fe9597
CK		 2732 break;
2733 case SNDRV_PCM_TRIGGER_STOP:
2734 break;
2735 default:
2736 ret = -EINVAL;
2737 break;
2738 }
2739
2740 mutex_unlock(&dsp->pwr_lock);
2741
2742 return ret;
2743}
2744EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger);
2745
565ace46
CK		 2746static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf)
2747{
2748 int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1;
2749
2750 return buf->regions[last_region].cumulative_size;
2751}
2752
2753static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf)
2754{
2755 u32 next_read_index, next_write_index;
2756 int write_index, read_index, avail;
2757 int ret;
2758
2759 /* Only sync read index if we haven't already read a valid index */
2760 if (buf->read_index < 0) {
2761 ret = wm_adsp_buffer_read(buf,
2762 HOST_BUFFER_FIELD(next_read_index),
2763 &next_read_index);
2764 if (ret < 0)
2765 return ret;
2766
2767 read_index = sign_extend32(next_read_index, 23);
2768
2769 if (read_index < 0) {
2770 adsp_dbg(buf->dsp, "Avail check on unstarted stream\n");
2771 return 0;
2772 }
2773
2774 buf->read_index = read_index;
2775 }
2776
2777 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index),
2778 &next_write_index);
2779 if (ret < 0)
2780 return ret;
2781
2782 write_index = sign_extend32(next_write_index, 23);
2783
2784 avail = write_index - buf->read_index;
2785 if (avail < 0)
2786 avail += wm_adsp_buffer_size(buf);
2787
2788 adsp_dbg(buf->dsp, "readindex=0x%x, writeindex=0x%x, avail=%d\n",
2789 buf->read_index, write_index, avail);
2790
2791 buf->avail = avail;
2792
2793 return 0;
2794}
2795
2796int wm_adsp_compr_handle_irq(struct wm_adsp *dsp)
2797{
2798 struct wm_adsp_compr_buf *buf = dsp->buffer;
2799 int ret = 0;
2800
2801 mutex_lock(&dsp->pwr_lock);
2802
2803 if (!buf) {
2804 adsp_err(dsp, "Spurious buffer IRQ\n");
2805 ret = -ENODEV;
2806 goto out;
2807 }
2808
2809 adsp_dbg(dsp, "Handling buffer IRQ\n");
2810
2811 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error);
2812 if (ret < 0) {
2813 adsp_err(dsp, "Failed to check buffer error: %d\n", ret);
2814 goto out;
2815 }
2816 if (buf->error != 0) {
2817 adsp_err(dsp, "Buffer error occurred: %d\n", buf->error);
2818 ret = -EIO;
2819 goto out;
2820 }
2821
2822 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count),
2823 &buf->irq_count);
2824 if (ret < 0) {
2825 adsp_err(dsp, "Failed to get irq_count: %d\n", ret);
2826 goto out;
2827 }
2828
2829 ret = wm_adsp_buffer_update_avail(buf);
2830 if (ret < 0) {
2831 adsp_err(dsp, "Error reading avail: %d\n", ret);
2832 goto out;
2833 }
2834
2835out:
2836 mutex_unlock(&dsp->pwr_lock);
2837
2838 return ret;
2839}
2840EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq);
2841
2842static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf)
2843{
2844 if (buf->irq_count & 0x01)
2845 return 0;
2846
2847 adsp_dbg(buf->dsp, "Enable IRQ(0x%x) for next fragment\n",
2848 buf->irq_count);
2849
2850 buf->irq_count |= 0x01;
2851
2852 return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack),
2853 buf->irq_count);
2854}
2855
2856int wm_adsp_compr_pointer(struct snd_compr_stream *stream,
2857 struct snd_compr_tstamp *tstamp)
2858{
2859 struct wm_adsp_compr *compr = stream->runtime->private_data;
2860 struct wm_adsp_compr_buf *buf = compr->buf;
2861 struct wm_adsp *dsp = compr->dsp;
2862 int ret = 0;
2863
2864 adsp_dbg(dsp, "Pointer request\n");
2865
2866 mutex_lock(&dsp->pwr_lock);
2867
2868 if (!compr->buf) {
2869 ret = -ENXIO;
2870 goto out;
2871 }
2872
2873 if (compr->buf->error) {
2874 ret = -EIO;
2875 goto out;
2876 }
2877
2878 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
2879 ret = wm_adsp_buffer_update_avail(buf);
2880 if (ret < 0) {
2881 adsp_err(dsp, "Error reading avail: %d\n", ret);
2882 goto out;
2883 }
2884
2885 /*
2886 * If we really have less than 1 fragment available tell the
2887 * DSP to inform us once a whole fragment is available.
2888 */
2889 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
2890 ret = wm_adsp_buffer_reenable_irq(buf);
2891 if (ret < 0) {
2892 adsp_err(dsp,
2893 "Failed to re-enable buffer IRQ: %d\n",
2894 ret);
2895 goto out;
2896 }
2897 }
2898 }
2899
2900 tstamp->copied_total = compr->copied_total;
2901 tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE;
2902
2903out:
2904 mutex_unlock(&dsp->pwr_lock);
2905
2906 return ret;
2907}
2908EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer);
2909
0a37c6ef 2910MODULE_LICENSE("GPL v2");
Empty description
This page took 1.123555 seconds and 4 git commands to generate.