[linux.git] / drivers / spi / spi-ar934x.c

// SPDX-License-Identifier: GPL-2.0
//
// SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs
//
// Copyright (C) 2020 Chuanhong Guo <[email protected]>
//
// Based on spi-mt7621.c:
// Copyright (C) 2011 Sergiy <[email protected]>
// Copyright (C) 2011-2013 Gabor Juhos <[email protected]>
// Copyright (C) 2014-2015 Felix Fietkau <[email protected]>

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>

#define DRIVER_NAME "spi-ar934x"

#define AR934X_SPI_REG_FS		0x00
#define AR934X_SPI_ENABLE		BIT(0)

#define AR934X_SPI_REG_IOC		0x08
#define AR934X_SPI_IOC_INITVAL		0x70000

#define AR934X_SPI_REG_CTRL		0x04
#define AR934X_SPI_CLK_MASK		GENMASK(5, 0)

#define AR934X_SPI_DATAOUT		0x10

#define AR934X_SPI_REG_SHIFT_CTRL	0x14
#define AR934X_SPI_SHIFT_EN		BIT(31)
#define AR934X_SPI_SHIFT_CS(n)		BIT(28 + (n))
#define AR934X_SPI_SHIFT_TERM		26
#define AR934X_SPI_SHIFT_VAL(cs, term, count)			\
	(AR934X_SPI_SHIFT_EN | AR934X_SPI_SHIFT_CS(cs) |	\
	(term) << AR934X_SPI_SHIFT_TERM | (count))

#define AR934X_SPI_DATAIN 0x18

struct ar934x_spi {
	struct spi_controller *ctlr;
	void __iomem *base;
	struct clk *clk;
	unsigned int clk_freq;
};

static inline int ar934x_spi_clk_div(struct ar934x_spi *sp, unsigned int freq)
{
	int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1;

	if (div < 0)
		return 0;
	else if (div > AR934X_SPI_CLK_MASK)
		return -EINVAL;
	else
		return div;
}

static int ar934x_spi_setup(struct spi_device *spi)
{
	struct ar934x_spi *sp = spi_controller_get_devdata(spi->controller);

	if ((spi->max_speed_hz == 0) ||
	    (spi->max_speed_hz > (sp->clk_freq / 2))) {
		spi->max_speed_hz = sp->clk_freq / 2;
	} else if (spi->max_speed_hz < (sp->clk_freq / 128)) {
		dev_err(&spi->dev, "spi clock is too low\n");
		return -EINVAL;
	}

	return 0;
}

static int ar934x_spi_transfer_one_message(struct spi_controller *ctlr,
					   struct spi_message *m)
{
	struct ar934x_spi *sp = spi_controller_get_devdata(ctlr);
	struct spi_transfer *t = NULL;
	struct spi_device *spi = m->spi;
	unsigned long trx_done, trx_cur;
	int stat = 0;
	u8 bpw, term = 0;
	int div, i;
	u32 reg;
	const u8 *tx_buf;
	u8 *buf;

	m->actual_length = 0;
	list_for_each_entry(t, &m->transfers, transfer_list) {
		if (t->bits_per_word >= 8 && t->bits_per_word < 32)
			bpw = t->bits_per_word >> 3;
		else
			bpw = 4;

		if (t->speed_hz)
			div = ar934x_spi_clk_div(sp, t->speed_hz);
		else
			div = ar934x_spi_clk_div(sp, spi->max_speed_hz);
		if (div < 0) {
			stat = -EIO;
			goto msg_done;
		}

		reg = ioread32(sp->base + AR934X_SPI_REG_CTRL);
		reg &= ~AR934X_SPI_CLK_MASK;
		reg |= div;
		iowrite32(reg, sp->base + AR934X_SPI_REG_CTRL);
		iowrite32(0, sp->base + AR934X_SPI_DATAOUT);

		for (trx_done = 0; trx_done < t->len; trx_done += bpw) {
			trx_cur = t->len - trx_done;
			if (trx_cur > bpw)
				trx_cur = bpw;
			else if (list_is_last(&t->transfer_list, &m->transfers))
				term = 1;

			if (t->tx_buf) {
				tx_buf = t->tx_buf + trx_done;
				reg = tx_buf[0];
				for (i = 1; i < trx_cur; i++)
					reg = reg << 8 | tx_buf[i];
				iowrite32(reg, sp->base + AR934X_SPI_DATAOUT);
			}

			reg = AR934X_SPI_SHIFT_VAL(spi_get_chipselect(spi, 0), term,
						   trx_cur * 8);
			iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL);
			stat = readl_poll_timeout(
				sp->base + AR934X_SPI_REG_SHIFT_CTRL, reg,
				!(reg & AR934X_SPI_SHIFT_EN), 0, 5);
			if (stat < 0)
				goto msg_done;

			if (t->rx_buf) {
				reg = ioread32(sp->base + AR934X_SPI_DATAIN);
				buf = t->rx_buf + trx_done;
				for (i = 0; i < trx_cur; i++) {
					buf[trx_cur - i - 1] = reg & 0xff;
					reg >>= 8;
				}
			}
			spi_delay_exec(&t->word_delay, t);
		}
		m->actual_length += t->len;
		spi_transfer_delay_exec(t);
	}

msg_done:
	m->status = stat;
	spi_finalize_current_message(ctlr);

	return 0;
}

static const struct of_device_id ar934x_spi_match[] = {
	{ .compatible = "qca,ar934x-spi" },
	{},
};
MODULE_DEVICE_TABLE(of, ar934x_spi_match);

static int ar934x_spi_probe(struct platform_device *pdev)
{
	struct spi_controller *ctlr;
	struct ar934x_spi *sp;
	void __iomem *base;
	struct clk *clk;

	base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(base))
		return PTR_ERR(base);

	clk = devm_clk_get_enabled(&pdev->dev, NULL);
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "failed to get clock\n");
		return PTR_ERR(clk);
	}

	ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*sp));
	if (!ctlr) {
		dev_info(&pdev->dev, "failed to allocate spi controller\n");
		return -ENOMEM;
	}

	/* disable flash mapping and expose spi controller registers */
	iowrite32(AR934X_SPI_ENABLE, base + AR934X_SPI_REG_FS);
	/* restore pins to default state: CSn=1 DO=CLK=0 */
	iowrite32(AR934X_SPI_IOC_INITVAL, base + AR934X_SPI_REG_IOC);

	ctlr->mode_bits = SPI_LSB_FIRST;
	ctlr->setup = ar934x_spi_setup;
	ctlr->transfer_one_message = ar934x_spi_transfer_one_message;
	ctlr->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(24) |
				   SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
	ctlr->dev.of_node = pdev->dev.of_node;
	ctlr->num_chipselect = 3;

	dev_set_drvdata(&pdev->dev, ctlr);

	sp = spi_controller_get_devdata(ctlr);
	sp->base = base;
	sp->clk = clk;
	sp->clk_freq = clk_get_rate(clk);
	sp->ctlr = ctlr;

	return spi_register_controller(ctlr);
}

static void ar934x_spi_remove(struct platform_device *pdev)
{
	struct spi_controller *ctlr;

	ctlr = dev_get_drvdata(&pdev->dev);
	spi_unregister_controller(ctlr);
}

static struct platform_driver ar934x_spi_driver = {
	.driver = {
		.name = DRIVER_NAME,
		.of_match_table = ar934x_spi_match,
	},
	.probe = ar934x_spi_probe,
	.remove_new = ar934x_spi_remove,
};

module_platform_driver(ar934x_spi_driver);

MODULE_DESCRIPTION("SPI controller driver for Qualcomm Atheros AR934x/QCA95xx");
MODULE_AUTHOR("Chuanhong Guo <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
047980c5 CG	1	// SPDX-License-Identifier: GPL-2.0
	2	//
	3	// SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs
	4	//
	5	// Copyright (C) 2020 Chuanhong Guo <[email protected]>
	6	//
	7	// Based on spi-mt7621.c:
	8	// Copyright (C) 2011 Sergiy <[email protected]>
	9	// Copyright (C) 2011-2013 Gabor Juhos <[email protected]>
	10	// Copyright (C) 2014-2015 Felix Fietkau <[email protected]>
	11
	12	#include <linux/clk.h>
	13	#include <linux/io.h>
	14	#include <linux/iopoll.h>
	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
749396cb RH	17	#include <linux/of.h>
749396cb RH	18	#include <linux/platform_device.h>
047980c5 CG	19	#include <linux/spi/spi.h>
	20
	21	#define DRIVER_NAME "spi-ar934x"
	22
	23	#define AR934X_SPI_REG_FS 0x00
	24	#define AR934X_SPI_ENABLE BIT(0)
	25
	26	#define AR934X_SPI_REG_IOC 0x08
	27	#define AR934X_SPI_IOC_INITVAL 0x70000
	28
	29	#define AR934X_SPI_REG_CTRL 0x04
	30	#define AR934X_SPI_CLK_MASK GENMASK(5, 0)
	31
	32	#define AR934X_SPI_DATAOUT 0x10
	33
	34	#define AR934X_SPI_REG_SHIFT_CTRL 0x14
	35	#define AR934X_SPI_SHIFT_EN BIT(31)
	36	#define AR934X_SPI_SHIFT_CS(n) BIT(28 + (n))
	37	#define AR934X_SPI_SHIFT_TERM 26
	38	#define AR934X_SPI_SHIFT_VAL(cs, term, count) \
	39	(AR934X_SPI_SHIFT_EN \| AR934X_SPI_SHIFT_CS(cs) \| \
	40	(term) << AR934X_SPI_SHIFT_TERM \| (count))
	41
	42	#define AR934X_SPI_DATAIN 0x18
	43
	44	struct ar934x_spi {
	45	struct spi_controller *ctlr;
	46	void __iomem *base;
	47	struct clk *clk;
	48	unsigned int clk_freq;
	49	};
	50
	51	static inline int ar934x_spi_clk_div(struct ar934x_spi *sp, unsigned int freq)
	52	{
	53	int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1;
	54
	55	if (div < 0)
	56	return 0;
	57	else if (div > AR934X_SPI_CLK_MASK)
	58	return -EINVAL;
	59	else
	60	return div;
	61	}
	62
	63	static int ar934x_spi_setup(struct spi_device *spi)
	64	{
87384599	65	struct ar934x_spi *sp = spi_controller_get_devdata(spi->controller);
047980c5 CG	66
	67	if ((spi->max_speed_hz == 0) \|\|
	68	(spi->max_speed_hz > (sp->clk_freq / 2))) {
	69	spi->max_speed_hz = sp->clk_freq / 2;
	70	} else if (spi->max_speed_hz < (sp->clk_freq / 128)) {
	71	dev_err(&spi->dev, "spi clock is too low\n");
	72	return -EINVAL;
	73	}
	74
	75	return 0;
	76	}
	77
87384599	78	static int ar934x_spi_transfer_one_message(struct spi_controller *ctlr,
047980c5 CG	79	struct spi_message *m)
047980c5 CG	80	{
87384599	81	struct ar934x_spi *sp = spi_controller_get_devdata(ctlr);
047980c5 CG	82	struct spi_transfer *t = NULL;
	83	struct spi_device *spi = m->spi;
	84	unsigned long trx_done, trx_cur;
	85	int stat = 0;
ebe33e5a	86	u8 bpw, term = 0;
047980c5 CG	87	int div, i;
	88	u32 reg;
	89	const u8 *tx_buf;
	90	u8 *buf;
	91
	92	m->actual_length = 0;
	93	list_for_each_entry(t, &m->transfers, transfer_list) {
ebe33e5a OL	94	if (t->bits_per_word >= 8 && t->bits_per_word < 32)
	95	bpw = t->bits_per_word >> 3;
	96	else
	97	bpw = 4;
	98
047980c5 CG	99	if (t->speed_hz)
	100	div = ar934x_spi_clk_div(sp, t->speed_hz);
	101	else
	102	div = ar934x_spi_clk_div(sp, spi->max_speed_hz);
	103	if (div < 0) {
	104	stat = -EIO;
	105	goto msg_done;
	106	}
	107
	108	reg = ioread32(sp->base + AR934X_SPI_REG_CTRL);
	109	reg &= ~AR934X_SPI_CLK_MASK;
	110	reg \|= div;
	111	iowrite32(reg, sp->base + AR934X_SPI_REG_CTRL);
	112	iowrite32(0, sp->base + AR934X_SPI_DATAOUT);
	113
ebe33e5a	114	for (trx_done = 0; trx_done < t->len; trx_done += bpw) {
047980c5	115	trx_cur = t->len - trx_done;
ebe33e5a OL	116	if (trx_cur > bpw)
ebe33e5a OL	117	trx_cur = bpw;
047980c5 CG	118	else if (list_is_last(&t->transfer_list, &m->transfers))
	119	term = 1;
	120
	121	if (t->tx_buf) {
	122	tx_buf = t->tx_buf + trx_done;
	123	reg = tx_buf[0];
	124	for (i = 1; i < trx_cur; i++)
	125	reg = reg << 8 \| tx_buf[i];
	126	iowrite32(reg, sp->base + AR934X_SPI_DATAOUT);
	127	}
	128
9e264f3f	129	reg = AR934X_SPI_SHIFT_VAL(spi_get_chipselect(spi, 0), term,
047980c5 CG	130	trx_cur * 8);
	131	iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL);
	132	stat = readl_poll_timeout(
	133	sp->base + AR934X_SPI_REG_SHIFT_CTRL, reg,
	134	!(reg & AR934X_SPI_SHIFT_EN), 0, 5);
	135	if (stat < 0)
	136	goto msg_done;
	137
	138	if (t->rx_buf) {
	139	reg = ioread32(sp->base + AR934X_SPI_DATAIN);
	140	buf = t->rx_buf + trx_done;
	141	for (i = 0; i < trx_cur; i++) {
	142	buf[trx_cur - i - 1] = reg & 0xff;
	143	reg >>= 8;
	144	}
	145	}
c7028245	146	spi_delay_exec(&t->word_delay, t);
047980c5 CG	147	}
047980c5 CG	148	m->actual_length += t->len;
c7028245	149	spi_transfer_delay_exec(t);
047980c5 CG	150	}
	151
	152	msg_done:
	153	m->status = stat;
87384599	154	spi_finalize_current_message(ctlr);
047980c5 CG	155
	156	return 0;
	157	}
	158
	159	static const struct of_device_id ar934x_spi_match[] = {
	160	{ .compatible = "qca,ar934x-spi" },
	161	{},
	162	};
	163	MODULE_DEVICE_TABLE(of, ar934x_spi_match);
	164
	165	static int ar934x_spi_probe(struct platform_device *pdev)
	166	{
	167	struct spi_controller *ctlr;
	168	struct ar934x_spi *sp;
	169	void __iomem *base;
	170	struct clk *clk;
047980c5 CG	171
	172	base = devm_platform_ioremap_resource(pdev, 0);
	173	if (IS_ERR(base))
	174	return PTR_ERR(base);
	175
1d3ea34b	176	clk = devm_clk_get_enabled(&pdev->dev, NULL);
047980c5 CG	177	if (IS_ERR(clk)) {
	178	dev_err(&pdev->dev, "failed to get clock\n");
	179	return PTR_ERR(clk);
	180	}
	181
87384599	182	ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*sp));
047980c5 CG	183	if (!ctlr) {
047980c5 CG	184	dev_info(&pdev->dev, "failed to allocate spi controller\n");
1d3ea34b	185	return -ENOMEM;
047980c5 CG	186	}
	187
	188	/* disable flash mapping and expose spi controller registers */
	189	iowrite32(AR934X_SPI_ENABLE, base + AR934X_SPI_REG_FS);
	190	/* restore pins to default state: CSn=1 DO=CLK=0 */
	191	iowrite32(AR934X_SPI_IOC_INITVAL, base + AR934X_SPI_REG_IOC);
	192
	193	ctlr->mode_bits = SPI_LSB_FIRST;
	194	ctlr->setup = ar934x_spi_setup;
	195	ctlr->transfer_one_message = ar934x_spi_transfer_one_message;
ebe33e5a OL	196	ctlr->bits_per_word_mask = SPI_BPW_MASK(32) \| SPI_BPW_MASK(24) \|
ebe33e5a OL	197	SPI_BPW_MASK(16) \| SPI_BPW_MASK(8);
047980c5 CG	198	ctlr->dev.of_node = pdev->dev.of_node;
	199	ctlr->num_chipselect = 3;
	200
	201	dev_set_drvdata(&pdev->dev, ctlr);
	202
	203	sp = spi_controller_get_devdata(ctlr);
	204	sp->base = base;
	205	sp->clk = clk;
	206	sp->clk_freq = clk_get_rate(clk);
	207	sp->ctlr = ctlr;
	208
1d3ea34b	209	return spi_register_controller(ctlr);
047980c5 CG	210	}
047980c5 CG	211
24644ae0	212	static void ar934x_spi_remove(struct platform_device *pdev)
047980c5 CG	213	{
047980c5 CG	214	struct spi_controller *ctlr;
047980c5 CG	215
047980c5 CG	216	ctlr = dev_get_drvdata(&pdev->dev);
236924ee	217	spi_unregister_controller(ctlr);
047980c5 CG	218	}
	219
	220	static struct platform_driver ar934x_spi_driver = {
	221	.driver = {
	222	.name = DRIVER_NAME,
	223	.of_match_table = ar934x_spi_match,
	224	},
	225	.probe = ar934x_spi_probe,
24644ae0	226	.remove_new = ar934x_spi_remove,
047980c5 CG	227	};
	228
	229	module_platform_driver(ar934x_spi_driver);
	230
	231	MODULE_DESCRIPTION("SPI controller driver for Qualcomm Atheros AR934x/QCA95xx");
	232	MODULE_AUTHOR("Chuanhong Guo <[email protected]>");
	233	MODULE_LICENSE("GPL v2");
	234	MODULE_ALIAS("platform:" DRIVER_NAME);