[linux.git] / include / asm-s390 / tlb.h

#ifndef _S390_TLB_H
#define _S390_TLB_H

/*
 * TLB flushing on s390 is complicated. The following requirement
 * from the principles of operation is the most arduous:
 *
 * "A valid table entry must not be changed while it is attached
 * to any CPU and may be used for translation by that CPU except to
 * (1) invalidate the entry by using INVALIDATE PAGE TABLE ENTRY,
 * or INVALIDATE DAT TABLE ENTRY, (2) alter bits 56-63 of a page
 * table entry, or (3) make a change by means of a COMPARE AND SWAP
 * AND PURGE instruction that purges the TLB."
 *
 * The modification of a pte of an active mm struct therefore is
 * a two step process: i) invalidate the pte, ii) store the new pte.
 * This is true for the page protection bit as well.
 * The only possible optimization is to flush at the beginning of
 * a tlb_gather_mmu cycle if the mm_struct is currently not in use.
 *
 * Pages used for the page tables is a different story. FIXME: more
 */

#include <linux/mm.h>
#include <linux/swap.h>
#include <asm/processor.h>
#include <asm/pgalloc.h>
#include <asm/smp.h>
#include <asm/tlbflush.h>

#ifndef CONFIG_SMP
#define TLB_NR_PTRS	1
#else
#define TLB_NR_PTRS	508
#endif

struct mmu_gather {
	struct mm_struct *mm;
	unsigned int fullmm;
	unsigned int nr_ptes;
	unsigned int nr_pxds;
	void *array[TLB_NR_PTRS];
};

DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);

static inline struct mmu_gather *tlb_gather_mmu(struct mm_struct *mm,
						unsigned int full_mm_flush)
{
	struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);

	tlb->mm = mm;
	tlb->fullmm = full_mm_flush || (num_online_cpus() == 1) ||
		(atomic_read(&mm->mm_users) <= 1 && mm == current->active_mm);
	tlb->nr_ptes = 0;
	tlb->nr_pxds = TLB_NR_PTRS;
	if (tlb->fullmm)
		__tlb_flush_mm(mm);
	return tlb;
}

static inline void tlb_flush_mmu(struct mmu_gather *tlb,
				 unsigned long start, unsigned long end)
{
	if (!tlb->fullmm && (tlb->nr_ptes > 0 || tlb->nr_pxds < TLB_NR_PTRS))
		__tlb_flush_mm(tlb->mm);
	while (tlb->nr_ptes > 0)
		pte_free(tlb->mm, tlb->array[--tlb->nr_ptes]);
	while (tlb->nr_pxds < TLB_NR_PTRS)
		/* pgd_free frees the pointer as region or segment table */
		pgd_free(tlb->mm, tlb->array[tlb->nr_pxds++]);
}

static inline void tlb_finish_mmu(struct mmu_gather *tlb,
				  unsigned long start, unsigned long end)
{
	tlb_flush_mmu(tlb, start, end);

	/* keep the page table cache within bounds */
	check_pgt_cache();

	put_cpu_var(mmu_gathers);
}

/*
 * Release the page cache reference for a pte removed by
 * tlb_ptep_clear_flush. In both flush modes the tlb fo a page cache page
 * has already been freed, so just do free_page_and_swap_cache.
 */
static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
{
	free_page_and_swap_cache(page);
}

/*
 * pte_free_tlb frees a pte table and clears the CRSTE for the
 * page table from the tlb.
 */
static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte)
{
	if (!tlb->fullmm) {
		tlb->array[tlb->nr_ptes++] = pte;
		if (tlb->nr_ptes >= tlb->nr_pxds)
			tlb_flush_mmu(tlb, 0, 0);
	} else
		pte_free(tlb->mm, pte);
}

/*
 * pmd_free_tlb frees a pmd table and clears the CRSTE for the
 * segment table entry from the tlb.
 * If the mm uses a two level page table the single pmd is freed
 * as the pgd. pmd_free_tlb checks the asce_limit against 2GB
 * to avoid the double free of the pmd in this case.
 */
static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd)
{
#ifdef __s390x__
	if (tlb->mm->context.asce_limit <= (1UL << 31))
		return;
	if (!tlb->fullmm) {
		tlb->array[--tlb->nr_pxds] = pmd;
		if (tlb->nr_ptes >= tlb->nr_pxds)
			tlb_flush_mmu(tlb, 0, 0);
	} else
		pmd_free(tlb->mm, pmd);
#endif
}

/*
 * pud_free_tlb frees a pud table and clears the CRSTE for the
 * region third table entry from the tlb.
 * If the mm uses a three level page table the single pud is freed
 * as the pgd. pud_free_tlb checks the asce_limit against 4TB
 * to avoid the double free of the pud in this case.
 */
static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud)
{
#ifdef __s390x__
	if (tlb->mm->context.asce_limit <= (1UL << 42))
		return;
	if (!tlb->fullmm) {
		tlb->array[--tlb->nr_pxds] = pud;
		if (tlb->nr_ptes >= tlb->nr_pxds)
			tlb_flush_mmu(tlb, 0, 0);
	} else
		pud_free(tlb->mm, pud);
#endif
}

#define tlb_start_vma(tlb, vma)			do { } while (0)
#define tlb_end_vma(tlb, vma)			do { } while (0)
#define tlb_remove_tlb_entry(tlb, ptep, addr)	do { } while (0)
#define tlb_migrate_finish(mm)			do { } while (0)

#endif /* _S390_TLB_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef _S390_TLB_H
	2	#define _S390_TLB_H
	3
	4	/*
ba8a9229 MS	5	* TLB flushing on s390 is complicated. The following requirement
	6	* from the principles of operation is the most arduous:
	7	*
	8	* "A valid table entry must not be changed while it is attached
	9	* to any CPU and may be used for translation by that CPU except to
	10	* (1) invalidate the entry by using INVALIDATE PAGE TABLE ENTRY,
	11	* or INVALIDATE DAT TABLE ENTRY, (2) alter bits 56-63 of a page
	12	* table entry, or (3) make a change by means of a COMPARE AND SWAP
	13	* AND PURGE instruction that purges the TLB."
	14	*
	15	* The modification of a pte of an active mm struct therefore is
	16	* a two step process: i) invalidate the pte, ii) store the new pte.
	17	* This is true for the page protection bit as well.
	18	* The only possible optimization is to flush at the beginning of
	19	* a tlb_gather_mmu cycle if the mm_struct is currently not in use.
	20	*
	21	* Pages used for the page tables is a different story. FIXME: more
1da177e4	22	*/
ba8a9229 MS	23
	24	#include <linux/mm.h>
	25	#include <linux/swap.h>
	26	#include <asm/processor.h>
	27	#include <asm/pgalloc.h>
	28	#include <asm/smp.h>
	29	#include <asm/tlbflush.h>
	30
	31	#ifndef CONFIG_SMP
	32	#define TLB_NR_PTRS 1
	33	#else
	34	#define TLB_NR_PTRS 508
	35	#endif
	36
	37	struct mmu_gather {
	38	struct mm_struct *mm;
	39	unsigned int fullmm;
	40	unsigned int nr_ptes;
5a216a20	41	unsigned int nr_pxds;
ba8a9229 MS	42	void *array[TLB_NR_PTRS];
	43	};
	44
	45	DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
	46
	47	static inline struct mmu_gather tlb_gather_mmu(struct mm_struct mm,
	48	unsigned int full_mm_flush)
	49	{
	50	struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
	51
	52	tlb->mm = mm;
	53	tlb->fullmm = full_mm_flush \|\| (num_online_cpus() == 1) \|\|
	54	(atomic_read(&mm->mm_users) <= 1 && mm == current->active_mm);
	55	tlb->nr_ptes = 0;
5a216a20	56	tlb->nr_pxds = TLB_NR_PTRS;
ba8a9229 MS	57	if (tlb->fullmm)
	58	__tlb_flush_mm(mm);
	59	return tlb;
	60	}
	61
	62	static inline void tlb_flush_mmu(struct mmu_gather *tlb,
	63	unsigned long start, unsigned long end)
	64	{
5a216a20	65	if (!tlb->fullmm && (tlb->nr_ptes > 0 \|\| tlb->nr_pxds < TLB_NR_PTRS))
ba8a9229 MS	66	__tlb_flush_mm(tlb->mm);
ba8a9229 MS	67	while (tlb->nr_ptes > 0)
5e541973	68	pte_free(tlb->mm, tlb->array[--tlb->nr_ptes]);
5a216a20 MS	69	while (tlb->nr_pxds < TLB_NR_PTRS)
	70	/* pgd_free frees the pointer as region or segment table */
	71	pgd_free(tlb->mm, tlb->array[tlb->nr_pxds++]);
ba8a9229 MS	72	}
	73
	74	static inline void tlb_finish_mmu(struct mmu_gather *tlb,
	75	unsigned long start, unsigned long end)
	76	{
	77	tlb_flush_mmu(tlb, start, end);
	78
	79	/* keep the page table cache within bounds */
	80	check_pgt_cache();
	81
	82	put_cpu_var(mmu_gathers);
	83	}
1da177e4 LT	84
1da177e4 LT	85	/*
ba8a9229 MS	86	* Release the page cache reference for a pte removed by
	87	* tlb_ptep_clear_flush. In both flush modes the tlb fo a page cache page
	88	* has already been freed, so just do free_page_and_swap_cache.
1da177e4	89	*/
ba8a9229 MS	90	static inline void tlb_remove_page(struct mmu_gather tlb, struct page page)
	91	{
	92	free_page_and_swap_cache(page);
	93	}
1da177e4	94
ba8a9229 MS	95	/*
	96	* pte_free_tlb frees a pte table and clears the CRSTE for the
	97	* page table from the tlb.
	98	*/
146e4b3c	99	static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte)
ba8a9229 MS	100	{
ba8a9229 MS	101	if (!tlb->fullmm) {
146e4b3c	102	tlb->array[tlb->nr_ptes++] = pte;
5a216a20	103	if (tlb->nr_ptes >= tlb->nr_pxds)
ba8a9229 MS	104	tlb_flush_mmu(tlb, 0, 0);
ba8a9229 MS	105	} else
146e4b3c	106	pte_free(tlb->mm, pte);
ba8a9229	107	}
1da177e4	108
ba8a9229 MS	109	/*
	110	* pmd_free_tlb frees a pmd table and clears the CRSTE for the
	111	* segment table entry from the tlb.
6252d702 MS	112	* If the mm uses a two level page table the single pmd is freed
	113	* as the pgd. pmd_free_tlb checks the asce_limit against 2GB
	114	* to avoid the double free of the pmd in this case.
ba8a9229 MS	115	*/
	116	static inline void pmd_free_tlb(struct mmu_gather tlb, pmd_t pmd)
	117	{
	118	#ifdef __s390x__
6252d702 MS	119	if (tlb->mm->context.asce_limit <= (1UL << 31))
6252d702 MS	120	return;
ba8a9229	121	if (!tlb->fullmm) {
5a216a20 MS	122	tlb->array[--tlb->nr_pxds] = pmd;
5a216a20 MS	123	if (tlb->nr_ptes >= tlb->nr_pxds)
ba8a9229 MS	124	tlb_flush_mmu(tlb, 0, 0);
ba8a9229 MS	125	} else
5e541973	126	pmd_free(tlb->mm, pmd);
1da177e4	127	#endif
ba8a9229 MS	128	}
ba8a9229 MS	129
5a216a20 MS	130	/*
	131	* pud_free_tlb frees a pud table and clears the CRSTE for the
	132	* region third table entry from the tlb.
6252d702 MS	133	* If the mm uses a three level page table the single pud is freed
	134	* as the pgd. pud_free_tlb checks the asce_limit against 4TB
	135	* to avoid the double free of the pud in this case.
5a216a20 MS	136	*/
	137	static inline void pud_free_tlb(struct mmu_gather tlb, pud_t pud)
	138	{
	139	#ifdef __s390x__
6252d702 MS	140	if (tlb->mm->context.asce_limit <= (1UL << 42))
6252d702 MS	141	return;
5a216a20 MS	142	if (!tlb->fullmm) {
	143	tlb->array[--tlb->nr_pxds] = pud;
	144	if (tlb->nr_ptes >= tlb->nr_pxds)
	145	tlb_flush_mmu(tlb, 0, 0);
	146	} else
	147	pud_free(tlb->mm, pud);
	148	#endif
	149	}
190a1d72	150
ba8a9229 MS	151	#define tlb_start_vma(tlb, vma) do { } while (0)
	152	#define tlb_end_vma(tlb, vma) do { } while (0)
	153	#define tlb_remove_tlb_entry(tlb, ptep, addr) do { } while (0)
	154	#define tlb_migrate_finish(mm) do { } while (0)
	155
	156	#endif /* _S390_TLB_H */