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66aaa7a5 MZ |
1 | /* |
2 | * drivers/char/watchdog/max63xx_wdt.c | |
3 | * | |
4 | * Driver for max63{69,70,71,72,73,74} watchdog timers | |
5 | * | |
6 | * Copyright (C) 2009 Marc Zyngier <[email protected]> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | * | |
12 | * This driver assumes the watchdog pins are memory mapped (as it is | |
13 | * the case for the Arcom Zeus). Should it be connected over GPIOs or | |
14 | * another interface, some abstraction will have to be introduced. | |
15 | */ | |
16 | ||
4c271bb6 | 17 | #include <linux/err.h> |
66aaa7a5 MZ |
18 | #include <linux/module.h> |
19 | #include <linux/moduleparam.h> | |
ac316725 | 20 | #include <linux/mod_devicetable.h> |
66aaa7a5 MZ |
21 | #include <linux/types.h> |
22 | #include <linux/kernel.h> | |
66aaa7a5 | 23 | #include <linux/watchdog.h> |
66aaa7a5 MZ |
24 | #include <linux/bitops.h> |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/spinlock.h> | |
66aaa7a5 | 27 | #include <linux/io.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
66aaa7a5 MZ |
29 | |
30 | #define DEFAULT_HEARTBEAT 60 | |
31 | #define MAX_HEARTBEAT 60 | |
32 | ||
a0f36833 | 33 | static unsigned int heartbeat = DEFAULT_HEARTBEAT; |
86a1e189 | 34 | static bool nowayout = WATCHDOG_NOWAYOUT; |
66aaa7a5 MZ |
35 | |
36 | /* | |
37 | * Memory mapping: a single byte, 3 first lower bits to select bit 3 | |
38 | * to ping the watchdog. | |
39 | */ | |
40 | #define MAX6369_WDSET (7 << 0) | |
5f3b2756 | 41 | #define MAX6369_WDI (1 << 3) |
66aaa7a5 | 42 | |
b9be9660 | 43 | #define MAX6369_WDSET_DISABLED 3 |
66aaa7a5 | 44 | |
66aaa7a5 | 45 | static int nodelay; |
b9be9660 VD |
46 | |
47 | struct max63xx_wdt { | |
48 | struct watchdog_device wdd; | |
49 | const struct max63xx_timeout *timeout; | |
50 | ||
51 | /* memory mapping */ | |
52 | void __iomem *base; | |
53 | spinlock_t lock; | |
54 | ||
55 | /* WDI and WSET bits write access routines */ | |
56 | void (*ping)(struct max63xx_wdt *wdt); | |
57 | void (*set)(struct max63xx_wdt *wdt, u8 set); | |
58 | }; | |
66aaa7a5 MZ |
59 | |
60 | /* | |
61 | * The timeout values used are actually the absolute minimum the chip | |
62 | * offers. Typical values on my board are slightly over twice as long | |
63 | * (10s setting ends up with a 25s timeout), and can be up to 3 times | |
64 | * the nominal setting (according to the datasheet). So please take | |
65 | * these values with a grain of salt. Same goes for the initial delay | |
66 | * "feature". Only max6373/74 have a few settings without this initial | |
67 | * delay (selected with the "nodelay" parameter). | |
68 | * | |
69 | * I also decided to remove from the tables any timeout smaller than a | |
70 | * second, as it looked completly overkill... | |
71 | */ | |
72 | ||
73 | /* Timeouts in second */ | |
74 | struct max63xx_timeout { | |
b9be9660 VD |
75 | const u8 wdset; |
76 | const u8 tdelay; | |
77 | const u8 twd; | |
66aaa7a5 MZ |
78 | }; |
79 | ||
b9be9660 | 80 | static const struct max63xx_timeout max6369_table[] = { |
66aaa7a5 MZ |
81 | { 5, 1, 1 }, |
82 | { 6, 10, 10 }, | |
83 | { 7, 60, 60 }, | |
84 | { }, | |
85 | }; | |
86 | ||
b9be9660 | 87 | static const struct max63xx_timeout max6371_table[] = { |
66aaa7a5 MZ |
88 | { 6, 60, 3 }, |
89 | { 7, 60, 60 }, | |
90 | { }, | |
91 | }; | |
92 | ||
b9be9660 | 93 | static const struct max63xx_timeout max6373_table[] = { |
66aaa7a5 MZ |
94 | { 2, 60, 1 }, |
95 | { 5, 0, 1 }, | |
96 | { 1, 3, 3 }, | |
97 | { 7, 60, 10 }, | |
98 | { 6, 0, 10 }, | |
99 | { }, | |
100 | }; | |
101 | ||
66aaa7a5 MZ |
102 | static struct max63xx_timeout * |
103 | max63xx_select_timeout(struct max63xx_timeout *table, int value) | |
104 | { | |
105 | while (table->twd) { | |
106 | if (value <= table->twd) { | |
107 | if (nodelay && table->tdelay == 0) | |
108 | return table; | |
109 | ||
110 | if (!nodelay) | |
111 | return table; | |
112 | } | |
113 | ||
114 | table++; | |
115 | } | |
116 | ||
117 | return NULL; | |
118 | } | |
119 | ||
a0f36833 | 120 | static int max63xx_wdt_ping(struct watchdog_device *wdd) |
66aaa7a5 | 121 | { |
b9be9660 | 122 | struct max63xx_wdt *wdt = watchdog_get_drvdata(wdd); |
66aaa7a5 | 123 | |
b9be9660 | 124 | wdt->ping(wdt); |
a0f36833 | 125 | return 0; |
66aaa7a5 MZ |
126 | } |
127 | ||
a0f36833 | 128 | static int max63xx_wdt_start(struct watchdog_device *wdd) |
66aaa7a5 | 129 | { |
b9be9660 | 130 | struct max63xx_wdt *wdt = watchdog_get_drvdata(wdd); |
66aaa7a5 | 131 | |
b9be9660 | 132 | wdt->set(wdt, wdt->timeout->wdset); |
66aaa7a5 MZ |
133 | |
134 | /* check for a edge triggered startup */ | |
b9be9660 VD |
135 | if (wdt->timeout->tdelay == 0) |
136 | wdt->ping(wdt); | |
a0f36833 | 137 | return 0; |
66aaa7a5 MZ |
138 | } |
139 | ||
a0f36833 | 140 | static int max63xx_wdt_stop(struct watchdog_device *wdd) |
66aaa7a5 | 141 | { |
b9be9660 | 142 | struct max63xx_wdt *wdt = watchdog_get_drvdata(wdd); |
b1183e06 | 143 | |
b9be9660 | 144 | wdt->set(wdt, MAX6369_WDSET_DISABLED); |
a0f36833 | 145 | return 0; |
66aaa7a5 MZ |
146 | } |
147 | ||
a0f36833 AL |
148 | static const struct watchdog_ops max63xx_wdt_ops = { |
149 | .owner = THIS_MODULE, | |
150 | .start = max63xx_wdt_start, | |
151 | .stop = max63xx_wdt_stop, | |
152 | .ping = max63xx_wdt_ping, | |
66aaa7a5 MZ |
153 | }; |
154 | ||
b9be9660 VD |
155 | static const struct watchdog_info max63xx_wdt_info = { |
156 | .options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, | |
157 | .identity = "max63xx Watchdog", | |
66aaa7a5 MZ |
158 | }; |
159 | ||
b9be9660 VD |
160 | static void max63xx_mmap_ping(struct max63xx_wdt *wdt) |
161 | { | |
162 | u8 val; | |
163 | ||
164 | spin_lock(&wdt->lock); | |
165 | ||
166 | val = __raw_readb(wdt->base); | |
167 | ||
168 | __raw_writeb(val | MAX6369_WDI, wdt->base); | |
169 | __raw_writeb(val & ~MAX6369_WDI, wdt->base); | |
170 | ||
171 | spin_unlock(&wdt->lock); | |
172 | } | |
173 | ||
174 | static void max63xx_mmap_set(struct max63xx_wdt *wdt, u8 set) | |
175 | { | |
176 | u8 val; | |
177 | ||
178 | spin_lock(&wdt->lock); | |
179 | ||
180 | val = __raw_readb(wdt->base); | |
181 | val &= ~MAX6369_WDSET; | |
182 | val |= set & MAX6369_WDSET; | |
183 | __raw_writeb(val, wdt->base); | |
184 | ||
185 | spin_unlock(&wdt->lock); | |
186 | } | |
187 | ||
188 | static int max63xx_mmap_init(struct platform_device *p, struct max63xx_wdt *wdt) | |
189 | { | |
190 | struct resource *mem = platform_get_resource(p, IORESOURCE_MEM, 0); | |
191 | ||
192 | wdt->base = devm_ioremap_resource(&p->dev, mem); | |
193 | if (IS_ERR(wdt->base)) | |
194 | return PTR_ERR(wdt->base); | |
195 | ||
196 | spin_lock_init(&wdt->lock); | |
197 | ||
198 | wdt->ping = max63xx_mmap_ping; | |
199 | wdt->set = max63xx_mmap_set; | |
200 | return 0; | |
201 | } | |
202 | ||
2d991a16 | 203 | static int max63xx_wdt_probe(struct platform_device *pdev) |
66aaa7a5 | 204 | { |
b9be9660 | 205 | struct max63xx_wdt *wdt; |
66aaa7a5 | 206 | struct max63xx_timeout *table; |
b9be9660 VD |
207 | int err; |
208 | ||
209 | wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL); | |
210 | if (!wdt) | |
211 | return -ENOMEM; | |
66aaa7a5 MZ |
212 | |
213 | table = (struct max63xx_timeout *)pdev->id_entry->driver_data; | |
214 | ||
215 | if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT) | |
216 | heartbeat = DEFAULT_HEARTBEAT; | |
217 | ||
b9be9660 VD |
218 | wdt->timeout = max63xx_select_timeout(table, heartbeat); |
219 | if (!wdt->timeout) { | |
220 | dev_err(&pdev->dev, "unable to satisfy %ds heartbeat request\n", | |
221 | heartbeat); | |
66aaa7a5 MZ |
222 | return -EINVAL; |
223 | } | |
224 | ||
b9be9660 VD |
225 | err = max63xx_mmap_init(pdev, wdt); |
226 | if (err) | |
227 | return err; | |
228 | ||
229 | platform_set_drvdata(pdev, &wdt->wdd); | |
230 | watchdog_set_drvdata(&wdt->wdd, wdt); | |
66aaa7a5 | 231 | |
b9be9660 VD |
232 | wdt->wdd.parent = &pdev->dev; |
233 | wdt->wdd.timeout = wdt->timeout->twd; | |
234 | wdt->wdd.info = &max63xx_wdt_info; | |
235 | wdt->wdd.ops = &max63xx_wdt_ops; | |
66aaa7a5 | 236 | |
b9be9660 | 237 | watchdog_set_nowayout(&wdt->wdd, nowayout); |
66aaa7a5 | 238 | |
b9be9660 VD |
239 | err = watchdog_register_device(&wdt->wdd); |
240 | if (err) | |
241 | return err; | |
66aaa7a5 | 242 | |
b9be9660 VD |
243 | dev_info(&pdev->dev, "using %ds heartbeat with %ds initial delay\n", |
244 | wdt->timeout->twd, wdt->timeout->tdelay); | |
245 | return 0; | |
66aaa7a5 MZ |
246 | } |
247 | ||
4b12b896 | 248 | static int max63xx_wdt_remove(struct platform_device *pdev) |
66aaa7a5 | 249 | { |
b9be9660 VD |
250 | struct watchdog_device *wdd = platform_get_drvdata(pdev); |
251 | ||
252 | watchdog_unregister_device(wdd); | |
66aaa7a5 MZ |
253 | return 0; |
254 | } | |
255 | ||
8c7c72c9 | 256 | static const struct platform_device_id max63xx_id_table[] = { |
66aaa7a5 MZ |
257 | { "max6369_wdt", (kernel_ulong_t)max6369_table, }, |
258 | { "max6370_wdt", (kernel_ulong_t)max6369_table, }, | |
259 | { "max6371_wdt", (kernel_ulong_t)max6371_table, }, | |
260 | { "max6372_wdt", (kernel_ulong_t)max6371_table, }, | |
261 | { "max6373_wdt", (kernel_ulong_t)max6373_table, }, | |
262 | { "max6374_wdt", (kernel_ulong_t)max6373_table, }, | |
263 | { }, | |
264 | }; | |
265 | MODULE_DEVICE_TABLE(platform, max63xx_id_table); | |
266 | ||
267 | static struct platform_driver max63xx_wdt_driver = { | |
268 | .probe = max63xx_wdt_probe, | |
82268714 | 269 | .remove = max63xx_wdt_remove, |
66aaa7a5 MZ |
270 | .id_table = max63xx_id_table, |
271 | .driver = { | |
272 | .name = "max63xx_wdt", | |
66aaa7a5 MZ |
273 | }, |
274 | }; | |
275 | ||
b8ec6118 | 276 | module_platform_driver(max63xx_wdt_driver); |
66aaa7a5 MZ |
277 | |
278 | MODULE_AUTHOR("Marc Zyngier <[email protected]>"); | |
279 | MODULE_DESCRIPTION("max63xx Watchdog Driver"); | |
280 | ||
281 | module_param(heartbeat, int, 0); | |
282 | MODULE_PARM_DESC(heartbeat, | |
283 | "Watchdog heartbeat period in seconds from 1 to " | |
284 | __MODULE_STRING(MAX_HEARTBEAT) ", default " | |
285 | __MODULE_STRING(DEFAULT_HEARTBEAT)); | |
286 | ||
86a1e189 | 287 | module_param(nowayout, bool, 0); |
66aaa7a5 MZ |
288 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
289 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
290 | ||
291 | module_param(nodelay, int, 0); | |
292 | MODULE_PARM_DESC(nodelay, | |
293 | "Force selection of a timeout setting without initial delay " | |
294 | "(max6373/74 only, default=0)"); | |
295 | ||
29efefb9 | 296 | MODULE_LICENSE("GPL v2"); |