[linux.git] / drivers / watchdog / lantiq_wdt.c

/*
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 *
 *  Copyright (C) 2010 John Crispin <[email protected]>
 *  Copyright (C) 2017 Hauke Mehrtens <[email protected]>
 *  Based on EP93xx wdt driver
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/fs.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/of_platform.h>
#include <linux/uaccess.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>

#include <lantiq_soc.h>

#define LTQ_XRX_RCU_RST_STAT		0x0014
#define LTQ_XRX_RCU_RST_STAT_WDT	BIT(31)

/* CPU0 Reset Source Register */
#define LTQ_FALCON_SYS1_CPU0RS		0x0060
/* reset cause mask */
#define LTQ_FALCON_SYS1_CPU0RS_MASK	0x0007
#define LTQ_FALCON_SYS1_CPU0RS_WDT	0x02

/*
 * Section 3.4 of the datasheet
 * The password sequence protects the WDT control register from unintended
 * write actions, which might cause malfunction of the WDT.
 *
 * essentially the following two magic passwords need to be written to allow
 * IO access to the WDT core
 */
#define LTQ_WDT_PW1		0x00BE0000
#define LTQ_WDT_PW2		0x00DC0000

#define LTQ_WDT_CR		0x0	/* watchdog control register */
#define LTQ_WDT_SR		0x8	/* watchdog status register */

#define LTQ_WDT_SR_EN		(0x1 << 31)	/* enable bit */
#define LTQ_WDT_SR_PWD		(0x3 << 26)	/* turn on power */
#define LTQ_WDT_SR_CLKDIV	(0x3 << 24)	/* turn on clock and set */
						/* divider to 0x40000 */
#define LTQ_WDT_DIVIDER		0x40000
#define LTQ_MAX_TIMEOUT		((1 << 16) - 1)	/* the reload field is 16 bit */

static bool nowayout = WATCHDOG_NOWAYOUT;

static void __iomem *ltq_wdt_membase;
static unsigned long ltq_io_region_clk_rate;

static unsigned long ltq_wdt_bootstatus;
static unsigned long ltq_wdt_in_use;
static int ltq_wdt_timeout = 30;
static int ltq_wdt_ok_to_close;

static void
ltq_wdt_enable(void)
{
	unsigned long int timeout = ltq_wdt_timeout *
			(ltq_io_region_clk_rate / LTQ_WDT_DIVIDER) + 0x1000;
	if (timeout > LTQ_MAX_TIMEOUT)
		timeout = LTQ_MAX_TIMEOUT;

	/* write the first password magic */
	ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR);
	/* write the second magic plus the configuration and new timeout */
	ltq_w32(LTQ_WDT_SR_EN | LTQ_WDT_SR_PWD | LTQ_WDT_SR_CLKDIV |
		LTQ_WDT_PW2 | timeout, ltq_wdt_membase + LTQ_WDT_CR);
}

static void
ltq_wdt_disable(void)
{
	/* write the first password magic */
	ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR);
	/*
	 * write the second password magic with no config
	 * this turns the watchdog off
	 */
	ltq_w32(LTQ_WDT_PW2, ltq_wdt_membase + LTQ_WDT_CR);
}

static ssize_t
ltq_wdt_write(struct file *file, const char __user *data,
		size_t len, loff_t *ppos)
{
	if (len) {
		if (!nowayout) {
			size_t i;

			ltq_wdt_ok_to_close = 0;
			for (i = 0; i != len; i++) {
				char c;

				if (get_user(c, data + i))
					return -EFAULT;
				if (c == 'V')
					ltq_wdt_ok_to_close = 1;
				else
					ltq_wdt_ok_to_close = 0;
			}
		}
		ltq_wdt_enable();
	}

	return len;
}

static struct watchdog_info ident = {
	.options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
			WDIOF_CARDRESET,
	.identity = "ltq_wdt",
};

static long
ltq_wdt_ioctl(struct file *file,
		unsigned int cmd, unsigned long arg)
{
	int ret = -ENOTTY;

	switch (cmd) {
	case WDIOC_GETSUPPORT:
		ret = copy_to_user((struct watchdog_info __user *)arg, &ident,
				sizeof(ident)) ? -EFAULT : 0;
		break;

	case WDIOC_GETBOOTSTATUS:
		ret = put_user(ltq_wdt_bootstatus, (int __user *)arg);
		break;

	case WDIOC_GETSTATUS:
		ret = put_user(0, (int __user *)arg);
		break;

	case WDIOC_SETTIMEOUT:
		ret = get_user(ltq_wdt_timeout, (int __user *)arg);
		if (!ret)
			ltq_wdt_enable();
		/* intentional drop through */
	case WDIOC_GETTIMEOUT:
		ret = put_user(ltq_wdt_timeout, (int __user *)arg);
		break;

	case WDIOC_KEEPALIVE:
		ltq_wdt_enable();
		ret = 0;
		break;
	}
	return ret;
}

static int
ltq_wdt_open(struct inode *inode, struct file *file)
{
	if (test_and_set_bit(0, &ltq_wdt_in_use))
		return -EBUSY;
	ltq_wdt_in_use = 1;
	ltq_wdt_enable();

	return nonseekable_open(inode, file);
}

static int
ltq_wdt_release(struct inode *inode, struct file *file)
{
	if (ltq_wdt_ok_to_close)
		ltq_wdt_disable();
	else
		pr_err("watchdog closed without warning\n");
	ltq_wdt_ok_to_close = 0;
	clear_bit(0, &ltq_wdt_in_use);

	return 0;
}

static const struct file_operations ltq_wdt_fops = {
	.owner		= THIS_MODULE,
	.write		= ltq_wdt_write,
	.unlocked_ioctl	= ltq_wdt_ioctl,
	.open		= ltq_wdt_open,
	.release	= ltq_wdt_release,
	.llseek		= no_llseek,
};

static struct miscdevice ltq_wdt_miscdev = {
	.minor	= WATCHDOG_MINOR,
	.name	= "watchdog",
	.fops	= &ltq_wdt_fops,
};

typedef int (*ltq_wdt_bootstatus_set)(struct platform_device *pdev);

static int ltq_wdt_bootstatus_xrx(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct regmap *rcu_regmap;
	u32 val;
	int err;

	rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
	if (IS_ERR(rcu_regmap))
		return PTR_ERR(rcu_regmap);

	err = regmap_read(rcu_regmap, LTQ_XRX_RCU_RST_STAT, &val);
	if (err)
		return err;

	if (val & LTQ_XRX_RCU_RST_STAT_WDT)
		ltq_wdt_bootstatus = WDIOF_CARDRESET;

	return 0;
}

static int ltq_wdt_bootstatus_falcon(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct regmap *rcu_regmap;
	u32 val;
	int err;

	rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
						     "lantiq,rcu");
	if (IS_ERR(rcu_regmap))
		return PTR_ERR(rcu_regmap);

	err = regmap_read(rcu_regmap, LTQ_FALCON_SYS1_CPU0RS, &val);
	if (err)
		return err;

	if ((val & LTQ_FALCON_SYS1_CPU0RS_MASK) == LTQ_FALCON_SYS1_CPU0RS_WDT)
		ltq_wdt_bootstatus = WDIOF_CARDRESET;

	return 0;
}

static int
ltq_wdt_probe(struct platform_device *pdev)
{
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct clk *clk;
	ltq_wdt_bootstatus_set ltq_wdt_bootstatus_set;
	int ret;

	ltq_wdt_membase = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(ltq_wdt_membase))
		return PTR_ERR(ltq_wdt_membase);

	ltq_wdt_bootstatus_set = of_device_get_match_data(&pdev->dev);
	if (ltq_wdt_bootstatus_set) {
		ret = ltq_wdt_bootstatus_set(pdev);
		if (ret)
			return ret;
	}

	/* we do not need to enable the clock as it is always running */
	clk = clk_get_io();
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "Failed to get clock\n");
		return -ENOENT;
	}
	ltq_io_region_clk_rate = clk_get_rate(clk);
	clk_put(clk);

	dev_info(&pdev->dev, "Init done\n");
	return misc_register(&ltq_wdt_miscdev);
}

static int
ltq_wdt_remove(struct platform_device *pdev)
{
	misc_deregister(&ltq_wdt_miscdev);

	return 0;
}

static const struct of_device_id ltq_wdt_match[] = {
	{ .compatible = "lantiq,wdt", .data = NULL},
	{ .compatible = "lantiq,xrx100-wdt", .data = ltq_wdt_bootstatus_xrx },
	{ .compatible = "lantiq,falcon-wdt", .data = ltq_wdt_bootstatus_falcon },
	{},
};
MODULE_DEVICE_TABLE(of, ltq_wdt_match);

static struct platform_driver ltq_wdt_driver = {
	.probe = ltq_wdt_probe,
	.remove = ltq_wdt_remove,
	.driver = {
		.name = "wdt",
		.of_match_table = ltq_wdt_match,
	},
};

module_platform_driver(ltq_wdt_driver);

module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
MODULE_AUTHOR("John Crispin <[email protected]>");
MODULE_DESCRIPTION("Lantiq SoC Watchdog");
MODULE_LICENSE("GPL");
Commit	Line	Data
2f58b8d0 JC	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License version 2 as published
	4	* by the Free Software Foundation.
	5	*
f3519a66	6	* Copyright (C) 2010 John Crispin <[email protected]>
710322ba	7	* Copyright (C) 2017 Hauke Mehrtens <[email protected]>
2f58b8d0 JC	8	* Based on EP93xx wdt driver
	9	*/
	10
27c766aa JP	11	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	12
2f58b8d0 JC	13	#include <linux/module.h>
	14	#include <linux/fs.h>
	15	#include <linux/miscdevice.h>
	16	#include <linux/watchdog.h>
cdb86121	17	#include <linux/of_platform.h>
2f58b8d0 JC	18	#include <linux/uaccess.h>
	19	#include <linux/clk.h>
	20	#include <linux/io.h>
710322ba HM	21	#include <linux/regmap.h>
710322ba HM	22	#include <linux/mfd/syscon.h>
2f58b8d0	23
cdb86121	24	#include <lantiq_soc.h>
2f58b8d0	25
710322ba HM	26	#define LTQ_XRX_RCU_RST_STAT 0x0014
	27	#define LTQ_XRX_RCU_RST_STAT_WDT BIT(31)
	28
	29	/* CPU0 Reset Source Register */
	30	#define LTQ_FALCON_SYS1_CPU0RS 0x0060
	31	/* reset cause mask */
	32	#define LTQ_FALCON_SYS1_CPU0RS_MASK 0x0007
	33	#define LTQ_FALCON_SYS1_CPU0RS_WDT 0x02
	34
cdb86121 JC	35	/*
cdb86121 JC	36	* Section 3.4 of the datasheet
2f58b8d0 JC	37	* The password sequence protects the WDT control register from unintended
	38	* write actions, which might cause malfunction of the WDT.
	39	*
	40	* essentially the following two magic passwords need to be written to allow
	41	* IO access to the WDT core
	42	*/
	43	#define LTQ_WDT_PW1 0x00BE0000
	44	#define LTQ_WDT_PW2 0x00DC0000
	45
	46	#define LTQ_WDT_CR 0x0 /* watchdog control register */
	47	#define LTQ_WDT_SR 0x8 /* watchdog status register */
	48
	49	#define LTQ_WDT_SR_EN (0x1 << 31) /* enable bit */
	50	#define LTQ_WDT_SR_PWD (0x3 << 26) /* turn on power */
	51	#define LTQ_WDT_SR_CLKDIV (0x3 << 24) /* turn on clock and set */
	52	/* divider to 0x40000 */
	53	#define LTQ_WDT_DIVIDER 0x40000
	54	#define LTQ_MAX_TIMEOUT ((1 << 16) - 1) /* the reload field is 16 bit */
	55
86a1e189	56	static bool nowayout = WATCHDOG_NOWAYOUT;
2f58b8d0 JC	57
	58	static void __iomem *ltq_wdt_membase;
	59	static unsigned long ltq_io_region_clk_rate;
	60
	61	static unsigned long ltq_wdt_bootstatus;
	62	static unsigned long ltq_wdt_in_use;
	63	static int ltq_wdt_timeout = 30;
	64	static int ltq_wdt_ok_to_close;
	65
	66	static void
	67	ltq_wdt_enable(void)
	68	{
9cfce47b	69	unsigned long int timeout = ltq_wdt_timeout *
2f58b8d0	70	(ltq_io_region_clk_rate / LTQ_WDT_DIVIDER) + 0x1000;
9cfce47b JC	71	if (timeout > LTQ_MAX_TIMEOUT)
9cfce47b JC	72	timeout = LTQ_MAX_TIMEOUT;
2f58b8d0 JC	73
	74	/* write the first password magic */
	75	ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR);
	76	/* write the second magic plus the configuration and new timeout */
	77	ltq_w32(LTQ_WDT_SR_EN \| LTQ_WDT_SR_PWD \| LTQ_WDT_SR_CLKDIV \|
9cfce47b	78	LTQ_WDT_PW2 \| timeout, ltq_wdt_membase + LTQ_WDT_CR);
2f58b8d0 JC	79	}
	80
	81	static void
	82	ltq_wdt_disable(void)
	83	{
	84	/* write the first password magic */
	85	ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR);
cdb86121 JC	86	/*
cdb86121 JC	87	* write the second password magic with no config
2f58b8d0 JC	88	* this turns the watchdog off
	89	*/
	90	ltq_w32(LTQ_WDT_PW2, ltq_wdt_membase + LTQ_WDT_CR);
	91	}
	92
	93	static ssize_t
	94	ltq_wdt_write(struct file file, const char __user data,
	95	size_t len, loff_t *ppos)
	96	{
	97	if (len) {
	98	if (!nowayout) {
	99	size_t i;
	100
	101	ltq_wdt_ok_to_close = 0;
	102	for (i = 0; i != len; i++) {
	103	char c;
	104
	105	if (get_user(c, data + i))
	106	return -EFAULT;
	107	if (c == 'V')
	108	ltq_wdt_ok_to_close = 1;
	109	else
	110	ltq_wdt_ok_to_close = 0;
	111	}
	112	}
	113	ltq_wdt_enable();
	114	}
	115
	116	return len;
	117	}
	118
	119	static struct watchdog_info ident = {
	120	.options = WDIOF_MAGICCLOSE \| WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING \|
	121	WDIOF_CARDRESET,
	122	.identity = "ltq_wdt",
	123	};
	124
	125	static long
	126	ltq_wdt_ioctl(struct file *file,
	127	unsigned int cmd, unsigned long arg)
	128	{
	129	int ret = -ENOTTY;
	130
	131	switch (cmd) {
	132	case WDIOC_GETSUPPORT:
	133	ret = copy_to_user((struct watchdog_info __user *)arg, &ident,
	134	sizeof(ident)) ? -EFAULT : 0;
	135	break;
	136
	137	case WDIOC_GETBOOTSTATUS:
	138	ret = put_user(ltq_wdt_bootstatus, (int __user *)arg);
	139	break;
	140
	141	case WDIOC_GETSTATUS:
	142	ret = put_user(0, (int __user *)arg);
	143	break;
	144
	145	case WDIOC_SETTIMEOUT:
	146	ret = get_user(ltq_wdt_timeout, (int __user *)arg);
	147	if (!ret)
	148	ltq_wdt_enable();
	149	/* intentional drop through */
	150	case WDIOC_GETTIMEOUT:
	151	ret = put_user(ltq_wdt_timeout, (int __user *)arg);
152	break;
153
154	case WDIOC_KEEPALIVE:
155	ltq_wdt_enable();
156	ret = 0;
157	break;
158	}
159	return ret;
160	}
161
162	static int
163	ltq_wdt_open(struct inode inode, struct file file)
164	{
165	if (test_and_set_bit(0, &ltq_wdt_in_use))
166	return -EBUSY;
167	ltq_wdt_in_use = 1;
168	ltq_wdt_enable();
169
170	return nonseekable_open(inode, file);
171	}
172
173	static int
174	ltq_wdt_release(struct inode inode, struct file file)
175	{
176	if (ltq_wdt_ok_to_close)
177	ltq_wdt_disable();
178	else
27c766aa	179	pr_err("watchdog closed without warning\n");
2f58b8d0 JC	180	ltq_wdt_ok_to_close = 0;
	181	clear_bit(0, &ltq_wdt_in_use);
	182
	183	return 0;
	184	}
	185
	186	static const struct file_operations ltq_wdt_fops = {
	187	.owner = THIS_MODULE,
	188	.write = ltq_wdt_write,
	189	.unlocked_ioctl = ltq_wdt_ioctl,
	190	.open = ltq_wdt_open,
	191	.release = ltq_wdt_release,
	192	.llseek = no_llseek,
	193	};
	194
	195	static struct miscdevice ltq_wdt_miscdev = {
	196	.minor = WATCHDOG_MINOR,
	197	.name = "watchdog",
	198	.fops = &ltq_wdt_fops,
	199	};
	200
710322ba HM	201	typedef int (ltq_wdt_bootstatus_set)(struct platform_device pdev);
	202
	203	static int ltq_wdt_bootstatus_xrx(struct platform_device *pdev)
	204	{
	205	struct device *dev = &pdev->dev;
	206	struct regmap *rcu_regmap;
	207	u32 val;
	208	int err;
	209
	210	rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
	211	if (IS_ERR(rcu_regmap))
	212	return PTR_ERR(rcu_regmap);
	213
	214	err = regmap_read(rcu_regmap, LTQ_XRX_RCU_RST_STAT, &val);
	215	if (err)
	216	return err;
	217
	218	if (val & LTQ_XRX_RCU_RST_STAT_WDT)
	219	ltq_wdt_bootstatus = WDIOF_CARDRESET;
	220
	221	return 0;
	222	}
	223
	224	static int ltq_wdt_bootstatus_falcon(struct platform_device *pdev)
	225	{
	226	struct device *dev = &pdev->dev;
	227	struct regmap *rcu_regmap;
	228	u32 val;
	229	int err;
	230
	231	rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
	232	"lantiq,rcu");
	233	if (IS_ERR(rcu_regmap))
	234	return PTR_ERR(rcu_regmap);
	235
	236	err = regmap_read(rcu_regmap, LTQ_FALCON_SYS1_CPU0RS, &val);
	237	if (err)
	238	return err;
	239
	240	if ((val & LTQ_FALCON_SYS1_CPU0RS_MASK) == LTQ_FALCON_SYS1_CPU0RS_WDT)
	241	ltq_wdt_bootstatus = WDIOF_CARDRESET;
	242
	243	return 0;
	244	}
	245
2d991a16	246	static int
2f58b8d0 JC	247	ltq_wdt_probe(struct platform_device *pdev)
	248	{
	249	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	250	struct clk *clk;
710322ba HM	251	ltq_wdt_bootstatus_set ltq_wdt_bootstatus_set;
710322ba HM	252	int ret;
2f58b8d0	253
4c271bb6 TR	254	ltq_wdt_membase = devm_ioremap_resource(&pdev->dev, res);
	255	if (IS_ERR(ltq_wdt_membase))
	256	return PTR_ERR(ltq_wdt_membase);
2f58b8d0	257
710322ba HM	258	ltq_wdt_bootstatus_set = of_device_get_match_data(&pdev->dev);
	259	if (ltq_wdt_bootstatus_set) {
	260	ret = ltq_wdt_bootstatus_set(pdev);
	261	if (ret)
	262	return ret;
	263	}
	264
2f58b8d0	265	/* we do not need to enable the clock as it is always running */
cdb86121 JC	266	clk = clk_get_io();
	267	if (IS_ERR(clk)) {
	268	dev_err(&pdev->dev, "Failed to get clock\n");
	269	return -ENOENT;
	270	}
2f58b8d0 JC	271	ltq_io_region_clk_rate = clk_get_rate(clk);
	272	clk_put(clk);
	273
cdb86121	274	dev_info(&pdev->dev, "Init done\n");
2f58b8d0 JC	275	return misc_register(&ltq_wdt_miscdev);
	276	}
	277
4b12b896	278	static int
2f58b8d0 JC	279	ltq_wdt_remove(struct platform_device *pdev)
	280	{
	281	misc_deregister(&ltq_wdt_miscdev);
	282
2f58b8d0 JC	283	return 0;
	284	}
	285
cdb86121	286	static const struct of_device_id ltq_wdt_match[] = {
710322ba HM	287	{ .compatible = "lantiq,wdt", .data = NULL},
	288	{ .compatible = "lantiq,xrx100-wdt", .data = ltq_wdt_bootstatus_xrx },
	289	{ .compatible = "lantiq,falcon-wdt", .data = ltq_wdt_bootstatus_falcon },
cdb86121 JC	290	{},
	291	};
	292	MODULE_DEVICE_TABLE(of, ltq_wdt_match);
2f58b8d0 JC	293
2f58b8d0 JC	294	static struct platform_driver ltq_wdt_driver = {
cdb86121	295	.probe = ltq_wdt_probe,
82268714	296	.remove = ltq_wdt_remove,
2f58b8d0	297	.driver = {
cdb86121	298	.name = "wdt",
cdb86121	299	.of_match_table = ltq_wdt_match,
2f58b8d0 JC	300	},
	301	};
	302
cdb86121	303	module_platform_driver(ltq_wdt_driver);
2f58b8d0	304
86a1e189	305	module_param(nowayout, bool, 0);
2f58b8d0	306	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
f3519a66	307	MODULE_AUTHOR("John Crispin <[email protected]>");
2f58b8d0 JC	308	MODULE_DESCRIPTION("Lantiq SoC Watchdog");
2f58b8d0 JC	309	MODULE_LICENSE("GPL");