[linux.git] / drivers / watchdog / at91sam9_wdt.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * drivers/watchdog/at91sam9_wdt.h
 *
 * Copyright (C) 2007 Andrew Victor
 * Copyright (C) 2007 Atmel Corporation.
 *
 * Watchdog Timer (WDT) - System peripherals regsters.
 * Based on AT91SAM9261 datasheet revision D.
 *
 */

#ifndef AT91_WDT_H
#define AT91_WDT_H

#define AT91_WDT_CR		0x00			/* Watchdog Control Register */
#define		AT91_WDT_WDRSTT		(1    << 0)		/* Restart */
#define		AT91_WDT_KEY		(0xa5 << 24)		/* KEY Password */

#define AT91_WDT_MR		0x04			/* Watchdog Mode Register */
#define		AT91_WDT_WDV		(0xfff << 0)		/* Counter Value */
#define			AT91_WDT_SET_WDV(x)	((x) & AT91_WDT_WDV)
#define		AT91_WDT_WDFIEN		(1     << 12)		/* Fault Interrupt Enable */
#define		AT91_WDT_WDRSTEN	(1     << 13)		/* Reset Processor */
#define		AT91_WDT_WDRPROC	(1     << 14)		/* Timer Restart */
#define		AT91_WDT_WDDIS		(1     << 15)		/* Watchdog Disable */
#define		AT91_WDT_WDD		(0xfff << 16)		/* Delta Value */
#define			AT91_WDT_SET_WDD(x)	(((x) << 16) & AT91_WDT_WDD)
#define		AT91_WDT_WDDBGHLT	(1     << 28)		/* Debug Halt */
#define		AT91_WDT_WDIDLEHLT	(1     << 29)		/* Idle Halt */

#define AT91_WDT_SR		0x08			/* Watchdog Status Register */
#define		AT91_WDT_WDUNF		(1 << 0)		/* Watchdog Underflow */
#define		AT91_WDT_WDERR		(1 << 1)		/* Watchdog Error */

#endif
Commit	Line	Data
2e62c498	1	/* SPDX-License-Identifier: GPL-2.0+ */
eaa595cb	2	/*
e7b39145	3	* drivers/watchdog/at91sam9_wdt.h
eaa595cb	4	*
3d73e893 AV	5	* Copyright (C) 2007 Andrew Victor
	6	* Copyright (C) 2007 Atmel Corporation.
	7	*
eaa595cb AV	8	* Watchdog Timer (WDT) - System peripherals regsters.
	9	* Based on AT91SAM9261 datasheet revision D.
	10	*
eaa595cb AV	11	*/
	12
	13	#ifndef AT91_WDT_H
	14	#define AT91_WDT_H
	15
c1c30a29	16	#define AT91_WDT_CR 0x00 /* Watchdog Control Register */
eaa595cb	17	#define AT91_WDT_WDRSTT (1 << 0) /* Restart */
0e5f82dd	18	#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */
eaa595cb	19
c1c30a29	20	#define AT91_WDT_MR 0x04 /* Watchdog Mode Register */
eaa595cb	21	#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */
76534860	22	#define AT91_WDT_SET_WDV(x) ((x) & AT91_WDT_WDV)
eaa595cb AV	23	#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */
	24	#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */
	25	#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */
	26	#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */
	27	#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */
76534860	28	#define AT91_WDT_SET_WDD(x) (((x) << 16) & AT91_WDT_WDD)
eaa595cb AV	29	#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */
	30	#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */
	31
c1c30a29	32	#define AT91_WDT_SR 0x08 /* Watchdog Status Register */
eaa595cb AV	33	#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
	34	#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
	35
	36	#endif