[linux.git] / drivers / char / agp / sgi-agp.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2003-2005 Silicon Graphics, Inc.  All Rights Reserved.
 */

/*
 * SGI TIOCA AGPGART routines.
 *
 */

#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/agp_backend.h>
#include <asm/sn/addrs.h>
#include <asm/sn/io.h>
#include <asm/sn/pcidev.h>
#include <asm/sn/pcibus_provider_defs.h>
#include <asm/sn/tioca_provider.h>
#include "agp.h"

extern int agp_memory_reserved;
extern uint32_t tioca_gart_found;
extern struct list_head tioca_list;
static struct agp_bridge_data **sgi_tioca_agp_bridges;

/*
 * The aperature size and related information is set up at TIOCA init time.
 * Values for this table will be extracted and filled in at
 * sgi_tioca_fetch_size() time.
 */

static struct aper_size_info_fixed sgi_tioca_sizes[] = {
	{0, 0, 0},
};

static struct page *sgi_tioca_alloc_page(struct agp_bridge_data *bridge)
{
	struct page *page;
	int nid;
	struct tioca_kernel *info =
	    (struct tioca_kernel *)bridge->dev_private_data;

	nid = info->ca_closest_node;
	page = alloc_pages_node(nid, GFP_KERNEL, 0);
	if (!page)
		return NULL;

	get_page(page);
	atomic_inc(&agp_bridge->current_memory_agp);
	return page;
}

/*
 * Flush GART tlb's.  Cannot selectively flush based on memory so the mem
 * arg is ignored.
 */

static void sgi_tioca_tlbflush(struct agp_memory *mem)
{
	tioca_tlbflush(mem->bridge->dev_private_data);
}

/*
 * Given an address of a host physical page, turn it into a valid gart
 * entry.
 */
static unsigned long
sgi_tioca_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr,
		      int type)
{
	return tioca_physpage_to_gart(addr);
}

static void sgi_tioca_agp_enable(struct agp_bridge_data *bridge, u32 mode)
{
	tioca_fastwrite_enable(bridge->dev_private_data);
}

/*
 * sgi_tioca_configure() doesn't have anything to do since the base CA driver
 * has alreay set up the GART.
 */

static int sgi_tioca_configure(void)
{
	return 0;
}

/*
 * Determine gfx aperature size.  This has already been determined by the
 * CA driver init, so just need to set agp_bridge values accordingly.
 */

static int sgi_tioca_fetch_size(void)
{
	struct tioca_kernel *info =
	    (struct tioca_kernel *)agp_bridge->dev_private_data;

	sgi_tioca_sizes[0].size = info->ca_gfxap_size / MB(1);
	sgi_tioca_sizes[0].num_entries = info->ca_gfxgart_entries;

	return sgi_tioca_sizes[0].size;
}

static int sgi_tioca_create_gatt_table(struct agp_bridge_data *bridge)
{
	struct tioca_kernel *info =
	    (struct tioca_kernel *)bridge->dev_private_data;

	bridge->gatt_table_real = (u32 *) info->ca_gfxgart;
	bridge->gatt_table = bridge->gatt_table_real;
	bridge->gatt_bus_addr = info->ca_gfxgart_base;

	return 0;
}

static int sgi_tioca_free_gatt_table(struct agp_bridge_data *bridge)
{
	return 0;
}

static int sgi_tioca_insert_memory(struct agp_memory *mem, off_t pg_start,
				   int type)
{
	int num_entries;
	size_t i;
	off_t j;
	void *temp;
	struct agp_bridge_data *bridge;
	u64 *table;

	bridge = mem->bridge;
	if (!bridge)
		return -EINVAL;

	table = (u64 *)bridge->gatt_table;

	temp = bridge->current_size;

	switch (bridge->driver->size_type) {
	case U8_APER_SIZE:
		num_entries = A_SIZE_8(temp)->num_entries;
		break;
	case U16_APER_SIZE:
		num_entries = A_SIZE_16(temp)->num_entries;
		break;
	case U32_APER_SIZE:
		num_entries = A_SIZE_32(temp)->num_entries;
		break;
	case FIXED_APER_SIZE:
		num_entries = A_SIZE_FIX(temp)->num_entries;
		break;
	case LVL2_APER_SIZE:
		return -EINVAL;
	default:
		num_entries = 0;
		break;
	}

	num_entries -= agp_memory_reserved / PAGE_SIZE;
	if (num_entries < 0)
		num_entries = 0;

	if (type != 0 || mem->type != 0) {
		return -EINVAL;
	}

	if ((pg_start + mem->page_count) > num_entries)
		return -EINVAL;

	j = pg_start;

	while (j < (pg_start + mem->page_count)) {
		if (table[j])
			return -EBUSY;
		j++;
	}

	if (!mem->is_flushed) {
		bridge->driver->cache_flush();
		mem->is_flushed = true;
	}

	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
		table[j] =
		    bridge->driver->mask_memory(bridge,
						page_to_phys(mem->pages[i]),
						mem->type);
	}

	bridge->driver->tlb_flush(mem);
	return 0;
}

static int sgi_tioca_remove_memory(struct agp_memory *mem, off_t pg_start,
				   int type)
{
	size_t i;
	struct agp_bridge_data *bridge;
	u64 *table;

	bridge = mem->bridge;
	if (!bridge)
		return -EINVAL;

	if (type != 0 || mem->type != 0) {
		return -EINVAL;
	}

	table = (u64 *)bridge->gatt_table;

	for (i = pg_start; i < (mem->page_count + pg_start); i++) {
		table[i] = 0;
	}

	bridge->driver->tlb_flush(mem);
	return 0;
}

static void sgi_tioca_cache_flush(void)
{
}

/*
 * Cleanup.  Nothing to do as the CA driver owns the GART.
 */

static void sgi_tioca_cleanup(void)
{
}

static struct agp_bridge_data *sgi_tioca_find_bridge(struct pci_dev *pdev)
{
	struct agp_bridge_data *bridge;

	list_for_each_entry(bridge, &agp_bridges, list) {
		if (bridge->dev->bus == pdev->bus)
			break;
	}
	return bridge;
}

const struct agp_bridge_driver sgi_tioca_driver = {
	.owner = THIS_MODULE,
	.size_type = U16_APER_SIZE,
	.configure = sgi_tioca_configure,
	.fetch_size = sgi_tioca_fetch_size,
	.cleanup = sgi_tioca_cleanup,
	.tlb_flush = sgi_tioca_tlbflush,
	.mask_memory = sgi_tioca_mask_memory,
	.agp_enable = sgi_tioca_agp_enable,
	.cache_flush = sgi_tioca_cache_flush,
	.create_gatt_table = sgi_tioca_create_gatt_table,
	.free_gatt_table = sgi_tioca_free_gatt_table,
	.insert_memory = sgi_tioca_insert_memory,
	.remove_memory = sgi_tioca_remove_memory,
	.alloc_by_type = agp_generic_alloc_by_type,
	.free_by_type = agp_generic_free_by_type,
	.agp_alloc_page = sgi_tioca_alloc_page,
	.agp_destroy_page = agp_generic_destroy_page,
	.agp_type_to_mask_type  = agp_generic_type_to_mask_type,
	.cant_use_aperture = true,
	.needs_scratch_page = false,
	.num_aperture_sizes = 1,
};

static int agp_sgi_init(void)
{
	unsigned int j;
	struct tioca_kernel *info;
	struct pci_dev *pdev = NULL;

	if (tioca_gart_found)
		printk(KERN_INFO PFX "SGI TIO CA GART driver initialized.\n");
	else
		return 0;

	sgi_tioca_agp_bridges = kmalloc(tioca_gart_found *
					sizeof(struct agp_bridge_data *),
					GFP_KERNEL);
	if (!sgi_tioca_agp_bridges)
		return -ENOMEM;

	j = 0;
	list_for_each_entry(info, &tioca_list, ca_list) {
		if (list_empty(info->ca_devices))
			continue;
		list_for_each_entry(pdev, info->ca_devices, bus_list) {
			u8 cap_ptr;

			if (pdev->class != (PCI_CLASS_DISPLAY_VGA << 8))
				continue;
			cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
			if (!cap_ptr)
				continue;
		}
		sgi_tioca_agp_bridges[j] = agp_alloc_bridge();
		printk(KERN_INFO PFX "bridge %d = 0x%p\n", j,
		       sgi_tioca_agp_bridges[j]);
		if (sgi_tioca_agp_bridges[j]) {
			sgi_tioca_agp_bridges[j]->dev = pdev;
			sgi_tioca_agp_bridges[j]->dev_private_data = info;
			sgi_tioca_agp_bridges[j]->driver = &sgi_tioca_driver;
			sgi_tioca_agp_bridges[j]->gart_bus_addr =
			    info->ca_gfxap_base;
			sgi_tioca_agp_bridges[j]->mode = (0x7D << 24) |	/* 126 requests */
			    (0x1 << 9) |	/* SBA supported */
			    (0x1 << 5) |	/* 64-bit addresses supported */
			    (0x1 << 4) |	/* FW supported */
			    (0x1 << 3) |	/* AGP 3.0 mode */
			    0x2;	/* 8x transfer only */
			sgi_tioca_agp_bridges[j]->current_size =
			    sgi_tioca_agp_bridges[j]->previous_size =
			    (void *)&sgi_tioca_sizes[0];
			agp_add_bridge(sgi_tioca_agp_bridges[j]);
		}
		j++;
	}

	agp_find_bridge = &sgi_tioca_find_bridge;
	return 0;
}

static void agp_sgi_cleanup(void)
{
	kfree(sgi_tioca_agp_bridges);
	sgi_tioca_agp_bridges = NULL;
}

module_init(agp_sgi_init);
module_exit(agp_sgi_cleanup);

MODULE_LICENSE("GPL and additional rights");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2003-2005 Silicon Graphics, Inc. All Rights Reserved.
	7	*/
	8
	9	/*
	10	* SGI TIOCA AGPGART routines.
	11	*
	12	*/
	13
	14	#include <linux/acpi.h>
	15	#include <linux/module.h>
	16	#include <linux/pci.h>
5a0e3ad6	17	#include <linux/slab.h>
1da177e4 LT	18	#include <linux/init.h>
	19	#include <linux/agp_backend.h>
	20	#include <asm/sn/addrs.h>
1fa92957	21	#include <asm/sn/io.h>
1da177e4 LT	22	#include <asm/sn/pcidev.h>
	23	#include <asm/sn/pcibus_provider_defs.h>
	24	#include <asm/sn/tioca_provider.h>
	25	#include "agp.h"
	26
	27	extern int agp_memory_reserved;
	28	extern uint32_t tioca_gart_found;
	29	extern struct list_head tioca_list;
	30	static struct agp_bridge_data **sgi_tioca_agp_bridges;
	31
	32	/*
	33	* The aperature size and related information is set up at TIOCA init time.
	34	* Values for this table will be extracted and filled in at
	35	* sgi_tioca_fetch_size() time.
	36	*/
	37
	38	static struct aper_size_info_fixed sgi_tioca_sizes[] = {
	39	{0, 0, 0},
	40	};
	41
07613ba2	42	static struct page sgi_tioca_alloc_page(struct agp_bridge_data bridge)
1da177e4 LT	43	{
	44	struct page *page;
	45	int nid;
	46	struct tioca_kernel *info =
	47	(struct tioca_kernel *)bridge->dev_private_data;
	48
	49	nid = info->ca_closest_node;
	50	page = alloc_pages_node(nid, GFP_KERNEL, 0);
b826b4d6 DJ	51	if (!page)
b826b4d6 DJ	52	return NULL;
1da177e4 LT	53
1da177e4 LT	54	get_page(page);
1da177e4	55	atomic_inc(&agp_bridge->current_memory_agp);
07613ba2	56	return page;
1da177e4 LT	57	}
	58
	59	/*
	60	* Flush GART tlb's. Cannot selectively flush based on memory so the mem
	61	* arg is ignored.
	62	*/
	63
	64	static void sgi_tioca_tlbflush(struct agp_memory *mem)
	65	{
	66	tioca_tlbflush(mem->bridge->dev_private_data);
	67	}
	68
	69	/*
	70	* Given an address of a host physical page, turn it into a valid gart
	71	* entry.
	72	*/
	73	static unsigned long
2a4ceb6d DW	74	sgi_tioca_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr,
2a4ceb6d DW	75	int type)
1da177e4 LT	76	{
	77	return tioca_physpage_to_gart(addr);
	78	}
	79
	80	static void sgi_tioca_agp_enable(struct agp_bridge_data *bridge, u32 mode)
	81	{
	82	tioca_fastwrite_enable(bridge->dev_private_data);
	83	}
	84
	85	/*
	86	* sgi_tioca_configure() doesn't have anything to do since the base CA driver
	87	* has alreay set up the GART.
	88	*/
	89
	90	static int sgi_tioca_configure(void)
	91	{
	92	return 0;
	93	}
	94
	95	/*
	96	* Determine gfx aperature size. This has already been determined by the
	97	* CA driver init, so just need to set agp_bridge values accordingly.
	98	*/
	99
	100	static int sgi_tioca_fetch_size(void)
	101	{
	102	struct tioca_kernel *info =
	103	(struct tioca_kernel *)agp_bridge->dev_private_data;
	104
	105	sgi_tioca_sizes[0].size = info->ca_gfxap_size / MB(1);
	106	sgi_tioca_sizes[0].num_entries = info->ca_gfxgart_entries;
	107
	108	return sgi_tioca_sizes[0].size;
	109	}
	110
	111	static int sgi_tioca_create_gatt_table(struct agp_bridge_data *bridge)
	112	{
	113	struct tioca_kernel *info =
	114	(struct tioca_kernel *)bridge->dev_private_data;
	115
	116	bridge->gatt_table_real = (u32 *) info->ca_gfxgart;
	117	bridge->gatt_table = bridge->gatt_table_real;
	118	bridge->gatt_bus_addr = info->ca_gfxgart_base;
	119
	120	return 0;
	121	}
	122
	123	static int sgi_tioca_free_gatt_table(struct agp_bridge_data *bridge)
	124	{
	125	return 0;
	126	}
	127
	128	static int sgi_tioca_insert_memory(struct agp_memory *mem, off_t pg_start,
	129	int type)
	130	{
	131	int num_entries;
	132	size_t i;
	133	off_t j;
	134	void *temp;
	135	struct agp_bridge_data *bridge;
e29b545c	136	u64 *table;
1da177e4 LT	137
	138	bridge = mem->bridge;
	139	if (!bridge)
	140	return -EINVAL;
	141
e29b545c MW	142	table = (u64 *)bridge->gatt_table;
e29b545c MW	143
1da177e4 LT	144	temp = bridge->current_size;
	145
	146	switch (bridge->driver->size_type) {
	147	case U8_APER_SIZE:
	148	num_entries = A_SIZE_8(temp)->num_entries;
	149	break;
	150	case U16_APER_SIZE:
	151	num_entries = A_SIZE_16(temp)->num_entries;
	152	break;
	153	case U32_APER_SIZE:
	154	num_entries = A_SIZE_32(temp)->num_entries;
	155	break;
	156	case FIXED_APER_SIZE:
	157	num_entries = A_SIZE_FIX(temp)->num_entries;
	158	break;
	159	case LVL2_APER_SIZE:
	160	return -EINVAL;
1da177e4 LT	161	default:
	162	num_entries = 0;
	163	break;
	164	}
	165
	166	num_entries -= agp_memory_reserved / PAGE_SIZE;
	167	if (num_entries < 0)
	168	num_entries = 0;
	169
	170	if (type != 0 \|\| mem->type != 0) {
	171	return -EINVAL;
	172	}
	173
	174	if ((pg_start + mem->page_count) > num_entries)
	175	return -EINVAL;
	176
	177	j = pg_start;
	178
	179	while (j < (pg_start + mem->page_count)) {
e29b545c	180	if (table[j])
1da177e4 LT	181	return -EBUSY;
	182	j++;
	183	}
	184
c7258012	185	if (!mem->is_flushed) {
1da177e4	186	bridge->driver->cache_flush();
c7258012	187	mem->is_flushed = true;
1da177e4 LT	188	}
	189
	190	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
e29b545c	191	table[j] =
2a4ceb6d	192	bridge->driver->mask_memory(bridge,
6a12235c	193	page_to_phys(mem->pages[i]),
1da177e4 LT	194	mem->type);
	195	}
	196
	197	bridge->driver->tlb_flush(mem);
	198	return 0;
	199	}
	200
	201	static int sgi_tioca_remove_memory(struct agp_memory *mem, off_t pg_start,
	202	int type)
	203	{
	204	size_t i;
	205	struct agp_bridge_data *bridge;
e29b545c	206	u64 *table;
1da177e4 LT	207
	208	bridge = mem->bridge;
	209	if (!bridge)
	210	return -EINVAL;
	211
	212	if (type != 0 \|\| mem->type != 0) {
	213	return -EINVAL;
	214	}
	215
e29b545c MW	216	table = (u64 *)bridge->gatt_table;
e29b545c MW	217
1da177e4	218	for (i = pg_start; i < (mem->page_count + pg_start); i++) {
e29b545c	219	table[i] = 0;
1da177e4 LT	220	}
	221
	222	bridge->driver->tlb_flush(mem);
	223	return 0;
	224	}
	225
	226	static void sgi_tioca_cache_flush(void)
	227	{
	228	}
	229
	230	/*
	231	* Cleanup. Nothing to do as the CA driver owns the GART.
	232	*/
	233
	234	static void sgi_tioca_cleanup(void)
	235	{
	236	}
	237
	238	static struct agp_bridge_data sgi_tioca_find_bridge(struct pci_dev pdev)
	239	{
	240	struct agp_bridge_data *bridge;
	241
	242	list_for_each_entry(bridge, &agp_bridges, list) {
	243	if (bridge->dev->bus == pdev->bus)
	244	break;
	245	}
	246	return bridge;
	247	}
	248
e047d1cf	249	const struct agp_bridge_driver sgi_tioca_driver = {
1da177e4 LT	250	.owner = THIS_MODULE,
	251	.size_type = U16_APER_SIZE,
	252	.configure = sgi_tioca_configure,
	253	.fetch_size = sgi_tioca_fetch_size,
	254	.cleanup = sgi_tioca_cleanup,
	255	.tlb_flush = sgi_tioca_tlbflush,
	256	.mask_memory = sgi_tioca_mask_memory,
	257	.agp_enable = sgi_tioca_agp_enable,
	258	.cache_flush = sgi_tioca_cache_flush,
	259	.create_gatt_table = sgi_tioca_create_gatt_table,
	260	.free_gatt_table = sgi_tioca_free_gatt_table,
	261	.insert_memory = sgi_tioca_insert_memory,
	262	.remove_memory = sgi_tioca_remove_memory,
	263	.alloc_by_type = agp_generic_alloc_by_type,
	264	.free_by_type = agp_generic_free_by_type,
	265	.agp_alloc_page = sgi_tioca_alloc_page,
	266	.agp_destroy_page = agp_generic_destroy_page,
a030ce44	267	.agp_type_to_mask_type = agp_generic_type_to_mask_type,
c7258012 JP	268	.cant_use_aperture = true,
c7258012 JP	269	.needs_scratch_page = false,
1da177e4 LT	270	.num_aperture_sizes = 1,
	271	};
	272
bcd2982a	273	static int agp_sgi_init(void)
1da177e4 LT	274	{
	275	unsigned int j;
	276	struct tioca_kernel *info;
	277	struct pci_dev *pdev = NULL;
	278
	279	if (tioca_gart_found)
	280	printk(KERN_INFO PFX "SGI TIO CA GART driver initialized.\n");
	281	else
	282	return 0;
	283
7b37b064	284	sgi_tioca_agp_bridges = kmalloc(tioca_gart_found *
	285	sizeof(struct agp_bridge_data *),
	286	GFP_KERNEL);
	287	if (!sgi_tioca_agp_bridges)
	288	return -ENOMEM;
1da177e4 LT	289
	290	j = 0;
	291	list_for_each_entry(info, &tioca_list, ca_list) {
146a2099 DJ	292	if (list_empty(info->ca_devices))
146a2099 DJ	293	continue;
0a4af147	294	list_for_each_entry(pdev, info->ca_devices, bus_list) {
1da177e4	295	u8 cap_ptr;
0a4af147	296
1da177e4 LT	297	if (pdev->class != (PCI_CLASS_DISPLAY_VGA << 8))
	298	continue;
	299	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
	300	if (!cap_ptr)
	301	continue;
	302	}
	303	sgi_tioca_agp_bridges[j] = agp_alloc_bridge();
	304	printk(KERN_INFO PFX "bridge %d = 0x%p\n", j,
	305	sgi_tioca_agp_bridges[j]);
	306	if (sgi_tioca_agp_bridges[j]) {
	307	sgi_tioca_agp_bridges[j]->dev = pdev;
	308	sgi_tioca_agp_bridges[j]->dev_private_data = info;
	309	sgi_tioca_agp_bridges[j]->driver = &sgi_tioca_driver;
	310	sgi_tioca_agp_bridges[j]->gart_bus_addr =
	311	info->ca_gfxap_base;
	312	sgi_tioca_agp_bridges[j]->mode = (0x7D << 24) \| /* 126 requests */
	313	(0x1 << 9) \| /* SBA supported */
	314	(0x1 << 5) \| /* 64-bit addresses supported */
	315	(0x1 << 4) \| /* FW supported */
	316	(0x1 << 3) \| /* AGP 3.0 mode */
	317	0x2; /* 8x transfer only */
	318	sgi_tioca_agp_bridges[j]->current_size =
	319	sgi_tioca_agp_bridges[j]->previous_size =
	320	(void *)&sgi_tioca_sizes[0];
	321	agp_add_bridge(sgi_tioca_agp_bridges[j]);
	322	}
	323	j++;
	324	}
	325
	326	agp_find_bridge = &sgi_tioca_find_bridge;
	327	return 0;
	328	}
	329
39af33fc	330	static void agp_sgi_cleanup(void)
1da177e4	331	{
8f760780 JJ	332	kfree(sgi_tioca_agp_bridges);
8f760780 JJ	333	sgi_tioca_agp_bridges = NULL;
1da177e4 LT	334	}
	335
	336	module_init(agp_sgi_init);
	337	module_exit(agp_sgi_cleanup);
	338
	339	MODULE_LICENSE("GPL and additional rights");